diff options
Diffstat (limited to 'src/devices/cpu/tlcs900/tmp95c061.h')
-rw-r--r-- | src/devices/cpu/tlcs900/tmp95c061.h | 119 |
1 files changed, 36 insertions, 83 deletions
diff --git a/src/devices/cpu/tlcs900/tmp95c061.h b/src/devices/cpu/tlcs900/tmp95c061.h index 106ca5c57ce..fc59747457e 100644 --- a/src/devices/cpu/tlcs900/tmp95c061.h +++ b/src/devices/cpu/tlcs900/tmp95c061.h @@ -13,26 +13,37 @@ DECLARE_DEVICE_TYPE(TMP95C061, tmp95c061_device) class tmp95c061_device : public tlcs900h_device { + static constexpr uint8_t PORT_1 = 0; // 8 bit I/O. Shared with D8-D15 + static constexpr uint8_t PORT_2 = 1; // 8 bit output only. Shared with A16-A23 + static constexpr uint8_t PORT_5 = 2; // 4 bit I/O. Shared with HWR, BUSRQ, BUSAK, RW + static constexpr uint8_t PORT_6 = 3; // 6 bit I/O. Shared with CS0, CS1, CS3/LCAS, RAS, REFOUT + static constexpr uint8_t PORT_7 = 4; // 8 bit I/O. Shared with PG0-OUT, PG1-OUT + static constexpr uint8_t PORT_8 = 5; // 6 bit I/O. Shared with TXD0, TXD1, RXD0, RXD1, CTS0, SCLK0, SCLK1 + static constexpr uint8_t PORT_9 = 6; // 4 bit input only. Shared with AN0-AN3 + static constexpr uint8_t PORT_A = 7; // 4 bit I/O. Shared with WAIT, TI0, TO1, TO2 + static constexpr uint8_t PORT_B = 8; // 8 bit I/O. Shared with TI4/INT4, TI5/INT5, TI6/INT6, TI7/INT7, TO4, TO5, TO6 + static constexpr uint8_t NUM_PORTS = 9; + public: // construction/destruction tmp95c061_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); // configuration helpers - auto port1_read() { return m_port1_read.bind(); } - auto port1_write() { return m_port1_write.bind(); } - auto port2_write() { return m_port2_write.bind(); } - auto port5_read() { return m_port5_read.bind(); } - auto port5_write() { return m_port5_write.bind(); } - auto port6_write() { return m_port6_write.bind(); } - auto port7_read() { return m_port7_read.bind(); } - auto port7_write() { return m_port7_write.bind(); } - auto port8_read() { return m_port8_read.bind(); } - auto port8_write() { return m_port8_write.bind(); } - auto port9_read() { return m_port9_read.bind(); } - auto porta_read() { return m_porta_read.bind(); } - auto porta_write() { return m_porta_write.bind(); } - auto portb_read() { return m_portb_read.bind(); } - auto portb_write() { return m_portb_write.bind(); } + auto port1_read() { return m_port_read[PORT_1].bind(); } + auto port1_write() { return m_port_write[PORT_1].bind(); } + auto port2_write() { return m_port_write[PORT_2].bind(); } + auto port5_read() { return m_port_read[PORT_5].bind(); } + auto port5_write() { return m_port_write[PORT_5].bind(); } + auto port6_write() { return m_port_write[PORT_6].bind(); } + auto port7_read() { return m_port_read[PORT_7].bind(); } + auto port7_write() { return m_port_write[PORT_7].bind(); } + auto port8_read() { return m_port_read[PORT_8].bind(); } + auto port8_write() { return m_port_write[PORT_8].bind(); } + auto port9_read() { return m_port_read[PORT_9].bind(); } + auto porta_read() { return m_port_read[PORT_A].bind(); } + auto porta_write() { return m_port_write[PORT_A].bind(); } + auto portb_read() { return m_port_read[PORT_B].bind(); } + auto portb_write() { return m_port_write[PORT_B].bind(); } template <size_t Bit> auto an_read() { return m_an_read[Bit].bind(); } protected: @@ -51,36 +62,10 @@ protected: void update_porta(); private: - uint8_t p1_r(); - void p1_w(uint8_t data); - void p1cr_w(uint8_t data); - uint8_t p2_r(); - void p2_w(uint8_t data); - void p2fc_w(uint8_t data); - uint8_t p5_r(); - void p5_w(uint8_t data); - void p5cr_w(uint8_t data); - void p5fc_w(uint8_t data); - uint8_t p6_r(); - void p6_w(uint8_t data); - void p6fc_w(uint8_t data); - uint8_t p7_r(); - void p7_w(uint8_t data); - void p7cr_w(uint8_t data); - void p7fc_w(uint8_t data); - uint8_t p8_r(); - void p8_w(uint8_t data); - void p8cr_w(uint8_t data); - void p8fc_w(uint8_t data); - uint8_t p9_r(); - uint8_t pa_r(); - void pa_w(uint8_t data); - void pacr_w(uint8_t data); - void pafc_w(uint8_t data); - uint8_t pb_r(); - void pb_w(uint8_t data); - void pbcr_w(uint8_t data); - void pbfc_w(uint8_t data); + template <uint8_t> uint8_t port_r(); + template <uint8_t> void port_w(uint8_t data); + template <uint8_t> void port_cr_w(uint8_t data); + template <uint8_t> void port_fc_w(uint8_t data); uint8_t trun_r(); void trun_w(uint8_t data); void treg01_w(offs_t offset, uint8_t data); @@ -150,47 +135,15 @@ private: void internal_mem(address_map &map); - // Port 1: 8 bit I/O. Shared with D8-D15 - devcb_read8 m_port1_read; - devcb_write8 m_port1_write; - - // Port 2: 8 bit output only. Shared with A16-A23 - devcb_write8 m_port2_write; - - // Port 5: 4 bit I/O. Shared with HWR, BUSRQ, BUSAK, RW - devcb_read8 m_port5_read; - devcb_write8 m_port5_write; - - // Port 6: 6 bit I/O. Shared with CS0, CS1, CS3/LCAS, RAS, REFOUT - devcb_read8 m_port6_read; - devcb_write8 m_port6_write; - - // Port 7: 8 bit I/O. Shared with PG0-OUT, PG1-OUT - devcb_read8 m_port7_read; - devcb_write8 m_port7_write; - - // Port 8: 6 bit I/O. Shared with TXD0, TXD1, RXD0, RXD1, CTS0, SCLK0, SCLK1 - devcb_read8 m_port8_read; - devcb_write8 m_port8_write; - - // Port 9: 4 bit input only. Shared with AN0-AN3 - devcb_read8 m_port9_read; - - // Port A: 4 bit I/O. Shared with WAIT, TI0, TO1, TO2 - devcb_read8 m_porta_read; - devcb_write8 m_porta_write; - - // Port B: 8 bit I/O. Shared with TI4/INT4, TI5/INT5, TI6/INT6, TI7/INT7, TO4, TO5, TO6 - devcb_read8 m_portb_read; - devcb_write8 m_portb_write; - // analogue inputs, sampled at 10 bits devcb_read16::array<4> m_an_read; - // I/O Port Control - uint8_t m_port_latch[0xc]; - uint8_t m_port_control[0xc]; - uint8_t m_port_function[0xc]; + // I/O Ports + devcb_read8::array<NUM_PORTS> m_port_read; + devcb_write8::array<NUM_PORTS> m_port_write; + uint8_t m_port_latch[NUM_PORTS]; + uint8_t m_port_control[NUM_PORTS]; + uint8_t m_port_function[NUM_PORTS]; // Timer Control uint8_t m_trun; |