diff options
Diffstat (limited to 'src/devices/cpu/tlcs870')
-rw-r--r-- | src/devices/cpu/tlcs870/tlcs870.cpp | 106 | ||||
-rw-r--r-- | src/devices/cpu/tlcs870/tlcs870.h | 4 | ||||
-rw-r--r-- | src/devices/cpu/tlcs870/tlcs870_ops.cpp | 176 | ||||
-rw-r--r-- | src/devices/cpu/tlcs870/tlcs870_ops_dst.cpp | 86 | ||||
-rw-r--r-- | src/devices/cpu/tlcs870/tlcs870_ops_helper.cpp | 58 | ||||
-rw-r--r-- | src/devices/cpu/tlcs870/tlcs870_ops_reg.cpp | 226 | ||||
-rw-r--r-- | src/devices/cpu/tlcs870/tlcs870_ops_src.cpp | 828 | ||||
-rw-r--r-- | src/devices/cpu/tlcs870/tlcs870d.cpp | 2 |
8 files changed, 743 insertions, 743 deletions
diff --git a/src/devices/cpu/tlcs870/tlcs870.cpp b/src/devices/cpu/tlcs870/tlcs870.cpp index 79af9af88b4..c29db26f769 100644 --- a/src/devices/cpu/tlcs870/tlcs870.cpp +++ b/src/devices/cpu/tlcs870/tlcs870.cpp @@ -94,7 +94,7 @@ void tlcs870_device::tmp87ph40an_mem(address_map &map) map(0x003c, 0x003c).rw(FUNC(tlcs870_device::il_l_r), FUNC(tlcs870_device::il_l_w)); // Interrupt latch map(0x003d, 0x003d).rw(FUNC(tlcs870_device::il_h_r), FUNC(tlcs870_device::il_h_w)); // - + // 0x3e reserved map(0x003f, 0x003f).rw(FUNC(tlcs870_device::psw_r), FUNC(tlcs870_device::rbs_w)); // Program status word / Register bank selector @@ -296,9 +296,9 @@ WRITE8_MEMBER(tlcs870_device::tc1cr_w) LOG("%d: SCAP1/MCAP1/METT1/MPPG1\n", (m_TC1CR & 0x40) ? 1 : 0); LOG("%d: TC1S-1 (TC1 Start Control)\n", (m_TC1CR & 0x20) ? 1 : 0); LOG("%d: TC1S-0 (TC1 Start Control)\n", (m_TC1CR & 0x10) ? 1 : 0); - LOG("%d: TC1CK-1 (TC1 Source Clock select)\n", (m_TC1CR & 0x08) ? 1 : 0); - LOG("%d: TC1CK-0 (TC1 Source Clock select)\n", (m_TC1CR & 0x04) ? 1 : 0); - LOG("%d: TC1M-1 (TC1 Mode Select)\n", (m_TC1CR & 0x02) ? 1 : 0); + LOG("%d: TC1CK-1 (TC1 Source Clock select)\n", (m_TC1CR & 0x08) ? 1 : 0); + LOG("%d: TC1CK-0 (TC1 Source Clock select)\n", (m_TC1CR & 0x04) ? 1 : 0); + LOG("%d: TC1M-1 (TC1 Mode Select)\n", (m_TC1CR & 0x02) ? 1 : 0); LOG("%d: TC1M-0 (TC1 Mode Select)\n", (m_TC1CR & 0x01) ? 1 : 0); } @@ -371,9 +371,9 @@ WRITE8_MEMBER(tlcs870_device::tc2cr_w) LOG("%d: (invalid)\n", (m_TC2CR & 0x40) ? 1 : 0); LOG("%d: TC2S (TC2 Start Control)\n", (m_TC2CR & 0x20) ? 1 : 0); LOG("%d: TC2CK-2 (TC2 Source Clock select)\n", (m_TC2CR & 0x10) ? 1 : 0); - LOG("%d: TC2CK-1 (TC2 Source Clock select)\n", (m_TC2CR & 0x08) ? 1 : 0); - LOG("%d: TC2CK-0 (TC2 Source Clock select)\n", (m_TC2CR & 0x04) ? 1 : 0); - LOG("%d: (invalid)\n", (m_TC2CR & 0x02) ? 1 : 0); + LOG("%d: TC2CK-1 (TC2 Source Clock select)\n", (m_TC2CR & 0x08) ? 1 : 0); + LOG("%d: TC2CK-0 (TC2 Source Clock select)\n", (m_TC2CR & 0x04) ? 1 : 0); + LOG("%d: (invalid)\n", (m_TC2CR & 0x02) ? 1 : 0); LOG("%d: TC2M (TC2 Mode Select)\n", (m_TC2CR & 0x01) ? 1 : 0); } @@ -403,9 +403,9 @@ WRITE8_MEMBER(tlcs870_device::tc3cr_w) LOG("%d: SCAP (Software Capture Control)\n", (m_TC3CR & 0x40) ? 1 : 0); LOG("%d: (invalid)\n", (m_TC3CR & 0x20) ? 1 : 0); LOG("%d: TC3S (TC3 Start Control)\n", (m_TC3CR & 0x10) ? 1 : 0); - LOG("%d: TC3CK-1 (TC3 Source Clock select)\n", (m_TC3CR & 0x08) ? 1 : 0); - LOG("%d: TC3CK-0 (TC3 Source Clock select)\n", (m_TC3CR & 0x04) ? 1 : 0); - LOG("%d: (invalid)\n", (m_TC3CR & 0x02) ? 1 : 0); + LOG("%d: TC3CK-1 (TC3 Source Clock select)\n", (m_TC3CR & 0x08) ? 1 : 0); + LOG("%d: TC3CK-0 (TC3 Source Clock select)\n", (m_TC3CR & 0x04) ? 1 : 0); + LOG("%d: (invalid)\n", (m_TC3CR & 0x02) ? 1 : 0); LOG("%d: TC3M (TC3 Mode Select)\n", (m_TC3CR & 0x01) ? 1 : 0); } @@ -440,9 +440,9 @@ WRITE8_MEMBER(tlcs870_device::tc4cr_w) LOG("%d: TFF4-0 (Timer F/F 4 Control)\n", (m_TC4CR & 0x40) ? 1 : 0); LOG("%d: (invalid)\n", (m_TC4CR & 0x20) ? 1 : 0); LOG("%d: TC4S (TC4 Start Control)\n", (m_TC4CR & 0x10) ? 1 : 0); - LOG("%d: TC4CK-1 (TC4 Source Clock select)\n", (m_TC4CR & 0x08) ? 1 : 0); - LOG("%d: TC4CK-0 (TC4 Source Clock select)\n", (m_TC4CR & 0x04) ? 1 : 0); - LOG("%d: TC4M-1 (TC4 Mode Select)\n", (m_TC4CR & 0x02) ? 1 : 0); + LOG("%d: TC4CK-1 (TC4 Source Clock select)\n", (m_TC4CR & 0x08) ? 1 : 0); + LOG("%d: TC4CK-0 (TC4 Source Clock select)\n", (m_TC4CR & 0x04) ? 1 : 0); + LOG("%d: TC4M-1 (TC4 Mode Select)\n", (m_TC4CR & 0x02) ? 1 : 0); LOG("%d: TC4M-0 (TC4 Mode Select)\n", (m_TC4CR & 0x01) ? 1 : 0); } @@ -453,7 +453,7 @@ WRITE8_MEMBER(tlcs870_device::treg4_w) // Time Base Timer -// this is used with TLCS870_IRQ_INTTBT (FFF2 INTTBT) (not used by hng64) +// this is used with TLCS870_IRQ_INTTBT (FFF2 INTTBT) (not used by hng64) // the divider output makes use of PORT1 bit 3, which must be properly configured WRITE8_MEMBER(tlcs870_device::tbtcr_w) { @@ -464,9 +464,9 @@ WRITE8_MEMBER(tlcs870_device::tbtcr_w) LOG("%d: DVOCK-1 (Divide Output Frequency Selection)n", (m_TBTCR & 0x40) ? 1 : 0); LOG("%d: DVOCK-0 (Divide Output Frequency Selection)\n", (m_TBTCR & 0x20) ? 1 : 0); LOG("%d: DV7CK (?)\n", (m_TBTCR & 0x10) ? 1 : 0); - LOG("%d: TBTEN (Time Base Timer Enable)\n", (m_TBTCR & 0x08) ? 1 : 0); - LOG("%d: TBTCK-2 (Time Base Timer Interrupt Frequency)\n", (m_TBTCR & 0x04) ? 1 : 0); - LOG("%d: TBTCK-1 (Time Base Timer Interrupt Frequency)\n", (m_TBTCR & 0x02) ? 1 : 0); + LOG("%d: TBTEN (Time Base Timer Enable)\n", (m_TBTCR & 0x08) ? 1 : 0); + LOG("%d: TBTCK-2 (Time Base Timer Interrupt Frequency)\n", (m_TBTCR & 0x04) ? 1 : 0); + LOG("%d: TBTCK-1 (Time Base Timer Interrupt Frequency)\n", (m_TBTCR & 0x02) ? 1 : 0); LOG("%d: TBTCK-0 (Time Base Timer Interrupt Frequency)\n", (m_TBTCR & 0x01) ? 1 : 0); } @@ -489,9 +489,9 @@ WRITE8_MEMBER(tlcs870_device::sio1cr1_w) LOG("%d: SIOINH1 (Abort/Continue transfer)\n", (m_SIOCR1[0] & 0x40) ? 1 : 0); LOG("%d: SIOM1-2 (Serial Mode)\n", (m_SIOCR1[0] & 0x20) ? 1 : 0); LOG("%d: SIOM1-1 (Serial Mode)\n", (m_SIOCR1[0] & 0x10) ? 1 : 0); - LOG("%d: SIOM1-0 (Serial Mode)\n", (m_SIOCR1[0] & 0x08) ? 1 : 0); - LOG("%d: SCK1-2 (Serial Clock)\n", (m_SIOCR1[0] & 0x04) ? 1 : 0); - LOG("%d: SCK1-1 (Serial Clock)\n", (m_SIOCR1[0] & 0x02) ? 1 : 0); + LOG("%d: SIOM1-0 (Serial Mode)\n", (m_SIOCR1[0] & 0x08) ? 1 : 0); + LOG("%d: SCK1-2 (Serial Clock)\n", (m_SIOCR1[0] & 0x04) ? 1 : 0); + LOG("%d: SCK1-1 (Serial Clock)\n", (m_SIOCR1[0] & 0x02) ? 1 : 0); LOG("%d: SCK1-0 (Serial Clock)\n", (m_SIOCR1[0] & 0x01) ? 1 : 0); m_transfer_mode[0] = (m_SIOCR1[0] & 0x38) >> 3; @@ -503,7 +503,7 @@ WRITE8_MEMBER(tlcs870_device::sio1cr1_w) m_receive_bits[0] = 0; break; - case 0x2: + case 0x2: LOG("(Serial set to 4-bit transmit mode)\n"); m_transmit_bits[0] = 4; m_receive_bits[0] = 0; @@ -523,7 +523,7 @@ WRITE8_MEMBER(tlcs870_device::sio1cr1_w) case 0x6: LOG("(Serial set to 4-bit receive mode)\n"); m_transmit_bits[0] = 0; - m_receive_bits[0] = 4; + m_receive_bits[0] = 4; break; default: @@ -540,7 +540,7 @@ WRITE8_MEMBER(tlcs870_device::sio1cr1_w) m_transfer_shiftreg[0] = 0; m_transfer_pos[0] = 0; - m_serial_transmit_timer[0]->adjust(attotime::zero); + m_serial_transmit_timer[0]->adjust(attotime::zero); } } @@ -554,9 +554,9 @@ WRITE8_MEMBER(tlcs870_device::sio1cr2_w) LOG("%d: (invalid)\n", (m_SIOCR2[0] & 0x40) ? 1 : 0); LOG("%d: (invalid)\n", (m_SIOCR2[0] & 0x20) ? 1 : 0); LOG("%d: WAIT1-1 (Wait Control\n", (m_SIOCR2[0] & 0x10) ? 1 : 0); - LOG("%d: WAIT1-0 (Wait Control)\n", (m_SIOCR2[0] & 0x08) ? 1 : 0); - LOG("%d: BUF1-2 (Number of Transfer Bytes)\n", (m_SIOCR2[0] & 0x04) ? 1 : 0); - LOG("%d: BUF1-1 (Number of Transfer Bytes)\n", (m_SIOCR2[0] & 0x02) ? 1 : 0); + LOG("%d: WAIT1-0 (Wait Control)\n", (m_SIOCR2[0] & 0x08) ? 1 : 0); + LOG("%d: BUF1-2 (Number of Transfer Bytes)\n", (m_SIOCR2[0] & 0x04) ? 1 : 0); + LOG("%d: BUF1-1 (Number of Transfer Bytes)\n", (m_SIOCR2[0] & 0x02) ? 1 : 0); LOG("%d: BUF1-0 (Number of Transfer Bytes)\n", (m_SIOCR2[0] & 0x01) ? 1 : 0); m_transfer_numbytes[0] = (m_SIOCR2[0] & 0x7); @@ -567,7 +567,7 @@ WRITE8_MEMBER(tlcs870_device::sio1cr2_w) READ8_MEMBER(tlcs870_device::sio1sr_r) { /* TS-- ---- - + T = Transfer in Progress S = Shift in Progress @@ -625,9 +625,9 @@ WRITE8_MEMBER(tlcs870_device::sio2cr1_w) LOG("%d: SIOINH2 (Abort/Continue transfer)\n", (m_SIOCR1[1] & 0x40) ? 1 : 0); LOG("%d: SIOM2-2 (Serial Mode)\n", (m_SIOCR1[1] & 0x20) ? 1 : 0); LOG("%d: SIOM2-1 (Serial Mode)\n", (m_SIOCR1[1] & 0x10) ? 1 : 0); - LOG("%d: SIOM2-0 (Serial Mode)\n", (m_SIOCR1[1] & 0x08) ? 1 : 0); - LOG("%d: SCK2-2 (Serial Clock)\n", (m_SIOCR1[1] & 0x04) ? 1 : 0); - LOG("%d: SCK2-1 (Serial Clock)\n", (m_SIOCR1[1] & 0x02) ? 1 : 0); + LOG("%d: SIOM2-0 (Serial Mode)\n", (m_SIOCR1[1] & 0x08) ? 1 : 0); + LOG("%d: SCK2-2 (Serial Clock)\n", (m_SIOCR1[1] & 0x04) ? 1 : 0); + LOG("%d: SCK2-1 (Serial Clock)\n", (m_SIOCR1[1] & 0x02) ? 1 : 0); LOG("%d: SCK2-0 (Serial Clock)\n", (m_SIOCR1[1] & 0x01) ? 1 : 0); } @@ -640,9 +640,9 @@ WRITE8_MEMBER(tlcs870_device::sio2cr2_w) LOG("%d: (invalid)\n", (m_SIOCR2[1] & 0x40) ? 1 : 0); LOG("%d: (invalid)\n", (m_SIOCR2[1] & 0x20) ? 1 : 0); LOG("%d: WAIT2-1 (Wait Control\n", (m_SIOCR2[1] & 0x10) ? 1 : 0); - LOG("%d: WAIT2-0 (Wait Control)\n", (m_SIOCR2[1] & 0x08) ? 1 : 0); - LOG("%d: BUF2-2 (Number of Transfer Bytes)\n", (m_SIOCR2[1] & 0x04) ? 1 : 0); - LOG("%d: BUF2-1 (Number of Transfer Bytes)\n", (m_SIOCR2[1] & 0x02) ? 1 : 0); + LOG("%d: WAIT2-0 (Wait Control)\n", (m_SIOCR2[1] & 0x08) ? 1 : 0); + LOG("%d: BUF2-2 (Number of Transfer Bytes)\n", (m_SIOCR2[1] & 0x04) ? 1 : 0); + LOG("%d: BUF2-1 (Number of Transfer Bytes)\n", (m_SIOCR2[1] & 0x02) ? 1 : 0); LOG("%d: BUF2-0 (Number of Transfer Bytes)\n", (m_SIOCR2[1] & 0x01) ? 1 : 0); } @@ -653,7 +653,7 @@ TIMER_CALLBACK_MEMBER(tlcs870_device::sio1_transmit_cb) READ8_MEMBER(tlcs870_device::sio2sr_r) { /* TS-- ---- - + T = Transfer in Progress S = Shift in Progress @@ -672,9 +672,9 @@ WRITE8_MEMBER(tlcs870_device::wdtcr1_w) LOG("%d: (invalid)\n", (m_WDTCR1 & 0x40) ? 1 : 0); LOG("%d: (invalid)\n", (m_WDTCR1 & 0x20) ? 1 : 0); LOG("%d: (invalid)\n", (m_WDTCR1 & 0x10) ? 1 : 0); - LOG("%d: WDTEN (Watchdog Timer Enable, also req disable code to WDTCR2)\n", (m_WDTCR1 & 0x08) ? 1 : 0); - LOG("%d: WDTT-1 (Watchdog Timer Detection Time)\n", (m_WDTCR1 & 0x04) ? 1 : 0); - LOG("%d: WDTT-0 (Watchdog Timer Detection Time)\n", (m_WDTCR1 & 0x02) ? 1 : 0); + LOG("%d: WDTEN (Watchdog Timer Enable, also req disable code to WDTCR2)\n", (m_WDTCR1 & 0x08) ? 1 : 0); + LOG("%d: WDTT-1 (Watchdog Timer Detection Time)\n", (m_WDTCR1 & 0x04) ? 1 : 0); + LOG("%d: WDTT-0 (Watchdog Timer Detection Time)\n", (m_WDTCR1 & 0x02) ? 1 : 0); LOG("%d: WDTOUT (Watchdog Timer Output select, 0 = interrupt, 1 = reset out)\n",(m_WDTCR1 & 0x01) ? 1 : 0); // WDTOUT cannot be set to 1 by software @@ -708,9 +708,9 @@ WRITE8_MEMBER(tlcs870_device::syscr1_w) LOG("%d: RELM (release method for STOP, 0 edge, 1 level)\n", (m_SYSCR1 & 0x40) ? 1 : 0); LOG("%d: RETM (return mode after STOP, 0 normal, 1 slow)\n", (m_SYSCR1 & 0x20) ? 1 : 0); LOG("%d: OUTEN (port output control during STOP)\n", (m_SYSCR1 & 0x10) ? 1 : 0); - LOG("%d: WUT-1 (warm up time at STOP release)\n", (m_SYSCR1 & 0x08) ? 1 : 0); - LOG("%d: WUT-0 (warm up time at STOP release)\n", (m_SYSCR1 & 0x04) ? 1 : 0); - LOG("%d: (invalid)\n", (m_SYSCR1 & 0x02) ? 1 : 0); + LOG("%d: WUT-1 (warm up time at STOP release)\n", (m_SYSCR1 & 0x08) ? 1 : 0); + LOG("%d: WUT-0 (warm up time at STOP release)\n", (m_SYSCR1 & 0x04) ? 1 : 0); + LOG("%d: (invalid)\n", (m_SYSCR1 & 0x02) ? 1 : 0); LOG("%d: (invalid)\n", (m_SYSCR1 & 0x01) ? 1 : 0); } @@ -723,9 +723,9 @@ WRITE8_MEMBER(tlcs870_device::syscr2_w) LOG("%d: XTEN (Low Frequency Oscillator control)\n", (m_SYSCR2 & 0x40) ? 1 : 0); LOG("%d: SYSCK (system clock select 0 high, 1 low)\n", (m_SYSCR2 & 0x20) ? 1 : 0); LOG("%d: IDLE (IDLE mode start)\n", (m_SYSCR2 & 0x10) ? 1 : 0); // hng64 sets this in case of ram test failures - LOG("%d: (invalid)\n", (m_SYSCR2 & 0x08) ? 1 : 0); - LOG("%d: (invalid)\n", (m_SYSCR2 & 0x04) ? 1 : 0); - LOG("%d: (invalid)\n", (m_SYSCR2 & 0x02) ? 1 : 0); + LOG("%d: (invalid)\n", (m_SYSCR2 & 0x08) ? 1 : 0); + LOG("%d: (invalid)\n", (m_SYSCR2 & 0x04) ? 1 : 0); + LOG("%d: (invalid)\n", (m_SYSCR2 & 0x02) ? 1 : 0); LOG("%d: (invalid)\n", (m_SYSCR2 & 0x01) ? 1 : 0); } @@ -760,12 +760,12 @@ READ8_MEMBER(tlcs870_device::adcdr_r) return m_ADCDR; } -/* +/* ADCCR register bits es-apppp - + e = end flag (1 = done, data available in ADCDR, 0 = not requested / not finished) (r/o) s = start flag (1 = request data be processed and put in ADCDR) @@ -810,9 +810,9 @@ WRITE8_MEMBER(tlcs870_device::eintcr_w) LOG("%d: INT0EN (Interrupt 0 enable)\n", (m_EINTCR & 0x40) ? 1 : 0); LOG("%d: (invalid)\n", (m_EINTCR & 0x20) ? 1 : 0); LOG("%d: INT4ES (edge select)\n", (m_EINTCR & 0x10) ? 1 : 0); - LOG("%d: INT3ES (edge select)\n", (m_EINTCR & 0x08) ? 1 : 0); - LOG("%d: INT2ES (edge select)\n", (m_EINTCR & 0x04) ? 1 : 0); - LOG("%d: INT1ES (edge select)\n", (m_EINTCR & 0x02) ? 1 : 0); + LOG("%d: INT3ES (edge select)\n", (m_EINTCR & 0x08) ? 1 : 0); + LOG("%d: INT2ES (edge select)\n", (m_EINTCR & 0x04) ? 1 : 0); + LOG("%d: INT1ES (edge select)\n", (m_EINTCR & 0x02) ? 1 : 0); LOG("%d: (invalid)\n", (m_EINTCR & 0x01) ? 1 : 0); /* For edge select register 0 = rising edge, 1 = falling edge @@ -858,15 +858,15 @@ WRITE8_MEMBER(tlcs870_device::eir_h_w) LOG("%d: EF12 (External Interrupt 4)\n", (m_EIR & 0x1000) ? 1 : 0); LOG("%d: EF11 (External Interrupt 3)\n", (m_EIR & 0x0800) ? 1 : 0); LOG("%d: EF10 (8-bit TC4 Interrupt)\n", (m_EIR & 0x0400) ? 1 : 0); - LOG("%d: EF9 (Serial Interface 1 Interrupt)\n", (m_EIR & 0x0200) ? 1 : 0); + LOG("%d: EF9 (Serial Interface 1 Interrupt)\n", (m_EIR & 0x0200) ? 1 : 0); LOG("%d: EF8 (8-bit TC3 Interrupt)\n", (m_EIR & 0x0100) ? 1 : 0); } /* - the READ/WRITE/MODIFY operations cannot be used to clear interrupt latches + the READ/WRITE/MODIFY operations cannot be used to clear interrupt latches - also you can't set a latch by writing '1' to it, only clear a latch - by writing 0 to it + also you can't set a latch by writing '1' to it, only clear a latch + by writing 0 to it */ READ8_MEMBER(tlcs870_device::il_l_r) @@ -1028,7 +1028,7 @@ void tlcs870_device::execute_run() void tlcs870_device::device_reset() { m_pc.d = RM16(0xfffe); - + m_RBS = 0x00; m_EIR = 0x0000; m_IL = 0x0000; diff --git a/src/devices/cpu/tlcs870/tlcs870.h b/src/devices/cpu/tlcs870/tlcs870.h index 7d23d08c71e..93390d1be0c 100644 --- a/src/devices/cpu/tlcs870/tlcs870.h +++ b/src/devices/cpu/tlcs870/tlcs870.h @@ -174,7 +174,7 @@ private: uint8_t m_port_out_latch[8]; int m_read_input_port; uint8_t m_port0_cr, m_port1_cr, m_port6_cr, m_port7_cr; - + DECLARE_READ8_MEMBER(port0_r); DECLARE_READ8_MEMBER(port1_r); DECLARE_READ8_MEMBER(port2_r); @@ -279,7 +279,7 @@ private: uint16_t m_TREG1B; uint8_t m_TC1CR; uint16_t m_TREG2; - uint8_t m_TC2CR; + uint8_t m_TC2CR; uint8_t m_TREG3A; uint8_t m_TREG3B; uint8_t m_TC3CR; diff --git a/src/devices/cpu/tlcs870/tlcs870_ops.cpp b/src/devices/cpu/tlcs870/tlcs870_ops.cpp index 3a14f319ae2..f215774b5d0 100644 --- a/src/devices/cpu/tlcs870/tlcs870_ops.cpp +++ b/src/devices/cpu/tlcs870/tlcs870_ops.cpp @@ -4,7 +4,7 @@ Toshiba TLCS-870 Series MCUs - direct opcodes, no prefix + direct opcodes, no prefix *************************************************************************************************************/ @@ -158,7 +158,7 @@ void tlcs870_device::do_NOP(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - NOP 0000 0000 - - - - 1 + NOP 0000 0000 - - - - 1 */ m_cycles = 1; } @@ -167,7 +167,7 @@ void tlcs870_device::do_SWAP_A(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - SWAP A 0000 0001 1 - - - 3 + SWAP A 0000 0001 1 - - - 3 */ m_cycles = 3; @@ -178,7 +178,7 @@ void tlcs870_device::do_MUL_W_A(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - MUL W, A 0000 0010 Z Z - - 7 + MUL W, A 0000 0010 Z Z - - 7 */ m_cycles = 7; @@ -189,7 +189,7 @@ void tlcs870_device::do_DIV_WA_C(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - DIV WA, C 0000 0011 Z Z C - 7 + DIV WA, C 0000 0011 Z Z C - 7 */ m_cycles = 7; @@ -199,10 +199,10 @@ void tlcs870_device::do_DIV_WA_C(const uint8_t opbyte0) void tlcs870_device::do_RETI(const uint8_t opbyte0) { /* - Return from maskable interrupt service (how does this differ from RETN?) + Return from maskable interrupt service (how does this differ from RETN?) OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - RETI 0000 0100 * * * * 6 + RETI 0000 0100 * * * * 6 */ m_cycles = 6; @@ -218,7 +218,7 @@ void tlcs870_device::do_RET(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - RET 0000 0101 - - - - 6 + RET 0000 0101 - - - - 6 */ m_cycles = 6; @@ -230,7 +230,7 @@ void tlcs870_device::do_POP_PSW(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - POP PSW 0000 0110 * * * * 3 + POP PSW 0000 0110 * * * * 3 */ m_cycles = 3; @@ -243,7 +243,7 @@ void tlcs870_device::do_PUSH_PSW(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - POP PSW 0000 0111 - - - - 2 + POP PSW 0000 0111 - - - - 2 */ m_cycles = 2; @@ -256,7 +256,7 @@ void tlcs870_device::do_DAA_A(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - DAA A 0000 1010 C Z C H 2 + DAA A 0000 1010 C Z C H 2 */ m_cycles = 2; @@ -271,7 +271,7 @@ void tlcs870_device::do_DAS_A(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - DAS A 0000 1011 C Z C H 2 + DAS A 0000 1011 C Z C H 2 */ m_cycles = 2; @@ -286,7 +286,7 @@ void tlcs870_device::do_CLR_CF(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - CLR CF 0000 1100 1 - 0 - 1 + CLR CF 0000 1100 1 - 0 - 1 */ m_cycles = 1; @@ -298,7 +298,7 @@ void tlcs870_device::do_SET_CF(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - SET CF 0000 1101 0 - 1 - 1 + SET CF 0000 1101 0 - 1 - 1 */ m_cycles = 1; @@ -310,7 +310,7 @@ void tlcs870_device::do_CPL_CF(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - CPL CF 0000 1110 * - * - 1 + CPL CF 0000 1110 * - * - 1 */ m_cycles = 1; @@ -330,7 +330,7 @@ void tlcs870_device::do_LD_RBS_n(const uint8_t opbyte0) // register bank switchi { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - LD RBS, n 0000 1111 0000 nnnn 1 - - - 4 + LD RBS, n 0000 1111 0000 nnnn 1 - - - 4 */ m_cycles = 4; @@ -344,7 +344,7 @@ void tlcs870_device::do_INC_rr(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - INC rr 0001 00rr C Z - - 2 + INC rr 0001 00rr C Z - - 2 */ m_cycles = 2; @@ -371,7 +371,7 @@ void tlcs870_device::do_LD_rr_mn(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - LD rr,mn 0001 01rr nnnn nnnn mmmm mmmm 1 - - - 3 + LD rr,mn 0001 01rr nnnn nnnn mmmm mmmm 1 - - - 3 */ m_cycles = 3; @@ -385,7 +385,7 @@ void tlcs870_device::do_DEC_rr(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - DEC rr 0001 10rr C Z - - 2 + DEC rr 0001 10rr C Z - - 2 */ m_cycles = 2; @@ -419,7 +419,7 @@ void tlcs870_device::do_SHLC_A(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - SHLC A 0001 1100 C Z * - 1 + SHLC A 0001 1100 C Z * - 1 */ m_cycles = 1; @@ -434,7 +434,7 @@ void tlcs870_device::do_SHRC_A(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - SHRC A 0001 1101 C Z * - 1 + SHRC A 0001 1101 C Z * - 1 */ m_cycles = 1; @@ -449,7 +449,7 @@ void tlcs870_device::do_ROLC_A(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - ROLC A 0001 1110 C Z * - 1 + ROLC A 0001 1110 C Z * - 1 */ m_cycles = 1; @@ -464,7 +464,7 @@ void tlcs870_device::do_RORC_A(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - RORC A 0001 1111 C Z * - 1 + RORC A 0001 1111 C Z * - 1 */ m_cycles = 1; @@ -479,7 +479,7 @@ void tlcs870_device::do_INC_inx(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - INC (x) 0010 0000 xxxx xxxx C Z - - 5 + INC (x) 0010 0000 xxxx xxxx C Z - - 5 */ m_cycles = 5; @@ -507,7 +507,7 @@ void tlcs870_device::do_INC_inHL(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - INC (HL) 0010 0001 C Z - - 4 + INC (HL) 0010 0001 C Z - - 4 */ m_cycles = 4; @@ -534,7 +534,7 @@ void tlcs870_device::do_LD_A_inx(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - LD A, (x) 0010 0010 xxxx xxxx 1 Z - - 3 + LD A, (x) 0010 0010 xxxx xxxx 1 Z - - 3 */ m_cycles = 3; @@ -553,7 +553,7 @@ void tlcs870_device::do_LD_A_inHL(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - LD A, (HL) 0010 0011 1 Z - - 2 + LD A, (HL) 0010 0011 1 Z - - 2 */ m_cycles = 2; @@ -572,7 +572,7 @@ void tlcs870_device::do_LD_inx_iny(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - LD (x), (y) 0010 0110 yyyy yyyy xxxx xxxx 1 Z - - 5 + LD (x), (y) 0010 0110 yyyy yyyy xxxx xxxx 1 Z - - 5 */ m_cycles = 5; @@ -593,7 +593,7 @@ void tlcs870_device::do_DEC_inx(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - DEC (x) 0010 1000 xxxx xxxx C Z - - 5 + DEC (x) 0010 1000 xxxx xxxx C Z - - 5 */ m_cycles = 5; @@ -627,7 +627,7 @@ void tlcs870_device::do_DEC_inHL(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - DEC (HL) 0010 1001 C Z - - 4 + DEC (HL) 0010 1001 C Z - - 4 */ m_cycles = 4; @@ -661,7 +661,7 @@ void tlcs870_device::do_LD_inx_A(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - LD (x), A 0010 1010 xxxx xxxx 1 - - - 3 + LD (x), A 0010 1010 xxxx xxxx 1 - - - 3 */ m_cycles = 3; @@ -680,7 +680,7 @@ void tlcs870_device::do_LD_inHL_A(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - LD (HL), A 0010 1011 1 - - - 2 + LD (HL), A 0010 1011 1 - - - 2 */ m_cycles = 2; @@ -696,7 +696,7 @@ void tlcs870_device::do_LD_inx_n(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - LD (x), n 0010 1100 xxxx xxxx nnnn nnnn 1 - - - 4 + LD (x), n 0010 1100 xxxx xxxx nnnn nnnn 1 - - - 4 */ m_cycles = 4; @@ -712,7 +712,7 @@ void tlcs870_device::do_LD_inHL_n(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - LD (HL), n 0010 1101 nnnn nnnn 1 - - - 3 + LD (HL), n 0010 1101 nnnn nnnn 1 - - - 3 */ m_cycles = 3; @@ -728,7 +728,7 @@ void tlcs870_device::do_CLR_inx(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - CLR (x) 0010 1110 xxxx xxxx 1 - - - 4 + CLR (x) 0010 1110 xxxx xxxx 1 - - - 4 */ m_cycles = 4; @@ -743,7 +743,7 @@ void tlcs870_device::do_CLR_inHL(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - CLR (HL) 0010 1111 1 - - - 2 + CLR (HL) 0010 1111 1 - - - 2 */ m_cycles = 2; @@ -757,7 +757,7 @@ void tlcs870_device::do_LD_r_n(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - LD r,n 0011 0rrr nnnn nnnn 1 - - - 2 + LD r,n 0011 0rrr nnnn nnnn 1 - - - 2 */ m_cycles = 2; @@ -773,9 +773,9 @@ void tlcs870_device::do_SET_inxbit(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - SET (x).b 0100 0bbb xxxx xxxx Z * - - 5 + SET (x).b 0100 0bbb xxxx xxxx Z * - - 5 - (opbyte0 == 0x40) && (opval == 0x3a) is EI + (opbyte0 == 0x40) && (opval == 0x3a) is EI */ m_cycles = 5; @@ -807,9 +807,9 @@ void tlcs870_device::do_CLR_inxbit(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - CLR (x).b 0100 1bbb xxxx xxxx Z * - - 5 + CLR (x).b 0100 1bbb xxxx xxxx Z * - - 5 - (opbyte0 == 0x48) && (opval == 0x3a) is DI + (opbyte0 == 0x48) && (opval == 0x3a) is DI */ m_cycles = 5; @@ -841,7 +841,7 @@ void tlcs870_device::do_LD_A_r(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - LD A, r 0101 0rrr 1 Z - - 1 + LD A, r 0101 0rrr 1 Z - - 1 */ m_cycles = 1; @@ -858,7 +858,7 @@ void tlcs870_device::do_LD_r_A(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - LD r, A 0101 1rrr 1 Z - - 1 + LD r, A 0101 1rrr 1 Z - - 1 */ m_cycles = 1; @@ -875,7 +875,7 @@ void tlcs870_device::do_INC_r(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - INC r 0110 0rrr C Z - - 1 + INC r 0110 0rrr C Z - - 1 */ m_cycles = 1; @@ -901,7 +901,7 @@ void tlcs870_device::do_DEC_r(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - DEC r 0110 1rrr C Z - - 1 + DEC r 0110 1rrr C Z - - 1 */ m_cycles = 1; @@ -933,10 +933,10 @@ void tlcs870_device::do_DEC_r(const uint8_t opbyte0) void tlcs870_device::do_JRS_T_a(const uint8_t opbyte0) { /* - Jump Relative Short, if True + Jump Relative Short, if True OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - JRS T, a 100d dddd 1 - - - 4 (2 if not taken) + JRS T, a 100d dddd 1 - - - 4 (2 if not taken) */ m_cycles = 2; @@ -950,7 +950,7 @@ void tlcs870_device::do_JRS_T_a(const uint8_t opbyte0) m_cycles += 2; m_addr = m_tmppc + 2 + val; } - + // always gets set? set_JF(); } @@ -958,10 +958,10 @@ void tlcs870_device::do_JRS_T_a(const uint8_t opbyte0) void tlcs870_device::do_JRS_F_a(const uint8_t opbyte0) { /* - Jump Relative Short, if False + Jump Relative Short, if False OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - JRS F, a 101d dddd 1 - - - 4 (2 if not taken) + JRS F, a 101d dddd 1 - - - 4 (2 if not taken) */ m_cycles = 2; @@ -975,7 +975,7 @@ void tlcs870_device::do_JRS_F_a(const uint8_t opbyte0) m_cycles += 2; m_addr = m_tmppc + 2 + val; } - + // manual isn't clear in description, but probably always set? set_JF(); } @@ -983,10 +983,10 @@ void tlcs870_device::do_JRS_F_a(const uint8_t opbyte0) void tlcs870_device::do_CALLV_n(const uint8_t opbyte0) { /* - Call Vector + Call Vector OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - CALLV n 1100 nnnn - - - - 7 + CALLV n 1100 nnnn - - - - 7 */ m_cycles = 7; @@ -1002,14 +1002,14 @@ void tlcs870_device::do_JR_cc_a(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - JR T, a 1101 0110 dddd dddd 1 - - - 4 (2 if not taken) - JR F, a 1101 0111 dddd dddd 1 - - - 4 (2 if not taken) - JR EQ, a (Z, a) 1101 0000 dddd dddd 1 - - - 4 (2 if not taken) - JR NE, a (NZ, a) 1101 0001 dddd dddd 1 - - - 4 (2 if not taken) - JR CS, a (LT, a) 1101 0010 dddd dddd 1 - - - 4 (2 if not taken) - JR CC, a (GE, a) 1101 0011 dddd dddd 1 - - - 4 (2 if not taken) - JR LE, a 1101 0100 dddd dddd 1 - - - 4 (2 if not taken) - JR GT, a 1101 0101 dddd dddd 1 - - - 4 (2 if not taken) + JR T, a 1101 0110 dddd dddd 1 - - - 4 (2 if not taken) + JR F, a 1101 0111 dddd dddd 1 - - - 4 (2 if not taken) + JR EQ, a (Z, a) 1101 0000 dddd dddd 1 - - - 4 (2 if not taken) + JR NE, a (NZ, a) 1101 0001 dddd dddd 1 - - - 4 (2 if not taken) + JR CS, a (LT, a) 1101 0010 dddd dddd 1 - - - 4 (2 if not taken) + JR CC, a (GE, a) 1101 0011 dddd dddd 1 - - - 4 (2 if not taken) + JR LE, a 1101 0100 dddd dddd 1 - - - 4 (2 if not taken) + JR GT, a 1101 0101 dddd dddd 1 - - - 4 (2 if not taken) */ m_cycles = 2; @@ -1034,9 +1034,9 @@ void tlcs870_device::do_LD_CF_inxbit(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - LD CF, (x).b 1101 1bbb xxxx xxxx ~C - * - 4 + LD CF, (x).b 1101 1bbb xxxx xxxx ~C - * - 4 - aka TEST (x).b + aka TEST (x).b */ m_cycles = 4; @@ -1057,7 +1057,7 @@ void tlcs870_device::do_LD_SP_mn(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - LD SP ,mn 1111 1010 nnnn nnnn mmmm mmmm 1 - - - 3 + LD SP ,mn 1111 1010 nnnn nnnn mmmm mmmm 1 - - - 3 */ m_cycles = 3; @@ -1070,7 +1070,7 @@ void tlcs870_device::do_JR_a(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - JR a 1111 1011 dddd dddd 1 - - - 4 + JR a 1111 1011 dddd dddd 1 - - - 4 */ m_cycles = 4; @@ -1086,7 +1086,7 @@ void tlcs870_device::do_CALL_mn(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - CALL mn 1111 1100 nnnn nnnn mmmm mmmm - - - - 6 + CALL mn 1111 1100 nnnn nnnn mmmm mmmm - - - - 6 */ m_cycles = 6; @@ -1102,7 +1102,7 @@ void tlcs870_device::do_CALLP_n(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - CALLP n 1111 1101 nnnn nnnn - - - - 6 + CALLP n 1111 1101 nnnn nnnn - - - - 6 */ m_cycles = 6; @@ -1118,7 +1118,7 @@ void tlcs870_device::do_JP_mn(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - JP mn 1111 1110 nnnn nnnn mmmm mmmm 1 - - - 4 + JP mn 1111 1110 nnnn nnnn mmmm mmmm 1 - - - 4 */ m_cycles = 4; @@ -1130,8 +1130,8 @@ void tlcs870_device::do_JP_mn(const uint8_t opbyte0) void tlcs870_device::do_ff_opcode(const uint8_t opbyte0) { /* - OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - SWI 1111 1111 - - - - 9 (1 if already in NMI) + OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles + SWI 1111 1111 - - - - 9 (1 if already in NMI) */ m_cycles = 9; // TODO: 1 if in NMI this acts as a NOP @@ -1147,14 +1147,14 @@ void tlcs870_device::do_ALUOP_A_n(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - ADDC A, n 0111 0000 nnnn nnnn C Z C H 2 - ADD A, n 0111 0001 nnnn nnnn C Z C H 2 - SUBB A, n 0111 0010 nnnn nnnn C Z C H 2 - SUB A, n 0111 0011 nnnn nnnn C Z C H 2 - AND A, n 0111 0100 nnnn nnnn Z Z - - 2 - XOR A, n 0111 0101 nnnn nnnn Z Z - - 2 - OR A, n 0111 0110 nnnn nnnn Z Z - - 2 - CMP A, n 0111 0111 nnnn nnnn Z Z C H 2 + ADDC A, n 0111 0000 nnnn nnnn C Z C H 2 + ADD A, n 0111 0001 nnnn nnnn C Z C H 2 + SUBB A, n 0111 0010 nnnn nnnn C Z C H 2 + SUB A, n 0111 0011 nnnn nnnn C Z C H 2 + AND A, n 0111 0100 nnnn nnnn Z Z - - 2 + XOR A, n 0111 0101 nnnn nnnn Z Z - - 2 + OR A, n 0111 0110 nnnn nnnn Z Z - - 2 + CMP A, n 0111 0111 nnnn nnnn Z Z C H 2 */ m_cycles = 2; @@ -1173,14 +1173,14 @@ void tlcs870_device::do_ALUOP_A_inx(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - ADDC A, (x) 0111 1000 xxxx xxxx C Z C H 4 - ADD A, (x) 0111 1001 xxxx xxxx C Z C H 4 - SUBB A, (x) 0111 1010 xxxx xxxx C Z C H 4 - SUB A, (x) 0111 1011 xxxx xxxx C Z C H 4 - AND A, (x) 0111 1100 xxxx xxxx Z Z - - 4 - XOR A, (x) 0111 1101 xxxx xxxx Z Z - - 4 - OR A, (x) 0111 1110 xxxx xxxx Z Z - - 4 - CMP A, (x) 0111 1111 xxxx xxxx Z Z C H 4 + ADDC A, (x) 0111 1000 xxxx xxxx C Z C H 4 + ADD A, (x) 0111 1001 xxxx xxxx C Z C H 4 + SUBB A, (x) 0111 1010 xxxx xxxx C Z C H 4 + SUB A, (x) 0111 1011 xxxx xxxx C Z C H 4 + AND A, (x) 0111 1100 xxxx xxxx Z Z - - 4 + XOR A, (x) 0111 1101 xxxx xxxx Z Z - - 4 + OR A, (x) 0111 1110 xxxx xxxx Z Z - - 4 + CMP A, (x) 0111 1111 xxxx xxxx Z Z C H 4 */ m_cycles = 4; @@ -1204,7 +1204,7 @@ void tlcs870_device::do_LDW_inx_mn(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - LDW (x), mn 0010 0100 xxxx xxxx nnnn nnnn mmmm mmmm 1 - - - 6 + LDW (x), mn 0010 0100 xxxx xxxx nnnn nnnn mmmm mmmm 1 - - - 6 */ m_cycles = 6; @@ -1221,7 +1221,7 @@ void tlcs870_device::do_LDW_inHL_mn(const uint8_t opbyte0) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - LDW (HL), mn 0010 0101 nnnn nnnn mmmm mmmm 1 - - - 5 + LDW (HL), mn 0010 0101 nnnn nnnn mmmm mmmm 1 - - - 5 */ m_cycles = 5; diff --git a/src/devices/cpu/tlcs870/tlcs870_ops_dst.cpp b/src/devices/cpu/tlcs870/tlcs870_ops_dst.cpp index 3f5a77d0217..058368d5a5d 100644 --- a/src/devices/cpu/tlcs870/tlcs870_ops_dst.cpp +++ b/src/devices/cpu/tlcs870/tlcs870_ops_dst.cpp @@ -6,19 +6,19 @@ (dst) prefix ops (f0 to f7 subtable) - (dst) address depends on the first byte of the opcode + (dst) address depends on the first byte of the opcode - F0 (x) - F1 invalid (would be (PC+A) based on the src table, check for undefined behavior?) - F2 (DE) - F3 (HL) - F4 (HL+d) - F5 invalid (would be (HL+C) based on the src table, check for undefined behavior?) - F6 (HL+) - F7 (-HL) + F0 (x) + F1 invalid (would be (PC+A) based on the src table, check for undefined behavior?) + F2 (DE) + F3 (HL) + F4 (HL+d) + F5 invalid (would be (HL+C) based on the src table, check for undefined behavior?) + F6 (HL+) + F7 (-HL) - note, in cases where the address is an immediate value, not a register (x) and (HL+d) the - immediate value is directly after the first byte of the opcode + note, in cases where the address is an immediate value, not a register (x) and (HL+d) the + immediate value is directly after the first byte of the opcode *************************************************************************************************************/ @@ -83,17 +83,17 @@ void tlcs870_device::do_LD_indst_rr(const uint8_t opbyte0, const uint8_t opbyte1 { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - LD (x), rr 1111 0000 xxxx xxxx 0001 00rr 1 - - - 5 - LD (PC+A), rr invalid encoding (all PC+A are invalid for dst) ? ? ? ? ? - LD (DE), rr 1111 0010 0001 00rr 1 - - - 4 - LD (HL), rr 1111 0011 0001 00rr 1 - - - 4 - LD (HL+d), rr 1111 0100 dddd dddd 0001 00rr 1 - - - 6 - LD (HL+C), rr invalid encoding (all HL+C are invalid for dst) ? ? ? ? ? - LD (HL+), rr not listed, invalid due to 16-bit op? ? ? ? ? ? - LD (-HL), rr not listed, invalid due to 16-bit op? ? ? ? ? ? - - aka LD (dst),rr - (dst) can only be (x) (pp) or (HL+d) ? not (HL+) or (-HL) ? + LD (x), rr 1111 0000 xxxx xxxx 0001 00rr 1 - - - 5 + LD (PC+A), rr invalid encoding (all PC+A are invalid for dst) ? ? ? ? ? + LD (DE), rr 1111 0010 0001 00rr 1 - - - 4 + LD (HL), rr 1111 0011 0001 00rr 1 - - - 4 + LD (HL+d), rr 1111 0100 dddd dddd 0001 00rr 1 - - - 6 + LD (HL+C), rr invalid encoding (all HL+C are invalid for dst) ? ? ? ? ? + LD (HL+), rr not listed, invalid due to 16-bit op? ? ? ? ? ? + LD (-HL), rr not listed, invalid due to 16-bit op? ? ? ? ? ? + + aka LD (dst),rr + (dst) can only be (x) (pp) or (HL+d) ? not (HL+) or (-HL) ? */ m_cycles += 4; @@ -111,17 +111,17 @@ void tlcs870_device::do_LD_indst_n(const uint8_t opbyte0, const uint8_t opbyte1, { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - LD (x), n not listed, redundant encoding? ? ? ? ? ? - LD (PC+A), n invalid encoding (all PC+A are invalid for dst) ? ? ? ? ? - LD (DE), n 1111 0010 0010 1100 nnnn nnnn 1 - - - 4 - LD (HL), n not listed, redundant encoding? ? ? ? ? ? - LD (HL+d), n 1111 0100 dddd dddd 0010 1100 nnnn nnnn 1 - - - 6 - LD (HL+C), n invalid encoding (all HL+C are invalid for dst) ? ? ? ? ? - LD (HL+), n 1111 0110 0010 1100 nnnn nnnn 1 - - - 5 - LD (-HL), n 1111 0111 0010 1100 nnnn nnnn 1 - - - 5 - - aka (dst),n - (dst) can only be (DE), (HL+), (-HL), or (HL+d) because (x) and (HL) are redundant encodings? + LD (x), n not listed, redundant encoding? ? ? ? ? ? + LD (PC+A), n invalid encoding (all PC+A are invalid for dst) ? ? ? ? ? + LD (DE), n 1111 0010 0010 1100 nnnn nnnn 1 - - - 4 + LD (HL), n not listed, redundant encoding? ? ? ? ? ? + LD (HL+d), n 1111 0100 dddd dddd 0010 1100 nnnn nnnn 1 - - - 6 + LD (HL+C), n invalid encoding (all HL+C are invalid for dst) ? ? ? ? ? + LD (HL+), n 1111 0110 0010 1100 nnnn nnnn 1 - - - 5 + LD (-HL), n 1111 0111 0010 1100 nnnn nnnn 1 - - - 5 + + aka (dst),n + (dst) can only be (DE), (HL+), (-HL), or (HL+d) because (x) and (HL) are redundant encodings? */ m_cycles += 4; @@ -135,16 +135,16 @@ void tlcs870_device::do_LD_indst_r(const uint8_t opbyte0, const uint8_t opbyte1, { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - LD (x), r 1111 0000 xxxx xxxx 0101 1rrr 1 - - - 4 - LD (PC+A), r invalid encoding (all PC+A are invalid for dst) ? ? ? ? ? - LD (DE), r 1111 0010 0101 1rrr 1 - - - 3 - LD (HL), r 1111 0011 0101 1rrr 1 - - - 3 - LD (HL+d), r 1111 0100 dddd dddd 0101 1rrr 1 - - - 5 - LD (HL+C), r invalid encoding (all HL+C are invalid for dst) ? ? ? ? ? - LD (HL+), r 1111 0110 0101 0rrr 1 - - - 4 (invalid if r is H or L) - LD (-HL), r 1111 0111 0101 0rrr 1 - - - 4 - - aka LD (dst),r + LD (x), r 1111 0000 xxxx xxxx 0101 1rrr 1 - - - 4 + LD (PC+A), r invalid encoding (all PC+A are invalid for dst) ? ? ? ? ? + LD (DE), r 1111 0010 0101 1rrr 1 - - - 3 + LD (HL), r 1111 0011 0101 1rrr 1 - - - 3 + LD (HL+d), r 1111 0100 dddd dddd 0101 1rrr 1 - - - 5 + LD (HL+C), r invalid encoding (all HL+C are invalid for dst) ? ? ? ? ? + LD (HL+), r 1111 0110 0101 0rrr 1 - - - 4 (invalid if r is H or L) + LD (-HL), r 1111 0111 0101 0rrr 1 - - - 4 + + aka LD (dst),r */ m_cycles += 3; diff --git a/src/devices/cpu/tlcs870/tlcs870_ops_helper.cpp b/src/devices/cpu/tlcs870/tlcs870_ops_helper.cpp index c2fb2fb90cb..d0e6f9de3ef 100644 --- a/src/devices/cpu/tlcs870/tlcs870_ops_helper.cpp +++ b/src/devices/cpu/tlcs870/tlcs870_ops_helper.cpp @@ -216,35 +216,35 @@ const bool tlcs870_device::check_jump_condition(int param1) return takejump; } -/* - All 16-bit ALU ops that would set the 'H' flag list the behavior as undefined. - Logically the half flag would be the 8/9 bit carry (usual C flag) in a 16-bit - op, but since this isn't listed as being the case there's a chance the behavior - is something unexpected, such as still using the 3/4 carry, or, if it's - internally handled as 4 4-bit operations, maybe the 12/13 bit carry - - This needs testing on hardware. - - (8-bit) JF ZF CF HF - ADDC C Z C H - ADD C Z C H - SUBB C Z C H - SUB C Z C H - AND Z Z - - - XOR Z Z - - - OR Z Z - - - CMP Z Z C H - - (16-bit) - ADDC C Z C U - ADD C Z C U - SUBB C Z C U - SUB C Z C U - AND Z Z - - - XOR Z Z - - - OR Z Z - - - CMP Z Z C U - +/* + All 16-bit ALU ops that would set the 'H' flag list the behavior as undefined. + Logically the half flag would be the 8/9 bit carry (usual C flag) in a 16-bit + op, but since this isn't listed as being the case there's a chance the behavior + is something unexpected, such as still using the 3/4 carry, or, if it's + internally handled as 4 4-bit operations, maybe the 12/13 bit carry + + This needs testing on hardware. + + (8-bit) JF ZF CF HF + ADDC C Z C H + ADD C Z C H + SUBB C Z C H + SUB C Z C H + AND Z Z - - + XOR Z Z - - + OR Z Z - - + CMP Z Z C H + + (16-bit) + ADDC C Z C U + ADD C Z C U + SUBB C Z C U + SUB C Z C U + AND Z Z - - + XOR Z Z - - + OR Z Z - - + CMP Z Z C U + */ uint8_t tlcs870_device::do_add_8bit(uint16_t param1, uint16_t param2) diff --git a/src/devices/cpu/tlcs870/tlcs870_ops_reg.cpp b/src/devices/cpu/tlcs870/tlcs870_ops_reg.cpp index 9a5177d5831..74cbd7d071a 100644 --- a/src/devices/cpu/tlcs870/tlcs870_ops_reg.cpp +++ b/src/devices/cpu/tlcs870/tlcs870_ops_reg.cpp @@ -6,31 +6,31 @@ (reg) prefix ops (e8 to ef subtable) - (reg) implies one of the follow registers + (reg) implies one of the follow registers (8-bit mode operations) - E8 A - E9 W - EA C - EB B - EC E - ED D - EE L - EF H - - (16-bit mode operations) + E8 A + E9 W + EA C + EB B + EC E + ED D + EE L + EF H + + (16-bit mode operations) E8 WA - E9 BC - EA DE - EB HL - EC WA - ED BC - EE DE - EF HL - - (RETN operation - special) - E8 RETN - E9-EF invalid + E9 BC + EA DE + EB HL + EC WA + ED BC + EE DE + EF HL + + (RETN operation - special) + E8 RETN + E9-EF invalid *************************************************************************************************************/ @@ -145,9 +145,9 @@ void tlcs870_device::do_RETN(const uint8_t opbyte0, const uint8_t opbyte1) if (opbyte0 == 0xe8) { /* - Return from non-maskable interrupt service (how does this differ from RETI?) - OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - RETN 1110 1000 0000 0100 * * * * 7 + Return from non-maskable interrupt service (how does this differ from RETI?) + OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles + RETN 1110 1000 0000 0100 * * * * 7 */ m_cycles = 7; @@ -169,7 +169,7 @@ void tlcs870_device::do_SWAP_g(const uint8_t opbyte0, const uint8_t opbyte1) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - SWAP g 1110 1ggg 0000 0001 1 - - - 4 + SWAP g 1110 1ggg 0000 0001 1 - - - 4 */ m_cycles = 4; @@ -181,7 +181,7 @@ void tlcs870_device::do_DAA_g(const uint8_t opbyte0, const uint8_t opbyte1) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - DAS g 1110 1ggg 0000 1010 C Z C H 3 + DAS g 1110 1ggg 0000 1010 C Z C H 3 */ m_cycles = 3; @@ -197,7 +197,7 @@ void tlcs870_device::do_DAS_g(const uint8_t opbyte0, const uint8_t opbyte1) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - DAS g 1110 1ggg 0000 1011 C Z C H 3 + DAS g 1110 1ggg 0000 1011 C Z C H 3 */ m_cycles = 3; @@ -212,9 +212,9 @@ void tlcs870_device::do_DAS_g(const uint8_t opbyte0, const uint8_t opbyte1) void tlcs870_device::do_SHLC_g(const uint8_t opbyte0, const uint8_t opbyte1) { /* - Logical Shift Left with Carry Flag + Logical Shift Left with Carry Flag OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - SHLC g 1110 1ggg 0001 1100 C Z * - 2 + SHLC g 1110 1ggg 0001 1100 C Z * - 2 */ m_cycles = 2; @@ -228,9 +228,9 @@ void tlcs870_device::do_SHLC_g(const uint8_t opbyte0, const uint8_t opbyte1) void tlcs870_device::do_SHRC_g(const uint8_t opbyte0, const uint8_t opbyte1) { /* - Logical Shift Right with Carry Flag + Logical Shift Right with Carry Flag OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - SHRC g 1110 1ggg 0001 1101 C Z * - 2 + SHRC g 1110 1ggg 0001 1101 C Z * - 2 */ m_cycles = 2; @@ -244,9 +244,9 @@ void tlcs870_device::do_SHRC_g(const uint8_t opbyte0, const uint8_t opbyte1) void tlcs870_device::do_ROLC_g(const uint8_t opbyte0, const uint8_t opbyte1) { /* - Rotate Left through Carry flag + Rotate Left through Carry flag OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - ROLC g 1110 1ggg 0001 1110 C Z * - 2 + ROLC g 1110 1ggg 0001 1110 C Z * - 2 */ m_cycles = 2; @@ -261,9 +261,9 @@ void tlcs870_device::do_ROLC_g(const uint8_t opbyte0, const uint8_t opbyte1) void tlcs870_device::do_RORC_g(const uint8_t opbyte0, const uint8_t opbyte1) { /* - Rotate Right through Carry flag + Rotate Right through Carry flag OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - RORC g 1110 1ggg 0001 1111 C Z * - 2 + RORC g 1110 1ggg 0001 1111 C Z * - 2 */ m_cycles = 2; @@ -279,7 +279,7 @@ void tlcs870_device::do_LD_r_g(const uint8_t opbyte0, const uint8_t opbyte1) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - LD r, g 1110 1ggg 0101 1rrr 1 Z - - 2 + LD r, g 1110 1ggg 0101 1rrr 1 Z - - 2 */ m_cycles = 2; @@ -296,7 +296,7 @@ void tlcs870_device::do_XCH_r_g(const uint8_t opbyte0, const uint8_t opbyte1) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - XCG r, g 1110 1ggg 1010 1rrr 1 Z - - 3 + XCG r, g 1110 1ggg 1010 1rrr 1 Z - - 3 */ m_cycles = 3; @@ -320,14 +320,14 @@ void tlcs870_device::do_ALUOP_A_g(const uint8_t opbyte0, const uint8_t opbyte1) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - ADDC A, g 1110 1ggg 0110 0000 C Z C H 2 - ADD A, g 1110 1ggg 0110 0001 C Z C H 2 - SUBB A, g 1110 1ggg 0110 0010 C Z C H 2 - SUB A, g 1110 1ggg 0110 0011 C Z C H 2 - AND A, g 1110 1ggg 0110 0100 Z Z - - 2 - XOR A, g 1110 1ggg 0110 0101 Z Z - - 2 - OR A, g 1110 1ggg 0110 0110 Z Z - - 2 - CMP A, g 1110 1ggg 0110 0111 Z Z C H 2 + ADDC A, g 1110 1ggg 0110 0000 C Z C H 2 + ADD A, g 1110 1ggg 0110 0001 C Z C H 2 + SUBB A, g 1110 1ggg 0110 0010 C Z C H 2 + SUB A, g 1110 1ggg 0110 0011 C Z C H 2 + AND A, g 1110 1ggg 0110 0100 Z Z - - 2 + XOR A, g 1110 1ggg 0110 0101 Z Z - - 2 + OR A, g 1110 1ggg 0110 0110 Z Z - - 2 + CMP A, g 1110 1ggg 0110 0111 Z Z C H 2 */ m_cycles = 2; @@ -345,14 +345,14 @@ void tlcs870_device::do_ALUOP_g_A(const uint8_t opbyte0, const uint8_t opbyte1) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - ADDC g, A 1110 1ggg 0110 1000 C Z C H 3 - ADD g, A 1110 1ggg 0110 1001 C Z C H 3 - SUBB g, A 1110 1ggg 0110 1010 C Z C H 3 - SUB g, A 1110 1ggg 0110 1011 C Z C H 3 - AND g, A 1110 1ggg 0110 1100 Z Z - - 3 - XOR g, A 1110 1ggg 0110 1101 Z Z - - 3 - OR g, A 1110 1ggg 0110 1110 Z Z - - 3 - CMP g, A 1110 1ggg 0110 1111 Z Z C H 3 + ADDC g, A 1110 1ggg 0110 1000 C Z C H 3 + ADD g, A 1110 1ggg 0110 1001 C Z C H 3 + SUBB g, A 1110 1ggg 0110 1010 C Z C H 3 + SUB g, A 1110 1ggg 0110 1011 C Z C H 3 + AND g, A 1110 1ggg 0110 1100 Z Z - - 3 + XOR g, A 1110 1ggg 0110 1101 Z Z - - 3 + OR g, A 1110 1ggg 0110 1110 Z Z - - 3 + CMP g, A 1110 1ggg 0110 1111 Z Z C H 3 */ m_cycles = 3; @@ -369,14 +369,14 @@ void tlcs870_device::do_ALUOP_g_n(const uint8_t opbyte0, const uint8_t opbyte1) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - ADDC g, n 1110 1ggg 0111 0000 nnnn nnnn C Z C H 3 - ADD g, n 1110 1ggg 0111 0001 nnnn nnnn C Z C H 3 - SUBB g, n 1110 1ggg 0111 0010 nnnn nnnn C Z C H 3 - SUB g, n 1110 1ggg 0111 0011 nnnn nnnn C Z C H 3 - AND g, n 1110 1ggg 0111 0100 nnnn nnnn Z Z - - 3 - XOR g, n 1110 1ggg 0111 0101 nnnn nnnn Z Z - - 3 - OR g, n 1110 1ggg 0111 0110 nnnn nnnn Z Z - - 3 - CMP g, n 1110 1ggg 0111 0111 nnnn nnnn Z Z C H 3 + ADDC g, n 1110 1ggg 0111 0000 nnnn nnnn C Z C H 3 + ADD g, n 1110 1ggg 0111 0001 nnnn nnnn C Z C H 3 + SUBB g, n 1110 1ggg 0111 0010 nnnn nnnn C Z C H 3 + SUB g, n 1110 1ggg 0111 0011 nnnn nnnn C Z C H 3 + AND g, n 1110 1ggg 0111 0100 nnnn nnnn Z Z - - 3 + XOR g, n 1110 1ggg 0111 0101 nnnn nnnn Z Z - - 3 + OR g, n 1110 1ggg 0111 0110 nnnn nnnn Z Z - - 3 + CMP g, n 1110 1ggg 0111 0111 nnnn nnnn Z Z C H 3 */ m_cycles = 3; @@ -400,14 +400,14 @@ void tlcs870_device::do_ALUOP_WA_gg(const uint8_t opbyte0, const uint8_t opbyte1 { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - ADDC WA, gg 1110 10gg 0011 0000 C Z C U 4 - ADD WA, gg 1110 10gg 0011 0001 C Z C U 4 - SUBB WA, gg 1110 10gg 0011 0010 C Z C U 4 - SUB WA, gg 1110 10gg 0011 0011 C Z C U 4 - AND WA, gg 1110 10gg 0011 0100 Z Z - - 4 - XOR WA, gg 1110 10gg 0011 0101 Z Z - - 4 - OR WA, gg 1110 10gg 0011 0110 Z Z - - 4 - CMP WA, gg 1110 10gg 0011 0111 Z Z C U 4 + ADDC WA, gg 1110 10gg 0011 0000 C Z C U 4 + ADD WA, gg 1110 10gg 0011 0001 C Z C U 4 + SUBB WA, gg 1110 10gg 0011 0010 C Z C U 4 + SUB WA, gg 1110 10gg 0011 0011 C Z C U 4 + AND WA, gg 1110 10gg 0011 0100 Z Z - - 4 + XOR WA, gg 1110 10gg 0011 0101 Z Z - - 4 + OR WA, gg 1110 10gg 0011 0110 Z Z - - 4 + CMP WA, gg 1110 10gg 0011 0111 Z Z C U 4 */ m_cycles = 4; @@ -426,14 +426,14 @@ void tlcs870_device::do_ALUOP_gg_mn(const uint8_t opbyte0, const uint8_t opbyte1 { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - ADDC gg, mn 1110 10gg 0011 1000 nnnn nnnn mmmm mmmm C Z C U 4 - ADD gg, mn 1110 10gg 0011 1001 nnnn nnnn mmmm mmmm C Z C U 4 - SUBB gg, mn 1110 10gg 0011 1010 nnnn nnnn mmmm mmmm C Z C U 4 - SUB gg, mn 1110 10gg 0011 1011 nnnn nnnn mmmm mmmm C Z C U 4 - AND gg, mn 1110 10gg 0011 1100 nnnn nnnn mmmm mmmm Z Z - - 4 - XOR gg, mn 1110 10gg 0011 1101 nnnn nnnn mmmm mmmm Z Z - - 4 - OR gg, mn 1110 10gg 0011 1110 nnnn nnnn mmmm mmmm Z Z - - 4 - CMP gg, mn 1110 10gg 0011 1111 nnnn nnnn mmmm mmmm Z Z C U 4 + ADDC gg, mn 1110 10gg 0011 1000 nnnn nnnn mmmm mmmm C Z C U 4 + ADD gg, mn 1110 10gg 0011 1001 nnnn nnnn mmmm mmmm C Z C U 4 + SUBB gg, mn 1110 10gg 0011 1010 nnnn nnnn mmmm mmmm C Z C U 4 + SUB gg, mn 1110 10gg 0011 1011 nnnn nnnn mmmm mmmm C Z C U 4 + AND gg, mn 1110 10gg 0011 1100 nnnn nnnn mmmm mmmm Z Z - - 4 + XOR gg, mn 1110 10gg 0011 1101 nnnn nnnn mmmm mmmm Z Z - - 4 + OR gg, mn 1110 10gg 0011 1110 nnnn nnnn mmmm mmmm Z Z - - 4 + CMP gg, mn 1110 10gg 0011 1111 nnnn nnnn mmmm mmmm Z Z C U 4 */ m_cycles = 4; @@ -459,8 +459,8 @@ void tlcs870_device::do_SET_inppbit(const uint8_t opbyte0, const uint8_t opbyte1 { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - SET (DE).g 1110 1ggg 1000 0010 Z * - - 5 - SET (HL).g 1110 1ggg 1000 0011 Z * - - 5 + SET (DE).g 1110 1ggg 1000 0010 Z * - - 5 + SET (HL).g 1110 1ggg 1000 0011 Z * - - 5 */ m_cycles = 5; @@ -489,8 +489,8 @@ void tlcs870_device::do_CLR_inppbit(const uint8_t opbyte0, const uint8_t opbyte1 { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - CLR (DE).g 1110 1ggg 1000 1010 Z * - - 5 - CLR (HL).g 1110 1ggg 1000 1011 Z * - - 5 + CLR (DE).g 1110 1ggg 1000 1010 Z * - - 5 + CLR (HL).g 1110 1ggg 1000 1011 Z * - - 5 */ m_cycles = 5; @@ -520,8 +520,8 @@ void tlcs870_device::do_CPL_inpp_indirectbit(const uint8_t opbyte0, const uint8_ { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - CPL (DE).g 1110 1ggg 1001 0010 Z * - - 5 - CPL (HL).g 1110 1ggg 1001 0011 Z * - - 5 + CPL (DE).g 1110 1ggg 1001 0010 Z * - - 5 + CPL (HL).g 1110 1ggg 1001 0011 Z * - - 5 */ m_cycles = 5; @@ -555,8 +555,8 @@ void tlcs870_device::do_LD_inpp_indirectbit_CF(const uint8_t opbyte0, const uint { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - LD (DE).g, CF 1110 1ggg 1001 1010 1 - - - 5 - LD (HL).g, CF 1110 1ggg 1001 1011 1 - - - 5 + LD (DE).g, CF 1110 1ggg 1001 1010 1 - - - 5 + LD (HL).g, CF 1110 1ggg 1001 1011 1 - - - 5 */ m_cycles = 5; @@ -585,10 +585,10 @@ void tlcs870_device::do_LD_CF_inpp_indirectbit(const uint8_t opbyte0, const uint { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - LD CF, (DE).g 1110 1ggg 1001 1110 ~C - * - 4 - LD CF, (HL).g 1110 1ggg 1001 1111 ~C - * - 4 + LD CF, (DE).g 1110 1ggg 1001 1110 ~C - * - 4 + LD CF, (HL).g 1110 1ggg 1001 1111 ~C - * - 4 - aka aka TEST (pp).g + aka aka TEST (pp).g */ m_cycles = 4; @@ -610,7 +610,7 @@ void tlcs870_device::do_SET_gbit(const uint8_t opbyte0, const uint8_t opbyte1) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - SET g.b 1110 1ggg 0100 0bbb Z * - - 3 + SET g.b 1110 1ggg 0100 0bbb Z * - - 3 */ m_cycles = 3; @@ -639,7 +639,7 @@ void tlcs870_device::do_CLR_gbit(const uint8_t opbyte0, const uint8_t opbyte1) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - CLR g.b 1110 1ggg 0100 1bbb Z * - - 3 + CLR g.b 1110 1ggg 0100 1bbb Z * - - 3 */ m_cycles = 3; @@ -668,7 +668,7 @@ void tlcs870_device::do_CPL_gbit(const uint8_t opbyte0, const uint8_t opbyte1) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - CPL g.b 1110 1ggg 1100 0bbb Z * - - 3 + CPL g.b 1110 1ggg 1100 0bbb Z * - - 3 */ m_cycles = 3; @@ -701,7 +701,7 @@ void tlcs870_device::do_LD_gbit_CF(const uint8_t opbyte0, const uint8_t opbyte1) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - LD g.b, CF 1110 1ggg 1100 1bbb 1 - - - 2 + LD g.b, CF 1110 1ggg 1100 1bbb 1 - - - 2 */ m_cycles = 2; @@ -730,7 +730,7 @@ void tlcs870_device::do_XOR_CF_gbit(const uint8_t opbyte0, const uint8_t opbyte1 { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - XOR CF, g.b 1110 1ggg 1101 0bbb ~C - * - 2 + XOR CF, g.b 1110 1ggg 1101 0bbb ~C - * - 2 */ m_cycles = 2; @@ -776,9 +776,9 @@ void tlcs870_device::do_LD_CF_gbit(const uint8_t opbyte0, const uint8_t opbyte1) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - LD CF, g.b 1110 1ggg 1101 1bbb ~C - * - 2 + LD CF, g.b 1110 1ggg 1101 1bbb ~C - * - 2 - aka TEST g.b + aka TEST g.b */ m_cycles = 2; @@ -802,12 +802,12 @@ void tlcs870_device::do_MUL_gg(const uint8_t opbyte0, const uint8_t opbyte1) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - MUL W, A not listed (redundant encoding?) ? ? ? ? ? - MUL B, C 1110 1010 0000 0010 Z Z - - 8 - MUL D, E 1110 1010 0000 0010 Z Z - - 8 - MUL H, L 1110 1011 0000 0010 Z Z - - 8 + MUL W, A not listed (redundant encoding?) ? ? ? ? ? + MUL B, C 1110 1010 0000 0010 Z Z - - 8 + MUL D, E 1110 1010 0000 0010 Z Z - - 8 + MUL H, L 1110 1011 0000 0010 Z Z - - 8 - aka MUL ggH, ggL (odd syntax, basically MUL gg) + aka MUL ggH, ggL (odd syntax, basically MUL gg) */ m_cycles = 8; @@ -819,10 +819,10 @@ void tlcs870_device::do_DIV_gg_C(const uint8_t opbyte0, const uint8_t opbyte1) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - DIV WA, C not listed (redundant encoding?) ? ? ? ? ? - DIV BC, C not listed (illegal?) ? ? ? ? ? - DIV DE, C 1110 1010 0000 0011 Z Z C - 8 - DIV HL, C 1110 1011 0000 0011 Z Z C - 8 + DIV WA, C not listed (redundant encoding?) ? ? ? ? ? + DIV BC, C not listed (illegal?) ? ? ? ? ? + DIV DE, C 1110 1010 0000 0011 Z Z C - 8 + DIV HL, C 1110 1011 0000 0011 Z Z C - 8 */ m_cycles = 8; @@ -834,7 +834,7 @@ void tlcs870_device::do_POP_gg(const uint8_t opbyte0, const uint8_t opbyte1) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - POP gg 1110 10gg 0000 0110 - - - - 5 + POP gg 1110 10gg 0000 0110 - - - - 5 */ m_cycles = 5; @@ -848,7 +848,7 @@ void tlcs870_device::do_PUSH_gg(const uint8_t opbyte0, const uint8_t opbyte1) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - PUSH gg 1110 10gg 0000 0111 - - - - 4 + PUSH gg 1110 10gg 0000 0111 - - - - 4 */ m_cycles = 4; @@ -863,7 +863,7 @@ void tlcs870_device::do_LD_SP_gg(const uint8_t opbyte0, const uint8_t opbyte1) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - LD SP, gg 1110 10gg 1111 1010 1 - - - 3 + LD SP, gg 1110 10gg 1111 1010 1 - - - 3 */ m_cycles = 3; @@ -875,7 +875,7 @@ void tlcs870_device::do_LD_gg_SP(const uint8_t opbyte0, const uint8_t opbyte1) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - LD gg, SP 1110 10gg 1111 1011 1 - - - 3 + LD gg, SP 1110 10gg 1111 1011 1 - - - 3 */ m_cycles = 3; @@ -887,7 +887,7 @@ void tlcs870_device::do_LD_rr_gg(const uint8_t opbyte0, const uint8_t opbyte1) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - LD rr, gg 1110 10gg 0001 00rr 1 - - - 2 + LD rr, gg 1110 10gg 0001 00rr 1 - - - 2 */ m_cycles = 2; @@ -902,7 +902,7 @@ void tlcs870_device::do_XCH_rr_gg(const uint8_t opbyte0, const uint8_t opbyte1) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - XCH rr, gg 1110 10gg 0001 01rr 1 - - - 3 + XCH rr, gg 1110 10gg 0001 01rr 1 - - - 3 */ m_cycles = 3; @@ -920,7 +920,7 @@ void tlcs870_device::do_CALL_gg(const uint8_t opbyte0, const uint8_t opbyte1) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - CALL gg 1110 10gg 1111 1100 - - - - 6 + CALL gg 1110 10gg 1111 1100 - - - - 6 */ m_cycles = 6; @@ -938,7 +938,7 @@ void tlcs870_device::do_JP_gg(const uint8_t opbyte0, const uint8_t opbyte1) { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - JP gg 1110 10gg 1111 1110 1 - - - 3 + JP gg 1110 10gg 1111 1110 1 - - - 3 */ m_cycles = 3; diff --git a/src/devices/cpu/tlcs870/tlcs870_ops_src.cpp b/src/devices/cpu/tlcs870/tlcs870_ops_src.cpp index 6295d9c06b3..3f4103f7b4a 100644 --- a/src/devices/cpu/tlcs870/tlcs870_ops_src.cpp +++ b/src/devices/cpu/tlcs870/tlcs870_ops_src.cpp @@ -6,19 +6,19 @@ (src) prefix ops (e0 to e7 subtable) - (src) address depends on the first byte of the opcode + (src) address depends on the first byte of the opcode - E0 (x) - E1 (PC+A) - E2 (DE) - E3 (HL) - E4 (HL+d) - E5 (HL+C) - E6 (HL+) - E7 (-HL) + E0 (x) + E1 (PC+A) + E2 (DE) + E3 (HL) + E4 (HL+d) + E5 (HL+C) + E6 (HL+) + E7 (-HL) - note, in cases where the address is an immediate value, not a register (x) and (HL+d) the - immediate value is directly after the first byte of the opcode + note, in cases where the address is an immediate value, not a register (x) and (HL+d) the + immediate value is directly after the first byte of the opcode *************************************************************************************************************/ @@ -109,16 +109,16 @@ void tlcs870_device::do_LD_rr_insrc(const uint8_t opbyte0, const uint8_t opbyte1 { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - LD rr, (x) 1110 0000 xxxx xxxx 0001 01rr 1 - - - 5 - LD rr, (PC+A) 1110 0001 0001 01rr 1 - - - 6 - LD rr, (DE) 1110 0010 0001 01rr 1 - - - 4 - LD rr, (HL) 1110 0011 0001 01rr 1 - - - 4 - LD rr, (HL+d) 1110 0100 dddd dddd 0001 01rr 1 - - - 6 - LD rr, (HL+C) 1110 0101 0001 01rr 1 - - - 6 - LD rr, (HL+) not listed, invalid due to 16-bit op? ? ? ? ? ? - LD rr, (-HL) not listed, invalid due to 16-bit op? ? ? ? ? ? - - aka LD rr, (src) + LD rr, (x) 1110 0000 xxxx xxxx 0001 01rr 1 - - - 5 + LD rr, (PC+A) 1110 0001 0001 01rr 1 - - - 6 + LD rr, (DE) 1110 0010 0001 01rr 1 - - - 4 + LD rr, (HL) 1110 0011 0001 01rr 1 - - - 4 + LD rr, (HL+d) 1110 0100 dddd dddd 0001 01rr 1 - - - 6 + LD rr, (HL+C) 1110 0101 0001 01rr 1 - - - 6 + LD rr, (HL+) not listed, invalid due to 16-bit op? ? ? ? ? ? + LD rr, (-HL) not listed, invalid due to 16-bit op? ? ? ? ? ? + + aka LD rr, (src) */ m_cycles += 4; @@ -135,16 +135,16 @@ void tlcs870_device::do_INC_insrc(const uint8_t opbyte0, const uint8_t opbyte1, { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - INC (x) not listed, redundant encoding? ? ? ? ? ? - INC (PC+A) 1110 0001 0010 0000 C Z - - 6 - INC (DE) 1110 0010 0010 0000 C Z - - 4 - INC (HL) not listed, redundant encoding? ? ? ? ? ? - INC (HL+d) 1110 0100 dddd dddd 0010 0000 C Z - - 6 - INC (HL+C) 1110 0101 0010 0000 C Z - - 6 - INC (HL+) 1110 0110 0010 0000 C Z - - 5 - INC (-HL) 1110 0111 0010 0000 C Z - - 5 - - aka INC (src) + INC (x) not listed, redundant encoding? ? ? ? ? ? + INC (PC+A) 1110 0001 0010 0000 C Z - - 6 + INC (DE) 1110 0010 0010 0000 C Z - - 4 + INC (HL) not listed, redundant encoding? ? ? ? ? ? + INC (HL+d) 1110 0100 dddd dddd 0010 0000 C Z - - 6 + INC (HL+C) 1110 0101 0010 0000 C Z - - 6 + INC (HL+) 1110 0110 0010 0000 C Z - - 5 + INC (-HL) 1110 0111 0010 0000 C Z - - 5 + + aka INC (src) */ m_cycles += 4; @@ -169,16 +169,16 @@ void tlcs870_device::do_DEC_insrc(const uint8_t opbyte0, const uint8_t opbyte1, { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - DEC (x) not listed, redundant encoding? ? ? ? ? ? - DEC (PC+A) 1110 0001 0010 1000 C Z - - 6 - DEC (DE) 1110 0010 0010 1000 C Z - - 4 - DEC (HL) not listed, redundant encoding? ? ? ? ? ? - DEC (HL+d) 1110 0100 dddd dddd 0010 1000 C Z - - 6 - DEC (HL+C) 1110 0101 0010 1000 C Z - - 6 - DEC (HL+) 1110 0110 0010 1000 C Z - - 5 - DEC (-HL) 1110 0111 0010 1000 C Z - - 5 - - aka DEC (src) + DEC (x) not listed, redundant encoding? ? ? ? ? ? + DEC (PC+A) 1110 0001 0010 1000 C Z - - 6 + DEC (DE) 1110 0010 0010 1000 C Z - - 4 + DEC (HL) not listed, redundant encoding? ? ? ? ? ? + DEC (HL+d) 1110 0100 dddd dddd 0010 1000 C Z - - 6 + DEC (HL+C) 1110 0101 0010 1000 C Z - - 6 + DEC (HL+) 1110 0110 0010 1000 C Z - - 5 + DEC (-HL) 1110 0111 0010 1000 C Z - - 5 + + aka DEC (src) */ m_cycles += 4; @@ -211,17 +211,17 @@ void tlcs870_device::do_ROLD_A_insrc(const uint8_t opbyte0, const uint8_t opbyte { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - ROLD A, (x) 1110 0000 xxxx xxxx 0000 1000 1 0 0 0 8 - ROLD A, (PC+A) not listed, invalid? ? ? ? ? ? - ROLD A, (DE) 1110 0010 0000 1000 1 0 0 0 7 - ROLD A, (HL) 1110 0011 0000 1000 1 0 0 0 7 - ROLD A, (HL+d) 1110 0100 dddd dddd 0000 1000 1 0 0 0 9 - ROLD A, (HL+C) 1110 0101 0000 1000 1 0 0 0 9 - ROLD A, (HL+) 1110 0110 0000 1000 1 0 0 0 8 - ROLD A, (-HL) 1110 0111 0000 1000 1 0 0 0 8 - - aka ROLD A,(src) - 12-bit left rotation using lower 4 bits of REG_A and content of (src) + ROLD A, (x) 1110 0000 xxxx xxxx 0000 1000 1 0 0 0 8 + ROLD A, (PC+A) not listed, invalid? ? ? ? ? ? + ROLD A, (DE) 1110 0010 0000 1000 1 0 0 0 7 + ROLD A, (HL) 1110 0011 0000 1000 1 0 0 0 7 + ROLD A, (HL+d) 1110 0100 dddd dddd 0000 1000 1 0 0 0 9 + ROLD A, (HL+C) 1110 0101 0000 1000 1 0 0 0 9 + ROLD A, (HL+) 1110 0110 0000 1000 1 0 0 0 8 + ROLD A, (-HL) 1110 0111 0000 1000 1 0 0 0 8 + + aka ROLD A,(src) + 12-bit left rotation using lower 4 bits of REG_A and content of (src) */ m_cycles += 7; @@ -242,17 +242,17 @@ void tlcs870_device::do_RORD_A_insrc(const uint8_t opbyte0, const uint8_t opbyte { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - RORD A, (x) 1110 0000 xxxx xxxx 0000 1001 1 0 0 0 8 - RORD A, (PC+A) not listed, invalid? ? ? ? ? ? - RORD A, (DE) 1110 0010 0000 1001 1 0 0 0 7 - RORD A, (HL) 1110 0011 0000 1001 1 0 0 0 7 - RORD A, (HL+d) 1110 0100 dddd dddd 0000 1001 1 0 0 0 9 - RORD A, (HL+C) 1110 0101 0000 1001 1 0 0 0 9 - RORD A, (HL+) 1110 0110 0000 1001 1 0 0 0 8 - RORD A, (-HL) 1110 0111 0000 1001 1 0 0 0 8 - - aka RORD A,(src) - 12-bit right rotation using lower 4 bits of REG_A and content of (src) + RORD A, (x) 1110 0000 xxxx xxxx 0000 1001 1 0 0 0 8 + RORD A, (PC+A) not listed, invalid? ? ? ? ? ? + RORD A, (DE) 1110 0010 0000 1001 1 0 0 0 7 + RORD A, (HL) 1110 0011 0000 1001 1 0 0 0 7 + RORD A, (HL+d) 1110 0100 dddd dddd 0000 1001 1 0 0 0 9 + RORD A, (HL+C) 1110 0101 0000 1001 1 0 0 0 9 + RORD A, (HL+) 1110 0110 0000 1001 1 0 0 0 8 + RORD A, (-HL) 1110 0111 0000 1001 1 0 0 0 8 + + aka RORD A,(src) + 12-bit right rotation using lower 4 bits of REG_A and content of (src) */ m_cycles += 7; @@ -275,16 +275,16 @@ void tlcs870_device::do_LD_inx_insrc(const uint8_t opbyte0, const uint8_t opbyte { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - LD (x), (x) not listed, invalid? or redundant? ? ? ? ? ? - LD (x), (PC+A) 1110 0001 0010 0110 xxxx xxxx 1 U - - 7 - LD (x), (DE) 1110 0010 0010 0110 xxxx xxxx 1 U - - 5 - LD (x), (HL) 1110 0011 0010 0110 xxxx xxxx 1 U - - 5 - LD (x), (HL+d) 1110 0100 dddd dddd 0010 0110 xxxx xxxx 1 U - - 7 - LD (x), (HL+C) 1110 0101 0010 0110 xxxx xxxx 1 U - - 7 - LD (x), (HL+) not listed, invalid? ? ? ? ? ? - LD (x), (-HL) not listed, invalid? ? ? ? ? ? - - aka LD (x),(src) + LD (x), (x) not listed, invalid? or redundant? ? ? ? ? ? + LD (x), (PC+A) 1110 0001 0010 0110 xxxx xxxx 1 U - - 7 + LD (x), (DE) 1110 0010 0010 0110 xxxx xxxx 1 U - - 5 + LD (x), (HL) 1110 0011 0010 0110 xxxx xxxx 1 U - - 5 + LD (x), (HL+d) 1110 0100 dddd dddd 0010 0110 xxxx xxxx 1 U - - 7 + LD (x), (HL+C) 1110 0101 0010 0110 xxxx xxxx 1 U - - 7 + LD (x), (HL+) not listed, invalid? ? ? ? ? ? + LD (x), (-HL) not listed, invalid? ? ? ? ? ? + + aka LD (x),(src) */ m_cycles += 5; @@ -300,16 +300,16 @@ void tlcs870_device::do_LD_inHL_insrc(const uint8_t opbyte0, const uint8_t opbyt { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - LD (HL), (x) 1110 0000 xxxx xxxx 0010 0111 1 Z - - 5 - LD (HL), (PC+A) 1110 0001 0010 0111 1 Z - - 6 - LD (HL), (DE) 1110 0010 0010 0111 1 Z - - 4 - LD (HL), (HL) 1110 0011 0010 0111 1 Z - - 4 - LD (HL), (HL+d) 1110 0100 dddd dddd 0010 0111 1 Z - - 6 - LD (HL), (HL+C) 1110 0101 0010 0111 1 Z - - 6 - LD (HL), (HL+) not listed, invalid? ? ? ? ? ? - LD (HL), (-HL) not listed, invalid? ? ? ? ? ? - - aka LD (HL),(src) + LD (HL), (x) 1110 0000 xxxx xxxx 0010 0111 1 Z - - 5 + LD (HL), (PC+A) 1110 0001 0010 0111 1 Z - - 6 + LD (HL), (DE) 1110 0010 0010 0111 1 Z - - 4 + LD (HL), (HL) 1110 0011 0010 0111 1 Z - - 4 + LD (HL), (HL+d) 1110 0100 dddd dddd 0010 0111 1 Z - - 6 + LD (HL), (HL+C) 1110 0101 0010 0111 1 Z - - 6 + LD (HL), (HL+) not listed, invalid? ? ? ? ? ? + LD (HL), (-HL) not listed, invalid? ? ? ? ? ? + + aka LD (HL),(src) */ m_cycles += 4; @@ -327,16 +327,16 @@ void tlcs870_device::do_LD_r_insrc(const uint8_t opbyte0, const uint8_t opbyte1, { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - LD r, (x) 1110 0000 xxxx xxxx 0101 1rrr 1 Z - - 4 - LD r, (PC+A) 1110 0001 0101 1rrr 1 Z - - 5 - LD r, (DE) 1110 0010 0101 1rrr 1 Z - - 3 - LD r, (HL) 1110 0011 0101 1rrr 1 Z - - 3 - LD r, (HL+d) 1110 0100 dddd dddd 0101 1rrr 1 Z - - 5 - LD r, (HL+C) 1110 0101 0101 1rrr 1 Z - - 5 - LD r, (HL+) 1110 0110 0101 1rrr 1 Z - - 4 (invalid if r is H or L) - LD r, (-HL) 1110 0111 0101 1rrr 1 Z - - 4 - - aka LD r, (src) + LD r, (x) 1110 0000 xxxx xxxx 0101 1rrr 1 Z - - 4 + LD r, (PC+A) 1110 0001 0101 1rrr 1 Z - - 5 + LD r, (DE) 1110 0010 0101 1rrr 1 Z - - 3 + LD r, (HL) 1110 0011 0101 1rrr 1 Z - - 3 + LD r, (HL+d) 1110 0100 dddd dddd 0101 1rrr 1 Z - - 5 + LD r, (HL+C) 1110 0101 0101 1rrr 1 Z - - 5 + LD r, (HL+) 1110 0110 0101 1rrr 1 Z - - 4 (invalid if r is H or L) + LD r, (-HL) 1110 0111 0101 1rrr 1 Z - - 4 + + aka LD r, (src) */ m_cycles += 3; @@ -354,16 +354,16 @@ void tlcs870_device::do_MCMP_insrc_n(const uint8_t opbyte0, const uint8_t opbyte { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - MCMP (x), n 1110 0000 xxxx xxxx 0010 1111 nnnn nnnn Z Z C H 6 - MCMP (PC+A), n 1110 0001 0010 1111 nnnn nnnn Z Z C H 7 - MCMP (DE), n 1110 0010 0010 1111 nnnn nnnn Z Z C H 5 - MCMP (HL), n 1110 0011 0010 1111 nnnn nnnn Z Z C H 5 - MCMP (HL+d), n 1110 0100 dddd dddd 0010 1111 nnnn nnnn Z Z C H 7 - MCMP (HL+C), n 1110 0101 0010 1111 nnnn nnnn Z Z C H 7 - MCMP (HL+), n 1110 0110 0010 1111 nnnn nnnn Z Z C H 6 - MCMP (-HL), n 1110 0111 0010 1111 nnnn nnnn Z Z C H 6 - - aka MCMP (src), n + MCMP (x), n 1110 0000 xxxx xxxx 0010 1111 nnnn nnnn Z Z C H 6 + MCMP (PC+A), n 1110 0001 0010 1111 nnnn nnnn Z Z C H 7 + MCMP (DE), n 1110 0010 0010 1111 nnnn nnnn Z Z C H 5 + MCMP (HL), n 1110 0011 0010 1111 nnnn nnnn Z Z C H 5 + MCMP (HL+d), n 1110 0100 dddd dddd 0010 1111 nnnn nnnn Z Z C H 7 + MCMP (HL+C), n 1110 0101 0010 1111 nnnn nnnn Z Z C H 7 + MCMP (HL+), n 1110 0110 0010 1111 nnnn nnnn Z Z C H 6 + MCMP (-HL), n 1110 0111 0010 1111 nnnn nnnn Z Z C H 6 + + aka MCMP (src), n */ m_cycles += 5; @@ -403,16 +403,16 @@ void tlcs870_device::do_XCH_r_insrc(const uint8_t opbyte0, const uint8_t opbyte1 { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - XCH r, (x) 1110 0000 xxxx xxxx 1010 1rrr 1 Z - - 5 - XCH r, (PC+A) 1110 0001 1010 1rrr 1 Z - - 6 - XCH r, (DE) 1110 0010 1010 1rrr 1 Z - - 4 - XCH r, (HL) 1110 0011 1010 1rrr 1 Z - - 4 - XCH r, (HL+d) 1110 0100 dddd dddd 1010 1rrr 1 Z - - 6 - XCH r, (HL+C) 1110 0101 1010 1rrr 1 Z - - 6 - XCH r, (HL+) 1110 0110 1010 1rrr 1 Z - - 5 (invalid if r is H or L) - XCH r, (-HL) 1110 0111 1010 1rrr 1 Z - - 5 - - aka XCH r,(src) + XCH r, (x) 1110 0000 xxxx xxxx 1010 1rrr 1 Z - - 5 + XCH r, (PC+A) 1110 0001 1010 1rrr 1 Z - - 6 + XCH r, (DE) 1110 0010 1010 1rrr 1 Z - - 4 + XCH r, (HL) 1110 0011 1010 1rrr 1 Z - - 4 + XCH r, (HL+d) 1110 0100 dddd dddd 1010 1rrr 1 Z - - 6 + XCH r, (HL+C) 1110 0101 1010 1rrr 1 Z - - 6 + XCH r, (HL+) 1110 0110 1010 1rrr 1 Z - - 5 (invalid if r is H or L) + XCH r, (-HL) 1110 0111 1010 1rrr 1 Z - - 5 + + aka XCH r,(src) */ m_cycles += 4; @@ -444,79 +444,79 @@ void tlcs870_device::do_ALUOP_insrc_inHL(const uint8_t opbyte0, const uint8_t op { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - ADDC (x), (HL) 1110 0000 xxxx xxxx 0110 0000 C Z C H 7 - ADDC (PC+A), (HL) 1110 0001 0110 0000 C Z C H 8 - ADDC (DE), (HL) 1110 0010 0110 0000 C Z C H 6 - ADDC (HL), (HL) 1110 0011 0110 0000 C Z C H 6 - ADDC (HL+d), (HL) 1110 0100 dddd dddd 0110 0000 C Z C H 8 - ADDC (HL+C), (HL) 1110 0101 0110 0000 C Z C H 8 - ADDC (HL+), (HL) not listed, invalid? ? ? ? ? ? - ADDC (-HL), (HL) not listed, invalid? ? ? ? ? ? - - ADD (x), (HL) 1110 0000 xxxx xxxx 0110 0001 C Z C H 7 - ADD (PC+A), (HL) 1110 0001 0110 0001 C Z C H 8 - ADD (DE), (HL) 1110 0010 0110 0001 C Z C H 6 - ADD (HL), (HL) 1110 0011 0110 0001 C Z C H 6 - ADD (HL+d), (HL) 1110 0100 dddd dddd 0110 0001 C Z C H 8 - ADD (HL+C), (HL) 1110 0101 0110 0001 C Z C H 8 - ADD (HL+), (HL) not listed, invalid? ? ? ? ? ? - ADD (-HL), (HL) not listed, invalid? ? ? ? ? ? - - SUBB (x), (HL) 1110 0000 xxxx xxxx 0110 0010 C Z C H 7 - SUBB (PC+A), (HL) 1110 0001 0110 0010 C Z C H 8 - SUBB (DE), (HL) 1110 0010 0110 0010 C Z C H 6 - SUBB (HL), (HL) 1110 0011 0110 0010 C Z C H 6 - SUBB (HL+d), (HL) 1110 0100 dddd dddd 0110 0010 C Z C H 8 - SUBB (HL+C), (HL) 1110 0101 0110 0010 C Z C H 8 - SUBB (HL+), (HL) not listed, invalid? ? ? ? ? ? - SUBB (-HL), (HL) not listed, invalid? ? ? ? ? ? - - SUB (x), (HL) 1110 0000 xxxx xxxx 0110 0011 C Z C H 7 - SUB (PC+A), (HL) 1110 0001 0110 0011 C Z C H 8 - SUB (DE), (HL) 1110 0010 0110 0011 C Z C H 6 - SUB (HL), (HL) 1110 0011 0110 0011 C Z C H 6 - SUB (HL+d), (HL) 1110 0100 dddd dddd 0110 0011 C Z C H 8 - SUB (HL+C), (HL) 1110 0101 0110 0011 C Z C H 8 - SUB (HL+), (HL) not listed, invalid? ? ? ? ? ? - SUB (-HL), (HL) not listed, invalid? ? ? ? ? ? - - AND (x), (HL) 1110 0000 xxxx xxxx 0110 0100 Z Z - - 7 - AND (PC+A), (HL) 1110 0001 0110 0100 Z Z - - 8 - AND (DE), (HL) 1110 0010 0110 0100 Z Z - - 6 - AND (HL), (HL) 1110 0011 0110 0100 Z Z - - 6 - AND (HL+d), (HL) 1110 0100 dddd dddd 0110 0100 Z Z - - 8 - AND (HL+C), (HL) 1110 0101 0110 0100 Z Z - - 8 - AND (HL+), (HL) not listed, invalid? ? ? ? ? ? - AND (-HL), (HL) not listed, invalid? ? ? ? ? ? - - XOR (x), (HL) 1110 0000 xxxx xxxx 0110 0101 Z Z - - 7 - XOR (PC+A), (HL) 1110 0001 0110 0101 Z Z - - 8 - XOR (DE), (HL) 1110 0010 0110 0101 Z Z - - 6 - XOR (HL), (HL) 1110 0011 0110 0101 Z Z - - 6 - XOR (HL+d), (HL) 1110 0100 dddd dddd 0110 0101 Z Z - - 8 - XOR (HL+C), (HL) 1110 0101 0110 0101 Z Z - - 8 - XOR (HL+), (HL) not listed, invalid? ? ? ? ? ? - XOR (-HL), (HL) not listed, invalid? ? ? ? ? ? - - OR (x), (HL) 1110 0000 xxxx xxxx 0110 0110 Z Z - - 7 - OR (PC+A), (HL) 1110 0001 0110 0110 Z Z - - 8 - OR (DE), (HL) 1110 0010 0110 0110 Z Z - - 6 - OR (HL), (HL) 1110 0011 0110 0110 Z Z - - 6 - OR (HL+d), (HL) 1110 0100 dddd dddd 0110 0110 Z Z - - 8 - OR (HL+C), (HL) 1110 0101 0110 0110 Z Z - - 8 - OR (HL+), (HL) not listed, invalid? ? ? ? ? ? - OR (-HL), (HL) not listed, invalid? ? ? ? ? ? - - CMP (x), (HL) 1110 0000 xxxx xxxx 0110 0111 Z Z C H 6 - CMP (PC+A), (HL) 1110 0001 0110 0111 Z Z C H 7 - CMP (DE), (HL) 1110 0010 0110 0111 Z Z C H 5 - CMP (HL), (HL) 1110 0011 0110 0111 Z Z C H 5 - CMP (HL+d), (HL) 1110 0100 dddd dddd 0110 0111 Z Z C H 7 - CMP (HL+C), (HL) 1110 0101 0110 0111 Z Z C H 7 - CMP (HL+), (HL) not listed, invalid? ? ? ? ? ? - CMP (-HL), (HL) not listed, invalid? ? ? ? ? ? - - aka (ALU OP) (src), (HL) + ADDC (x), (HL) 1110 0000 xxxx xxxx 0110 0000 C Z C H 7 + ADDC (PC+A), (HL) 1110 0001 0110 0000 C Z C H 8 + ADDC (DE), (HL) 1110 0010 0110 0000 C Z C H 6 + ADDC (HL), (HL) 1110 0011 0110 0000 C Z C H 6 + ADDC (HL+d), (HL) 1110 0100 dddd dddd 0110 0000 C Z C H 8 + ADDC (HL+C), (HL) 1110 0101 0110 0000 C Z C H 8 + ADDC (HL+), (HL) not listed, invalid? ? ? ? ? ? + ADDC (-HL), (HL) not listed, invalid? ? ? ? ? ? + + ADD (x), (HL) 1110 0000 xxxx xxxx 0110 0001 C Z C H 7 + ADD (PC+A), (HL) 1110 0001 0110 0001 C Z C H 8 + ADD (DE), (HL) 1110 0010 0110 0001 C Z C H 6 + ADD (HL), (HL) 1110 0011 0110 0001 C Z C H 6 + ADD (HL+d), (HL) 1110 0100 dddd dddd 0110 0001 C Z C H 8 + ADD (HL+C), (HL) 1110 0101 0110 0001 C Z C H 8 + ADD (HL+), (HL) not listed, invalid? ? ? ? ? ? + ADD (-HL), (HL) not listed, invalid? ? ? ? ? ? + + SUBB (x), (HL) 1110 0000 xxxx xxxx 0110 0010 C Z C H 7 + SUBB (PC+A), (HL) 1110 0001 0110 0010 C Z C H 8 + SUBB (DE), (HL) 1110 0010 0110 0010 C Z C H 6 + SUBB (HL), (HL) 1110 0011 0110 0010 C Z C H 6 + SUBB (HL+d), (HL) 1110 0100 dddd dddd 0110 0010 C Z C H 8 + SUBB (HL+C), (HL) 1110 0101 0110 0010 C Z C H 8 + SUBB (HL+), (HL) not listed, invalid? ? ? ? ? ? + SUBB (-HL), (HL) not listed, invalid? ? ? ? ? ? + + SUB (x), (HL) 1110 0000 xxxx xxxx 0110 0011 C Z C H 7 + SUB (PC+A), (HL) 1110 0001 0110 0011 C Z C H 8 + SUB (DE), (HL) 1110 0010 0110 0011 C Z C H 6 + SUB (HL), (HL) 1110 0011 0110 0011 C Z C H 6 + SUB (HL+d), (HL) 1110 0100 dddd dddd 0110 0011 C Z C H 8 + SUB (HL+C), (HL) 1110 0101 0110 0011 C Z C H 8 + SUB (HL+), (HL) not listed, invalid? ? ? ? ? ? + SUB (-HL), (HL) not listed, invalid? ? ? ? ? ? + + AND (x), (HL) 1110 0000 xxxx xxxx 0110 0100 Z Z - - 7 + AND (PC+A), (HL) 1110 0001 0110 0100 Z Z - - 8 + AND (DE), (HL) 1110 0010 0110 0100 Z Z - - 6 + AND (HL), (HL) 1110 0011 0110 0100 Z Z - - 6 + AND (HL+d), (HL) 1110 0100 dddd dddd 0110 0100 Z Z - - 8 + AND (HL+C), (HL) 1110 0101 0110 0100 Z Z - - 8 + AND (HL+), (HL) not listed, invalid? ? ? ? ? ? + AND (-HL), (HL) not listed, invalid? ? ? ? ? ? + + XOR (x), (HL) 1110 0000 xxxx xxxx 0110 0101 Z Z - - 7 + XOR (PC+A), (HL) 1110 0001 0110 0101 Z Z - - 8 + XOR (DE), (HL) 1110 0010 0110 0101 Z Z - - 6 + XOR (HL), (HL) 1110 0011 0110 0101 Z Z - - 6 + XOR (HL+d), (HL) 1110 0100 dddd dddd 0110 0101 Z Z - - 8 + XOR (HL+C), (HL) 1110 0101 0110 0101 Z Z - - 8 + XOR (HL+), (HL) not listed, invalid? ? ? ? ? ? + XOR (-HL), (HL) not listed, invalid? ? ? ? ? ? + + OR (x), (HL) 1110 0000 xxxx xxxx 0110 0110 Z Z - - 7 + OR (PC+A), (HL) 1110 0001 0110 0110 Z Z - - 8 + OR (DE), (HL) 1110 0010 0110 0110 Z Z - - 6 + OR (HL), (HL) 1110 0011 0110 0110 Z Z - - 6 + OR (HL+d), (HL) 1110 0100 dddd dddd 0110 0110 Z Z - - 8 + OR (HL+C), (HL) 1110 0101 0110 0110 Z Z - - 8 + OR (HL+), (HL) not listed, invalid? ? ? ? ? ? + OR (-HL), (HL) not listed, invalid? ? ? ? ? ? + + CMP (x), (HL) 1110 0000 xxxx xxxx 0110 0111 Z Z C H 6 + CMP (PC+A), (HL) 1110 0001 0110 0111 Z Z C H 7 + CMP (DE), (HL) 1110 0010 0110 0111 Z Z C H 5 + CMP (HL), (HL) 1110 0011 0110 0111 Z Z C H 5 + CMP (HL+d), (HL) 1110 0100 dddd dddd 0110 0111 Z Z C H 7 + CMP (HL+C), (HL) 1110 0101 0110 0111 Z Z C H 7 + CMP (HL+), (HL) not listed, invalid? ? ? ? ? ? + CMP (-HL), (HL) not listed, invalid? ? ? ? ? ? + + aka (ALU OP) (src), (HL) */ m_cycles += 6; @@ -541,89 +541,89 @@ void tlcs870_device::do_ALUOP_insrc_n(const uint8_t opbyte0, const uint8_t opbyt { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - ADDC (x), n 1110 0000 xxxx xxxx 0111 0000 nnnn nnnn C Z C H 6 - ADDC (PC+A), n 1110 0001 0111 0000 nnnn nnnn C Z C H 7 - ADDC (DE), n 1110 0010 0111 0000 nnnn nnnn C Z C H 5 - ADDC (HL), n 1110 0011 0111 0000 nnnn nnnn C Z C H 5 - ADDC (HL+d), n 1110 0100 dddd dddd 0111 0000 nnnn nnnn C Z C H 7 - ADDC (HL+C), n 1110 0101 0111 0000 nnnn nnnn C Z C H 7 - ADDC (HL+), n 1110 0110 0111 0000 nnnn nnnn C Z C H 6 - ADDC (-HL), n 1110 0111 0111 0000 nnnn nnnn C Z C H 6 - - ADD (x), n 1110 0000 xxxx xxxx 0111 0001 nnnn nnnn C Z C H 6 - ADD (PC+A), n 1110 0001 0111 0001 nnnn nnnn C Z C H 7 - ADD (DE), n 1110 0010 0111 0001 nnnn nnnn C Z C H 5 - ADD (HL), n 1110 0011 0111 0001 nnnn nnnn C Z C H 5 - ADD (HL+d), n 1110 0100 dddd dddd 0111 0001 nnnn nnnn C Z C H 7 - ADD (HL+C), n 1110 0101 0111 0001 nnnn nnnn C Z C H 7 - ADD (HL+), n 1110 0110 0111 0001 nnnn nnnn C Z C H 6 - ADD (-HL), n 1110 0111 0111 0001 nnnn nnnn C Z C H 6 - - SUBB (x), n 1110 0000 xxxx xxxx 0111 0010 nnnn nnnn C Z C H 6 - SUBB (PC+A), n 1110 0001 0111 0010 nnnn nnnn C Z C H 7 - SUBB (DE), n 1110 0010 0111 0010 nnnn nnnn C Z C H 5 - SUBB (HL), n 1110 0011 0111 0010 nnnn nnnn C Z C H 5 - SUBB (HL+d), n 1110 0100 dddd dddd 0111 0010 nnnn nnnn C Z C H 7 - SUBB (HL+C), n 1110 0101 0111 0010 nnnn nnnn C Z C H 7 - SUBB (HL+), n 1110 0110 0111 0010 nnnn nnnn C Z C H 6 - SUBB (-HL), n 1110 0111 0111 0010 nnnn nnnn C Z C H 6 - - SUB (x), n 1110 0000 xxxx xxxx 0111 0011 nnnn nnnn C Z C H 6 - SUB (PC+A), n 1110 0001 0111 0011 nnnn nnnn C Z C H 7 - SUB (DE), n 1110 0010 0111 0011 nnnn nnnn C Z C H 5 - SUB (HL), n 1110 0011 0111 0011 nnnn nnnn C Z C H 5 - SUB (HL+d), n 1110 0100 dddd dddd 0111 0011 nnnn nnnn C Z C H 7 - SUB (HL+C), n 1110 0101 0111 0011 nnnn nnnn C Z C H 7 - SUB (HL+), n 1110 0110 0111 0011 nnnn nnnn C Z C H 6 - SUB (-HL), n 1110 0111 0111 0011 nnnn nnnn C Z C H 6 - - AND (x), n 1110 0000 xxxx xxxx 0111 0100 nnnn nnnn Z Z - - 6 - AND (PC+A), n 1110 0001 0111 0100 nnnn nnnn Z Z - - 7 - AND (DE), n 1110 0010 0111 0100 nnnn nnnn Z Z - - 5 - AND (HL), n 1110 0011 0111 0100 nnnn nnnn Z Z - - 5 - AND (HL+d), n 1110 0100 dddd dddd 0111 0100 nnnn nnnn Z Z - - 7 - AND (HL+C), n 1110 0101 0111 0100 nnnn nnnn Z Z - - 7 - AND (HL+), n 1110 0110 0111 0100 nnnn nnnn Z Z - - 6 - AND (-HL), n 1110 0111 0111 0100 nnnn nnnn Z Z - - 6 - - XOR (x), n 1110 0000 xxxx xxxx 0111 0101 nnnn nnnn Z Z - - 6 - XOR (PC+A), n 1110 0001 0111 0101 nnnn nnnn Z Z - - 7 - XOR (DE), n 1110 0010 0111 0101 nnnn nnnn Z Z - - 5 - XOR (HL), n 1110 0011 0111 0101 nnnn nnnn Z Z - - 5 - XOR (HL+d), n 1110 0100 dddd dddd 0111 0101 nnnn nnnn Z Z - - 7 - XOR (HL+C), n 1110 0101 0111 0101 nnnn nnnn Z Z - - 7 - XOR (HL+), n 1110 0110 0111 0101 nnnn nnnn Z Z - - 6 - XOR (-HL), n 1110 0111 0111 0101 nnnn nnnn Z Z - - 6 - - OR (x), n 1110 0000 xxxx xxxx 0111 0110 nnnn nnnn Z Z - - 6 - OR (PC+A), n 1110 0001 0111 0110 nnnn nnnn Z Z - - 7 - OR (DE), n 1110 0010 0111 0110 nnnn nnnn Z Z - - 5 - OR (HL), n 1110 0011 0111 0110 nnnn nnnn Z Z - - 5 - OR (HL+d), n 1110 0100 dddd dddd 0111 0110 nnnn nnnn Z Z - - 7 - OR (HL+C), n 1110 0101 0111 0110 nnnn nnnn Z Z - - 7 - OR (HL+), n 1110 0110 0111 0110 nnnn nnnn Z Z - - 6 - OR (-HL), n 1110 0111 0111 0110 nnnn nnnn Z Z - - 6 - - CMP (x), n 1110 0000 xxxx xxxx 0111 0111 nnnn nnnn Z Z C H 5 - CMP (PC+A), n 1110 0001 0111 0111 nnnn nnnn Z Z C H 6 - CMP (DE), n 1110 0010 0111 0111 nnnn nnnn Z Z C H 4 - CMP (HL), n 1110 0011 0111 0111 nnnn nnnn Z Z C H 4 - CMP (HL+d), n 1110 0100 dddd dddd 0111 0111 nnnn nnnn Z Z C H 6 - CMP (HL+C), n 1110 0101 0111 0111 nnnn nnnn Z Z C H 6 - CMP (HL+), n 1110 0110 0111 0111 nnnn nnnn Z Z C H 5 - CMP (-HL), n 1110 0111 0111 0111 nnnn nnnn Z Z C H 5 - - aka (ALU OP) (src), n + ADDC (x), n 1110 0000 xxxx xxxx 0111 0000 nnnn nnnn C Z C H 6 + ADDC (PC+A), n 1110 0001 0111 0000 nnnn nnnn C Z C H 7 + ADDC (DE), n 1110 0010 0111 0000 nnnn nnnn C Z C H 5 + ADDC (HL), n 1110 0011 0111 0000 nnnn nnnn C Z C H 5 + ADDC (HL+d), n 1110 0100 dddd dddd 0111 0000 nnnn nnnn C Z C H 7 + ADDC (HL+C), n 1110 0101 0111 0000 nnnn nnnn C Z C H 7 + ADDC (HL+), n 1110 0110 0111 0000 nnnn nnnn C Z C H 6 + ADDC (-HL), n 1110 0111 0111 0000 nnnn nnnn C Z C H 6 + + ADD (x), n 1110 0000 xxxx xxxx 0111 0001 nnnn nnnn C Z C H 6 + ADD (PC+A), n 1110 0001 0111 0001 nnnn nnnn C Z C H 7 + ADD (DE), n 1110 0010 0111 0001 nnnn nnnn C Z C H 5 + ADD (HL), n 1110 0011 0111 0001 nnnn nnnn C Z C H 5 + ADD (HL+d), n 1110 0100 dddd dddd 0111 0001 nnnn nnnn C Z C H 7 + ADD (HL+C), n 1110 0101 0111 0001 nnnn nnnn C Z C H 7 + ADD (HL+), n 1110 0110 0111 0001 nnnn nnnn C Z C H 6 + ADD (-HL), n 1110 0111 0111 0001 nnnn nnnn C Z C H 6 + + SUBB (x), n 1110 0000 xxxx xxxx 0111 0010 nnnn nnnn C Z C H 6 + SUBB (PC+A), n 1110 0001 0111 0010 nnnn nnnn C Z C H 7 + SUBB (DE), n 1110 0010 0111 0010 nnnn nnnn C Z C H 5 + SUBB (HL), n 1110 0011 0111 0010 nnnn nnnn C Z C H 5 + SUBB (HL+d), n 1110 0100 dddd dddd 0111 0010 nnnn nnnn C Z C H 7 + SUBB (HL+C), n 1110 0101 0111 0010 nnnn nnnn C Z C H 7 + SUBB (HL+), n 1110 0110 0111 0010 nnnn nnnn C Z C H 6 + SUBB (-HL), n 1110 0111 0111 0010 nnnn nnnn C Z C H 6 + + SUB (x), n 1110 0000 xxxx xxxx 0111 0011 nnnn nnnn C Z C H 6 + SUB (PC+A), n 1110 0001 0111 0011 nnnn nnnn C Z C H 7 + SUB (DE), n 1110 0010 0111 0011 nnnn nnnn C Z C H 5 + SUB (HL), n 1110 0011 0111 0011 nnnn nnnn C Z C H 5 + SUB (HL+d), n 1110 0100 dddd dddd 0111 0011 nnnn nnnn C Z C H 7 + SUB (HL+C), n 1110 0101 0111 0011 nnnn nnnn C Z C H 7 + SUB (HL+), n 1110 0110 0111 0011 nnnn nnnn C Z C H 6 + SUB (-HL), n 1110 0111 0111 0011 nnnn nnnn C Z C H 6 + + AND (x), n 1110 0000 xxxx xxxx 0111 0100 nnnn nnnn Z Z - - 6 + AND (PC+A), n 1110 0001 0111 0100 nnnn nnnn Z Z - - 7 + AND (DE), n 1110 0010 0111 0100 nnnn nnnn Z Z - - 5 + AND (HL), n 1110 0011 0111 0100 nnnn nnnn Z Z - - 5 + AND (HL+d), n 1110 0100 dddd dddd 0111 0100 nnnn nnnn Z Z - - 7 + AND (HL+C), n 1110 0101 0111 0100 nnnn nnnn Z Z - - 7 + AND (HL+), n 1110 0110 0111 0100 nnnn nnnn Z Z - - 6 + AND (-HL), n 1110 0111 0111 0100 nnnn nnnn Z Z - - 6 + + XOR (x), n 1110 0000 xxxx xxxx 0111 0101 nnnn nnnn Z Z - - 6 + XOR (PC+A), n 1110 0001 0111 0101 nnnn nnnn Z Z - - 7 + XOR (DE), n 1110 0010 0111 0101 nnnn nnnn Z Z - - 5 + XOR (HL), n 1110 0011 0111 0101 nnnn nnnn Z Z - - 5 + XOR (HL+d), n 1110 0100 dddd dddd 0111 0101 nnnn nnnn Z Z - - 7 + XOR (HL+C), n 1110 0101 0111 0101 nnnn nnnn Z Z - - 7 + XOR (HL+), n 1110 0110 0111 0101 nnnn nnnn Z Z - - 6 + XOR (-HL), n 1110 0111 0111 0101 nnnn nnnn Z Z - - 6 + + OR (x), n 1110 0000 xxxx xxxx 0111 0110 nnnn nnnn Z Z - - 6 + OR (PC+A), n 1110 0001 0111 0110 nnnn nnnn Z Z - - 7 + OR (DE), n 1110 0010 0111 0110 nnnn nnnn Z Z - - 5 + OR (HL), n 1110 0011 0111 0110 nnnn nnnn Z Z - - 5 + OR (HL+d), n 1110 0100 dddd dddd 0111 0110 nnnn nnnn Z Z - - 7 + OR (HL+C), n 1110 0101 0111 0110 nnnn nnnn Z Z - - 7 + OR (HL+), n 1110 0110 0111 0110 nnnn nnnn Z Z - - 6 + OR (-HL), n 1110 0111 0111 0110 nnnn nnnn Z Z - - 6 + + CMP (x), n 1110 0000 xxxx xxxx 0111 0111 nnnn nnnn Z Z C H 5 + CMP (PC+A), n 1110 0001 0111 0111 nnnn nnnn Z Z C H 6 + CMP (DE), n 1110 0010 0111 0111 nnnn nnnn Z Z C H 4 + CMP (HL), n 1110 0011 0111 0111 nnnn nnnn Z Z C H 4 + CMP (HL+d), n 1110 0100 dddd dddd 0111 0111 nnnn nnnn Z Z C H 6 + CMP (HL+C), n 1110 0101 0111 0111 nnnn nnnn Z Z C H 6 + CMP (HL+), n 1110 0110 0111 0111 nnnn nnnn Z Z C H 5 + CMP (-HL), n 1110 0111 0111 0111 nnnn nnnn Z Z C H 5 + + aka (ALU OP) (src), n */ m_cycles += 5; const uint8_t n = READ8(); const int aluop = (opbyte1 & 0x7); - + if (aluop != 0x07) m_read_input_port = 0; // reads output latch, not actual ports if accessing memory mapped ports - + const uint8_t val = RM8(srcaddr); const uint8_t result = do_alu_8bit(aluop, val, n); @@ -639,79 +639,79 @@ void tlcs870_device::do_ALUOP_A_insrc(const uint8_t opbyte0, const uint8_t opbyt { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - ADDC A, (x) 1110 0000 xxxx xxxx 0111 1000 C Z C H 4 - ADDC A, (PC+A) 1110 0001 0111 1000 C Z C H 5 - ADDC A, (DE) 1110 0010 0111 1000 C Z C H 3 - ADDC A, (HL) 1110 0011 0111 1000 C Z C H 3 - ADDC A, (HL+d) 1110 0100 dddd dddd 0111 1000 C Z C H 5 - ADDC A, (HL+C) 1110 0101 0111 1000 C Z C H 5 - ADDC A, (HL+) 1110 0110 0111 1000 C Z C H 4 - ADDC A, (-HL) 1110 0111 0111 1000 C Z C H 4 - - ADD A, (x) 1110 0000 xxxx xxxx 0111 1001 C Z C H 4 - ADD A, (PC+A) 1110 0001 0111 1001 C Z C H 5 - ADD A, (DE) 1110 0010 0111 1001 C Z C H 3 - ADD A, (HL) 1110 0011 0111 1001 C Z C H 3 - ADD A, (HL+d) 1110 0100 dddd dddd 0111 1001 C Z C H 5 - ADD A, (HL+C) 1110 0101 0111 1001 C Z C H 5 - ADD A, (HL+) 1110 0110 0111 1001 C Z C H 4 - ADD A, (-HL) 1110 0111 0111 1001 C Z C H 4 - - SUBB A, (x) 1110 0000 xxxx xxxx 0111 1010 C Z C H 4 - SUBB A, (PC+A) 1110 0001 0111 1010 C Z C H 5 - SUBB A, (DE) 1110 0010 0111 1010 C Z C H 3 - SUBB A, (HL) 1110 0011 0111 1010 C Z C H 3 - SUBB A, (HL+d) 1110 0100 dddd dddd 0111 1010 C Z C H 5 - SUBB A, (HL+C) 1110 0101 0111 1010 C Z C H 5 - SUBB A, (HL+) 1110 0110 0111 1010 C Z C H 4 - SUBB A, (-HL) 1110 0111 0111 1010 C Z C H 4 - - SUB A, (x) 1110 0000 xxxx xxxx 0111 1011 C Z C H 4 - SUB A, (PC+A) 1110 0001 0111 1011 C Z C H 5 - SUB A, (DE) 1110 0010 0111 1011 C Z C H 3 - SUB A, (HL) 1110 0011 0111 1011 C Z C H 3 - SUB A, (HL+d) 1110 0100 dddd dddd 0111 1011 C Z C H 5 - SUB A, (HL+C) 1110 0101 0111 1011 C Z C H 5 - SUB A, (HL+) 1110 0110 0111 1011 C Z C H 4 - SUB A, (-HL) 1110 0111 0111 1011 C Z C H 4 - - AND A, (x) 1110 0000 xxxx xxxx 0111 1100 Z Z - - 4 - AND A, (PC+A) 1110 0001 0111 1100 Z Z - - 5 - AND A, (DE) 1110 0010 0111 1100 Z Z - - 3 - AND A, (HL) 1110 0011 0111 1100 Z Z - - 3 - AND A, (HL+d) 1110 0100 dddd dddd 0111 1100 Z Z - - 5 - AND A, (HL+C) 1110 0101 0111 1100 Z Z - - 5 - AND A, (HL+) 1110 0110 0111 1100 Z Z - - 4 - AND A, (-HL) 1110 0111 0111 1100 Z Z - - 4 - - XOR A, (x) 1110 0000 xxxx xxxx 0111 1101 Z Z - - 4 - XOR A, (PC+A) 1110 0001 0111 1101 Z Z - - 5 - XOR A, (DE) 1110 0010 0111 1101 Z Z - - 3 - XOR A, (HL) 1110 0011 0111 1101 Z Z - - 3 - XOR A, (HL+d) 1110 0100 dddd dddd 0111 1101 Z Z - - 5 - XOR A, (HL+C) 1110 0101 0111 1101 Z Z - - 5 - XOR A, (HL+) 1110 0110 0111 1101 Z Z - - 4 - XOR A, (-HL) 1110 0111 0111 1101 Z Z - - 4 - - OR A, (x) 1110 0000 xxxx xxxx 0111 1110 Z Z - - 4 - OR A, (PC+A) 1110 0001 0111 1110 Z Z - - 5 - OR A, (DE) 1110 0010 0111 1110 Z Z - - 3 - OR A, (HL) 1110 0011 0111 1110 Z Z - - 3 - OR A, (HL+d) 1110 0100 dddd dddd 0111 1110 Z Z - - 5 - OR A, (HL+C) 1110 0101 0111 1110 Z Z - - 5 - OR A, (HL+) 1110 0110 0111 1110 Z Z - - 4 - OR A, (-HL) 1110 0111 0111 1110 Z Z - - 4 - - CMP A, (x) 1110 0000 xxxx xxxx 0111 1111 Z Z C H 4 - CMP A, (PC+A) 1110 0001 0111 1111 Z Z C H 5 - CMP A, (DE) 1110 0010 0111 1111 Z Z C H 3 - CMP A, (HL) 1110 0011 0111 1111 Z Z C H 3 - CMP A, (HL+d) 1110 0100 dddd dddd 0111 1111 Z Z C H 5 - CMP A, (HL+C) 1110 0101 0111 1111 Z Z C H 5 - CMP A, (HL+) 1110 0110 0111 1111 Z Z C H 4 - CMP A, (-HL) 1110 0111 0111 1111 Z Z C H 4 - - aka (ALU OP) A, (src) + ADDC A, (x) 1110 0000 xxxx xxxx 0111 1000 C Z C H 4 + ADDC A, (PC+A) 1110 0001 0111 1000 C Z C H 5 + ADDC A, (DE) 1110 0010 0111 1000 C Z C H 3 + ADDC A, (HL) 1110 0011 0111 1000 C Z C H 3 + ADDC A, (HL+d) 1110 0100 dddd dddd 0111 1000 C Z C H 5 + ADDC A, (HL+C) 1110 0101 0111 1000 C Z C H 5 + ADDC A, (HL+) 1110 0110 0111 1000 C Z C H 4 + ADDC A, (-HL) 1110 0111 0111 1000 C Z C H 4 + + ADD A, (x) 1110 0000 xxxx xxxx 0111 1001 C Z C H 4 + ADD A, (PC+A) 1110 0001 0111 1001 C Z C H 5 + ADD A, (DE) 1110 0010 0111 1001 C Z C H 3 + ADD A, (HL) 1110 0011 0111 1001 C Z C H 3 + ADD A, (HL+d) 1110 0100 dddd dddd 0111 1001 C Z C H 5 + ADD A, (HL+C) 1110 0101 0111 1001 C Z C H 5 + ADD A, (HL+) 1110 0110 0111 1001 C Z C H 4 + ADD A, (-HL) 1110 0111 0111 1001 C Z C H 4 + + SUBB A, (x) 1110 0000 xxxx xxxx 0111 1010 C Z C H 4 + SUBB A, (PC+A) 1110 0001 0111 1010 C Z C H 5 + SUBB A, (DE) 1110 0010 0111 1010 C Z C H 3 + SUBB A, (HL) 1110 0011 0111 1010 C Z C H 3 + SUBB A, (HL+d) 1110 0100 dddd dddd 0111 1010 C Z C H 5 + SUBB A, (HL+C) 1110 0101 0111 1010 C Z C H 5 + SUBB A, (HL+) 1110 0110 0111 1010 C Z C H 4 + SUBB A, (-HL) 1110 0111 0111 1010 C Z C H 4 + + SUB A, (x) 1110 0000 xxxx xxxx 0111 1011 C Z C H 4 + SUB A, (PC+A) 1110 0001 0111 1011 C Z C H 5 + SUB A, (DE) 1110 0010 0111 1011 C Z C H 3 + SUB A, (HL) 1110 0011 0111 1011 C Z C H 3 + SUB A, (HL+d) 1110 0100 dddd dddd 0111 1011 C Z C H 5 + SUB A, (HL+C) 1110 0101 0111 1011 C Z C H 5 + SUB A, (HL+) 1110 0110 0111 1011 C Z C H 4 + SUB A, (-HL) 1110 0111 0111 1011 C Z C H 4 + + AND A, (x) 1110 0000 xxxx xxxx 0111 1100 Z Z - - 4 + AND A, (PC+A) 1110 0001 0111 1100 Z Z - - 5 + AND A, (DE) 1110 0010 0111 1100 Z Z - - 3 + AND A, (HL) 1110 0011 0111 1100 Z Z - - 3 + AND A, (HL+d) 1110 0100 dddd dddd 0111 1100 Z Z - - 5 + AND A, (HL+C) 1110 0101 0111 1100 Z Z - - 5 + AND A, (HL+) 1110 0110 0111 1100 Z Z - - 4 + AND A, (-HL) 1110 0111 0111 1100 Z Z - - 4 + + XOR A, (x) 1110 0000 xxxx xxxx 0111 1101 Z Z - - 4 + XOR A, (PC+A) 1110 0001 0111 1101 Z Z - - 5 + XOR A, (DE) 1110 0010 0111 1101 Z Z - - 3 + XOR A, (HL) 1110 0011 0111 1101 Z Z - - 3 + XOR A, (HL+d) 1110 0100 dddd dddd 0111 1101 Z Z - - 5 + XOR A, (HL+C) 1110 0101 0111 1101 Z Z - - 5 + XOR A, (HL+) 1110 0110 0111 1101 Z Z - - 4 + XOR A, (-HL) 1110 0111 0111 1101 Z Z - - 4 + + OR A, (x) 1110 0000 xxxx xxxx 0111 1110 Z Z - - 4 + OR A, (PC+A) 1110 0001 0111 1110 Z Z - - 5 + OR A, (DE) 1110 0010 0111 1110 Z Z - - 3 + OR A, (HL) 1110 0011 0111 1110 Z Z - - 3 + OR A, (HL+d) 1110 0100 dddd dddd 0111 1110 Z Z - - 5 + OR A, (HL+C) 1110 0101 0111 1110 Z Z - - 5 + OR A, (HL+) 1110 0110 0111 1110 Z Z - - 4 + OR A, (-HL) 1110 0111 0111 1110 Z Z - - 4 + + CMP A, (x) 1110 0000 xxxx xxxx 0111 1111 Z Z C H 4 + CMP A, (PC+A) 1110 0001 0111 1111 Z Z C H 5 + CMP A, (DE) 1110 0010 0111 1111 Z Z C H 3 + CMP A, (HL) 1110 0011 0111 1111 Z Z C H 3 + CMP A, (HL+d) 1110 0100 dddd dddd 0111 1111 Z Z C H 5 + CMP A, (HL+C) 1110 0101 0111 1111 Z Z C H 5 + CMP A, (HL+) 1110 0110 0111 1111 Z Z C H 4 + CMP A, (-HL) 1110 0111 0111 1111 Z Z C H 4 + + aka (ALU OP) A, (src) */ m_cycles += 3; @@ -735,16 +735,16 @@ void tlcs870_device::do_CALL_insrc(const uint8_t opbyte0, const uint8_t opbyte1, { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - CALL (x) 1110 0000 xxxx xxxx 1111 1100 - - - - 9 - CALL (PC+A) 1110 0001 1111 1100 - - - - 10 - CALL (DE) 1110 0010 1111 1100 - - - - 8 - CALL (HL) 1110 0011 1111 1100 - - - - 8 - CALL (HL+d) 1110 0100 dddd dddd 1111 1100 - - - - 10 - CALL (HL+C) 1110 0101 1111 1100 - - - - 10 - CALL (HL+) not listed, invalid due to 16-bit op? ? ? ? ? ? - CALL (-HL) not listed, invalid due to 16-bit op? ? ? ? ? ? - - aka CALL (src) + CALL (x) 1110 0000 xxxx xxxx 1111 1100 - - - - 9 + CALL (PC+A) 1110 0001 1111 1100 - - - - 10 + CALL (DE) 1110 0010 1111 1100 - - - - 8 + CALL (HL) 1110 0011 1111 1100 - - - - 8 + CALL (HL+d) 1110 0100 dddd dddd 1111 1100 - - - - 10 + CALL (HL+C) 1110 0101 1111 1100 - - - - 10 + CALL (HL+) not listed, invalid due to 16-bit op? ? ? ? ? ? + CALL (-HL) not listed, invalid due to 16-bit op? ? ? ? ? ? + + aka CALL (src) */ m_cycles += 8; @@ -762,16 +762,16 @@ void tlcs870_device::do_JP_insrc(const uint8_t opbyte0, const uint8_t opbyte1, c { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - JP (x) 1110 0000 xxxx xxxx 1111 1110 1 - - - 6 - JP (PC+A) 1110 0001 1111 1110 1 - - - 7 - JP (DE) 1110 0010 1111 1110 1 - - - 5 - JP (HL) 1110 0011 1111 1110 1 - - - 5 - JP (HL+d) 1110 0100 dddd dddd 1111 1110 1 - - - 7 - JP (HL+C) 1110 0101 1111 1110 1 - - - 7 - JP (HL+) not listed, invalid due to 16-bit op? ? ? ? ? ? - JP (-HL) not listed, invalid due to 16-bit op? ? ? ? ? ? - - aka JP (src) + JP (x) 1110 0000 xxxx xxxx 1111 1110 1 - - - 6 + JP (PC+A) 1110 0001 1111 1110 1 - - - 7 + JP (DE) 1110 0010 1111 1110 1 - - - 5 + JP (HL) 1110 0011 1111 1110 1 - - - 5 + JP (HL+d) 1110 0100 dddd dddd 1111 1110 1 - - - 7 + JP (HL+C) 1110 0101 1111 1110 1 - - - 7 + JP (HL+) not listed, invalid due to 16-bit op? ? ? ? ? ? + JP (-HL) not listed, invalid due to 16-bit op? ? ? ? ? ? + + aka JP (src) */ m_cycles += 5; @@ -788,16 +788,16 @@ void tlcs870_device::do_XOR_CF_insrcbit(const uint8_t opbyte0, const uint8_t opb { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - XOR CF, (x).b 1110 0000 xxxx xxxx 1101 0bbb ~C - * - 4 - XOR CF, (PC+A).b 1110 0001 1101 0bbb ~C - * - 5 - XOR CF, (DE).b 1110 0010 1101 0bbb ~C - * - 3 - XOR CF, (HL).b 1110 0011 1101 0bbb ~C - * - 3 - XOR CF, (HL+d).b 1110 0100 dddd dddd 1101 0bbb ~C - * - 5 - XOR CF, (HL+C).b 1110 0101 1101 0bbb ~C - * - 5 - XOR CF, (HL+).b 1110 0110 1101 0bbb ~C - * - 4 - XOR CF, (-HL).b 1110 0111 1101 0bbb ~C - * - 4 - - aka XOR CF,(src).b + XOR CF, (x).b 1110 0000 xxxx xxxx 1101 0bbb ~C - * - 4 + XOR CF, (PC+A).b 1110 0001 1101 0bbb ~C - * - 5 + XOR CF, (DE).b 1110 0010 1101 0bbb ~C - * - 3 + XOR CF, (HL).b 1110 0011 1101 0bbb ~C - * - 3 + XOR CF, (HL+d).b 1110 0100 dddd dddd 1101 0bbb ~C - * - 5 + XOR CF, (HL+C).b 1110 0101 1101 0bbb ~C - * - 5 + XOR CF, (HL+).b 1110 0110 1101 0bbb ~C - * - 4 + XOR CF, (-HL).b 1110 0111 1101 0bbb ~C - * - 4 + + aka XOR CF,(src).b */ m_cycles += 3; @@ -843,16 +843,16 @@ void tlcs870_device::do_LD_insrcbit_CF(const uint8_t opbyte0, const uint8_t opby { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - LD (x).b, CF 1110 0000 xxxx xxxx 1100 1bbb 1 - - - 5 - LD (PC+A).b, CF 1110 0001 1100 1bbb 1 - - - 6 - LD (DE).b, CF 1110 0010 1100 1bbb 1 - - - 4 - LD (HL).b, CF 1110 0011 1100 1bbb 1 - - - 4 - LD (HL+d).b, CF 1110 0100 dddd dddd 1100 1bbb 1 - - - 6 - LD (HL+C).b, CF 1110 0101 1100 1bbb 1 - - - 6 - LD (HL+).b, CF 1110 0110 1100 1bbb 1 - - - 5 - LD (-HL).b, CF 1110 0111 1100 1bbb 1 - - - 5 - - aka LD (src).b,CF + LD (x).b, CF 1110 0000 xxxx xxxx 1100 1bbb 1 - - - 5 + LD (PC+A).b, CF 1110 0001 1100 1bbb 1 - - - 6 + LD (DE).b, CF 1110 0010 1100 1bbb 1 - - - 4 + LD (HL).b, CF 1110 0011 1100 1bbb 1 - - - 4 + LD (HL+d).b, CF 1110 0100 dddd dddd 1100 1bbb 1 - - - 6 + LD (HL+C).b, CF 1110 0101 1100 1bbb 1 - - - 6 + LD (HL+).b, CF 1110 0110 1100 1bbb 1 - - - 5 + LD (-HL).b, CF 1110 0111 1100 1bbb 1 - - - 5 + + aka LD (src).b,CF */ m_cycles += 4; @@ -881,16 +881,16 @@ void tlcs870_device::do_CPL_insrcbit(const uint8_t opbyte0, const uint8_t opbyte { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - CPL (x).b 1110 0000 xxxx xxxx 1100 0bbb Z * - - 5 - CPL (PC+A).b 1110 0001 1100 0bbb Z * - - 6 - CPL (DE).b 1110 0010 1100 0bbb Z * - - 4 - CPL (HL).b 1110 0011 1100 0bbb Z * - - 4 - CPL (HL+d).b 1110 0100 dddd dddd 1100 0bbb Z * - - 6 - CPL (HL+C).b 1110 0101 1100 0bbb Z * - - 6 - CPL (HL+).b 1110 0110 1100 0bbb Z * - - 5 - CPL (-HL).b 1110 0111 1100 0bbb Z * - - 5 - - aka CPL (src).b + CPL (x).b 1110 0000 xxxx xxxx 1100 0bbb Z * - - 5 + CPL (PC+A).b 1110 0001 1100 0bbb Z * - - 6 + CPL (DE).b 1110 0010 1100 0bbb Z * - - 4 + CPL (HL).b 1110 0011 1100 0bbb Z * - - 4 + CPL (HL+d).b 1110 0100 dddd dddd 1100 0bbb Z * - - 6 + CPL (HL+C).b 1110 0101 1100 0bbb Z * - - 6 + CPL (HL+).b 1110 0110 1100 0bbb Z * - - 5 + CPL (-HL).b 1110 0111 1100 0bbb Z * - - 5 + + aka CPL (src).b */ m_cycles += 4; @@ -924,16 +924,16 @@ void tlcs870_device::do_LD_CF_insrcbit(const uint8_t opbyte0, const uint8_t opby { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - LD CF, (x).b 1110 0000 xxxx xxxx 1101 1bbb ~C - * - 4 - LD CF, (PC+A).b 1110 0001 1101 1bbb ~C - * - 5 - LD CF, (DE).b 1110 0010 1101 1bbb ~C - * - 3 - LD CF, (HL).b 1110 0011 1101 1bbb ~C - * - 3 - LD CF, (HL+d).b 1110 0100 dddd dddd 1101 1bbb ~C - * - 5 - LD CF, (HL+C).b 1110 0101 1101 1bbb ~C - * - 5 - LD CF, (HL+).b 1110 0110 1101 1bbb ~C - * - 4 - LD CF, (-HL).b 1110 0111 1101 1bbb ~C - * - 4 - - aka LD CF,(src).b or TEST (src).b + LD CF, (x).b 1110 0000 xxxx xxxx 1101 1bbb ~C - * - 4 + LD CF, (PC+A).b 1110 0001 1101 1bbb ~C - * - 5 + LD CF, (DE).b 1110 0010 1101 1bbb ~C - * - 3 + LD CF, (HL).b 1110 0011 1101 1bbb ~C - * - 3 + LD CF, (HL+d).b 1110 0100 dddd dddd 1101 1bbb ~C - * - 5 + LD CF, (HL+C).b 1110 0101 1101 1bbb ~C - * - 5 + LD CF, (HL+).b 1110 0110 1101 1bbb ~C - * - 4 + LD CF, (-HL).b 1110 0111 1101 1bbb ~C - * - 4 + + aka LD CF,(src).b or TEST (src).b */ m_cycles += 3; @@ -953,16 +953,16 @@ void tlcs870_device::do_SET_insrcbit(const uint8_t opbyte0, const uint8_t opbyte { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - SET (x).b 1110 0000 xxxx xxxx 0100 0bbb Z * - - 5 - SET (PC+A).b 1110 0001 0100 0bbb Z * - - 6 - SET (DE).b 1110 0010 0100 0bbb Z * - - 4 - SET (HL).b 1110 0011 0100 0bbb Z * - - 4 - SET (HL+d).b 1110 0100 dddd dddd 0100 0bbb Z * - - 6 - SET (HL+C).b 1110 0101 0100 0bbb Z * - - 6 - SET (HL+).b 1110 0110 0100 0bbb Z * - - 5 - SET (-HL).b 1110 0111 0100 0bbb Z * - - 5 - - aka SET (src).b + SET (x).b 1110 0000 xxxx xxxx 0100 0bbb Z * - - 5 + SET (PC+A).b 1110 0001 0100 0bbb Z * - - 6 + SET (DE).b 1110 0010 0100 0bbb Z * - - 4 + SET (HL).b 1110 0011 0100 0bbb Z * - - 4 + SET (HL+d).b 1110 0100 dddd dddd 0100 0bbb Z * - - 6 + SET (HL+C).b 1110 0101 0100 0bbb Z * - - 6 + SET (HL+).b 1110 0110 0100 0bbb Z * - - 5 + SET (-HL).b 1110 0111 0100 0bbb Z * - - 5 + + aka SET (src).b */ m_cycles += 4; @@ -992,16 +992,16 @@ void tlcs870_device::do_CLR_insrcbit(const uint8_t opbyte0, const uint8_t opbyte { /* OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles - CLR (x).b 1110 0000 xxxx xxxx 0100 1bbb Z * - - 5 - CLR (PC+A).b 1110 0001 0100 1bbb Z * - - 6 - CLR (DE).b 1110 0010 0100 1bbb Z * - - 4 - CLR (HL).b 1110 0011 0100 1bbb Z * - - 4 - CLR (HL+d).b 1110 0100 dddd dddd 0100 1bbb Z * - - 6 - CLR (HL+C).b 1110 0101 0100 1bbb Z * - - 6 - CLR (HL+).b 1110 0110 0100 1bbb Z * - - 5 - CLR (-HL).b 1110 0111 0100 1bbb Z * - - 5 - - aka CLR (src).b + CLR (x).b 1110 0000 xxxx xxxx 0100 1bbb Z * - - 5 + CLR (PC+A).b 1110 0001 0100 1bbb Z * - - 6 + CLR (DE).b 1110 0010 0100 1bbb Z * - - 4 + CLR (HL).b 1110 0011 0100 1bbb Z * - - 4 + CLR (HL+d).b 1110 0100 dddd dddd 0100 1bbb Z * - - 6 + CLR (HL+C).b 1110 0101 0100 1bbb Z * - - 6 + CLR (HL+).b 1110 0110 0100 1bbb Z * - - 5 + CLR (-HL).b 1110 0111 0100 1bbb Z * - - 5 + + aka CLR (src).b */ m_cycles += 4; diff --git a/src/devices/cpu/tlcs870/tlcs870d.cpp b/src/devices/cpu/tlcs870/tlcs870d.cpp index 50b7b12f05d..7900e764158 100644 --- a/src/devices/cpu/tlcs870/tlcs870d.cpp +++ b/src/devices/cpu/tlcs870/tlcs870d.cpp @@ -1469,7 +1469,7 @@ void tlcs870_disassembler::decode_register_prefix(uint8_t b0) case 0xae: case 0xaf: // XCH r,g - m_op = XCH; + m_op = XCH; //m_flagsaffected |= FLAG_J | FLAG_Z; |