diff options
Diffstat (limited to 'src/devices/cpu/sparc/sparcdefs.h')
-rw-r--r-- | src/devices/cpu/sparc/sparcdefs.h | 129 |
1 files changed, 114 insertions, 15 deletions
diff --git a/src/devices/cpu/sparc/sparcdefs.h b/src/devices/cpu/sparc/sparcdefs.h index f023da44679..19784b173a7 100644 --- a/src/devices/cpu/sparc/sparcdefs.h +++ b/src/devices/cpu/sparc/sparcdefs.h @@ -2,15 +2,15 @@ // copyright-holders:Ryan Holtz //================================================================ // -// mb86901defs.h - Helpful #defines for emulating the MB86901 -// series of SPARC processor. +// sparcdefs.h - Helpful #defines for emulating the MB86901 +// series of SPARC processor. // //================================================================ -#pragma once +#ifndef MAME_CPU_SPARC_SPARCDEFS_H +#define MAME_CPU_SPARC_SPARCDEFS_H -#ifndef __MB86901_DEFS_H__ -#define __MB86901_DEFS_H__ +#pragma once #define PSR_CWP_MASK 0x0000001f #define PSR_ET_SHIFT 5 @@ -85,6 +85,8 @@ #define WIM m_wim #define TBR m_tbr +#define NWINDOWS m_nwindows + #define OP_NS (op & 0xc0000000) #define OP (op >> 30) @@ -95,17 +97,17 @@ #define OPFLOW ((op >> 5) & 0x3f) #define DISP30 (int32_t(op << 2)) -#define DISP22 (int32_t(op << 10) >> 8) -#define DISP19 (int32_t(op << 13) >> 11) -#define DISP16 (int32_t(((op << 10) & 0xc0000000) | ((op << 16) & 0x3fff0000)) >> 14) +#define DISP22 util::sext(op << 2, 24) +#define DISP19 util::sext(op << 2, 21) +#define DISP16 util::sext((op & 0x300000) >> 4 | (op & 0x3fff) << 2, 18) #define IMM22 (op << 10) #define CONST22 (op & 0x3fffff) -#define SIMM13 (int32_t(op << 19) >> 19) -#define SIMM11 (int32_t(op << 21) >> 21) -#define SIMM10 (int32_t(op << 22) >> 22) -#define SIMM8 (int32_t(op << 24) >> 24) +#define SIMM13 util::sext(op, 13) +#define SIMM11 util::sext(op, 11) +#define SIMM10 util::sext(op, 10) +#define SIMM8 util::sext(op, 8) #define IMM7 (op & 0x7f) -#define SIMM7 (int32_t(op << 25) >> 25) +#define SIMM7 util::sext(op, 7) #define SHCNT32 (op & 31) #define SHCNT64 (op & 63) #define IAMODE (op & 0x7) @@ -127,9 +129,12 @@ #define CMASK ((op >> 4) & 7) #define RD ((op >> 25) & 31) +#define RD_D ((op >> 25) & 30) #define RDBITS (op & 0x3e000000) #define RS1 ((op >> 14) & 31) +#define RS1_D ((op >> 14) & 30) #define RS2 (op & 31) +#define RS2_D (op & 30) #define FREG(x) m_fpr[(x)] #define FDREG m_fpr[RD] @@ -139,7 +144,7 @@ #define RDREG *m_regs[RD] #define RS1REG *m_regs[RS1] #define RS2REG *m_regs[RS2] -#define SET_RDREG(x) do { if(RD) { RDREG = (x); } } while (0) +#define SET_RDREG(x) do { if(RDBITS) { RDREG = (x); } } while (0) #define ADDRESS (USEIMM ? (RS1REG + SIMM13) : (RS1REG + RS2REG)) #define PC m_pc @@ -197,6 +202,7 @@ #define OP3_UMULCC 26 #define OP3_SMULCC 27 #define OP3_SUBXCC 28 +#define OP3_DIVSCC 29 #define OP3_UDIVCC 30 #define OP3_SDIVCC 31 #define OP3_TADDCC 32 @@ -211,6 +217,7 @@ #define OP3_RDPSR 41 #define OP3_RDWIM 42 #define OP3_RDTBR 43 +#define OP3_SCAN 44 #define OP3_WRASR 48 #define OP3_WRPSR 49 #define OP3_WRWIM 50 @@ -386,4 +393,96 @@ #define SDIV (OP3 == OP3_SDIV) #define SDIVCC (OP3 == OP3_SDIVCC) -#endif // __MB86901_DEFS_H__ +#define FSR_CEXC_MASK 0x0000001f +#define FSR_CEXC_NXC 0x00000001 +#define FSR_CEXC_DZC 0x00000002 +#define FSR_CEXC_UFC 0x00000004 +#define FSR_CEXC_OFC 0x00000008 +#define FSR_CEXC_NVC 0x00000010 + +#define FSR_AEXC_SHIFT 5 +#define FSR_AEXC_MASK 0x000003e0 +#define FSR_AEXC_NXA 0x00000020 +#define FSR_AEXC_DZA 0x00000040 +#define FSR_AEXC_UFA 0x00000080 +#define FSR_AEXC_OFA 0x00000100 +#define FSR_AEXC_NVA 0x00000200 + +#define FSR_FCC_SHIFT 10 +#define FSR_FCC_MASK 0x00000c00 +#define FSR_FCC_EQ 0x00000000 +#define FSR_FCC_LT 0x00000400 +#define FSR_FCC_GT 0x00000800 +#define FSR_FCC_UO 0x00000c00 + +#define FSR_QNE 0x00002000 + +#define FSR_FTT_MASK 0x0001c000 +#define FSR_FTT_NONE 0x00000000 +#define FSR_FTT_IEEE 0x00004000 +#define FSR_FTT_UNFIN 0x00008000 +#define FSR_FTT_UNIMP 0x0000c000 +#define FSR_FTT_SEQ 0x00010000 + +#define FSR_VER 0x00020000 + +#define FSR_NS 0x00400000 + +#define FSR_TEM_SHIFT 23 +#define FSR_TEM_MASK 0x0f800000 +#define FSR_TEM_NXM 0x00800000 +#define FSR_TEM_DZM 0x01000000 +#define FSR_TEM_UFM 0x02000000 +#define FSR_TEM_OFM 0x04000000 +#define FSR_TEM_NVM 0x08000000 + +#define FSR_RD_SHIFT 30 +#define FSR_RD_MASK 0xc0000000 +#define FSR_RD_NEAR 0x00000000 +#define FSR_RD_ZERO 0x40000000 +#define FSR_RD_UP 0x80000000 +#define FSR_RD_DOWN 0xc0000000 + +#define FSR_RESV_MASK 0x30301000 + +// FPop1 +#define FPOP_FMOVS 0x001 +#define FPOP_FNEGS 0x005 +#define FPOP_FABSS 0x009 +#define FPOP_FSQRTS 0x029 +#define FPOP_FSQRTD 0x02a +#define FPOP_FSQRTX 0x02b +#define FPOP_FADDS 0x041 +#define FPOP_FADDD 0x042 +#define FPOP_FADDX 0x043 +#define FPOP_FSUBS 0x045 +#define FPOP_FSUBD 0x046 +#define FPOP_FSUBX 0x047 +#define FPOP_FMULS 0x049 +#define FPOP_FMULD 0x04a +#define FPOP_FMULX 0x04b +#define FPOP_FDIVS 0x04d +#define FPOP_FDIVD 0x04e +#define FPOP_FDIVX 0x04f +#define FPOP_FITOS 0x0c4 +#define FPOP_FDTOS 0x0c6 +#define FPOP_FXTOS 0x0c7 +#define FPOP_FITOD 0x0c8 +#define FPOP_FSTOD 0x0c9 +#define FPOP_FXTOD 0x0cb +#define FPOP_FITOX 0x0cc +#define FPOP_FSTOX 0x0cd +#define FPOP_FDTOX 0x0ce +#define FPOP_FSTOI 0x0d1 +#define FPOP_FDTOI 0x0d2 +#define FPOP_FXTOI 0x0d3 + +// FPop2 +#define FPOP_FCMPS 0x051 +#define FPOP_FCMPD 0x052 +#define FPOP_FCMPX 0x053 +#define FPOP_FCMPES 0x055 +#define FPOP_FCMPED 0x056 +#define FPOP_FCMPEX 0x057 + +#endif // MAME_CPU_SPARC_SPARCDEFS_H |