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-rw-r--r--src/devices/cpu/sh/sh.cpp1493
-rw-r--r--src/devices/cpu/sh/sh.h23
-rw-r--r--src/devices/cpu/sh/sh2.cpp211
-rw-r--r--src/devices/cpu/sh/sh2.h15
-rw-r--r--src/devices/cpu/sh/sh2fe.cpp2
-rw-r--r--src/devices/cpu/sh/sh3comn.cpp224
-rw-r--r--src/devices/cpu/sh/sh4.cpp736
-rw-r--r--src/devices/cpu/sh/sh4.h31
-rw-r--r--src/devices/cpu/sh/sh4comn.cpp428
-rw-r--r--src/devices/cpu/sh/sh4comn.h25
-rw-r--r--src/devices/cpu/sh/sh4dmac.cpp190
-rw-r--r--src/devices/cpu/sh/sh4fe.cpp14
-rw-r--r--src/devices/cpu/sh/sh7021.cpp2219
-rw-r--r--src/devices/cpu/sh/sh7021.h328
-rw-r--r--src/devices/cpu/sh/sh7604.cpp456
-rw-r--r--src/devices/cpu/sh/sh7604.h17
-rw-r--r--src/devices/cpu/sh/sh7604_bus.cpp54
-rw-r--r--src/devices/cpu/sh/sh7604_sci.cpp22
-rw-r--r--src/devices/cpu/sh/sh7604_sci.h3
-rw-r--r--src/devices/cpu/sh/sh7604_wdt.cpp8
-rw-r--r--src/devices/cpu/sh/sh_dasm.cpp41
-rw-r--r--src/devices/cpu/sh/sh_fe.cpp250
22 files changed, 4594 insertions, 2196 deletions
diff --git a/src/devices/cpu/sh/sh.cpp b/src/devices/cpu/sh/sh.cpp
index 2a7c198668f..65b93057d00 100644
--- a/src/devices/cpu/sh/sh.cpp
+++ b/src/devices/cpu/sh/sh.cpp
@@ -169,7 +169,7 @@ void sh_common_execution::ADD(uint32_t m, uint32_t n)
*/
void sh_common_execution::ADDI(uint32_t i, uint32_t n)
{
- m_sh2_state->r[n] += (int32_t)(int16_t)(int8_t)i;
+ m_sh2_state->r[n] += util::sext(i, 8);
}
/* code cycles t-bit
@@ -197,24 +197,16 @@ void sh_common_execution::ADDC(uint32_t m, uint32_t n)
*/
void sh_common_execution::ADDV(uint32_t m, uint32_t n)
{
- int32_t dest, src, ans;
-
- if ((int32_t) m_sh2_state->r[n] >= 0)
- dest = 0;
- else
- dest = 1;
- if ((int32_t) m_sh2_state->r[m] >= 0)
- src = 0;
- else
- src = 1;
+ int32_t dest = BIT(m_sh2_state->r[n], 31);
+ int32_t src = BIT(m_sh2_state->r[m], 31);
src += dest;
+
m_sh2_state->r[n] += m_sh2_state->r[m];
- if ((int32_t) m_sh2_state->r[n] >= 0)
- ans = 0;
- else
- ans = 1;
+
+ int32_t ans = BIT(m_sh2_state->r[n], 31);
ans += dest;
- if (src == 0 || src == 2)
+
+ if (src != 1)
{
if (ans == 1)
m_sh2_state->sr |= SH_T;
@@ -249,11 +241,9 @@ void sh_common_execution::ANDI(uint32_t i)
*/
void sh_common_execution::ANDM(uint32_t i)
{
- uint32_t temp;
-
m_sh2_state->ea = m_sh2_state->gbr + m_sh2_state->r[0];
- temp = i & RB( m_sh2_state->ea );
- WB( m_sh2_state->ea, temp );
+ uint32_t temp = i & read_byte(m_sh2_state->ea);
+ write_byte(m_sh2_state->ea, temp);
m_sh2_state->icount -= 2;
}
@@ -296,7 +286,7 @@ void sh_common_execution::BRA(uint32_t d)
#if BUSY_LOOP_HACKS
if (disp == -2)
{
- uint32_t next_opcode = RW(m_sh2_state->pc & AM);
+ uint32_t next_opcode = read_word(m_sh2_state->pc & m_am);
/* BRA $
* NOP
*/
@@ -407,7 +397,7 @@ void sh_common_execution::CMPEQ(uint32_t m, uint32_t n)
*/
void sh_common_execution::CMPGE(uint32_t m, uint32_t n)
{
- if ((int32_t) m_sh2_state->r[n] >= (int32_t) m_sh2_state->r[m])
+ if ((int32_t)m_sh2_state->r[n] >= (int32_t)m_sh2_state->r[m])
m_sh2_state->sr |= SH_T;
else
m_sh2_state->sr &= ~SH_T;
@@ -419,7 +409,7 @@ void sh_common_execution::CMPGE(uint32_t m, uint32_t n)
*/
void sh_common_execution::CMPGT(uint32_t m, uint32_t n)
{
- if ((int32_t) m_sh2_state->r[n] > (int32_t) m_sh2_state->r[m])
+ if ((int32_t)m_sh2_state->r[n] > (int32_t)m_sh2_state->r[m])
m_sh2_state->sr |= SH_T;
else
m_sh2_state->sr &= ~SH_T;
@@ -431,7 +421,7 @@ void sh_common_execution::CMPGT(uint32_t m, uint32_t n)
*/
void sh_common_execution::CMPHI(uint32_t m, uint32_t n)
{
- if ((uint32_t) m_sh2_state->r[n] > (uint32_t) m_sh2_state->r[m])
+ if (m_sh2_state->r[n] > m_sh2_state->r[m])
m_sh2_state->sr |= SH_T;
else
m_sh2_state->sr &= ~SH_T;
@@ -443,7 +433,7 @@ void sh_common_execution::CMPHI(uint32_t m, uint32_t n)
*/
void sh_common_execution::CMPHS(uint32_t m, uint32_t n)
{
- if ((uint32_t) m_sh2_state->r[n] >= (uint32_t) m_sh2_state->r[m])
+ if (m_sh2_state->r[n] >= m_sh2_state->r[m])
m_sh2_state->sr |= SH_T;
else
m_sh2_state->sr &= ~SH_T;
@@ -455,7 +445,7 @@ void sh_common_execution::CMPHS(uint32_t m, uint32_t n)
*/
void sh_common_execution::CMPPL(uint32_t n)
{
- if ((int32_t) m_sh2_state->r[n] > 0)
+ if ((int32_t)m_sh2_state->r[n] > 0)
m_sh2_state->sr |= SH_T;
else
m_sh2_state->sr &= ~SH_T;
@@ -467,7 +457,7 @@ void sh_common_execution::CMPPL(uint32_t n)
*/
void sh_common_execution::CMPPZ(uint32_t n)
{
- if ((int32_t) m_sh2_state->r[n] >= 0)
+ if ((int32_t)m_sh2_state->r[n] >= 0)
m_sh2_state->sr |= SH_T;
else
m_sh2_state->sr &= ~SH_T;
@@ -479,14 +469,12 @@ void sh_common_execution::CMPPZ(uint32_t n)
*/
void sh_common_execution::CMPSTR(uint32_t m, uint32_t n)
{
- uint32_t temp;
- int32_t HH, HL, LH, LL;
- temp = m_sh2_state->r[n] ^ m_sh2_state->r[m];
- HH = (temp >> 24) & 0xff;
- HL = (temp >> 16) & 0xff;
- LH = (temp >> 8) & 0xff;
- LL = temp & 0xff;
- if (HH && HL && LH && LL)
+ uint32_t temp = m_sh2_state->r[n] ^ m_sh2_state->r[m];
+ uint8_t upper_byte = (temp >> 24) & 0xff;
+ uint8_t mid_upper_byte = (temp >> 16) & 0xff;
+ uint8_t mid_lower_byte = (temp >> 8) & 0xff;
+ uint8_t lower_byte = temp & 0xff;
+ if (upper_byte && mid_upper_byte && mid_lower_byte && lower_byte)
m_sh2_state->sr &= ~SH_T;
else
m_sh2_state->sr |= SH_T;
@@ -498,7 +486,7 @@ void sh_common_execution::CMPSTR(uint32_t m, uint32_t n)
*/
void sh_common_execution::CMPIM(uint32_t i)
{
- uint32_t imm = (uint32_t)(int32_t)(int16_t)(int8_t)i;
+ uint32_t imm = (uint32_t)util::sext(i, 8);
if (m_sh2_state->r[0] == imm)
m_sh2_state->sr |= SH_T;
@@ -512,15 +500,17 @@ void sh_common_execution::CMPIM(uint32_t i)
*/
void sh_common_execution::DIV0S(uint32_t m, uint32_t n)
{
- if ((m_sh2_state->r[n] & 0x80000000) == 0)
+ if (!BIT(m_sh2_state->r[n], 31))
m_sh2_state->sr &= ~SH_Q;
else
m_sh2_state->sr |= SH_Q;
- if ((m_sh2_state->r[m] & 0x80000000) == 0)
+
+ if (!BIT(m_sh2_state->r[m], 31))
m_sh2_state->sr &= ~SH_M;
else
m_sh2_state->sr |= SH_M;
- if ((m_sh2_state->r[m] ^ m_sh2_state->r[n]) & 0x80000000)
+
+ if (BIT(m_sh2_state->r[m] ^ m_sh2_state->r[n], 31))
m_sh2_state->sr |= SH_T;
else
m_sh2_state->sr &= ~SH_T;
@@ -541,10 +531,7 @@ void sh_common_execution::DIV0U()
*/
void sh_common_execution::DIV1(uint32_t m, uint32_t n)
{
- uint32_t tmp0;
- uint32_t old_q;
-
- old_q = m_sh2_state->sr & SH_Q;
+ uint32_t old_q = m_sh2_state->sr & SH_Q;
if (0x80000000 & m_sh2_state->r[n])
m_sh2_state->sr |= SH_Q;
else
@@ -556,33 +543,33 @@ void sh_common_execution::DIV1(uint32_t m, uint32_t n)
{
if (!(m_sh2_state->sr & SH_M))
{
- tmp0 = m_sh2_state->r[n];
+ uint32_t tmp = m_sh2_state->r[n];
m_sh2_state->r[n] -= m_sh2_state->r[m];
- if(!(m_sh2_state->sr & SH_Q))
- if(m_sh2_state->r[n] > tmp0)
+ if (!(m_sh2_state->sr & SH_Q))
+ if (m_sh2_state->r[n] > tmp)
m_sh2_state->sr |= SH_Q;
else
m_sh2_state->sr &= ~SH_Q;
else
- if(m_sh2_state->r[n] > tmp0)
+ if (m_sh2_state->r[n] > tmp)
m_sh2_state->sr &= ~SH_Q;
else
m_sh2_state->sr |= SH_Q;
}
else
{
- tmp0 = m_sh2_state->r[n];
+ uint32_t tmp = m_sh2_state->r[n];
m_sh2_state->r[n] += m_sh2_state->r[m];
- if(!(m_sh2_state->sr & SH_Q))
+ if (!(m_sh2_state->sr & SH_Q))
{
- if(m_sh2_state->r[n] < tmp0)
+ if (m_sh2_state->r[n] < tmp)
m_sh2_state->sr &= ~SH_Q;
else
m_sh2_state->sr |= SH_Q;
}
else
{
- if(m_sh2_state->r[n] < tmp0)
+ if (m_sh2_state->r[n] < tmp)
m_sh2_state->sr |= SH_Q;
else
m_sh2_state->sr &= ~SH_Q;
@@ -593,38 +580,38 @@ void sh_common_execution::DIV1(uint32_t m, uint32_t n)
{
if (!(m_sh2_state->sr & SH_M))
{
- tmp0 = m_sh2_state->r[n];
+ uint32_t tmp = m_sh2_state->r[n];
m_sh2_state->r[n] += m_sh2_state->r[m];
- if(!(m_sh2_state->sr & SH_Q))
- if(m_sh2_state->r[n] < tmp0)
+ if (!(m_sh2_state->sr & SH_Q))
+ if (m_sh2_state->r[n] < tmp)
m_sh2_state->sr |= SH_Q;
else
m_sh2_state->sr &= ~SH_Q;
else
- if(m_sh2_state->r[n] < tmp0)
+ if (m_sh2_state->r[n] < tmp)
m_sh2_state->sr &= ~SH_Q;
else
m_sh2_state->sr |= SH_Q;
}
else
{
- tmp0 = m_sh2_state->r[n];
+ uint32_t tmp = m_sh2_state->r[n];
m_sh2_state->r[n] -= m_sh2_state->r[m];
- if(!(m_sh2_state->sr & SH_Q))
- if(m_sh2_state->r[n] > tmp0)
+ if (!(m_sh2_state->sr & SH_Q))
+ if (m_sh2_state->r[n] > tmp)
m_sh2_state->sr &= ~SH_Q;
else
m_sh2_state->sr |= SH_Q;
else
- if(m_sh2_state->r[n] > tmp0)
+ if (m_sh2_state->r[n] > tmp)
m_sh2_state->sr |= SH_Q;
else
m_sh2_state->sr &= ~SH_Q;
}
}
- tmp0 = (m_sh2_state->sr & (SH_Q | SH_M));
- if((!tmp0) || (tmp0 == 0x300)) /* if Q == M set T else clear T */
+ uint32_t tmp = (m_sh2_state->sr & (SH_Q | SH_M));
+ if (tmp == 0 || tmp == 0x300) /* if Q == M set T else clear T */
m_sh2_state->sr |= SH_T;
else
m_sh2_state->sr &= ~SH_T;
@@ -633,77 +620,77 @@ void sh_common_execution::DIV1(uint32_t m, uint32_t n)
/* DMULS.L Rm,Rn */
void sh_common_execution::DMULS(uint32_t m, uint32_t n)
{
- uint32_t RnL, RnH, RmL, RmH, Res0, Res1, Res2;
- uint32_t temp0, temp1, temp2, temp3;
- int32_t tempm, tempn, fnLmL;
+ int32_t tempn = (int32_t)m_sh2_state->r[n];
+ int32_t tempm = (int32_t)m_sh2_state->r[m];
+ bool fnlml = (bool)BIT(tempn ^ tempm, 31);
- tempn = (int32_t) m_sh2_state->r[n];
- tempm = (int32_t) m_sh2_state->r[m];
if (tempn < 0)
tempn = 0 - tempn;
if (tempm < 0)
tempm = 0 - tempm;
- if ((int32_t) (m_sh2_state->r[n] ^ m_sh2_state->r[m]) < 0)
- fnLmL = -1;
- else
- fnLmL = 0;
- temp1 = (uint32_t) tempn;
- temp2 = (uint32_t) tempm;
- RnL = temp1 & 0x0000ffff;
- RnH = (temp1 >> 16) & 0x0000ffff;
- RmL = temp2 & 0x0000ffff;
- RmH = (temp2 >> 16) & 0x0000ffff;
- temp0 = RmL * RnL;
- temp1 = RmH * RnL;
- temp2 = RmL * RnH;
- temp3 = RmH * RnH;
- Res2 = 0;
- Res1 = temp1 + temp2;
- if (Res1 < temp1)
- Res2 += 0x00010000;
- temp1 = (Res1 << 16) & 0xffff0000;
- Res0 = temp0 + temp1;
- if (Res0 < temp0)
- Res2++;
- Res2 = Res2 + ((Res1 >> 16) & 0x0000ffff) + temp3;
- if (fnLmL < 0)
+
+ uint32_t rn_l = (uint32_t)tempn & 0x0000ffff;
+ uint32_t rn_h = (uint32_t)tempn >> 16;
+ uint32_t rm_l = (uint32_t)tempm & 0x0000ffff;
+ uint32_t rm_h = (uint32_t)tempm >> 16;
+
+ uint32_t temp0 = rm_l * rn_l;
+ uint32_t temp1 = rm_h * rn_l;
+ uint32_t temp2 = rm_l * rn_h;
+ uint32_t temp3 = rm_h * rn_h;
+
+ uint32_t res2 = 0;
+ uint32_t res1 = temp1 + temp2;
+ if (res1 < temp1)
+ res2 += 0x00010000;
+ temp1 = res1 << 16;
+
+ uint32_t res0 = temp0 + temp1;
+ if (res0 < temp0)
+ res2++;
+ res2 = res2 + (res1 >> 16) + temp3;
+
+ if (fnlml)
{
- Res2 = ~Res2;
- if (Res0 == 0)
- Res2++;
+ res2 = ~res2;
+ if (res0 == 0)
+ res2++;
else
- Res0 = (~Res0) + 1;
+ res0 = (~res0) + 1;
}
- m_sh2_state->mach = Res2;
- m_sh2_state->macl = Res0;
+
+ m_sh2_state->mach = res2;
+ m_sh2_state->macl = res0;
m_sh2_state->icount--;
}
/* DMULU.L Rm,Rn */
void sh_common_execution::DMULU(uint32_t m, uint32_t n)
{
- uint32_t RnL, RnH, RmL, RmH, Res0, Res1, Res2;
- uint32_t temp0, temp1, temp2, temp3;
-
- RnL = m_sh2_state->r[n] & 0x0000ffff;
- RnH = (m_sh2_state->r[n] >> 16) & 0x0000ffff;
- RmL = m_sh2_state->r[m] & 0x0000ffff;
- RmH = (m_sh2_state->r[m] >> 16) & 0x0000ffff;
- temp0 = RmL * RnL;
- temp1 = RmH * RnL;
- temp2 = RmL * RnH;
- temp3 = RmH * RnH;
- Res2 = 0;
- Res1 = temp1 + temp2;
- if (Res1 < temp1)
- Res2 += 0x00010000;
- temp1 = (Res1 << 16) & 0xffff0000;
- Res0 = temp0 + temp1;
- if (Res0 < temp0)
- Res2++;
- Res2 = Res2 + ((Res1 >> 16) & 0x0000ffff) + temp3;
- m_sh2_state->mach = Res2;
- m_sh2_state->macl = Res0;
+ uint32_t rn_l = m_sh2_state->r[n] & 0x0000ffff;
+ uint32_t rn_h = m_sh2_state->r[n] >> 16;
+ uint32_t rm_l = m_sh2_state->r[m] & 0x0000ffff;
+ uint32_t rm_h = m_sh2_state->r[m] >> 16;
+
+ uint32_t temp0 = rm_l * rn_l;
+ uint32_t temp1 = rm_h * rn_l;
+ uint32_t temp2 = rm_l * rn_h;
+ uint32_t temp3 = rm_h * rn_h;
+
+ uint32_t res2 = 0;
+ uint32_t res1 = temp1 + temp2;
+ if (res1 < temp1)
+ res2 += 0x00010000;
+
+ temp1 = res1 << 16;
+ uint32_t res0 = temp0 + temp1;
+ if (res0 < temp0)
+ res2++;
+
+ res2 = res2 + (res1 >> 16) + temp3;
+
+ m_sh2_state->mach = res2;
+ m_sh2_state->macl = res0;
m_sh2_state->icount--;
}
@@ -717,7 +704,7 @@ void sh_common_execution::DT(uint32_t n)
m_sh2_state->sr &= ~SH_T;
#if BUSY_LOOP_HACKS
{
- uint32_t next_opcode = RW(m_sh2_state->pc & AM);
+ uint32_t next_opcode = read_word(m_sh2_state->pc & AM);
/* DT Rn
* BF $-2
*/
@@ -788,7 +775,7 @@ void sh_common_execution::LDCVBR(uint32_t m)
void sh_common_execution::LDCMGBR(uint32_t m)
{
m_sh2_state->ea = m_sh2_state->r[m];
- m_sh2_state->gbr = RL( m_sh2_state->ea );
+ m_sh2_state->gbr = read_long(m_sh2_state->ea);
m_sh2_state->r[m] += 4;
m_sh2_state->icount -= 2;
}
@@ -797,7 +784,7 @@ void sh_common_execution::LDCMGBR(uint32_t m)
void sh_common_execution::LDCMVBR(uint32_t m)
{
m_sh2_state->ea = m_sh2_state->r[m];
- m_sh2_state->vbr = RL( m_sh2_state->ea );
+ m_sh2_state->vbr = read_long(m_sh2_state->ea);
m_sh2_state->r[m] += 4;
m_sh2_state->icount -= 2;
}
@@ -824,7 +811,7 @@ void sh_common_execution::LDSPR(uint32_t m)
void sh_common_execution::LDSMMACH(uint32_t m)
{
m_sh2_state->ea = m_sh2_state->r[m];
- m_sh2_state->mach = RL( m_sh2_state->ea );
+ m_sh2_state->mach = read_long(m_sh2_state->ea);
m_sh2_state->r[m] += 4;
}
@@ -832,7 +819,7 @@ void sh_common_execution::LDSMMACH(uint32_t m)
void sh_common_execution::LDSMMACL(uint32_t m)
{
m_sh2_state->ea = m_sh2_state->r[m];
- m_sh2_state->macl = RL( m_sh2_state->ea );
+ m_sh2_state->macl = read_long(m_sh2_state->ea);
m_sh2_state->r[m] += 4;
}
@@ -840,83 +827,83 @@ void sh_common_execution::LDSMMACL(uint32_t m)
void sh_common_execution::LDSMPR(uint32_t m)
{
m_sh2_state->ea = m_sh2_state->r[m];
- m_sh2_state->pr = RL( m_sh2_state->ea );
+ m_sh2_state->pr = read_long(m_sh2_state->ea);
m_sh2_state->r[m] += 4;
}
/* MAC.L @Rm+,@Rn+ */
void sh_common_execution::MAC_L(uint32_t m, uint32_t n)
{
- uint32_t RnL, RnH, RmL, RmH, Res0, Res1, Res2;
- uint32_t temp0, temp1, temp2, temp3;
- int32_t tempm, tempn, fnLmL;
-
- tempn = (int32_t) RL( m_sh2_state->r[n] );
+ int32_t tempn = (int32_t)read_long(m_sh2_state->r[n]);
m_sh2_state->r[n] += 4;
- tempm = (int32_t) RL( m_sh2_state->r[m] );
+
+ int32_t tempm = (int32_t)read_long(m_sh2_state->r[m]);
m_sh2_state->r[m] += 4;
- if ((int32_t) (tempn ^ tempm) < 0)
- fnLmL = -1;
- else
- fnLmL = 0;
+
+ bool fnlml = BIT(tempn ^ tempm, 31);
+
if (tempn < 0)
tempn = 0 - tempn;
if (tempm < 0)
tempm = 0 - tempm;
- temp1 = (uint32_t) tempn;
- temp2 = (uint32_t) tempm;
- RnL = temp1 & 0x0000ffff;
- RnH = (temp1 >> 16) & 0x0000ffff;
- RmL = temp2 & 0x0000ffff;
- RmH = (temp2 >> 16) & 0x0000ffff;
- temp0 = RmL * RnL;
- temp1 = RmH * RnL;
- temp2 = RmL * RnH;
- temp3 = RmH * RnH;
- Res2 = 0;
- Res1 = temp1 + temp2;
- if (Res1 < temp1)
- Res2 += 0x00010000;
- temp1 = (Res1 << 16) & 0xffff0000;
- Res0 = temp0 + temp1;
- if (Res0 < temp0)
- Res2++;
- Res2 = Res2 + ((Res1 >> 16) & 0x0000ffff) + temp3;
- if (fnLmL < 0)
+
+ uint32_t rn_l = (uint32_t)tempn & 0x0000ffff;
+ uint32_t rn_h = (uint32_t)tempn >> 16;
+ uint32_t rm_l = (uint32_t)tempm & 0x0000ffff;
+ uint32_t rm_h = (uint32_t)tempm >> 16;
+
+ uint32_t temp0 = rm_l * rn_l;
+ uint32_t temp1 = rm_h * rn_l;
+ uint32_t temp2 = rm_l * rn_h;
+ uint32_t temp3 = rm_h * rn_h;
+
+ uint32_t res2 = 0;
+ uint32_t res1 = temp1 + temp2;
+ if (res1 < temp1)
+ res2 += 0x00010000;
+ temp1 = res1 << 16;
+
+ uint32_t res0 = temp0 + temp1;
+ if (res0 < temp0)
+ res2++;
+ res2 = res2 + (res1 >> 16) + temp3;
+
+ if (fnlml)
{
- Res2 = ~Res2;
- if (Res0 == 0)
- Res2++;
+ res2 = ~res2;
+ if (res0 == 0)
+ res2++;
else
- Res0 = (~Res0) + 1;
+ res0 = (~res0) + 1;
}
+
if (m_sh2_state->sr & SH_S)
{
- Res0 = m_sh2_state->macl + Res0;
- if (m_sh2_state->macl > Res0)
- Res2++;
- Res2 += (m_sh2_state->mach & 0x0000ffff);
- if (((int32_t) Res2 < 0) && (Res2 < 0xffff8000))
+ res0 = m_sh2_state->macl + res0;
+ if (m_sh2_state->macl > res0)
+ res2++;
+ res2 += m_sh2_state->mach & 0x0000ffff;
+ if ((int32_t)res2 < 0 && res2 < 0xffff8000)
{
- Res2 = 0x00008000;
- Res0 = 0x00000000;
+ res2 = 0x00008000;
+ res0 = 0x00000000;
}
- else if (((int32_t) Res2 > 0) && (Res2 > 0x00007fff))
+ else if ((int32_t)res2 > 0 && res2 > 0x00007fff)
{
- Res2 = 0x00007fff;
- Res0 = 0xffffffff;
+ res2 = 0x00007fff;
+ res0 = 0xffffffff;
}
- m_sh2_state->mach = Res2;
- m_sh2_state->macl = Res0;
+ m_sh2_state->mach = res2;
+ m_sh2_state->macl = res0;
}
else
{
- Res0 = m_sh2_state->macl + Res0;
- if (m_sh2_state->macl > Res0)
- Res2++;
- Res2 += m_sh2_state->mach;
- m_sh2_state->mach = Res2;
- m_sh2_state->macl = Res0;
+ res0 = m_sh2_state->macl + res0;
+ if (m_sh2_state->macl > res0)
+ res2++;
+ res2 += m_sh2_state->mach;
+ m_sh2_state->mach = res2;
+ m_sh2_state->macl = res0;
}
m_sh2_state->icount -= 2;
}
@@ -924,45 +911,32 @@ void sh_common_execution::MAC_L(uint32_t m, uint32_t n)
/* MAC.W @Rm+,@Rn+ */
void sh_common_execution::MAC_W(uint32_t m, uint32_t n)
{
- int32_t tempm, tempn, dest, src, ans;
- uint32_t templ;
-
- tempn = (int32_t) RW( m_sh2_state->r[n] );
+ int32_t tempn = (int32_t)read_word(m_sh2_state->r[n]);
m_sh2_state->r[n] += 2;
- tempm = (int32_t) RW( m_sh2_state->r[m] );
+
+ int32_t tempm = (int32_t)read_word(m_sh2_state->r[m]);
m_sh2_state->r[m] += 2;
- templ = m_sh2_state->macl;
- tempm = ((int32_t) (short) tempn * (int32_t) (short) tempm);
- if ((int32_t) m_sh2_state->macl >= 0)
- dest = 0;
- else
- dest = 1;
- if ((int32_t) tempm >= 0)
- {
- src = 0;
- tempn = 0;
- }
- else
- {
- src = 1;
- tempn = 0xffffffff;
- }
- src += dest;
+
+ uint32_t templ = m_sh2_state->macl;
+ tempm *= tempn;
+
+ int32_t dest = BIT(m_sh2_state->macl, 31);
+ int32_t src = BIT(tempm, 31) + dest;
+ tempn = BIT(tempm, 31) ? -1 : 0;
+
m_sh2_state->macl += tempm;
- if ((int32_t) m_sh2_state->macl >= 0)
- ans = 0;
- else
- ans = 1;
- ans += dest;
+
+ int32_t ans = BIT(m_sh2_state->macl, 31) + dest;
+
if (m_sh2_state->sr & SH_S)
{
if (ans == 1)
- {
- if (src == 0)
- m_sh2_state->macl = 0x7fffffff;
- if (src == 2)
- m_sh2_state->macl = 0x80000000;
- }
+ {
+ if (src == 0)
+ m_sh2_state->macl = 0x7fffffff;
+ else if (src == 2)
+ m_sh2_state->macl = 0x80000000;
+ }
}
else
{
@@ -983,61 +957,60 @@ void sh_common_execution::MOV(uint32_t m, uint32_t n)
void sh_common_execution::MOVBS(uint32_t m, uint32_t n)
{
m_sh2_state->ea = m_sh2_state->r[n];
- WB( m_sh2_state->ea, m_sh2_state->r[m] & 0x000000ff);
+ write_byte(m_sh2_state->ea, m_sh2_state->r[m] & 0x000000ff);
}
/* MOV.W Rm,@Rn */
void sh_common_execution::MOVWS(uint32_t m, uint32_t n)
{
m_sh2_state->ea = m_sh2_state->r[n];
- WW( m_sh2_state->ea, m_sh2_state->r[m] & 0x0000ffff);
+ write_word(m_sh2_state->ea, m_sh2_state->r[m] & 0x0000ffff);
}
/* MOV.L Rm,@Rn */
void sh_common_execution::MOVLS(uint32_t m, uint32_t n)
{
m_sh2_state->ea = m_sh2_state->r[n];
- WL( m_sh2_state->ea, m_sh2_state->r[m] );
+ write_long(m_sh2_state->ea, m_sh2_state->r[m]);
}
/* MOV.B @Rm,Rn */
void sh_common_execution::MOVBL(uint32_t m, uint32_t n)
{
m_sh2_state->ea = m_sh2_state->r[m];
- m_sh2_state->r[n] = (uint32_t)(int32_t)(int16_t)(int8_t) RB( m_sh2_state->ea );
+ m_sh2_state->r[n] = (uint32_t)util::sext(read_byte(m_sh2_state->ea), 8);
}
/* MOV.W @Rm,Rn */
void sh_common_execution::MOVWL(uint32_t m, uint32_t n)
{
m_sh2_state->ea = m_sh2_state->r[m];
- m_sh2_state->r[n] = (uint32_t)(int32_t)(int16_t) RW( m_sh2_state->ea );
+ m_sh2_state->r[n] = (uint32_t)util::sext(read_word(m_sh2_state->ea), 16);
}
/* MOV.L @Rm,Rn */
void sh_common_execution::MOVLL(uint32_t m, uint32_t n)
{
m_sh2_state->ea = m_sh2_state->r[m];
- m_sh2_state->r[n] = RL( m_sh2_state->ea );
+ m_sh2_state->r[n] = read_long(m_sh2_state->ea);
}
/* MOV.B Rm,@-Rn */
void sh_common_execution::MOVBM(uint32_t m, uint32_t n)
{
- /* SMG : bug fix, was reading m_sh2_state->r[n] */
- uint32_t data = m_sh2_state->r[m] & 0x000000ff;
+ uint8_t data(m_sh2_state->r[m]);
m_sh2_state->r[n] -= 1;
- WB( m_sh2_state->r[n], data );
+ write_byte(m_sh2_state->r[n], data);
}
/* MOV.W Rm,@-Rn */
void sh_common_execution::MOVWM(uint32_t m, uint32_t n)
{
- uint32_t data = m_sh2_state->r[m] & 0x0000ffff;
+ uint16_t data(m_sh2_state->r[m]);
m_sh2_state->r[n] -= 2;
- WW( m_sh2_state->r[n], data );
+ write_word(m_sh2_state->r[n], data);
}
/* MOV.L Rm,@-Rn */
@@ -1046,13 +1019,13 @@ void sh_common_execution::MOVLM(uint32_t m, uint32_t n)
uint32_t data = m_sh2_state->r[m];
m_sh2_state->r[n] -= 4;
- WL( m_sh2_state->r[n], data );
+ write_long(m_sh2_state->r[n], data);
}
/* MOV.B @Rm+,Rn */
void sh_common_execution::MOVBP(uint32_t m, uint32_t n)
{
- m_sh2_state->r[n] = (uint32_t)(int32_t)(int16_t)(int8_t) RB( m_sh2_state->r[m] );
+ m_sh2_state->r[n] = (uint32_t)util::sext(read_byte(m_sh2_state->r[m]), 8);
if (n != m)
m_sh2_state->r[m] += 1;
}
@@ -1060,7 +1033,7 @@ void sh_common_execution::MOVBP(uint32_t m, uint32_t n)
/* MOV.W @Rm+,Rn */
void sh_common_execution::MOVWP(uint32_t m, uint32_t n)
{
- m_sh2_state->r[n] = (uint32_t)(int32_t)(int16_t) RW( m_sh2_state->r[m] );
+ m_sh2_state->r[n] = (uint32_t)util::sext(read_word(m_sh2_state->r[m]), 16);
if (n != m)
m_sh2_state->r[m] += 2;
}
@@ -1068,7 +1041,7 @@ void sh_common_execution::MOVWP(uint32_t m, uint32_t n)
/* MOV.L @Rm+,Rn */
void sh_common_execution::MOVLP(uint32_t m, uint32_t n)
{
- m_sh2_state->r[n] = RL( m_sh2_state->r[m] );
+ m_sh2_state->r[n] = read_long(m_sh2_state->r[m]);
if (n != m)
m_sh2_state->r[m] += 4;
}
@@ -1077,48 +1050,48 @@ void sh_common_execution::MOVLP(uint32_t m, uint32_t n)
void sh_common_execution::MOVBS0(uint32_t m, uint32_t n)
{
m_sh2_state->ea = m_sh2_state->r[n] + m_sh2_state->r[0];
- WB( m_sh2_state->ea, m_sh2_state->r[m] & 0x000000ff );
+ write_byte(m_sh2_state->ea, (uint8_t)m_sh2_state->r[m]);
}
/* MOV.W Rm,@(R0,Rn) */
void sh_common_execution::MOVWS0(uint32_t m, uint32_t n)
{
m_sh2_state->ea = m_sh2_state->r[n] + m_sh2_state->r[0];
- WW( m_sh2_state->ea, m_sh2_state->r[m] & 0x0000ffff );
+ write_word(m_sh2_state->ea, (uint16_t)m_sh2_state->r[m]);
}
/* MOV.L Rm,@(R0,Rn) */
void sh_common_execution::MOVLS0(uint32_t m, uint32_t n)
{
m_sh2_state->ea = m_sh2_state->r[n] + m_sh2_state->r[0];
- WL( m_sh2_state->ea, m_sh2_state->r[m] );
+ write_long(m_sh2_state->ea, m_sh2_state->r[m]);
}
/* MOV.B @(R0,Rm),Rn */
void sh_common_execution::MOVBL0(uint32_t m, uint32_t n)
{
m_sh2_state->ea = m_sh2_state->r[m] + m_sh2_state->r[0];
- m_sh2_state->r[n] = (uint32_t)(int32_t)(int16_t)(int8_t) RB( m_sh2_state->ea );
+ m_sh2_state->r[n] = (uint32_t)util::sext(read_byte(m_sh2_state->ea), 8);
}
/* MOV.W @(R0,Rm),Rn */
void sh_common_execution::MOVWL0(uint32_t m, uint32_t n)
{
m_sh2_state->ea = m_sh2_state->r[m] + m_sh2_state->r[0];
- m_sh2_state->r[n] = (uint32_t)(int32_t)(int16_t) RW( m_sh2_state->ea );
+ m_sh2_state->r[n] = (uint32_t)util::sext(read_word(m_sh2_state->ea), 16);
}
/* MOV.L @(R0,Rm),Rn */
void sh_common_execution::MOVLL0(uint32_t m, uint32_t n)
{
m_sh2_state->ea = m_sh2_state->r[m] + m_sh2_state->r[0];
- m_sh2_state->r[n] = RL( m_sh2_state->ea );
+ m_sh2_state->r[n] = read_long(m_sh2_state->ea);
}
/* MOV #imm,Rn */
void sh_common_execution::MOVI(uint32_t i, uint32_t n)
{
- m_sh2_state->r[n] = (uint32_t)(int32_t)(int16_t)(int8_t) i;
+ m_sh2_state->r[n] = (uint32_t)util::sext(i, 8);
}
/* MOV.W @(disp8,PC),Rn */
@@ -1126,7 +1099,7 @@ void sh_common_execution::MOVWI(uint32_t d, uint32_t n)
{
uint32_t disp = d & 0xff;
m_sh2_state->ea = m_sh2_state->pc + disp * 2 + 2;
- m_sh2_state->r[n] = (uint32_t)(int32_t)(int16_t) RW( m_sh2_state->ea );
+ m_sh2_state->r[n] = (uint32_t)util::sext(read_word(m_sh2_state->ea), 16);
}
/* MOV.L @(disp8,PC),Rn */
@@ -1134,7 +1107,7 @@ void sh_common_execution::MOVLI(uint32_t d, uint32_t n)
{
uint32_t disp = d & 0xff;
m_sh2_state->ea = ((m_sh2_state->pc + 2) & ~3) + disp * 4;
- m_sh2_state->r[n] = RL( m_sh2_state->ea );
+ m_sh2_state->r[n] = read_long(m_sh2_state->ea);
}
/* MOV.B @(disp8,GBR),R0 */
@@ -1142,7 +1115,7 @@ void sh_common_execution::MOVBLG(uint32_t d)
{
uint32_t disp = d & 0xff;
m_sh2_state->ea = m_sh2_state->gbr + disp;
- m_sh2_state->r[0] = (uint32_t)(int32_t)(int16_t)(int8_t) RB( m_sh2_state->ea );
+ m_sh2_state->r[0] = (uint32_t)util::sext(read_byte(m_sh2_state->ea), 8);
}
/* MOV.W @(disp8,GBR),R0 */
@@ -1150,7 +1123,7 @@ void sh_common_execution::MOVWLG(uint32_t d)
{
uint32_t disp = d & 0xff;
m_sh2_state->ea = m_sh2_state->gbr + disp * 2;
- m_sh2_state->r[0] = (int32_t)(int16_t) RW( m_sh2_state->ea );
+ m_sh2_state->r[0] = (int32_t)util::sext(read_word(m_sh2_state->ea), 16);
}
/* MOV.L @(disp8,GBR),R0 */
@@ -1158,7 +1131,7 @@ void sh_common_execution::MOVLLG(uint32_t d)
{
uint32_t disp = d & 0xff;
m_sh2_state->ea = m_sh2_state->gbr + disp * 4;
- m_sh2_state->r[0] = RL( m_sh2_state->ea );
+ m_sh2_state->r[0] = read_long(m_sh2_state->ea);
}
/* MOV.B R0,@(disp8,GBR) */
@@ -1166,7 +1139,7 @@ void sh_common_execution::MOVBSG(uint32_t d)
{
uint32_t disp = d & 0xff;
m_sh2_state->ea = m_sh2_state->gbr + disp;
- WB( m_sh2_state->ea, m_sh2_state->r[0] & 0x000000ff );
+ write_byte(m_sh2_state->ea, (uint8_t)m_sh2_state->r[0]);
}
/* MOV.W R0,@(disp8,GBR) */
@@ -1174,7 +1147,7 @@ void sh_common_execution::MOVWSG(uint32_t d)
{
uint32_t disp = d & 0xff;
m_sh2_state->ea = m_sh2_state->gbr + disp * 2;
- WW( m_sh2_state->ea, m_sh2_state->r[0] & 0x0000ffff );
+ write_word(m_sh2_state->ea, (uint16_t)m_sh2_state->r[0]);
}
/* MOV.L R0,@(disp8,GBR) */
@@ -1182,7 +1155,7 @@ void sh_common_execution::MOVLSG(uint32_t d)
{
uint32_t disp = d & 0xff;
m_sh2_state->ea = m_sh2_state->gbr + disp * 4;
- WL( m_sh2_state->ea, m_sh2_state->r[0] );
+ write_long(m_sh2_state->ea, m_sh2_state->r[0]);
}
/* MOV.B R0,@(disp4,Rn) */
@@ -1190,7 +1163,7 @@ void sh_common_execution::MOVBS4(uint32_t d, uint32_t n)
{
uint32_t disp = d & 0x0f;
m_sh2_state->ea = m_sh2_state->r[n] + disp;
- WB( m_sh2_state->ea, m_sh2_state->r[0] & 0x000000ff );
+ write_byte(m_sh2_state->ea, (uint8_t)m_sh2_state->r[0]);
}
/* MOV.W R0,@(disp4,Rn) */
@@ -1198,7 +1171,7 @@ void sh_common_execution::MOVWS4(uint32_t d, uint32_t n)
{
uint32_t disp = d & 0x0f;
m_sh2_state->ea = m_sh2_state->r[n] + disp * 2;
- WW( m_sh2_state->ea, m_sh2_state->r[0] & 0x0000ffff );
+ write_word(m_sh2_state->ea, (uint16_t)m_sh2_state->r[0]);
}
/* MOV.L Rm,@(disp4,Rn) */
@@ -1206,7 +1179,7 @@ void sh_common_execution::MOVLS4(uint32_t m, uint32_t d, uint32_t n)
{
uint32_t disp = d & 0x0f;
m_sh2_state->ea = m_sh2_state->r[n] + disp * 4;
- WL( m_sh2_state->ea, m_sh2_state->r[m] );
+ write_long(m_sh2_state->ea, m_sh2_state->r[m]);
}
/* MOV.B @(disp4,Rm),R0 */
@@ -1214,7 +1187,7 @@ void sh_common_execution::MOVBL4(uint32_t m, uint32_t d)
{
uint32_t disp = d & 0x0f;
m_sh2_state->ea = m_sh2_state->r[m] + disp;
- m_sh2_state->r[0] = (uint32_t)(int32_t)(int16_t)(int8_t) RB( m_sh2_state->ea );
+ m_sh2_state->r[0] = (uint32_t)util::sext(read_byte(m_sh2_state->ea), 8);
}
/* MOV.W @(disp4,Rm),R0 */
@@ -1222,7 +1195,7 @@ void sh_common_execution::MOVWL4(uint32_t m, uint32_t d)
{
uint32_t disp = d & 0x0f;
m_sh2_state->ea = m_sh2_state->r[m] + disp * 2;
- m_sh2_state->r[0] = (uint32_t)(int32_t)(int16_t) RW( m_sh2_state->ea );
+ m_sh2_state->r[0] = (uint32_t)util::sext(read_word(m_sh2_state->ea), 16);
}
/* MOV.L @(disp4,Rm),Rn */
@@ -1230,7 +1203,7 @@ void sh_common_execution::MOVLL4(uint32_t m, uint32_t d, uint32_t n)
{
uint32_t disp = d & 0x0f;
m_sh2_state->ea = m_sh2_state->r[m] + disp * 4;
- m_sh2_state->r[n] = RL( m_sh2_state->ea );
+ m_sh2_state->r[n] = read_long(m_sh2_state->ea);
}
/* MOVA @(disp8,PC),R0 */
@@ -1257,13 +1230,13 @@ void sh_common_execution::MULL(uint32_t m, uint32_t n)
/* MULS Rm,Rn */
void sh_common_execution::MULS(uint32_t m, uint32_t n)
{
- m_sh2_state->macl = (int16_t) m_sh2_state->r[n] * (int16_t) m_sh2_state->r[m];
+ m_sh2_state->macl = (int16_t)m_sh2_state->r[n] * (int16_t)m_sh2_state->r[m];
}
/* MULU Rm,Rn */
void sh_common_execution::MULU(uint32_t m, uint32_t n)
{
- m_sh2_state->macl = (uint16_t) m_sh2_state->r[n] * (uint16_t) m_sh2_state->r[m];
+ m_sh2_state->macl = (uint16_t)m_sh2_state->r[n] * (uint16_t)m_sh2_state->r[m];
}
/* NEG Rm,Rn */
@@ -1275,9 +1248,7 @@ void sh_common_execution::NEG(uint32_t m, uint32_t n)
/* NEGC Rm,Rn */
void sh_common_execution::NEGC(uint32_t m, uint32_t n)
{
- uint32_t temp;
-
- temp = m_sh2_state->r[m];
+ uint32_t temp = m_sh2_state->r[m];
m_sh2_state->r[n] = -temp - (m_sh2_state->sr & SH_T);
if (temp || (m_sh2_state->sr & SH_T))
m_sh2_state->sr |= SH_T;
@@ -1306,27 +1277,20 @@ void sh_common_execution::OR(uint32_t m, uint32_t n)
void sh_common_execution::ORI(uint32_t i)
{
m_sh2_state->r[0] |= i;
- m_sh2_state->icount -= 2; // not in SH2 implementation?
+ m_sh2_state->icount -= 2;
}
/* OR.B #imm,@(R0,GBR) */
void sh_common_execution::ORM(uint32_t i)
{
- uint32_t temp;
-
m_sh2_state->ea = m_sh2_state->gbr + m_sh2_state->r[0];
- temp = RB( m_sh2_state->ea );
- temp |= i;
- WB( m_sh2_state->ea, temp );
- //m_sh2_state->icount -= 2; // not in SH4 implementation?
+ write_byte(m_sh2_state->ea, read_byte(m_sh2_state->ea) | (uint8_t)i);
}
/* ROTCL Rn */
void sh_common_execution::ROTCL(uint32_t n)
{
- uint32_t temp;
-
- temp = (m_sh2_state->r[n] >> 31) & SH_T;
+ uint32_t temp = (m_sh2_state->r[n] >> 31) & SH_T;
m_sh2_state->r[n] = (m_sh2_state->r[n] << 1) | (m_sh2_state->sr & SH_T);
m_sh2_state->sr = (m_sh2_state->sr & ~SH_T) | temp;
}
@@ -1334,8 +1298,7 @@ void sh_common_execution::ROTCL(uint32_t n)
/* ROTCR Rn */
void sh_common_execution::ROTCR(uint32_t n)
{
- uint32_t temp;
- temp = (m_sh2_state->sr & SH_T) << 31;
+ uint32_t temp = (m_sh2_state->sr & SH_T) << 31;
if (m_sh2_state->r[n] & SH_T)
m_sh2_state->sr |= SH_T;
else
@@ -1458,7 +1421,7 @@ void sh_common_execution::STCMSR(uint32_t n)
{
m_sh2_state->r[n] -= 4;
m_sh2_state->ea = m_sh2_state->r[n];
- WL( m_sh2_state->ea, m_sh2_state->sr );
+ write_long(m_sh2_state->ea, m_sh2_state->sr);
m_sh2_state->icount--;
}
@@ -1467,7 +1430,7 @@ void sh_common_execution::STCMGBR(uint32_t n)
{
m_sh2_state->r[n] -= 4;
m_sh2_state->ea = m_sh2_state->r[n];
- WL( m_sh2_state->ea, m_sh2_state->gbr );
+ write_long(m_sh2_state->ea, m_sh2_state->gbr);
m_sh2_state->icount--;
}
@@ -1476,7 +1439,7 @@ void sh_common_execution::STCMVBR(uint32_t n)
{
m_sh2_state->r[n] -= 4;
m_sh2_state->ea = m_sh2_state->r[n];
- WL( m_sh2_state->ea, m_sh2_state->vbr );
+ write_long(m_sh2_state->ea, m_sh2_state->vbr);
m_sh2_state->icount--;
}
@@ -1503,7 +1466,7 @@ void sh_common_execution::STSMMACH(uint32_t n)
{
m_sh2_state->r[n] -= 4;
m_sh2_state->ea = m_sh2_state->r[n];
- WL( m_sh2_state->ea, m_sh2_state->mach );
+ write_long(m_sh2_state->ea, m_sh2_state->mach);
}
/* STS.L MACL,@-Rn */
@@ -1511,7 +1474,7 @@ void sh_common_execution::STSMMACL(uint32_t n)
{
m_sh2_state->r[n] -= 4;
m_sh2_state->ea = m_sh2_state->r[n];
- WL( m_sh2_state->ea, m_sh2_state->macl );
+ write_long(m_sh2_state->ea, m_sh2_state->macl);
}
/* STS.L PR,@-Rn */
@@ -1519,7 +1482,7 @@ void sh_common_execution::STSMPR(uint32_t n)
{
m_sh2_state->r[n] -= 4;
m_sh2_state->ea = m_sh2_state->r[n];
- WL( m_sh2_state->ea, m_sh2_state->pr );
+ write_long(m_sh2_state->ea, m_sh2_state->pr);
}
/* SUB Rm,Rn */
@@ -1531,10 +1494,8 @@ void sh_common_execution::SUB(uint32_t m, uint32_t n)
/* SUBC Rm,Rn */
void sh_common_execution::SUBC(uint32_t m, uint32_t n)
{
- uint32_t tmp0, tmp1;
-
- tmp1 = m_sh2_state->r[n] - m_sh2_state->r[m];
- tmp0 = m_sh2_state->r[n];
+ uint32_t tmp1 = m_sh2_state->r[n] - m_sh2_state->r[m];
+ uint32_t tmp0 = m_sh2_state->r[n];
m_sh2_state->r[n] = tmp1 - (m_sh2_state->sr & SH_T);
if (tmp0 < tmp1)
m_sh2_state->sr |= SH_T;
@@ -1547,30 +1508,17 @@ void sh_common_execution::SUBC(uint32_t m, uint32_t n)
/* SUBV Rm,Rn */
void sh_common_execution::SUBV(uint32_t m, uint32_t n)
{
- int32_t dest, src, ans;
-
- if ((int32_t) m_sh2_state->r[n] >= 0)
- dest = 0;
- else
- dest = 1;
- if ((int32_t) m_sh2_state->r[m] >= 0)
- src = 0;
- else
- src = 1;
+ int32_t dest = BIT(m_sh2_state->r[n], 31);
+ int32_t src = BIT(m_sh2_state->r[m], 31);
src += dest;
+
m_sh2_state->r[n] -= m_sh2_state->r[m];
- if ((int32_t) m_sh2_state->r[n] >= 0)
- ans = 0;
- else
- ans = 1;
+
+ int32_t ans = BIT(m_sh2_state->r[n], 31);
ans += dest;
- if (src == 1)
- {
- if (ans == 1)
- m_sh2_state->sr |= SH_T;
- else
- m_sh2_state->sr &= ~SH_T;
- }
+
+ if (src == 1 && ans == 1)
+ m_sh2_state->sr |= SH_T;
else
m_sh2_state->sr &= ~SH_T;
}
@@ -1578,37 +1526,33 @@ void sh_common_execution::SUBV(uint32_t m, uint32_t n)
/* SWAP.B Rm,Rn */
void sh_common_execution::SWAPB(uint32_t m, uint32_t n)
{
- uint32_t temp0, temp1;
-
- temp0 = m_sh2_state->r[m] & 0xffff0000;
- temp1 = (m_sh2_state->r[m] & 0x000000ff) << 8;
- m_sh2_state->r[n] = (m_sh2_state->r[m] >> 8) & 0x000000ff;
- m_sh2_state->r[n] = m_sh2_state->r[n] | temp1 | temp0;
+ uint32_t temp = m_sh2_state->r[m] & 0xffff0000;
+ temp |= (m_sh2_state->r[m] & 0x000000ff) << 8;
+ m_sh2_state->r[n] = (uint8_t)(m_sh2_state->r[m] >> 8);
+ m_sh2_state->r[n] = m_sh2_state->r[n] | temp;
}
/* SWAP.W Rm,Rn */
void sh_common_execution::SWAPW(uint32_t m, uint32_t n)
{
- uint32_t temp;
-
- temp = (m_sh2_state->r[m] >> 16) & 0x0000ffff;
+ uint32_t temp = m_sh2_state->r[m] >> 16;
m_sh2_state->r[n] = (m_sh2_state->r[m] << 16) | temp;
}
/* TAS.B @Rn */
void sh_common_execution::TAS(uint32_t n)
{
- uint32_t temp;
m_sh2_state->ea = m_sh2_state->r[n];
+
/* Bus Lock enable */
- temp = RB( m_sh2_state->ea );
+ uint32_t temp = read_byte(m_sh2_state->ea);
if (temp == 0)
m_sh2_state->sr |= SH_T;
else
m_sh2_state->sr &= ~SH_T;
temp |= 0x80;
/* Bus Lock disable */
- WB( m_sh2_state->ea, temp );
+ write_byte(m_sh2_state->ea, temp);
m_sh2_state->icount -= 3;
}
@@ -1638,7 +1582,7 @@ void sh_common_execution::TSTM(uint32_t i)
uint32_t imm = i & 0xff;
m_sh2_state->ea = m_sh2_state->gbr + m_sh2_state->r[0];
- if ((imm & RB( m_sh2_state->ea )) == 0)
+ if ((imm & read_byte(m_sh2_state->ea)) == 0)
m_sh2_state->sr |= SH_T;
else
m_sh2_state->sr &= ~SH_T;
@@ -1654,31 +1598,21 @@ void sh_common_execution::XOR(uint32_t m, uint32_t n)
/* XOR #imm,R0 */
void sh_common_execution::XORI(uint32_t i)
{
- uint32_t imm = i & 0xff;
- m_sh2_state->r[0] ^= imm;
+ m_sh2_state->r[0] ^= i & 0x000000ff;
}
/* XOR.B #imm,@(R0,GBR) */
void sh_common_execution::XORM(uint32_t i)
{
- uint32_t imm = i & 0xff;
- uint32_t temp;
-
m_sh2_state->ea = m_sh2_state->gbr + m_sh2_state->r[0];
- temp = RB( m_sh2_state->ea );
- temp ^= imm;
- WB( m_sh2_state->ea, temp );
+ write_byte(m_sh2_state->ea, read_byte(m_sh2_state->ea) ^ (uint8_t)i);
m_sh2_state->icount -= 2;
}
/* XTRCT Rm,Rn */
void sh_common_execution::XTRCT(uint32_t m, uint32_t n)
{
- uint32_t temp;
-
- temp = (m_sh2_state->r[m] << 16) & 0xffff0000;
- m_sh2_state->r[n] = (m_sh2_state->r[n] >> 16) & 0x0000ffff;
- m_sh2_state->r[n] |= temp;
+ m_sh2_state->r[n] = (m_sh2_state->r[n] >> 16) | (m_sh2_state->r[m] << 16);
}
/* SLEEP */
@@ -1687,13 +1621,13 @@ void sh_common_execution::SLEEP()
/* 0 = normal mode */
/* 1 = enters into power-down mode */
/* 2 = go out the power-down mode after an exception */
- if(m_sh2_state->sleep_mode != 2)
+ if (m_sh2_state->sleep_mode != 2)
m_sh2_state->pc -= 2;
m_sh2_state->icount -= 2;
/* Wait_for_exception; */
- if(m_sh2_state->sleep_mode == 0)
+ if (m_sh2_state->sleep_mode == 0)
m_sh2_state->sleep_mode = 1;
- else if(m_sh2_state->sleep_mode == 2)
+ else if (m_sh2_state->sleep_mode == 2)
m_sh2_state->sleep_mode = 0;
}
@@ -1703,22 +1637,22 @@ void sh_common_execution::op0010(uint16_t opcode)
{
switch (opcode & 15)
{
- case 0: MOVBS(Rm, Rn); break;
- case 1: MOVWS(Rm, Rn); break;
- case 2: MOVLS(Rm, Rn); break;
- case 3: ILLEGAL(); break;
- case 4: MOVBM(Rm, Rn); break;
- case 5: MOVWM(Rm, Rn); break;
- case 6: MOVLM(Rm, Rn); break;
- case 7: DIV0S(Rm, Rn); break;
- case 8: TST(Rm, Rn); break;
- case 9: AND(Rm, Rn); break;
- case 10: XOR(Rm, Rn); break;
- case 11: OR(Rm, Rn); break;
- case 12: CMPSTR(Rm, Rn); break;
- case 13: XTRCT(Rm, Rn); break;
- case 14: MULU(Rm, Rn); break;
- case 15: MULS(Rm, Rn); break;
+ case 0: MOVBS(REG_M, REG_N); break;
+ case 1: MOVWS(REG_M, REG_N); break;
+ case 2: MOVLS(REG_M, REG_N); break;
+ case 3: ILLEGAL(); break;
+ case 4: MOVBM(REG_M, REG_N); break;
+ case 5: MOVWM(REG_M, REG_N); break;
+ case 6: MOVLM(REG_M, REG_N); break;
+ case 7: DIV0S(REG_M, REG_N); break;
+ case 8: TST(REG_M, REG_N); break;
+ case 9: AND(REG_M, REG_N); break;
+ case 10: XOR(REG_M, REG_N); break;
+ case 11: OR(REG_M, REG_N); break;
+ case 12: CMPSTR(REG_M, REG_N); break;
+ case 13: XTRCT(REG_M, REG_N); break;
+ case 14: MULU(REG_M, REG_N); break;
+ case 15: MULS(REG_M, REG_N); break;
}
}
@@ -1726,22 +1660,22 @@ void sh_common_execution::op0011(uint16_t opcode)
{
switch (opcode & 15)
{
- case 0: CMPEQ(Rm, Rn); break;
- case 1: ILLEGAL(); break;
- case 2: CMPHS(Rm, Rn); break;
- case 3: CMPGE(Rm, Rn); break;
- case 4: DIV1(Rm, Rn); break;
- case 5: DMULU(Rm, Rn); break;
- case 6: CMPHI(Rm, Rn); break;
- case 7: CMPGT(Rm, Rn); break;
- case 8: SUB(Rm, Rn); break;
- case 9: ILLEGAL(); break;
- case 10: SUBC(Rm, Rn); break;
- case 11: SUBV(Rm, Rn); break;
- case 12: ADD(Rm, Rn); break;
- case 13: DMULS(Rm, Rn); break;
- case 14: ADDC(Rm, Rn); break;
- case 15: ADDV(Rm, Rn); break;
+ case 0: CMPEQ(REG_M, REG_N); break;
+ case 1: ILLEGAL(); break;
+ case 2: CMPHS(REG_M, REG_N); break;
+ case 3: CMPGE(REG_M, REG_N); break;
+ case 4: DIV1(REG_M, REG_N); break;
+ case 5: DMULU(REG_M, REG_N); break;
+ case 6: CMPHI(REG_M, REG_N); break;
+ case 7: CMPGT(REG_M, REG_N); break;
+ case 8: SUB(REG_M, REG_N); break;
+ case 9: ILLEGAL(); break;
+ case 10: SUBC(REG_M, REG_N); break;
+ case 11: SUBV(REG_M, REG_N); break;
+ case 12: ADD(REG_M, REG_N); break;
+ case 13: DMULS(REG_M, REG_N); break;
+ case 14: ADDC(REG_M, REG_N); break;
+ case 15: ADDV(REG_M, REG_N); break;
}
}
@@ -1749,69 +1683,69 @@ void sh_common_execution::op0110(uint16_t opcode)
{
switch (opcode & 15)
{
- case 0: MOVBL(Rm, Rn); break;
- case 1: MOVWL(Rm, Rn); break;
- case 2: MOVLL(Rm, Rn); break;
- case 3: MOV(Rm, Rn); break;
- case 4: MOVBP(Rm, Rn); break;
- case 5: MOVWP(Rm, Rn); break;
- case 6: MOVLP(Rm, Rn); break;
- case 7: NOT(Rm, Rn); break;
- case 8: SWAPB(Rm, Rn); break;
- case 9: SWAPW(Rm, Rn); break;
- case 10: NEGC(Rm, Rn); break;
- case 11: NEG(Rm, Rn); break;
- case 12: EXTUB(Rm, Rn); break;
- case 13: EXTUW(Rm, Rn); break;
- case 14: EXTSB(Rm, Rn); break;
- case 15: EXTSW(Rm, Rn); break;
+ case 0: MOVBL(REG_M, REG_N); break;
+ case 1: MOVWL(REG_M, REG_N); break;
+ case 2: MOVLL(REG_M, REG_N); break;
+ case 3: MOV(REG_M, REG_N); break;
+ case 4: MOVBP(REG_M, REG_N); break;
+ case 5: MOVWP(REG_M, REG_N); break;
+ case 6: MOVLP(REG_M, REG_N); break;
+ case 7: NOT(REG_M, REG_N); break;
+ case 8: SWAPB(REG_M, REG_N); break;
+ case 9: SWAPW(REG_M, REG_N); break;
+ case 10: NEGC(REG_M, REG_N); break;
+ case 11: NEG(REG_M, REG_N); break;
+ case 12: EXTUB(REG_M, REG_N); break;
+ case 13: EXTUW(REG_M, REG_N); break;
+ case 14: EXTSB(REG_M, REG_N); break;
+ case 15: EXTSW(REG_M, REG_N); break;
}
}
void sh_common_execution::op1000(uint16_t opcode)
{
- switch ( opcode & (15<<8) )
+ switch ((opcode >> 8) & 15)
{
- case 0 << 8: MOVBS4(opcode & 0x0f, Rm); break;
- case 1 << 8: MOVWS4(opcode & 0x0f, Rm); break;
- case 2<< 8: ILLEGAL(); break;
- case 3<< 8: ILLEGAL(); break;
- case 4<< 8: MOVBL4(Rm, opcode & 0x0f); break;
- case 5<< 8: MOVWL4(Rm, opcode & 0x0f); break;
- case 6<< 8: ILLEGAL(); break;
- case 7<< 8: ILLEGAL(); break;
- case 8<< 8: CMPIM(opcode & 0xff); break;
- case 9<< 8: BT(opcode & 0xff); break;
- case 10<< 8: ILLEGAL(); break;
- case 11<< 8: BF(opcode & 0xff); break;
- case 12<< 8: ILLEGAL(); break;
- case 13<< 8: BTS(opcode & 0xff); break;
- case 14<< 8: ILLEGAL(); break;
- case 15<< 8: BFS(opcode & 0xff); break;
+ case 0: MOVBS4(opcode & 0x0f, REG_M); break;
+ case 1: MOVWS4(opcode & 0x0f, REG_M); break;
+ case 2: ILLEGAL(); break;
+ case 3: ILLEGAL(); break;
+ case 4: MOVBL4(REG_M, opcode & 0x0f); break;
+ case 5: MOVWL4(REG_M, opcode & 0x0f); break;
+ case 6: ILLEGAL(); break;
+ case 7: ILLEGAL(); break;
+ case 8: CMPIM(opcode & 0xff); break;
+ case 9: BT(opcode & 0xff); break;
+ case 10: ILLEGAL(); break;
+ case 11: BF(opcode & 0xff); break;
+ case 12: ILLEGAL(); break;
+ case 13: BTS(opcode & 0xff); break;
+ case 14: ILLEGAL(); break;
+ case 15: BFS(opcode & 0xff); break;
}
}
void sh_common_execution::op1100(uint16_t opcode)
{
- switch (opcode & (15<<8))
+ switch ((opcode >> 8) & 15)
{
- case 0<<8: MOVBSG(opcode & 0xff); break;
- case 1<<8: MOVWSG(opcode & 0xff); break;
- case 2<<8: MOVLSG(opcode & 0xff); break;
- case 3<<8: TRAPA(opcode & 0xff); break; // sh2/4 differ
- case 4<<8: MOVBLG(opcode & 0xff); break;
- case 5<<8: MOVWLG(opcode & 0xff); break;
- case 6<<8: MOVLLG(opcode & 0xff); break;
- case 7<<8: MOVA(opcode & 0xff); break;
- case 8<<8: TSTI(opcode & 0xff); break;
- case 9<<8: ANDI(opcode & 0xff); break;
- case 10<<8: XORI(opcode & 0xff); break;
- case 11<<8: ORI(opcode & 0xff); break;
- case 12<<8: TSTM(opcode & 0xff); break;
- case 13<<8: ANDM(opcode & 0xff); break;
- case 14<<8: XORM(opcode & 0xff); break;
- case 15<<8: ORM(opcode & 0xff); break;
+ case 0: MOVBSG(opcode & 0xff); break;
+ case 1: MOVWSG(opcode & 0xff); break;
+ case 2: MOVLSG(opcode & 0xff); break;
+ case 3: TRAPA(opcode & 0xff); break; // sh2/4 differ
+ case 4: MOVBLG(opcode & 0xff); break;
+ case 5: MOVWLG(opcode & 0xff); break;
+ case 6: MOVLLG(opcode & 0xff); break;
+ case 7: MOVA(opcode & 0xff); break;
+ case 8: TSTI(opcode & 0xff); break;
+ case 9: ANDI(opcode & 0xff); break;
+ case 10: XORI(opcode & 0xff); break;
+ case 11: ORI(opcode & 0xff); break;
+ case 12: TSTM(opcode & 0xff); break;
+ case 13: ANDM(opcode & 0xff); break;
+ case 14: XORM(opcode & 0xff); break;
+ case 15: ORM(opcode & 0xff); break;
}
}
@@ -1820,75 +1754,75 @@ void sh_common_execution::execute_one_0000(uint16_t opcode)
{
// 04,05,06,07 always the same, 0c,0d,0e,0f always the same, other change based on upper bits
- switch (opcode & 0x3F)
+ switch (opcode & 0x3f)
{
- case 0x00: ILLEGAL(); break;
- case 0x01: ILLEGAL(); break;
- case 0x02: STCSR(Rn); break;
- case 0x03: BSRF(Rn); break;
- case 0x04: MOVBS0(Rm, Rn); break;
- case 0x05: MOVWS0(Rm, Rn); break;
- case 0x06: MOVLS0(Rm, Rn); break;
- case 0x07: MULL(Rm, Rn); break;
- case 0x08: CLRT(); break;
- case 0x09: NOP(); break;
- case 0x0a: STSMACH(Rn); break;
- case 0x0b: RTS(); break;
- case 0x0c: MOVBL0(Rm, Rn); break;
- case 0x0d: MOVWL0(Rm, Rn); break;
- case 0x0e: MOVLL0(Rm, Rn); break;
- case 0x0f: MAC_L(Rm, Rn); break;
-
- case 0x10: ILLEGAL(); break;
- case 0x11: ILLEGAL(); break;
- case 0x12: STCGBR(Rn); break;
- case 0x13: ILLEGAL(); break;
- case 0x14: MOVBS0(Rm, Rn); break;
- case 0x15: MOVWS0(Rm, Rn); break;
- case 0x16: MOVLS0(Rm, Rn); break;
- case 0x17: MULL(Rm, Rn); break;
- case 0x18: SETT(); break;
- case 0x19: DIV0U(); break;
- case 0x1a: STSMACL(Rn); break;
- case 0x1b: SLEEP(); break;
- case 0x1c: MOVBL0(Rm, Rn); break;
- case 0x1d: MOVWL0(Rm, Rn); break;
- case 0x1e: MOVLL0(Rm, Rn); break;
- case 0x1f: MAC_L(Rm, Rn); break;
-
- case 0x20: ILLEGAL(); break;
- case 0x21: ILLEGAL(); break;
- case 0x22: STCVBR(Rn); break;
- case 0x23: BRAF(Rn); break;
- case 0x24: MOVBS0(Rm, Rn); break;
- case 0x25: MOVWS0(Rm, Rn); break;
- case 0x26: MOVLS0(Rm, Rn); break;
- case 0x27: MULL(Rm, Rn); break;
- case 0x28: CLRMAC(); break;
- case 0x29: MOVT(Rn); break;
- case 0x2a: STSPR(Rn); break;
- case 0x2b: RTE(); break;
- case 0x2c: MOVBL0(Rm, Rn); break;
- case 0x2d: MOVWL0(Rm, Rn); break;
- case 0x2e: MOVLL0(Rm, Rn); break;
- case 0x2f: MAC_L(Rm, Rn); break;
-
- case 0x30: ILLEGAL(); break;
- case 0x31: ILLEGAL(); break;
- case 0x32: ILLEGAL(); break;
- case 0x33: ILLEGAL(); break;
- case 0x34: MOVBS0(Rm, Rn); break;
- case 0x35: MOVWS0(Rm, Rn); break;
- case 0x36: MOVLS0(Rm, Rn); break;
- case 0x37: MULL(Rm, Rn); break;
- case 0x38: ILLEGAL(); break;
- case 0x39: ILLEGAL(); break;
- case 0x3a: ILLEGAL(); break;
- case 0x3b: ILLEGAL(); break;
- case 0x3c: MOVBL0(Rm, Rn); break;
- case 0x3d: MOVWL0(Rm, Rn); break;
- case 0x3e: MOVLL0(Rm, Rn); break;
- case 0x3f: MAC_L(Rm, Rn); break;
+ case 0x00: ILLEGAL(); break;
+ case 0x01: ILLEGAL(); break;
+ case 0x02: STCSR(REG_N); break;
+ case 0x03: BSRF(REG_N); break;
+ case 0x04: MOVBS0(REG_M, REG_N); break;
+ case 0x05: MOVWS0(REG_M, REG_N); break;
+ case 0x06: MOVLS0(REG_M, REG_N); break;
+ case 0x07: MULL(REG_M, REG_N); break;
+ case 0x08: CLRT(); break;
+ case 0x09: NOP(); break;
+ case 0x0a: STSMACH(REG_N); break;
+ case 0x0b: RTS(); break;
+ case 0x0c: MOVBL0(REG_M, REG_N); break;
+ case 0x0d: MOVWL0(REG_M, REG_N); break;
+ case 0x0e: MOVLL0(REG_M, REG_N); break;
+ case 0x0f: MAC_L(REG_M, REG_N); break;
+
+ case 0x10: ILLEGAL(); break;
+ case 0x11: ILLEGAL(); break;
+ case 0x12: STCGBR(REG_N); break;
+ case 0x13: ILLEGAL(); break;
+ case 0x14: MOVBS0(REG_M, REG_N); break;
+ case 0x15: MOVWS0(REG_M, REG_N); break;
+ case 0x16: MOVLS0(REG_M, REG_N); break;
+ case 0x17: MULL(REG_M, REG_N); break;
+ case 0x18: SETT(); break;
+ case 0x19: DIV0U(); break;
+ case 0x1a: STSMACL(REG_N); break;
+ case 0x1b: SLEEP(); break;
+ case 0x1c: MOVBL0(REG_M, REG_N); break;
+ case 0x1d: MOVWL0(REG_M, REG_N); break;
+ case 0x1e: MOVLL0(REG_M, REG_N); break;
+ case 0x1f: MAC_L(REG_M, REG_N); break;
+
+ case 0x20: ILLEGAL(); break;
+ case 0x21: ILLEGAL(); break;
+ case 0x22: STCVBR(REG_N); break;
+ case 0x23: BRAF(REG_N); break;
+ case 0x24: MOVBS0(REG_M, REG_N); break;
+ case 0x25: MOVWS0(REG_M, REG_N); break;
+ case 0x26: MOVLS0(REG_M, REG_N); break;
+ case 0x27: MULL(REG_M, REG_N); break;
+ case 0x28: CLRMAC(); break;
+ case 0x29: MOVT(REG_N); break;
+ case 0x2a: STSPR(REG_N); break;
+ case 0x2b: RTE(); break;
+ case 0x2c: MOVBL0(REG_M, REG_N); break;
+ case 0x2d: MOVWL0(REG_M, REG_N); break;
+ case 0x2e: MOVLL0(REG_M, REG_N); break;
+ case 0x2f: MAC_L(REG_M, REG_N); break;
+
+ case 0x30: ILLEGAL(); break;
+ case 0x31: ILLEGAL(); break;
+ case 0x32: ILLEGAL(); break;
+ case 0x33: ILLEGAL(); break;
+ case 0x34: MOVBS0(REG_M, REG_N); break;
+ case 0x35: MOVWS0(REG_M, REG_N); break;
+ case 0x36: MOVLS0(REG_M, REG_N); break;
+ case 0x37: MULL(REG_M, REG_N); break;
+ case 0x38: ILLEGAL(); break;
+ case 0x39: ILLEGAL(); break;
+ case 0x3a: ILLEGAL(); break;
+ case 0x3b: ILLEGAL(); break;
+ case 0x3c: MOVBL0(REG_M, REG_N); break;
+ case 0x3d: MOVWL0(REG_M, REG_N); break;
+ case 0x3e: MOVLL0(REG_M, REG_N); break;
+ case 0x3f: MAC_L(REG_M, REG_N); break;
}
}
@@ -1897,99 +1831,99 @@ void sh_common_execution::execute_one_4000(uint16_t opcode)
{
// 0f always the same, others differ
- switch (opcode & 0x3F)
+ switch (opcode & 0x3f)
{
- case 0x00: SHLL(Rn); break;
- case 0x01: SHLR(Rn); break;
- case 0x02: STSMMACH(Rn); break;
- case 0x03: STCMSR(Rn); break;
- case 0x04: ROTL(Rn); break;
- case 0x05: ROTR(Rn); break;
- case 0x06: LDSMMACH(Rn); break;
- case 0x07: LDCMSR(opcode); break;
- case 0x08: SHLL2(Rn); break;
- case 0x09: SHLR2(Rn); break;
- case 0x0a: LDSMACH(Rn); break;
- case 0x0b: JSR(Rn); break;
- case 0x0c: ILLEGAL(); break;
- case 0x0d: ILLEGAL(); break;
- case 0x0e: LDCSR(opcode); break;
- case 0x0f: MAC_W(Rm, Rn); break;
-
- case 0x10: DT(Rn); break;
- case 0x11: CMPPZ(Rn); break;
- case 0x12: STSMMACL(Rn); break;
- case 0x13: STCMGBR(Rn); break;
- case 0x14: ILLEGAL(); break;
- case 0x15: CMPPL(Rn); break;
- case 0x16: LDSMMACL(Rn); break;
- case 0x17: LDCMGBR(Rn); break;
- case 0x18: SHLL8(Rn); break;
- case 0x19: SHLR8(Rn); break;
- case 0x1a: LDSMACL(Rn); break;
- case 0x1b: TAS(Rn); break;
- case 0x1c: ILLEGAL(); break;
- case 0x1d: ILLEGAL(); break;
- case 0x1e: LDCGBR(Rn); break;
- case 0x1f: MAC_W(Rm, Rn); break;
-
- case 0x20: SHAL(Rn); break;
- case 0x21: SHAR(Rn); break;
- case 0x22: STSMPR(Rn); break;
- case 0x23: STCMVBR(Rn); break;
- case 0x24: ROTCL(Rn); break;
- case 0x25: ROTCR(Rn); break;
- case 0x26: LDSMPR(Rn); break;
- case 0x27: LDCMVBR(Rn); break;
- case 0x28: SHLL16(Rn); break;
- case 0x29: SHLR16(Rn); break;
- case 0x2a: LDSPR(Rn); break;
- case 0x2b: JMP(Rn); break;
- case 0x2c: ILLEGAL(); break;
- case 0x2d: ILLEGAL(); break;
- case 0x2e: LDCVBR(Rn); break;
- case 0x2f: MAC_W(Rm, Rn); break;
-
- case 0x30: ILLEGAL(); break;
- case 0x31: ILLEGAL(); break;
- case 0x32: ILLEGAL(); break;
- case 0x33: ILLEGAL(); break;
- case 0x34: ILLEGAL(); break;
- case 0x35: ILLEGAL(); break;
- case 0x36: ILLEGAL(); break;
- case 0x37: ILLEGAL(); break;
- case 0x38: ILLEGAL(); break;
- case 0x39: ILLEGAL(); break;
- case 0x3a: ILLEGAL(); break;
- case 0x3b: ILLEGAL(); break;
- case 0x3c: ILLEGAL(); break;
- case 0x3d: ILLEGAL(); break;
- case 0x3e: ILLEGAL(); break;
- case 0x3f: MAC_W(Rm, Rn); break;
+ case 0x00: SHLL(REG_N); break;
+ case 0x01: SHLR(REG_N); break;
+ case 0x02: STSMMACH(REG_N); break;
+ case 0x03: STCMSR(REG_N); break;
+ case 0x04: ROTL(REG_N); break;
+ case 0x05: ROTR(REG_N); break;
+ case 0x06: LDSMMACH(REG_N); break;
+ case 0x07: LDCMSR(opcode); break;
+ case 0x08: SHLL2(REG_N); break;
+ case 0x09: SHLR2(REG_N); break;
+ case 0x0a: LDSMACH(REG_N); break;
+ case 0x0b: JSR(REG_N); break;
+ case 0x0c: ILLEGAL(); break;
+ case 0x0d: ILLEGAL(); break;
+ case 0x0e: LDCSR(opcode); break;
+ case 0x0f: MAC_W(REG_M, REG_N); break;
+
+ case 0x10: DT(REG_N); break;
+ case 0x11: CMPPZ(REG_N); break;
+ case 0x12: STSMMACL(REG_N); break;
+ case 0x13: STCMGBR(REG_N); break;
+ case 0x14: ILLEGAL(); break;
+ case 0x15: CMPPL(REG_N); break;
+ case 0x16: LDSMMACL(REG_N); break;
+ case 0x17: LDCMGBR(REG_N); break;
+ case 0x18: SHLL8(REG_N); break;
+ case 0x19: SHLR8(REG_N); break;
+ case 0x1a: LDSMACL(REG_N); break;
+ case 0x1b: TAS(REG_N); break;
+ case 0x1c: ILLEGAL(); break;
+ case 0x1d: ILLEGAL(); break;
+ case 0x1e: LDCGBR(REG_N); break;
+ case 0x1f: MAC_W(REG_M, REG_N); break;
+
+ case 0x20: SHAL(REG_N); break;
+ case 0x21: SHAR(REG_N); break;
+ case 0x22: STSMPR(REG_N); break;
+ case 0x23: STCMVBR(REG_N); break;
+ case 0x24: ROTCL(REG_N); break;
+ case 0x25: ROTCR(REG_N); break;
+ case 0x26: LDSMPR(REG_N); break;
+ case 0x27: LDCMVBR(REG_N); break;
+ case 0x28: SHLL16(REG_N); break;
+ case 0x29: SHLR16(REG_N); break;
+ case 0x2a: LDSPR(REG_N); break;
+ case 0x2b: JMP(REG_N); break;
+ case 0x2c: ILLEGAL(); break;
+ case 0x2d: ILLEGAL(); break;
+ case 0x2e: LDCVBR(REG_N); break;
+ case 0x2f: MAC_W(REG_M, REG_N); break;
+
+ case 0x30: ILLEGAL(); break;
+ case 0x31: ILLEGAL(); break;
+ case 0x32: ILLEGAL(); break;
+ case 0x33: ILLEGAL(); break;
+ case 0x34: ILLEGAL(); break;
+ case 0x35: ILLEGAL(); break;
+ case 0x36: ILLEGAL(); break;
+ case 0x37: ILLEGAL(); break;
+ case 0x38: ILLEGAL(); break;
+ case 0x39: ILLEGAL(); break;
+ case 0x3a: ILLEGAL(); break;
+ case 0x3b: ILLEGAL(); break;
+ case 0x3c: ILLEGAL(); break;
+ case 0x3d: ILLEGAL(); break;
+ case 0x3e: ILLEGAL(); break;
+ case 0x3f: MAC_W(REG_M, REG_N); break;
}
}
void sh_common_execution::execute_one(const uint16_t opcode)
{
- switch(opcode & 0xf000)
+ switch ((opcode >> 12) & 15)
{
- case 0x0000: execute_one_0000(opcode); break;
- case 0x1000: MOVLS4(Rm, opcode & 0x0f, Rn); break;
- case 0x2000: op0010(opcode); break;
- case 0x3000: op0011(opcode); break;
- case 0x4000: execute_one_4000(opcode); break;
- case 0x5000: MOVLL4(Rm, opcode & 0x0f, Rn); break;
- case 0x6000: op0110(opcode); break;
- case 0x7000: ADDI(opcode & 0xff, Rn); break;
- case 0x8000: op1000(opcode); break;
- case 0x9000: MOVWI(opcode & 0xff, Rn); break;
- case 0xa000: BRA(opcode & 0xfff); break;
- case 0xb000: BSR(opcode & 0xfff); break;
- case 0xc000: op1100(opcode); break;
- case 0xd000: MOVLI(opcode & 0xff, Rn); break;
- case 0xe000: MOVI(opcode & 0xff, Rn); break;
- case 0xf000: execute_one_f000(opcode); break;
+ case 0: execute_one_0000(opcode); break;
+ case 1: MOVLS4(REG_M, opcode & 0xf, REG_N); break;
+ case 2: op0010(opcode); break;
+ case 3: op0011(opcode); break;
+ case 4: execute_one_4000(opcode); break;
+ case 5: MOVLL4(REG_M, opcode & 0x0f, REG_N); break;
+ case 6: op0110(opcode); break;
+ case 7: ADDI(opcode & 0xff, REG_N); break;
+ case 8: op1000(opcode); break;
+ case 9: MOVWI(opcode & 0xff, REG_N); break;
+ case 10: BRA(opcode & 0xfff); break;
+ case 11: BSR(opcode & 0xfff); break;
+ case 12: op1100(opcode); break;
+ case 13: MOVLI(opcode & 0xff, REG_N); break;
+ case 14: MOVI(opcode & 0xff, REG_N); break;
+ case 15: execute_one_f000(opcode); break;
}
}
@@ -2642,7 +2576,7 @@ void sh_common_execution::generate_delay_slot(drcuml_block &block, compiler_stat
void sh_common_execution::func_unimplemented()
{
// set up an invalid opcode exception
- m_sh2_state->evec = RL( m_sh2_state->vbr + 4 * 4 );
+ m_sh2_state->evec = read_long(m_sh2_state->vbr + 4 * 4);
m_sh2_state->evec &= m_am;
m_sh2_state->irqsr = m_sh2_state->sr;
// claim it's an NMI, because it pretty much is
@@ -2651,15 +2585,12 @@ void sh_common_execution::func_unimplemented()
void sh_common_execution::func_MAC_W()
{
- uint16_t opcode;
- int n, m;
-
// recover the opcode
- opcode = m_sh2_state->arg0;
+ uint32_t opcode = m_sh2_state->arg0;
// extract the operands
- n = Rn;
- m = Rm;
+ uint32_t n = REG_N;
+ uint32_t m = REG_M;
MAC_W(m, n);
}
@@ -2667,15 +2598,12 @@ void sh_common_execution::func_MAC_W()
void sh_common_execution::func_MAC_L()
{
- uint16_t opcode;
- int n, m;
-
// recover the opcode
- opcode = m_sh2_state->arg0;
+ uint32_t opcode = m_sh2_state->arg0;
// extract the operands
- n = Rn;
- m = Rm;
+ uint32_t n = REG_N;
+ uint32_t m = REG_M;
MAC_L(m, n);
}
@@ -2683,15 +2611,12 @@ void sh_common_execution::func_MAC_L()
void sh_common_execution::func_DIV1()
{
- uint16_t opcode;
- int n, m;
-
// recover the opcode
- opcode = m_sh2_state->arg0;
+ uint32_t opcode = m_sh2_state->arg0;
// extract the operands
- n = Rn;
- m = Rm;
+ uint32_t n = REG_N;
+ uint32_t m = REG_M;
DIV1(m, n);
}
@@ -2699,15 +2624,12 @@ void sh_common_execution::func_DIV1()
void sh_common_execution::func_ADDV()
{
- uint16_t opcode;
- int n, m;
-
// recover the opcode
- opcode = m_sh2_state->arg0;
+ uint32_t opcode = m_sh2_state->arg0;
// extract the operands
- n = Rn;
- m = Rm;
+ uint32_t n = REG_N;
+ uint32_t m = REG_M;
ADDV(m, n);
}
@@ -2715,15 +2637,12 @@ void sh_common_execution::func_ADDV()
void sh_common_execution::func_SUBV()
{
- uint16_t opcode;
- int n, m;
-
// recover the opcode
- opcode = m_sh2_state->arg0;
+ uint32_t opcode = m_sh2_state->arg0;
// extract the operands
- n = Rn;
- m = Rm;
+ uint32_t n = REG_N;
+ uint32_t m = REG_M;
SUBV(m, n);
}
@@ -2785,8 +2704,8 @@ bool sh_common_execution::generate_opcode(drcuml_block &block, compiler_state &c
case 1: // MOVLS4
scratch = (opcode & 0x0f) * 4;
- UML_ADD(block, I0, R32(Rn), scratch); // add r0, Rn, scratch
- UML_MOV(block, I1, R32(Rm)); // mov r1, Rm
+ UML_ADD(block, I0, R32(REG_N), scratch); // add r0, Rn, scratch
+ UML_MOV(block, I1, R32(REG_M)); // mov r1, Rm
SETEA(0); // set ea for debug
UML_CALLH(block, *m_write32);
@@ -2803,10 +2722,10 @@ bool sh_common_execution::generate_opcode(drcuml_block &block, compiler_state &c
case 5: // MOVLL4
scratch = (opcode & 0x0f) * 4;
- UML_ADD(block, I0, R32(Rm), scratch); // add r0, Rm, scratch
+ UML_ADD(block, I0, R32(REG_M), scratch); // add r0, Rm, scratch
SETEA(0); // set ea for debug
UML_CALLH(block, *m_read32); // call read32
- UML_MOV(block, R32(Rn), I0); // mov Rn, r0
+ UML_MOV(block, R32(REG_N), I0); // mov Rn, r0
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 2, true);
@@ -2818,7 +2737,7 @@ bool sh_common_execution::generate_opcode(drcuml_block &block, compiler_state &c
case 7: // ADDI
scratch = opcode & 0xff;
scratch2 = (uint32_t)(int32_t)(int16_t)(int8_t)scratch;
- UML_ADD(block, R32(Rn), R32(Rn), scratch2); // add Rn, Rn, scratch2
+ UML_ADD(block, R32(REG_N), R32(REG_N), scratch2); // add Rn, Rn, scratch2
return true;
case 8:
@@ -2826,25 +2745,21 @@ bool sh_common_execution::generate_opcode(drcuml_block &block, compiler_state &c
case 9: // MOVWI
if (ovrpc == 0xffffffff)
- {
scratch = (desc->pc + 2) + ((opcode & 0xff) * 2) + 2;
- }
else
- {
scratch = (ovrpc + 2) + ((opcode & 0xff) * 2) + 2;
- }
if (m_drcoptions & SH2DRC_STRICT_PCREL)
{
UML_MOV(block, I0, scratch); // mov r0, scratch
SETEA(0); // set ea for debug
UML_CALLH(block, *m_read16); // read16(r0, r1)
- UML_SEXT(block, R32(Rn), I0, SIZE_WORD); // sext Rn, r0, WORD
+ UML_SEXT(block, R32(REG_N), I0, SIZE_WORD); // sext Rn, r0, WORD
}
else
{
- scratch2 = (uint32_t)(int32_t)(int16_t) RW(scratch);
- UML_MOV(block, R32(Rn), scratch2); // mov Rn, scratch2
+ scratch2 = (uint32_t)util::sext(read_word(scratch), 16);
+ UML_MOV(block, R32(REG_N), scratch2); // mov Rn, scratch2
}
if (!in_delay_slot)
@@ -2892,12 +2807,12 @@ bool sh_common_execution::generate_opcode(drcuml_block &block, compiler_state &c
{
UML_MOV(block, I0, scratch); // mov r0, scratch
UML_CALLH(block, *m_read32); // read32(r0, r1)
- UML_MOV(block, R32(Rn), I0); // mov Rn, r0
+ UML_MOV(block, R32(REG_N), I0); // mov Rn, r0
}
else
{
- scratch2 = RL(scratch);
- UML_MOV(block, R32(Rn), scratch2); // mov Rn, scratch2
+ scratch2 = read_long(scratch);
+ UML_MOV(block, R32(REG_N), scratch2); // mov Rn, scratch2
}
if (!in_delay_slot)
@@ -2907,7 +2822,7 @@ bool sh_common_execution::generate_opcode(drcuml_block &block, compiler_state &c
case 14: // MOVI
scratch = opcode & 0xff;
scratch2 = (uint32_t)(int32_t)(int16_t)(int8_t)scratch;
- UML_MOV(block, R32(Rn), scratch2);
+ UML_MOV(block, R32(REG_N), scratch2);
return true;
case 15:
@@ -2928,8 +2843,8 @@ bool sh_common_execution::generate_group_2(drcuml_block &block, compiler_state &
switch (opcode & 15)
{
case 0: // MOVBS(Rm, Rn);
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
- UML_AND(block, I1, R32(Rm), 0xff); // and r1, Rm, 0xff
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
+ UML_AND(block, I1, R32(REG_M), 0xff); // and r1, Rm, 0xff
UML_CALLH(block, *m_write8);
if (!in_delay_slot)
@@ -2937,8 +2852,8 @@ bool sh_common_execution::generate_group_2(drcuml_block &block, compiler_state &
return true;
case 1: // MOVWS(Rm, Rn);
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
- UML_AND(block, I1, R32(Rm), 0xffff); // and r1, Rm, 0xffff
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
+ UML_AND(block, I1, R32(REG_M), 0xffff); // and r1, Rm, 0xffff
UML_CALLH(block, *m_write16);
if (!in_delay_slot)
@@ -2946,8 +2861,8 @@ bool sh_common_execution::generate_group_2(drcuml_block &block, compiler_state &
return true;
case 2: // MOVLS(Rm, Rn);
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
- UML_MOV(block, I1, R32(Rm)); // mov r1, Rm
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
+ UML_MOV(block, I1, R32(REG_M)); // mov r1, Rm
UML_CALLH(block, *m_write32);
if (!in_delay_slot)
@@ -2958,9 +2873,9 @@ bool sh_common_execution::generate_group_2(drcuml_block &block, compiler_state &
return false;
case 4: // MOVBM(Rm, Rn);
- UML_MOV(block, I1, R32(Rm)); // mov r1, Rm
- UML_SUB(block, R32(Rn), R32(Rn), 1); // sub Rn, Rn, 1
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_MOV(block, I1, R32(REG_M)); // mov r1, Rm
+ UML_SUB(block, R32(REG_N), R32(REG_N), 1); // sub Rn, Rn, 1
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
UML_CALLH(block, *m_write8); // call write8
if (!in_delay_slot)
@@ -2968,9 +2883,9 @@ bool sh_common_execution::generate_group_2(drcuml_block &block, compiler_state &
return true;
case 5: // MOVWM(Rm, Rn);
- UML_MOV(block, I1, R32(Rm)); // mov r1, Rm
- UML_SUB(block, R32(Rn), R32(Rn), 2); // sub Rn, Rn, 2
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_MOV(block, I1, R32(REG_M)); // mov r1, Rm
+ UML_SUB(block, R32(REG_N), R32(REG_N), 2); // sub Rn, Rn, 2
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
UML_CALLH(block, *m_write16); // call write16
if (!in_delay_slot)
@@ -2978,9 +2893,9 @@ bool sh_common_execution::generate_group_2(drcuml_block &block, compiler_state &
return true;
case 6: // MOVLM(Rm, Rn);
- UML_MOV(block, I1, R32(Rm)); // mov r1, Rm
- UML_SUB(block, R32(Rn), R32(Rn), 4); // sub Rn, Rn, 4
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_MOV(block, I1, R32(REG_M)); // mov r1, Rm
+ UML_SUB(block, R32(REG_N), R32(REG_N), 4); // sub Rn, Rn, 4
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
UML_CALLH(block, *m_write32); // call write32
if (!in_delay_slot)
@@ -2988,32 +2903,32 @@ bool sh_common_execution::generate_group_2(drcuml_block &block, compiler_state &
return true;
case 13: // XTRCT(Rm, Rn);
- UML_SHL(block, I0, R32(Rm), 16); // shl r0, Rm, #16
+ UML_SHL(block, I0, R32(REG_M), 16); // shl r0, Rm, #16
UML_AND(block, I0, I0, 0xffff0000); // and r0, r0, #0xffff0000
- UML_SHR(block, I1, R32(Rn), 16); // shr, r1, Rn, #16
+ UML_SHR(block, I1, R32(REG_N), 16); // shr, r1, Rn, #16
UML_AND(block, I1, I1, 0xffff); // and r1, r1, #0x0000ffff
- UML_OR(block, R32(Rn), I0, I1); // or Rn, r0, r1
+ UML_OR(block, R32(REG_N), I0, I1); // or Rn, r0, r1
return true;
case 7: // DIV0S(Rm, Rn);
UML_MOV(block, I0, mem(&m_sh2_state->sr)); // move r0, sr
UML_AND(block, I0, I0, ~(SH_Q|SH_M|SH_T)); // and r0, r0, ~(Q|M|T) (clear the Q,M, and T bits)
- UML_TEST(block, R32(Rn), 0x80000000); // test Rn, #0x80000000
+ UML_TEST(block, R32(REG_N), 0x80000000); // test Rn, #0x80000000
UML_JMPc(block, COND_Z, compiler.labelnum); // jz labelnum
UML_OR(block, I0, I0, SH_Q); // or r0, r0, Q
UML_LABEL(block, compiler.labelnum++); // labelnum:
- UML_TEST(block, R32(Rm), 0x80000000); // test Rm, #0x80000000
+ UML_TEST(block, R32(REG_M), 0x80000000); // test Rm, #0x80000000
UML_JMPc(block, COND_Z, compiler.labelnum); // jz labelnum
UML_OR(block, I0, I0, SH_M); // or r0, r0, M
UML_LABEL(block, compiler.labelnum++); // labelnum:
- UML_XOR(block, I1, R32(Rn), R32(Rm)); // xor r1, Rn, Rm
+ UML_XOR(block, I1, R32(REG_N), R32(REG_M)); // xor r1, Rn, Rm
UML_TEST(block, I1, 0x80000000); // test r1, #0x80000000
UML_JMPc(block, COND_Z, compiler.labelnum); // jz labelnum
@@ -3024,7 +2939,7 @@ bool sh_common_execution::generate_group_2(drcuml_block &block, compiler_state &
case 8: // TST(Rm, Rn);
UML_AND(block, I0, mem(&m_sh2_state->sr), ~SH_T); // and r0, sr, ~T (clear the T bit)
- UML_TEST(block, R32(Rm), R32(Rn)); // test Rm, Rn
+ UML_TEST(block, R32(REG_M), R32(REG_N)); // test Rm, Rn
UML_JMPc(block, COND_NZ, compiler.labelnum); // jnz compiler.labelnum
UML_OR(block, I0, I0, SH_T); // or r0, r0, T
@@ -3034,7 +2949,7 @@ bool sh_common_execution::generate_group_2(drcuml_block &block, compiler_state &
return true;
case 12: // CMPSTR(Rm, Rn);
- UML_XOR(block, I0, R32(Rn), R32(Rm)); // xor r0, Rn, Rm (temp)
+ UML_XOR(block, I0, R32(REG_N), R32(REG_M)); // xor r0, Rn, Rm (temp)
UML_SHR(block, I1, I0, 24); // shr r1, r0, #24 (HH)
UML_AND(block, I1, I1, 0xff); // and r1, r1, #0xff
@@ -3065,26 +2980,26 @@ bool sh_common_execution::generate_group_2(drcuml_block &block, compiler_state &
return true;
case 9: // AND(Rm, Rn);
- UML_AND(block, R32(Rn), R32(Rn), R32(Rm)); // and Rn, Rn, Rm
+ UML_AND(block, R32(REG_N), R32(REG_N), R32(REG_M)); // and Rn, Rn, Rm
return true;
case 10: // XOR(Rm, Rn);
- UML_XOR(block, R32(Rn), R32(Rn), R32(Rm)); // xor Rn, Rn, Rm
+ UML_XOR(block, R32(REG_N), R32(REG_N), R32(REG_M)); // xor Rn, Rn, Rm
return true;
case 11: // OR(Rm, Rn);
- UML_OR(block, R32(Rn), R32(Rn), R32(Rm)); // or Rn, Rn, Rm
+ UML_OR(block, R32(REG_N), R32(REG_N), R32(REG_M)); // or Rn, Rn, Rm
return true;
case 14: // MULU(Rm, Rn);
- UML_AND(block, I0, R32(Rm), 0xffff); // and r0, Rm, 0xffff
- UML_AND(block, I1, R32(Rn), 0xffff); // and r1, Rn, 0xffff
+ UML_AND(block, I0, R32(REG_M), 0xffff); // and r0, Rm, 0xffff
+ UML_AND(block, I1, R32(REG_N), 0xffff); // and r1, Rn, 0xffff
UML_MULU(block, mem(&m_sh2_state->macl), mem(&m_sh2_state->ea), I0, I1); // mulu macl, ea, r0, r1
return true;
case 15: // MULS(Rm, Rn);
- UML_SEXT(block, I0, R32(Rm), SIZE_WORD); // sext r0, Rm
- UML_SEXT(block, I1, R32(Rn), SIZE_WORD); // sext r1, Rn
+ UML_SEXT(block, I0, R32(REG_M), SIZE_WORD); // sext r0, Rm
+ UML_SEXT(block, I1, R32(REG_N), SIZE_WORD); // sext r1, Rn
UML_MULS(block, mem(&m_sh2_state->macl), mem(&m_sh2_state->ea), I0, I1); // muls macl, ea, r0, r1
return true;
}
@@ -3098,31 +3013,31 @@ bool sh_common_execution::generate_group_3(drcuml_block &block, compiler_state &
switch (opcode & 15)
{
case 0: // CMPEQ(Rm, Rn); (equality)
- UML_CMP(block, R32(Rn), R32(Rm)); // cmp Rn, Rm
+ UML_CMP(block, R32(REG_N), R32(REG_M)); // cmp Rn, Rm
UML_SETc(block, COND_E, I0); // set E, r0
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, 1); // rolins sr, r0, 0, 1
return true;
case 2: // CMPHS(Rm, Rn); (unsigned greater than or equal)
- UML_CMP(block, R32(Rn), R32(Rm)); // cmp Rn, Rm
+ UML_CMP(block, R32(REG_N), R32(REG_M)); // cmp Rn, Rm
UML_SETc(block, COND_AE, I0); // set AE, r0
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, 1); // rolins sr, r0, 0, 1
return true;
case 3: // CMPGE(Rm, Rn); (signed greater than or equal)
- UML_CMP(block, R32(Rn), R32(Rm)); // cmp Rn, Rm
+ UML_CMP(block, R32(REG_N), R32(REG_M)); // cmp Rn, Rm
UML_SETc(block, COND_GE, I0); // set GE, r0
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, 1); // rolins sr, r0, 0, 1
return true;
case 6: // CMPHI(Rm, Rn); (unsigned greater than)
- UML_CMP(block, R32(Rn), R32(Rm)); // cmp Rn, Rm
+ UML_CMP(block, R32(REG_N), R32(REG_M)); // cmp Rn, Rm
UML_SETc(block, COND_A, I0); // set A, r0
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, 1); // rolins sr, r0, 0, 1
return true;
case 7: // CMPGT(Rm, Rn); (signed greater than)
- UML_CMP(block, R32(Rn), R32(Rm)); // cmp Rn, Rm
+ UML_CMP(block, R32(REG_N), R32(REG_M)); // cmp Rn, Rm
UML_SETc(block, COND_G, I0); // set G, r0
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, 1); // rolins sr, r0, 0, 1
return true;
@@ -3141,7 +3056,7 @@ bool sh_common_execution::generate_group_3(drcuml_block &block, compiler_state &
case 5: // DMULU(Rm, Rn);
if (m_cpu_type > CPU_TYPE_SH1)
{
- UML_MULU(block, mem(&m_sh2_state->macl), mem(&m_sh2_state->mach), R32(Rn), R32(Rm));
+ UML_MULU(block, mem(&m_sh2_state->macl), mem(&m_sh2_state->mach), R32(REG_N), R32(REG_M));
return true;
}
break;
@@ -3149,22 +3064,22 @@ bool sh_common_execution::generate_group_3(drcuml_block &block, compiler_state &
case 13: // DMULS(Rm, Rn);
if (m_cpu_type > CPU_TYPE_SH1)
{
- UML_MULS(block, mem(&m_sh2_state->macl), mem(&m_sh2_state->mach), R32(Rn), R32(Rm));
+ UML_MULS(block, mem(&m_sh2_state->macl), mem(&m_sh2_state->mach), R32(REG_N), R32(REG_M));
return true;
}
break;
case 8: // SUB(Rm, Rn);
- UML_SUB(block, R32(Rn), R32(Rn), R32(Rm)); // sub Rn, Rn, Rm
+ UML_SUB(block, R32(REG_N), R32(REG_N), R32(REG_M)); // sub Rn, Rn, Rm
return true;
case 12: // ADD(Rm, Rn);
- UML_ADD(block, R32(Rn), R32(Rn), R32(Rm)); // add Rn, Rn, Rm
+ UML_ADD(block, R32(REG_N), R32(REG_N), R32(REG_M)); // add Rn, Rn, Rm
return true;
case 10: // SUBC(Rm, Rn);
UML_CARRY(block, mem(&m_sh2_state->sr), 0); // carry = T (T is bit 0 of SR)
- UML_SUBB(block, R32(Rn), R32(Rn), R32(Rm)); // addc Rn, Rn, Rm
+ UML_SUBB(block, R32(REG_N), R32(REG_N), R32(REG_M)); // addc Rn, Rn, Rm
UML_SETc(block, COND_C, I0); // setc i0, C
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, SH_T); // rolins sr,i0,0,T
return true;
@@ -3178,7 +3093,7 @@ bool sh_common_execution::generate_group_3(drcuml_block &block, compiler_state &
case 14: // ADDC(Rm, Rn);
UML_CARRY(block, mem(&m_sh2_state->sr), 0); // carry = T (T is bit 0 of SR)
- UML_ADDC(block, R32(Rn), R32(Rn), R32(Rm)); // addc Rn, Rn, Rm
+ UML_ADDC(block, R32(REG_N), R32(REG_N), R32(REG_M)); // addc Rn, Rn, Rm
UML_SETc(block, COND_C, I0); // setc i0, C
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, SH_T); // rolins sr,i0,0,T
return true;
@@ -3199,118 +3114,118 @@ bool sh_common_execution::generate_group_6(drcuml_block &block, compiler_state &
switch (opcode & 15)
{
case 0: // MOVBL(Rm, Rn);
- UML_MOV(block, I0, R32(Rm)); // mov r0, Rm
+ UML_MOV(block, I0, R32(REG_M)); // mov r0, Rm
SETEA(0); // debug: ea = r0
UML_CALLH(block, *m_read8); // call read8
- UML_SEXT(block, R32(Rn), I0, SIZE_BYTE); // sext Rn, r0, BYTE
+ UML_SEXT(block, R32(REG_N), I0, SIZE_BYTE); // sext Rn, r0, BYTE
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
case 1: // MOVWL(Rm, Rn);
- UML_MOV(block, I0, R32(Rm)); // mov r0, Rm
+ UML_MOV(block, I0, R32(REG_M)); // mov r0, Rm
SETEA(0); // debug: ea = r0
UML_CALLH(block, *m_read16); // call read16
- UML_SEXT(block, R32(Rn), I0, SIZE_WORD); // sext Rn, r0, WORD
+ UML_SEXT(block, R32(REG_N), I0, SIZE_WORD); // sext Rn, r0, WORD
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
case 2: // MOVLL(Rm, Rn);
- UML_MOV(block, I0, R32(Rm)); // mov r0, Rm
+ UML_MOV(block, I0, R32(REG_M)); // mov r0, Rm
SETEA(0); // debug: ea = r0
UML_CALLH(block, *m_read32); // call read32
- UML_MOV(block, R32(Rn), I0); // mov Rn, r0
+ UML_MOV(block, R32(REG_N), I0); // mov Rn, r0
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
case 3: // MOV(Rm, Rn);
- UML_MOV(block, R32(Rn), R32(Rm)); // mov Rn, Rm
+ UML_MOV(block, R32(REG_N), R32(REG_M)); // mov Rn, Rm
return true;
case 7: // NOT(Rm, Rn);
- UML_XOR(block, R32(Rn), R32(Rm), 0xffffffff); // xor Rn, Rm, 0xffffffff
+ UML_XOR(block, R32(REG_N), R32(REG_M), 0xffffffff); // xor Rn, Rm, 0xffffffff
return true;
case 9: // SWAPW(Rm, Rn);
- UML_ROL(block, R32(Rn), R32(Rm), 16); // rol Rn, Rm, 16
+ UML_ROL(block, R32(REG_N), R32(REG_M), 16); // rol Rn, Rm, 16
return true;
case 11: // NEG(Rm, Rn);
- UML_SUB(block, R32(Rn), 0, R32(Rm)); // sub Rn, 0, Rm
+ UML_SUB(block, R32(REG_N), 0, R32(REG_M)); // sub Rn, 0, Rm
return true;
case 12: // EXTUB(Rm, Rn);
- UML_AND(block, R32(Rn), R32(Rm), 0x000000ff); // and Rn, Rm, 0xff
+ UML_AND(block, R32(REG_N), R32(REG_M), 0x000000ff); // and Rn, Rm, 0xff
return true;
case 13: // EXTUW(Rm, Rn);
- UML_AND(block, R32(Rn), R32(Rm), 0x0000ffff); // and Rn, Rm, 0xffff
+ UML_AND(block, R32(REG_N), R32(REG_M), 0x0000ffff); // and Rn, Rm, 0xffff
return true;
case 14: // EXTSB(Rm, Rn);
- UML_SEXT(block, R32(Rn), R32(Rm), SIZE_BYTE); // sext Rn, Rm, BYTE
+ UML_SEXT(block, R32(REG_N), R32(REG_M), SIZE_BYTE); // sext Rn, Rm, BYTE
return true;
case 15: // EXTSW(Rm, Rn);
- UML_SEXT(block, R32(Rn), R32(Rm), SIZE_WORD); // sext Rn, Rm, WORD
+ UML_SEXT(block, R32(REG_N), R32(REG_M), SIZE_WORD); // sext Rn, Rm, WORD
return true;
case 4: // MOVBP(Rm, Rn);
- UML_MOV(block, I0, R32(Rm)); // mov r0, Rm
+ UML_MOV(block, I0, R32(REG_M)); // mov r0, Rm
UML_CALLH(block, *m_read8); // call read8
- UML_SEXT(block, R32(Rn), I0, SIZE_BYTE); // sext Rn, r0, BYTE
+ UML_SEXT(block, R32(REG_N), I0, SIZE_BYTE); // sext Rn, r0, BYTE
- if (Rm != Rn)
- UML_ADD(block, R32(Rm), R32(Rm), 1); // add Rm, Rm, #1
+ if (REG_M != REG_N)
+ UML_ADD(block, R32(REG_M), R32(REG_M), 1); // add Rm, Rm, #1
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
case 5: // MOVWP(Rm, Rn);
- UML_MOV(block, I0, R32(Rm)); // mov r0, Rm
+ UML_MOV(block, I0, R32(REG_M)); // mov r0, Rm
UML_CALLH(block, *m_read16); // call read16
- UML_SEXT(block, R32(Rn), I0, SIZE_WORD); // sext Rn, r0, WORD
+ UML_SEXT(block, R32(REG_N), I0, SIZE_WORD); // sext Rn, r0, WORD
- if (Rm != Rn)
- UML_ADD(block, R32(Rm), R32(Rm), 2); // add Rm, Rm, #2
+ if (REG_M != REG_N)
+ UML_ADD(block, R32(REG_M), R32(REG_M), 2); // add Rm, Rm, #2
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
case 6: // MOVLP(Rm, Rn);
- UML_MOV(block, I0, R32(Rm)); // mov r0, Rm
+ UML_MOV(block, I0, R32(REG_M)); // mov r0, Rm
UML_CALLH(block, *m_read32); // call read32
- UML_MOV(block, R32(Rn), I0); // mov Rn, r0
+ UML_MOV(block, R32(REG_N), I0); // mov Rn, r0
- if (Rm != Rn)
- UML_ADD(block, R32(Rm), R32(Rm), 4); // add Rm, Rm, #4
+ if (REG_M != REG_N)
+ UML_ADD(block, R32(REG_M), R32(REG_M), 4); // add Rm, Rm, #4
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
case 8: // SWAPB(Rm, Rn);
- UML_AND(block, I0, R32(Rm), 0xffff0000); // and r0, Rm, #0xffff0000
- UML_AND(block, I1, R32(Rm), 0x000000ff); // and r0, Rm, #0x000000ff
- UML_AND(block, I2, R32(Rm), 0x0000ff00); // and r0, Rm, #0x0000ff00
+ UML_AND(block, I0, R32(REG_M), 0xffff0000); // and r0, Rm, #0xffff0000
+ UML_AND(block, I1, R32(REG_M), 0x000000ff); // and r0, Rm, #0x000000ff
+ UML_AND(block, I2, R32(REG_M), 0x0000ff00); // and r0, Rm, #0x0000ff00
UML_SHL(block, I1, I1, 8); // shl r1, r1, #8
UML_SHR(block, I2, I2, 8); // shr r2, r2, #8
UML_OR(block, I0, I0, I1); // or r0, r0, r1
- UML_OR(block, R32(Rn), I0, I2); // or Rn, r0, r2
+ UML_OR(block, R32(REG_N), I0, I2); // or Rn, r0, r2
return true;
case 10: // NEGC(Rm, Rn);
UML_MOV(block, I0, mem(&m_sh2_state->sr)); // mov r0, sr (save SR)
UML_AND(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), ~SH_T); // and sr, sr, ~T (clear the T bit)
UML_CARRY(block, I0, 0); // carry = T (T is bit 0 of SR)
- UML_SUBB(block, R32(Rn), 0, R32(Rm)); // subb Rn, #0, Rm
+ UML_SUBB(block, R32(REG_N), 0, R32(REG_M)); // subb Rn, #0, Rm
UML_JMPc(block, COND_NC, compiler.labelnum); // jnc labelnum
@@ -3330,11 +3245,11 @@ bool sh_common_execution::generate_group_8(drcuml_block &block, compiler_state &
uint32_t udisp;
uml::code_label templabel;
- switch ( opcode & (15<<8) )
+ switch ((opcode >> 8) & 15)
{
- case 0 << 8: // MOVBS4(opcode & 0x0f, Rm);
+ case 0: // MOVBS4(opcode & 0x0f, Rm);
udisp = (opcode & 0x0f);
- UML_ADD(block, I0, R32(Rm), udisp); // add r0, Rm, udisp
+ UML_ADD(block, I0, R32(REG_M), udisp); // add r0, Rm, udisp
UML_MOV(block, I1, R32(0)); // mov r1, R0
UML_CALLH(block, *m_write8); // call write8
@@ -3342,9 +3257,9 @@ bool sh_common_execution::generate_group_8(drcuml_block &block, compiler_state &
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
- case 1 << 8: // MOVWS4(opcode & 0x0f, Rm);
+ case 1: // MOVWS4(opcode & 0x0f, Rm);
udisp = (opcode & 0x0f) * 2;
- UML_ADD(block, I0, R32(Rm), udisp); // add r0, Rm, udisp
+ UML_ADD(block, I0, R32(REG_M), udisp); // add r0, Rm, udisp
UML_MOV(block, I1, R32(0)); // mov r1, R0
UML_CALLH(block, *m_write16); // call write16
@@ -3352,18 +3267,18 @@ bool sh_common_execution::generate_group_8(drcuml_block &block, compiler_state &
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
- case 2<< 8:
- case 3<< 8:
- case 6<< 8:
- case 7<< 8:
- case 10<< 8:
- case 12<< 8:
- case 14<< 8:
+ case 2:
+ case 3:
+ case 6:
+ case 7:
+ case 10:
+ case 12:
+ case 14:
return false;
- case 4<< 8: // MOVBL4(Rm, opcode & 0x0f);
+ case 4: // MOVBL4(Rm, opcode & 0x0f);
udisp = opcode & 0x0f;
- UML_ADD(block, I0, R32(Rm), udisp); // add r0, Rm, udisp
+ UML_ADD(block, I0, R32(REG_M), udisp); // add r0, Rm, udisp
SETEA(0);
UML_CALLH(block, *m_read8); // call read8
UML_SEXT(block, R32(0), I0, SIZE_BYTE); // sext R0, r0, BYTE
@@ -3372,9 +3287,9 @@ bool sh_common_execution::generate_group_8(drcuml_block &block, compiler_state &
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
- case 5<< 8: // MOVWL4(Rm, opcode & 0x0f);
+ case 5: // MOVWL4(Rm, opcode & 0x0f);
udisp = (opcode & 0x0f)*2;
- UML_ADD(block, I0, R32(Rm), udisp); // add r0, Rm, udisp
+ UML_ADD(block, I0, R32(REG_M), udisp); // add r0, Rm, udisp
SETEA(0);
UML_CALLH(block, *m_read16); // call read16
UML_SEXT(block, R32(0), I0, SIZE_WORD); // sext R0, r0, WORD
@@ -3383,7 +3298,7 @@ bool sh_common_execution::generate_group_8(drcuml_block &block, compiler_state &
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
- case 8<< 8: // CMPIM(opcode & 0xff);
+ case 8: // CMPIM(opcode & 0xff);
UML_AND(block, I0, mem(&m_sh2_state->sr), ~SH_T); // and r0, sr, ~T (clear the T bit)
UML_SEXT(block, I1, opcode&0xff, SIZE_BYTE); // sext r1, opcode&0xff, BYTE
@@ -3396,7 +3311,7 @@ bool sh_common_execution::generate_group_8(drcuml_block &block, compiler_state &
UML_MOV(block, mem(&m_sh2_state->sr), I0); // mov m_sh2_state->sr, r0
return true;
- case 9<< 8: // BT(opcode & 0xff);
+ case 9: // BT(opcode & 0xff);
UML_TEST(block, mem(&m_sh2_state->sr), SH_T); // test m_sh2_state->sr, T
UML_JMPc(block, COND_Z, compiler.labelnum); // jz compiler.labelnum
@@ -3409,7 +3324,7 @@ bool sh_common_execution::generate_group_8(drcuml_block &block, compiler_state &
UML_LABEL(block, compiler.labelnum++); // labelnum:
return true;
- case 11<< 8: // BF(opcode & 0xff);
+ case 11: // BF(opcode & 0xff);
UML_TEST(block, mem(&m_sh2_state->sr), SH_T); // test m_sh2_state->sr, T
UML_JMPc(block, COND_NZ, compiler.labelnum); // jnz compiler.labelnum
@@ -3422,7 +3337,7 @@ bool sh_common_execution::generate_group_8(drcuml_block &block, compiler_state &
UML_LABEL(block, compiler.labelnum++); // labelnum:
return true;
- case 13<< 8: // BTS(opcode & 0xff);
+ case 13: // BTS(opcode & 0xff);
if (m_cpu_type > CPU_TYPE_SH1)
{
UML_TEST(block, mem(&m_sh2_state->sr), SH_T); // test m_sh2_state->sr, T
@@ -3443,7 +3358,7 @@ bool sh_common_execution::generate_group_8(drcuml_block &block, compiler_state &
}
break;
- case 15<< 8: // BFS(opcode & 0xff);
+ case 15: // BFS(opcode & 0xff);
if (m_cpu_type > CPU_TYPE_SH1)
{
UML_TEST(block, mem(&m_sh2_state->sr), SH_T); // test m_sh2_state->sr, T
@@ -3494,9 +3409,9 @@ bool sh_common_execution::generate_group_12(drcuml_block &block, compiler_state
{
uint32_t scratch;
- switch (opcode & (15<<8))
+ switch ((opcode >> 8) & 15)
{
- case 0<<8: // MOVBSG(opcode & 0xff);
+ case 0: // MOVBSG(opcode & 0xff);
scratch = (opcode & 0xff);
UML_ADD(block, I0, mem(&m_sh2_state->gbr), scratch); // add r0, gbr, scratch
UML_AND(block, I1, R32(0), 0xff); // and r1, R0, 0xff
@@ -3506,7 +3421,7 @@ bool sh_common_execution::generate_group_12(drcuml_block &block, compiler_state
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
- case 1<<8: // MOVWSG(opcode & 0xff);
+ case 1: // MOVWSG(opcode & 0xff);
scratch = (opcode & 0xff) * 2;
UML_ADD(block, I0, mem(&m_sh2_state->gbr), scratch); // add r0, gbr, scratch
UML_AND(block, I1, R32(0), 0xffff); // and r1, R0, 0xffff
@@ -3516,7 +3431,7 @@ bool sh_common_execution::generate_group_12(drcuml_block &block, compiler_state
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
- case 2<<8: // MOVLSG(opcode & 0xff);
+ case 2: // MOVLSG(opcode & 0xff);
scratch = (opcode & 0xff) * 4;
UML_ADD(block, I0, mem(&m_sh2_state->gbr), scratch); // add r0, gbr, scratch
UML_MOV(block, I1, R32(0)); // mov r1, R0
@@ -3526,10 +3441,10 @@ bool sh_common_execution::generate_group_12(drcuml_block &block, compiler_state
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
- case 3<<8: // TRAPA(opcode & 0xff);
+ case 3: // TRAPA(opcode & 0xff);
return generate_group_12_TRAPA(block, compiler, desc, opcode, in_delay_slot, ovrpc);
- case 4<<8: // MOVBLG(opcode & 0xff);
+ case 4: // MOVBLG(opcode & 0xff);
scratch = (opcode & 0xff);
UML_ADD(block, I0, mem(&m_sh2_state->gbr), scratch); // add r0, gbr, scratch
UML_CALLH(block, *m_read8); // call read16
@@ -3539,7 +3454,7 @@ bool sh_common_execution::generate_group_12(drcuml_block &block, compiler_state
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
- case 5<<8: // MOVWLG(opcode & 0xff);
+ case 5: // MOVWLG(opcode & 0xff);
scratch = (opcode & 0xff) * 2;
UML_ADD(block, I0, mem(&m_sh2_state->gbr), scratch); // add r0, gbr, scratch
UML_CALLH(block, *m_read16); // call read16
@@ -3549,7 +3464,7 @@ bool sh_common_execution::generate_group_12(drcuml_block &block, compiler_state
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
- case 6<<8: // MOVLLG(opcode & 0xff);
+ case 6: // MOVLLG(opcode & 0xff);
scratch = (opcode & 0xff) * 4;
UML_ADD(block, I0, mem(&m_sh2_state->gbr), scratch); // add r0, gbr, scratch
UML_CALLH(block, *m_read32); // call read32
@@ -3559,14 +3474,14 @@ bool sh_common_execution::generate_group_12(drcuml_block &block, compiler_state
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
- case 7<<8: // MOVA(opcode & 0xff);
+ case 7: // MOVA(opcode & 0xff);
scratch = (opcode & 0xff) * 4;
scratch += ((desc->pc + 4) & ~3);
UML_MOV(block, R32(0), scratch); // mov R0, scratch
return true;
- case 8<<8: // TSTI(opcode & 0xff);
+ case 8: // TSTI(opcode & 0xff);
scratch = opcode & 0xff;
UML_AND(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), ~SH_T); // and sr, sr, ~T (clear the T bit)
@@ -3579,19 +3494,19 @@ bool sh_common_execution::generate_group_12(drcuml_block &block, compiler_state
UML_LABEL(block, compiler.labelnum++); // labelnum:
return true;
- case 9<<8: // ANDI(opcode & 0xff);
+ case 9: // ANDI(opcode & 0xff);
UML_AND(block, R32(0), R32(0), opcode & 0xff); // and r0, r0, opcode & 0xff
return true;
- case 10<<8: // XORI(opcode & 0xff);
+ case 10: // XORI(opcode & 0xff);
UML_XOR(block, R32(0), R32(0), opcode & 0xff); // xor r0, r0, opcode & 0xff
return true;
- case 11<<8: // ORI(opcode & 0xff);
+ case 11: // ORI(opcode & 0xff);
UML_OR(block, R32(0), R32(0), opcode & 0xff); // or r0, r0, opcode & 0xff
return true;
- case 12<<8: // TSTM(opcode & 0xff);
+ case 12: // TSTM(opcode & 0xff);
UML_AND(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), ~SH_T); // and sr, sr, ~T (clear the T bit)
UML_ADD(block, I0, R32(0), mem(&m_sh2_state->gbr)); // add r0, R0, gbr
UML_CALLH(block, *m_read8); // read8
@@ -3605,7 +3520,7 @@ bool sh_common_execution::generate_group_12(drcuml_block &block, compiler_state
UML_LABEL(block, compiler.labelnum++); // labelnum:
return true;
- case 13<<8: // ANDM(opcode & 0xff);
+ case 13: // ANDM(opcode & 0xff);
UML_ADD(block, I0, R32(0), mem(&m_sh2_state->gbr)); // add r0, R0, gbr
UML_CALLH(block, *m_read8); // read8
@@ -3615,7 +3530,7 @@ bool sh_common_execution::generate_group_12(drcuml_block &block, compiler_state
UML_CALLH(block, *m_write8); // write8
return true;
- case 14<<8: // XORM(opcode & 0xff);
+ case 14: // XORM(opcode & 0xff);
UML_ADD(block, I0, R32(0), mem(&m_sh2_state->gbr)); // add r0, R0, gbr
UML_CALLH(block, *m_read8); // read8
@@ -3625,7 +3540,7 @@ bool sh_common_execution::generate_group_12(drcuml_block &block, compiler_state
UML_CALLH(block, *m_write8); // write8
return true;
- case 15<<8: // ORM(opcode & 0xff);
+ case 15: // ORM(opcode & 0xff);
UML_ADD(block, I0, R32(0), mem(&m_sh2_state->gbr)); // add r0, R0, gbr
UML_CALLH(block, *m_read8); // read8
@@ -3687,13 +3602,13 @@ bool sh_common_execution::generate_group_0(drcuml_block &block, compiler_state &
return true;
case 0x02: // STCSR(Rn);
- UML_MOV(block, R32(Rn), mem(&m_sh2_state->sr));
+ UML_MOV(block, R32(REG_N), mem(&m_sh2_state->sr));
return true;
case 0x03: // BSRF(Rn);
if (m_cpu_type > CPU_TYPE_SH1)
{
- UML_ADD(block, mem(&m_sh2_state->target), R32(Rn), 4); // add target, Rm, #4
+ UML_ADD(block, mem(&m_sh2_state->target), R32(REG_N), 4); // add target, Rm, #4
UML_ADD(block, mem(&m_sh2_state->target), mem(&m_sh2_state->target), desc->pc); // add target, target, pc
// 32x Cosmic Carnage @ 6002cb0 relies on the delay slot
@@ -3712,8 +3627,8 @@ bool sh_common_execution::generate_group_0(drcuml_block &block, compiler_state &
case 0x14: // MOVBS0(Rm, Rn);
case 0x24: // MOVBS0(Rm, Rn);
case 0x34: // MOVBS0(Rm, Rn);
- UML_ADD(block, I0, R32(0), R32(Rn)); // add r0, R0, Rn
- UML_AND(block, I1, R32(Rm), 0x000000ff); // and r1, Rm, 0xff
+ UML_ADD(block, I0, R32(0), R32(REG_N)); // add r0, R0, Rn
+ UML_AND(block, I1, R32(REG_M), 0x000000ff); // and r1, Rm, 0xff
UML_CALLH(block, *m_write8); // call write8
if (!in_delay_slot)
@@ -3724,8 +3639,8 @@ bool sh_common_execution::generate_group_0(drcuml_block &block, compiler_state &
case 0x15: // MOVWS0(Rm, Rn);
case 0x25: // MOVWS0(Rm, Rn);
case 0x35: // MOVWS0(Rm, Rn);
- UML_ADD(block, I0, R32(0), R32(Rn)); // add r0, R0, Rn
- UML_AND(block, I1, R32(Rm), 0x0000ffff); // and r1, Rm, 0xffff
+ UML_ADD(block, I0, R32(0), R32(REG_N)); // add r0, R0, Rn
+ UML_AND(block, I1, R32(REG_M), 0x0000ffff); // and r1, Rm, 0xffff
UML_CALLH(block, *m_write16); // call write16
if (!in_delay_slot)
@@ -3736,8 +3651,8 @@ bool sh_common_execution::generate_group_0(drcuml_block &block, compiler_state &
case 0x16: // MOVLS0(Rm, Rn);
case 0x26: // MOVLS0(Rm, Rn);
case 0x36: // MOVLS0(Rm, Rn);
- UML_ADD(block, I0, R32(0), R32(Rn)); // add r0, R0, Rn
- UML_MOV(block, I1, R32(Rm)); // mov r1, Rm
+ UML_ADD(block, I0, R32(0), R32(REG_N)); // add r0, R0, Rn
+ UML_MOV(block, I1, R32(REG_M)); // mov r1, Rm
UML_CALLH(block, *m_write32); // call write32
if (!in_delay_slot)
@@ -3750,7 +3665,7 @@ bool sh_common_execution::generate_group_0(drcuml_block &block, compiler_state &
case 0x37: // MULL(Rm, Rn);
if (m_cpu_type > CPU_TYPE_SH1)
{
- UML_MULU(block, mem(&m_sh2_state->macl), mem(&m_sh2_state->ea), R32(Rn), R32(Rm)); // mulu macl, ea, Rn, Rm
+ UML_MULU(block, mem(&m_sh2_state->macl), mem(&m_sh2_state->ea), R32(REG_N), R32(REG_M)); // mulu macl, ea, Rn, Rm
return true;
}
break;
@@ -3760,7 +3675,7 @@ bool sh_common_execution::generate_group_0(drcuml_block &block, compiler_state &
return true;
case 0x0a: // STSMACH(Rn);
- UML_MOV(block, R32(Rn), mem(&m_sh2_state->mach)); // mov Rn, mach
+ UML_MOV(block, R32(REG_N), mem(&m_sh2_state->mach)); // mov Rn, mach
return true;
case 0x0b: // RTS();
@@ -3776,9 +3691,9 @@ bool sh_common_execution::generate_group_0(drcuml_block &block, compiler_state &
case 0x1c: // MOVBL0(Rm, Rn);
case 0x2c: // MOVBL0(Rm, Rn);
case 0x3c: // MOVBL0(Rm, Rn);
- UML_ADD(block, I0, R32(0), R32(Rm)); // add r0, R0, Rm
+ UML_ADD(block, I0, R32(0), R32(REG_M)); // add r0, R0, Rm
UML_CALLH(block, *m_read8); // call read8
- UML_SEXT(block, R32(Rn), I0, SIZE_BYTE); // sext Rn, r0, BYTE
+ UML_SEXT(block, R32(REG_N), I0, SIZE_BYTE); // sext Rn, r0, BYTE
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 2, true);
@@ -3788,9 +3703,9 @@ bool sh_common_execution::generate_group_0(drcuml_block &block, compiler_state &
case 0x1d: // MOVWL0(Rm, Rn);
case 0x2d: // MOVWL0(Rm, Rn);
case 0x3d: // MOVWL0(Rm, Rn);
- UML_ADD(block, I0, R32(0), R32(Rm)); // add r0, R0, Rm
+ UML_ADD(block, I0, R32(0), R32(REG_M)); // add r0, R0, Rm
UML_CALLH(block, *m_read16); // call read16
- UML_SEXT(block, R32(Rn), I0, SIZE_WORD); // sext Rn, r0, WORD
+ UML_SEXT(block, R32(REG_N), I0, SIZE_WORD); // sext Rn, r0, WORD
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 2, true);
@@ -3800,9 +3715,9 @@ bool sh_common_execution::generate_group_0(drcuml_block &block, compiler_state &
case 0x1e: // MOVLL0(Rm, Rn);
case 0x2e: // MOVLL0(Rm, Rn);
case 0x3e: // MOVLL0(Rm, Rn);
- UML_ADD(block, I0, R32(0), R32(Rm)); // add r0, R0, Rm
+ UML_ADD(block, I0, R32(0), R32(REG_M)); // add r0, R0, Rm
UML_CALLH(block, *m_read32); // call read32
- UML_MOV(block, R32(Rn), I0); // mov Rn, r0
+ UML_MOV(block, R32(REG_N), I0); // mov Rn, r0
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 2, true);
@@ -3823,7 +3738,7 @@ bool sh_common_execution::generate_group_0(drcuml_block &block, compiler_state &
break;
case 0x12: // STCGBR(Rn);
- UML_MOV(block, R32(Rn), mem(&m_sh2_state->gbr)); // mov Rn, gbr
+ UML_MOV(block, R32(REG_N), mem(&m_sh2_state->gbr)); // mov Rn, gbr
return true;
case 0x18: // SETT();
@@ -3835,7 +3750,7 @@ bool sh_common_execution::generate_group_0(drcuml_block &block, compiler_state &
return true;
case 0x1a: // STSMACL(Rn);
- UML_MOV(block, R32(Rn), mem(&m_sh2_state->macl)); // mov Rn, macl
+ UML_MOV(block, R32(REG_N), mem(&m_sh2_state->macl)); // mov Rn, macl
return true;
case 0x1b: // SLEEP();
@@ -3856,13 +3771,13 @@ bool sh_common_execution::generate_group_0(drcuml_block &block, compiler_state &
return true;
case 0x22: // STCVBR(Rn);
- UML_MOV(block, R32(Rn), mem(&m_sh2_state->vbr)); // mov Rn, vbr
+ UML_MOV(block, R32(REG_N), mem(&m_sh2_state->vbr)); // mov Rn, vbr
return true;
case 0x23: // BRAF(Rn);
if (m_cpu_type > CPU_TYPE_SH1)
{
- UML_ADD(block, mem(&m_sh2_state->target), R32(Rn), desc->pc+4); // add target, Rn, pc+4
+ UML_ADD(block, mem(&m_sh2_state->target), R32(REG_N), desc->pc+4); // add target, Rn, pc+4
generate_delay_slot(block, compiler, desc, m_sh2_state->target);
@@ -3878,11 +3793,11 @@ bool sh_common_execution::generate_group_0(drcuml_block &block, compiler_state &
return true;
case 0x29: // MOVT(Rn);
- UML_AND(block, R32(Rn), mem(&m_sh2_state->sr), SH_T); // and Rn, sr, T
+ UML_AND(block, R32(REG_N), mem(&m_sh2_state->sr), SH_T); // and Rn, sr, T
return true;
case 0x2a: // STSPR(Rn);
- UML_MOV(block, R32(Rn), mem(&m_sh2_state->pr)); // mov Rn, pr
+ UML_MOV(block, R32(REG_N), mem(&m_sh2_state->pr)); // mov Rn, pr
return true;
case 0x2b: // RTE();
@@ -3895,7 +3810,7 @@ bool sh_common_execution::generate_group_0(drcuml_block &block, compiler_state &
bool sh_common_execution::generate_group_4_LDCSR(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc)
{
// needs to be different on SH2 / 4
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
UML_AND(block, I0, I0, SH_FLAGS); // and r0, r0, FLAGS
UML_MOV(block, mem(&m_sh2_state->sr), I0);
@@ -3905,10 +3820,10 @@ bool sh_common_execution::generate_group_4_LDCSR(drcuml_block &block, compiler_s
bool sh_common_execution::generate_group_4_LDCMSR(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc)
{
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
SETEA(0);
UML_CALLH(block, *m_read32); // call read32
- UML_ADD(block, R32(Rn), R32(Rn), 4); // add Rn, #4
+ UML_ADD(block, R32(REG_N), R32(REG_N), 4); // add Rn, #4
UML_MOV(block, mem(&m_sh2_state->sr), I0); // mov sr, r0
compiler.checkints = true;
@@ -3922,32 +3837,32 @@ bool sh_common_execution::generate_group_4(drcuml_block &block, compiler_state &
switch (opcode & 0x3F)
{
case 0x00: // SHLL(Rn);
- UML_SHL(block, R32(Rn), R32(Rn), 1); // shl Rn, Rn, 1
+ UML_SHL(block, R32(REG_N), R32(REG_N), 1); // shl Rn, Rn, 1
UML_SETc(block, COND_C, I0); // set i0,C
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, SH_T); // rolins [sr],i0,0,T
return true;
case 0x01: // SHLR(Rn);
- UML_SHR(block, R32(Rn), R32(Rn), 1); // shr Rn, Rn, 1
+ UML_SHR(block, R32(REG_N), R32(REG_N), 1); // shr Rn, Rn, 1
UML_SETc(block, COND_C, I0); // set i0,C
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, SH_T); // rolins [sr],i0,0,T
return true;
case 0x04: // ROTL(Rn);
- UML_ROL(block, R32(Rn), R32(Rn), 1); // rol Rn, Rn, 1
+ UML_ROL(block, R32(REG_N), R32(REG_N), 1); // rol Rn, Rn, 1
UML_SETc(block, COND_C, I0); // set i0,C
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, SH_T); // rolins [sr],i0,0,T
return true;
case 0x05: // ROTR(Rn);
- UML_ROR(block, R32(Rn), R32(Rn), 1); // ror Rn, Rn, 1
+ UML_ROR(block, R32(REG_N), R32(REG_N), 1); // ror Rn, Rn, 1
UML_SETc(block, COND_C, I0); // set i0,C
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, SH_T); // rolins [sr],i0,0,T
return true;
case 0x02: // STSMMACH(Rn);
- UML_SUB(block, R32(Rn), R32(Rn), 4); // sub Rn, Rn, #4
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_SUB(block, R32(REG_N), R32(REG_N), 4); // sub Rn, Rn, #4
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
UML_MOV(block, I1, mem(&m_sh2_state->mach)); // mov r1, mach
SETEA(0); // set ea for debug
UML_CALLH(block, *m_write32); // call write32
@@ -3957,8 +3872,8 @@ bool sh_common_execution::generate_group_4(drcuml_block &block, compiler_state &
return true;
case 0x03: // STCMSR(Rn);
- UML_SUB(block, R32(Rn), R32(Rn), 4); // sub Rn, Rn, #4
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_SUB(block, R32(REG_N), R32(REG_N), 4); // sub Rn, Rn, #4
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
UML_MOV(block, I1, mem(&m_sh2_state->sr)); // mov r1, sr
SETEA(0); // set ea for debug
UML_CALLH(block, *m_write32); // call write32
@@ -3968,10 +3883,10 @@ bool sh_common_execution::generate_group_4(drcuml_block &block, compiler_state &
return true;
case 0x06: // LDSMMACH(Rn);
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
SETEA(0);
UML_CALLH(block, *m_read32); // call read32
- UML_ADD(block, R32(Rn), R32(Rn), 4); // add Rn, #4
+ UML_ADD(block, R32(REG_N), R32(REG_N), 4); // add Rn, #4
UML_MOV(block, mem(&m_sh2_state->mach), I0); // mov mach, r0
if (!in_delay_slot)
@@ -3982,35 +3897,35 @@ bool sh_common_execution::generate_group_4(drcuml_block &block, compiler_state &
return generate_group_4_LDCMSR(block, compiler, desc, opcode, in_delay_slot, ovrpc);
case 0x08: // SHLL2(Rn);
- UML_SHL(block, R32(Rn), R32(Rn), 2);
+ UML_SHL(block, R32(REG_N), R32(REG_N), 2);
return true;
case 0x09: // SHLR2(Rn);
- UML_SHR(block, R32(Rn), R32(Rn), 2);
+ UML_SHR(block, R32(REG_N), R32(REG_N), 2);
return true;
case 0x18: // SHLL8(Rn);
- UML_SHL(block, R32(Rn), R32(Rn), 8);
+ UML_SHL(block, R32(REG_N), R32(REG_N), 8);
return true;
case 0x19: // SHLR8(Rn);
- UML_SHR(block, R32(Rn), R32(Rn), 8);
+ UML_SHR(block, R32(REG_N), R32(REG_N), 8);
return true;
case 0x28: // SHLL16(Rn);
- UML_SHL(block, R32(Rn), R32(Rn), 16);
+ UML_SHL(block, R32(REG_N), R32(REG_N), 16);
return true;
case 0x29: // SHLR16(Rn);
- UML_SHR(block, R32(Rn), R32(Rn), 16);
+ UML_SHR(block, R32(REG_N), R32(REG_N), 16);
return true;
case 0x0a: // LDSMACH(Rn);
- UML_MOV(block, mem(&m_sh2_state->mach), R32(Rn)); // mov mach, Rn
+ UML_MOV(block, mem(&m_sh2_state->mach), R32(REG_N)); // mov mach, Rn
return true;
case 0x0b: // JSR(Rn);
- UML_MOV(block, mem(&m_sh2_state->target), R32(Rn)); // mov target, Rn
+ UML_MOV(block, mem(&m_sh2_state->target), R32(REG_N)); // mov target, Rn
UML_ADD(block, mem(&m_sh2_state->pr), desc->pc, 4); // add m_pr, desc->pc, #4 (skip the current insn & delay slot)
@@ -4037,7 +3952,7 @@ bool sh_common_execution::generate_group_4(drcuml_block &block, compiler_state &
if (m_cpu_type > CPU_TYPE_SH1)
{
UML_AND(block, I0, mem(&m_sh2_state->sr), ~SH_T); // and r0, sr, ~T (clear the T bit)
- UML_SUB(block, R32(Rn), R32(Rn), 1); // sub Rn, Rn, 1
+ UML_SUB(block, R32(REG_N), R32(REG_N), 1); // sub Rn, Rn, 1
UML_JMPc(block, COND_NZ, compiler.labelnum); // jz compiler.labelnum
UML_OR(block, I0, I0, SH_T); // or r0, r0, T
@@ -4051,7 +3966,7 @@ bool sh_common_execution::generate_group_4(drcuml_block &block, compiler_state &
case 0x11: // CMPPZ(Rn);
UML_AND(block, I0, mem(&m_sh2_state->sr), ~SH_T); // and r0, sr, ~T (clear the T bit)
- UML_CMP(block, R32(Rn), 0); // cmp Rn, 0
+ UML_CMP(block, R32(REG_N), 0); // cmp Rn, 0
UML_JMPc(block, COND_S, compiler.labelnum); // js compiler.labelnum (if negative)
UML_OR(block, I0, I0, SH_T); // or r0, r0, T
@@ -4063,7 +3978,7 @@ bool sh_common_execution::generate_group_4(drcuml_block &block, compiler_state &
case 0x15: // CMPPL(Rn);
UML_AND(block, I0, mem(&m_sh2_state->sr), ~SH_T); // and r0, sr, ~T (clear the T bit)
- UML_CMP(block, R32(Rn), 0); // cmp Rn, 0
+ UML_CMP(block, R32(REG_N), 0); // cmp Rn, 0
UML_JMPc(block, COND_S, compiler.labelnum); // js compiler.labelnum (if negative)
UML_JMPc(block, COND_Z, compiler.labelnum); // jz compiler.labelnum (if zero)
@@ -4075,8 +3990,8 @@ bool sh_common_execution::generate_group_4(drcuml_block &block, compiler_state &
return true;
case 0x12: // STSMMACL(Rn);
- UML_SUB(block, R32(Rn), R32(Rn), 4); // sub Rn, Rn, #4
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_SUB(block, R32(REG_N), R32(REG_N), 4); // sub Rn, Rn, #4
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
UML_MOV(block, I1, mem(&m_sh2_state->macl)); // mov r1, macl
SETEA(0); // set ea for debug
UML_CALLH(block, *m_write32); // call write32
@@ -4086,8 +4001,8 @@ bool sh_common_execution::generate_group_4(drcuml_block &block, compiler_state &
return true;
case 0x13: // STCMGBR(Rn);
- UML_SUB(block, R32(Rn), R32(Rn), 4); // sub Rn, Rn, #4
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_SUB(block, R32(REG_N), R32(REG_N), 4); // sub Rn, Rn, #4
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
UML_MOV(block, I1, mem(&m_sh2_state->gbr)); // mov r1, gbr
SETEA(0); // set ea for debug
UML_CALLH(block, *m_write32); // call write32
@@ -4097,10 +4012,10 @@ bool sh_common_execution::generate_group_4(drcuml_block &block, compiler_state &
return true;
case 0x16: // LDSMMACL(Rn);
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
SETEA(0);
UML_CALLH(block, *m_read32); // call read32
- UML_ADD(block, R32(Rn), R32(Rn), 4); // add Rn, #4
+ UML_ADD(block, R32(REG_N), R32(REG_N), 4); // add Rn, #4
UML_MOV(block, mem(&m_sh2_state->macl), I0); // mov macl, r0
if (!in_delay_slot)
@@ -4108,10 +4023,10 @@ bool sh_common_execution::generate_group_4(drcuml_block &block, compiler_state &
return true;
case 0x17: // LDCMGBR(Rn);
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
SETEA(0);
UML_CALLH(block, *m_read32); // call read32
- UML_ADD(block, R32(Rn), R32(Rn), 4); // add Rn, #4
+ UML_ADD(block, R32(REG_N), R32(REG_N), 4); // add Rn, #4
UML_MOV(block, mem(&m_sh2_state->gbr), I0); // mov gbr, r0
if (!in_delay_slot)
@@ -4119,11 +4034,11 @@ bool sh_common_execution::generate_group_4(drcuml_block &block, compiler_state &
return true;
case 0x1a: // LDSMACL(Rn);
- UML_MOV(block, mem(&m_sh2_state->macl), R32(Rn)); // mov macl, Rn
+ UML_MOV(block, mem(&m_sh2_state->macl), R32(REG_N)); // mov macl, Rn
return true;
case 0x1b: // TAS(Rn);
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
SETEA(0);
UML_CALLH(block, *m_read8); // call read8
@@ -4138,7 +4053,7 @@ bool sh_common_execution::generate_group_4(drcuml_block &block, compiler_state &
UML_OR(block, I1, I0, 0x80); // or r1, r0, #0x80
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
UML_CALLH(block, *m_write8); // write the value back
if (!in_delay_slot)
@@ -4146,27 +4061,27 @@ bool sh_common_execution::generate_group_4(drcuml_block &block, compiler_state &
return true;
case 0x1e: // LDCGBR(Rn);
- UML_MOV(block, mem(&m_sh2_state->gbr), R32(Rn)); // mov gbr, Rn
+ UML_MOV(block, mem(&m_sh2_state->gbr), R32(REG_N)); // mov gbr, Rn
return true;
case 0x20: // SHAL(Rn);
UML_AND(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), ~SH_T); // and sr, sr, ~T
- UML_SHR(block, I0, R32(Rn), 31); // shr r0, Rn, 31
+ UML_SHR(block, I0, R32(REG_N), 31); // shr r0, Rn, 31
UML_AND(block, I0, I0, SH_T); // and r0, r0, T
UML_OR(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), I0); // or sr, sr, r0
- UML_SHL(block, R32(Rn), R32(Rn), 1); // shl Rn, Rn, 1
+ UML_SHL(block, R32(REG_N), R32(REG_N), 1); // shl Rn, Rn, 1
return true;
case 0x21: // SHAR(Rn);
UML_AND(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), ~SH_T); // and sr, sr, ~T
- UML_AND(block, I0, R32(Rn), SH_T); // and r0, Rn, T
+ UML_AND(block, I0, R32(REG_N), SH_T); // and r0, Rn, T
UML_OR(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), I0); // or sr, sr, r0
- UML_SAR(block, R32(Rn), R32(Rn), 1); // sar Rn, Rn, 1
+ UML_SAR(block, R32(REG_N), R32(REG_N), 1); // sar Rn, Rn, 1
return true;
case 0x22: // STSMPR(Rn);
- UML_SUB(block, R32(Rn), R32(Rn), 4); // sub Rn, Rn, 4
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_SUB(block, R32(REG_N), R32(REG_N), 4); // sub Rn, Rn, 4
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
SETEA(0);
UML_MOV(block, I1, mem(&m_sh2_state->pr)); // mov r1, pr
UML_CALLH(block, *m_write32); // call write32
@@ -4176,8 +4091,8 @@ bool sh_common_execution::generate_group_4(drcuml_block &block, compiler_state &
return true;
case 0x23: // STCMVBR(Rn);
- UML_SUB(block, R32(Rn), R32(Rn), 4); // sub Rn, Rn, 4
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_SUB(block, R32(REG_N), R32(REG_N), 4); // sub Rn, Rn, 4
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
SETEA(0);
UML_MOV(block, I1, mem(&m_sh2_state->vbr)); // mov r1, vbr
UML_CALLH(block, *m_write32); // call write32
@@ -4188,46 +4103,46 @@ bool sh_common_execution::generate_group_4(drcuml_block &block, compiler_state &
case 0x24: // ROTCL(Rn);
UML_CARRY(block, mem(&m_sh2_state->sr), 0); // carry sr,0
- UML_ROLC(block, R32(Rn), R32(Rn), 1); // rolc Rn,Rn,1
+ UML_ROLC(block, R32(REG_N), R32(REG_N), 1); // rolc Rn,Rn,1
UML_SETc(block, COND_C, I0); // set i0,C
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, SH_T); // rolins sr,i0,0,T
return true;
case 0x25: // ROTCR(Rn);
UML_CARRY(block, mem(&m_sh2_state->sr), 0); // carry sr,0
- UML_RORC(block, R32(Rn), R32(Rn), 1); // rorc Rn,Rn,1
+ UML_RORC(block, R32(REG_N), R32(REG_N), 1); // rorc Rn,Rn,1
UML_SETc(block, COND_C, I0); // set i0,C
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, SH_T); // rolins sr,i0,0,T
return true;
case 0x26: // LDSMPR(Rn);
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
SETEA(0);
UML_CALLH(block, *m_read32); // call read32
UML_MOV(block, mem(&m_sh2_state->pr), I0); // mov m_pr, r0
- UML_ADD(block, R32(Rn), R32(Rn), 4); // add Rn, Rn, #4
+ UML_ADD(block, R32(REG_N), R32(REG_N), 4); // add Rn, Rn, #4
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
case 0x27: // LDCMVBR(Rn);
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
SETEA(0);
UML_CALLH(block, *m_read32); // call read32
UML_MOV(block, mem(&m_sh2_state->vbr), I0); // mov m_sh2_state->vbr, r0
- UML_ADD(block, R32(Rn), R32(Rn), 4); // add Rn, Rn, #4
+ UML_ADD(block, R32(REG_N), R32(REG_N), 4); // add Rn, Rn, #4
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
case 0x2a: // LDSPR(Rn);
- UML_MOV(block, mem(&m_sh2_state->pr), R32(Rn)); // mov m_pr, Rn
+ UML_MOV(block, mem(&m_sh2_state->pr), R32(REG_N)); // mov m_pr, Rn
return true;
case 0x2b: // JMP(Rn);
- UML_MOV(block, mem(&m_sh2_state->target), R32(Rn)); // mov target, Rn
+ UML_MOV(block, mem(&m_sh2_state->target), R32(REG_N)); // mov target, Rn
generate_delay_slot(block, compiler, desc, m_sh2_state->target);
@@ -4236,7 +4151,7 @@ bool sh_common_execution::generate_group_4(drcuml_block &block, compiler_state &
return true;
case 0x2e: // LDCVBR(Rn);
- UML_MOV(block, mem(&m_sh2_state->vbr), R32(Rn)); // mov vbr, Rn
+ UML_MOV(block, mem(&m_sh2_state->vbr), R32(REG_N)); // mov vbr, Rn
return true;
case 0x0c:
diff --git a/src/devices/cpu/sh/sh.h b/src/devices/cpu/sh/sh.h
index 33b7583cd1e..54e27e963fc 100644
--- a/src/devices/cpu/sh/sh.h
+++ b/src/devices/cpu/sh/sh.h
@@ -51,8 +51,8 @@
#define CPU_TYPE_SH3 (2)
#define CPU_TYPE_SH4 (3)
-#define Rn ((opcode>>8)&15)
-#define Rm ((opcode>>4)&15)
+#define REG_N ((opcode >> 8) & 15)
+#define REG_M ((opcode >> 4) & 15)
/* Bits in SR */
#define SH_T 0x00000001
@@ -84,9 +84,9 @@
MACROS
***************************************************************************/
-#define SH2_CODE_XOR(a) ((a) ^ NATIVE_ENDIAN_VALUE_LE_BE(2,0)) // sh2
-#define SH34LE_CODE_XOR(a) ((a) ^ NATIVE_ENDIAN_VALUE_LE_BE(0,6)) // naomi
-#define SH34BE_CODE_XOR(a) ((a) ^ NATIVE_ENDIAN_VALUE_LE_BE(6,0)) // cave
+#define SH2_CODE_XOR(a) ((a) ^ NATIVE_ENDIAN_VALUE_LE_BE(2, 0)) // sh2
+#define SH34LE_CODE_XOR(a) ((a) ^ NATIVE_ENDIAN_VALUE_LE_BE(0, 6)) // naomi
+#define SH34BE_CODE_XOR(a) ((a) ^ NATIVE_ENDIAN_VALUE_LE_BE(6, 0)) // cave
#define R32(reg) m_regmap[reg]
@@ -168,12 +168,13 @@ public:
internal_sh2_state *m_sh2_state;
- virtual uint8_t RB(offs_t A) = 0;
- virtual uint16_t RW(offs_t A) = 0;
- virtual uint32_t RL(offs_t A) = 0;
- virtual void WB(offs_t A, uint8_t V) = 0;
- virtual void WW(offs_t A, uint16_t V) = 0;
- virtual void WL(offs_t A, uint32_t V) = 0;
+ virtual uint8_t read_byte(offs_t offset) = 0;
+ virtual uint16_t read_word(offs_t offset) = 0;
+ virtual uint32_t read_long(offs_t offset) = 0;
+ virtual uint16_t decrypted_read_word(offs_t offset) = 0;
+ virtual void write_byte(offs_t offset, uint8_t data) = 0;
+ virtual void write_word(offs_t offset, uint16_t data) = 0;
+ virtual void write_long(offs_t offset, uint32_t data) = 0;
virtual void set_frt_input(int state) = 0;
void pulse_frt_input() { set_frt_input(ASSERT_LINE); set_frt_input(CLEAR_LINE); }
diff --git a/src/devices/cpu/sh/sh2.cpp b/src/devices/cpu/sh/sh2.cpp
index 72576a67b2d..38d378b8b91 100644
--- a/src/devices/cpu/sh/sh2.cpp
+++ b/src/devices/cpu/sh/sh2.cpp
@@ -2,7 +2,7 @@
// copyright-holders:Juergen Buchmueller, R. Belmont
/*****************************************************************************
*
- * sh2.c
+ * sh2.cpp
* Portable Hitachi SH-2 (SH7600 family) emulator
*
* This work is based on <tiraniddo@hotmail.com> C/C++ implementation of
@@ -23,31 +23,6 @@
constexpr int SH2_INT_15 = 15;
-#define CHECK_PENDING_IRQ(message) \
-do { \
- int irq = -1; \
- if (m_sh2_state->pending_irq & (1 << 0)) irq = 0; \
- if (m_sh2_state->pending_irq & (1 << 1)) irq = 1; \
- if (m_sh2_state->pending_irq & (1 << 2)) irq = 2; \
- if (m_sh2_state->pending_irq & (1 << 3)) irq = 3; \
- if (m_sh2_state->pending_irq & (1 << 4)) irq = 4; \
- if (m_sh2_state->pending_irq & (1 << 5)) irq = 5; \
- if (m_sh2_state->pending_irq & (1 << 6)) irq = 6; \
- if (m_sh2_state->pending_irq & (1 << 7)) irq = 7; \
- if (m_sh2_state->pending_irq & (1 << 8)) irq = 8; \
- if (m_sh2_state->pending_irq & (1 << 9)) irq = 9; \
- if (m_sh2_state->pending_irq & (1 << 10)) irq = 10; \
- if (m_sh2_state->pending_irq & (1 << 11)) irq = 11; \
- if (m_sh2_state->pending_irq & (1 << 12)) irq = 12; \
- if (m_sh2_state->pending_irq & (1 << 13)) irq = 13; \
- if (m_sh2_state->pending_irq & (1 << 14)) irq = 14; \
- if (m_sh2_state->pending_irq & (1 << 15)) irq = 15; \
- if ((m_sh2_state->internal_irq_level != -1) && (m_sh2_state->internal_irq_level > irq)) irq = m_sh2_state->internal_irq_level; \
- if (irq >= 0) \
- sh2_exception(message,irq); \
-} while(0)
-
-
sh2_device::sh2_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, int cpu_type, address_map_constructor internal_map, int addrlines, uint32_t address_mask)
: sh_common_execution(mconfig, type, tag, owner, clock, ENDIANNESS_BIG, internal_map)
, m_am(address_mask)
@@ -69,14 +44,14 @@ void sh2_device::device_start()
if (m_decrypted_program->endianness() != ENDIANNESS_NATIVE)
m_prptr = [this](offs_t address) -> const void * {
const u16 *ptr = reinterpret_cast<u16 *>(m_cache32.read_ptr(address & ~3));
- if(!(address & 2))
+ if (!(address & 2))
ptr++;
return ptr;
};
else
m_prptr = [this](offs_t address) -> const void * {
const u16 *ptr = reinterpret_cast<u16 *>(m_cache32.read_ptr(address & ~3));
- if(address & 2)
+ if (address & 2)
ptr++;
return ptr;
};
@@ -88,8 +63,8 @@ void sh2_device::device_start()
save_item(NAME(m_nmi_line_state));
save_item(NAME(m_internal_irq_vector));
- state_add( STATE_GENPC, "PC", m_sh2_state->pc).mask(m_am).callimport();
- state_add( STATE_GENPCBASE, "CURPC", m_sh2_state->pc ).callimport().noshow();
+ state_add(STATE_GENPC, "PC", m_sh2_state->pc).mask(m_am).callimport();
+ state_add(STATE_GENPCBASE, "CURPC", m_sh2_state->pc).callimport().noshow();
m_nmi_line_state = 0;
@@ -105,11 +80,12 @@ void sh2_device::device_reset()
m_sh2_state->evec = m_sh2_state->irqsr = 0;
m_sh2_state->ea = m_sh2_state->m_delay = 0;
m_sh2_state->pending_irq = 0;
+ m_sh2_state->pending_nmi = 0;
m_sh2_state->sleep_mode = 0;
m_sh2_state->internal_irq_level = -1;
m_sh2_state->sr = SH_I;
- m_sh2_state->pc = RL(0);
- m_sh2_state->r[15] = RL(4);
+ m_sh2_state->pc = read_long(0);
+ m_sh2_state->r[15] = read_long(4);
m_test_irq = 0;
m_cpu_off = 0;
@@ -119,13 +95,15 @@ void sh2_device::device_reset()
device_memory_interface::space_config_vector sh2_device::memory_space_config() const
{
- if(has_configured_map(AS_OPCODES))
- return space_config_vector {
+ if (has_configured_map(AS_OPCODES))
+ return space_config_vector
+ {
std::make_pair(AS_PROGRAM, &m_program_config),
std::make_pair(AS_OPCODES, &m_decrypted_program_config)
};
else
- return space_config_vector {
+ return space_config_vector
+ {
std::make_pair(AS_PROGRAM, &m_program_config)
};
}
@@ -135,75 +113,105 @@ std::unique_ptr<util::disasm_interface> sh2_device::create_disassembler()
return std::make_unique<sh_disassembler>(false);
}
-uint8_t sh2_device::RB(offs_t A)
+uint8_t sh2_device::read_byte(offs_t offset)
{
- if((A & 0xf0000000) == 0 || (A & 0xf0000000) == 0x20000000)
- return m_program->read_byte(A & m_am);
+ if ((offset & 0xf0000000) == 0 || (offset & 0xf0000000) == 0x20000000)
+ return m_program->read_byte(offset & m_am);
- return m_program->read_byte(A);
+ return m_program->read_byte(offset);
}
-uint16_t sh2_device::RW(offs_t A)
+uint16_t sh2_device::read_word(offs_t offset)
{
- if((A & 0xf0000000) == 0 || (A & 0xf0000000) == 0x20000000)
- return m_program->read_word(A & m_am);
+ if ((offset & 0xf0000000) == 0 || (offset & 0xf0000000) == 0x20000000)
+ return m_program->read_word(offset & m_am);
- return m_program->read_word(A);
+ return m_program->read_word(offset);
}
-uint32_t sh2_device::RL(offs_t A)
+uint32_t sh2_device::read_long(offs_t offset)
{
/* 0x20000000 no Cache */
/* 0x00000000 read thru Cache if CE bit is 1 */
- if((A & 0xf0000000) == 0 || (A & 0xf0000000) == 0x20000000)
- return m_program->read_dword(A & m_am);
+ if ((offset & 0xf0000000) == 0 || (offset & 0xf0000000) == 0x20000000)
+ return m_program->read_dword(offset & m_am);
+
+ return m_program->read_dword(offset);
+}
- return m_program->read_dword(A);
+uint16_t sh2_device::decrypted_read_word(offs_t offset)
+{
+ return m_decrypted_program->read_word(offset);
}
-void sh2_device::WB(offs_t A, uint8_t V)
+void sh2_device::write_byte(offs_t offset, uint8_t data)
{
- if((A & 0xf0000000) == 0 || (A & 0xf0000000) == 0x20000000)
+ if ((offset & 0xf0000000) == 0 || (offset & 0xf0000000) == 0x20000000)
{
- m_program->write_byte(A & m_am,V);
+ m_program->write_byte(offset & m_am, data);
return;
}
- m_program->write_byte(A,V);
+ m_program->write_byte(offset, data);
}
-void sh2_device::WW(offs_t A, uint16_t V)
+void sh2_device::write_word(offs_t offset, uint16_t data)
{
- if((A & 0xf0000000) == 0 || (A & 0xf0000000) == 0x20000000)
+ if ((offset & 0xf0000000) == 0 || (offset & 0xf0000000) == 0x20000000)
{
- m_program->write_word(A & m_am,V);
+ m_program->write_word(offset & m_am, data);
return;
}
- m_program->write_word(A,V);
+ m_program->write_word(offset, data);
}
-void sh2_device::WL(offs_t A, uint32_t V)
+void sh2_device::write_long(offs_t offset, uint32_t data)
{
- if((A & 0xf0000000) == 0 || (A & 0xf0000000) == 0x20000000)
+ if ((offset & 0xf0000000) == 0 || (offset & 0xf0000000) == 0x20000000)
{
- m_program->write_dword(A & m_am,V);
+ m_program->write_dword(offset & m_am, data);
return;
}
/* 0x20000000 no Cache */
/* 0x00000000 read thru Cache if CE bit is 1 */
- m_program->write_dword(A,V);
+ m_program->write_dword(offset, data);
+}
+
+void sh2_device::check_pending_irq(const char *message)
+{
+ if (m_sh2_state->pending_nmi)
+ {
+ sh2_exception(message, 16);
+ m_sh2_state->pending_nmi = 0;
+ }
+ else
+ {
+ int irq = m_sh2_state->internal_irq_level;
+ if (m_sh2_state->pending_irq)
+ {
+ int external_irq = 15 - (count_leading_zeros_32(m_sh2_state->pending_irq) - 16);
+ if (external_irq >= irq)
+ {
+ irq = external_irq;
+ }
+ }
+
+ if (irq >= 0)
+ {
+ sh2_exception(message, irq);
+ }
+ }
}
/* LDC.L @Rm+,SR */
inline void sh2_device::LDCMSR(const uint16_t opcode) // passes Rn
{
- uint32_t x = Rn;
-
- m_sh2_state->ea = m_sh2_state->r[x];
- m_sh2_state->sr = RL( m_sh2_state->ea ) & SH_FLAGS;
- m_sh2_state->r[x] += 4;
+ const uint32_t rn = REG_N;
+ m_sh2_state->ea = m_sh2_state->r[rn];
+ m_sh2_state->sr = read_long(m_sh2_state->ea) & SH_FLAGS;
+ m_sh2_state->r[rn] += 4;
m_sh2_state->icount -= 2;
m_test_irq = 1;
}
@@ -211,9 +219,7 @@ inline void sh2_device::LDCMSR(const uint16_t opcode) // passes Rn
/* LDC Rm,SR */
inline void sh2_device::LDCSR(const uint16_t opcode) // passes Rn
{
- uint32_t x = Rn;
-
- m_sh2_state->sr = m_sh2_state->r[x] & SH_FLAGS;
+ m_sh2_state->sr = m_sh2_state->r[REG_N] & SH_FLAGS;
m_test_irq = 1;
}
@@ -221,10 +227,10 @@ inline void sh2_device::LDCSR(const uint16_t opcode) // passes Rn
inline void sh2_device::RTE()
{
m_sh2_state->ea = m_sh2_state->r[15];
- m_sh2_state->m_delay = RL( m_sh2_state->ea );
+ m_sh2_state->m_delay = read_long(m_sh2_state->ea);
m_sh2_state->r[15] += 4;
m_sh2_state->ea = m_sh2_state->r[15];
- m_sh2_state->sr = RL( m_sh2_state->ea ) & SH_FLAGS;
+ m_sh2_state->sr = read_long(m_sh2_state->ea) & SH_FLAGS;
m_sh2_state->r[15] += 4;
m_sh2_state->icount -= 3;
m_test_irq = 1;
@@ -239,11 +245,11 @@ inline void sh2_device::TRAPA(uint32_t i)
m_sh2_state->ea = m_sh2_state->vbr + imm * 4;
m_sh2_state->r[15] -= 4;
- WL( m_sh2_state->r[15], m_sh2_state->sr );
+ write_long(m_sh2_state->r[15], m_sh2_state->sr);
m_sh2_state->r[15] -= 4;
- WL( m_sh2_state->r[15], m_sh2_state->pc );
+ write_long(m_sh2_state->r[15], m_sh2_state->pc);
- m_sh2_state->pc = RL( m_sh2_state->ea );
+ m_sh2_state->pc = read_long(m_sh2_state->ea);
m_sh2_state->icount -= 7;
}
@@ -255,12 +261,12 @@ inline void sh2_device::ILLEGAL()
debugger_exception_hook(4);
m_sh2_state->r[15] -= 4;
- WL( m_sh2_state->r[15], m_sh2_state->sr ); /* push SR onto stack */
+ write_long(m_sh2_state->r[15], m_sh2_state->sr); /* push SR onto stack */
m_sh2_state->r[15] -= 4;
- WL( m_sh2_state->r[15], m_sh2_state->pc - 2 ); /* push PC onto stack */
+ write_long(m_sh2_state->r[15], m_sh2_state->pc - 2); /* push PC onto stack */
/* fetch PC */
- m_sh2_state->pc = RL( m_sh2_state->vbr + 4 * 4 );
+ m_sh2_state->pc = read_long(m_sh2_state->vbr + 4 * 4);
/* TODO: timing is a guess */
m_sh2_state->icount -= 5;
@@ -273,7 +279,7 @@ void sh2_device::execute_one_f000(uint16_t opcode)
void sh2_device::execute_run()
{
- if ( m_isdrc )
+ if (m_isdrc)
{
execute_run_drc();
return;
@@ -301,13 +307,13 @@ void sh2_device::execute_run()
execute_one(opcode);
- if(m_test_irq && !m_sh2_state->m_delay)
+ if (m_test_irq && !m_sh2_state->m_delay)
{
- CHECK_PENDING_IRQ("mame_sh2_execute");
+ check_pending_irq("mame_sh2_execute");
m_test_irq = 0;
}
m_sh2_state->icount--;
- } while( m_sh2_state->icount > 0 );
+ } while (m_sh2_state->icount > 0);
}
void sh2_device::init_drc_frontend()
@@ -340,7 +346,7 @@ void sh2_device::state_import(const device_state_entry &entry)
break;
case SH_SR:
- CHECK_PENDING_IRQ("sh2_set_reg");
+ check_pending_irq("sh2_set_reg");
break;
}
}
@@ -351,26 +357,37 @@ void sh2_device::execute_set_input(int irqline, int state)
{
if (m_nmi_line_state == state)
return;
+
m_nmi_line_state = state;
if (state == CLEAR_LINE)
{
- LOG("SH-2 cleared nmi\n");
+ LOG("SH-2 cleared NMI\n");
}
else
{
- LOG("SH-2 asserted nmi\n");
+ LOG("SH-2 asserted NMI\n");
- sh2_exception("Set IRQ line", 16);
+ m_sh2_state->pending_nmi = 1;
if (m_isdrc)
- m_sh2_state->pending_nmi = 1;
+ {
+ sh2_exception("Set IRQ line", 16);
+ }
+ else
+ {
+ if (m_sh2_state->m_delay)
+ m_test_irq = 1;
+ else
+ check_pending_irq("sh2_set_nmi_line");
+ }
}
}
else
{
if (m_irq_line_state[irqline] == state)
return;
+
m_irq_line_state[irqline] = state;
if (state == CLEAR_LINE)
@@ -382,14 +399,17 @@ void sh2_device::execute_set_input(int irqline, int state)
{
LOG("SH-2 asserted irq #%d\n", irqline);
m_sh2_state->pending_irq |= 1 << irqline;
+
if (m_isdrc)
{
m_test_irq = 1;
- } else {
- if(m_sh2_state->m_delay)
+ }
+ else
+ {
+ if (m_sh2_state->m_delay)
m_test_irq = 1;
else
- CHECK_PENDING_IRQ("sh2_set_irq_line");
+ check_pending_irq("sh2_set_irq_line");
}
}
}
@@ -435,7 +455,7 @@ void sh2_device::sh2_exception_internal(const char *message, int irqline, int ve
if (m_isdrc)
{
- m_sh2_state->evec = RL( m_sh2_state->vbr + vector * 4 );
+ m_sh2_state->evec = read_long(m_sh2_state->vbr + vector * 4);
m_sh2_state->evec &= m_am;
m_sh2_state->irqsr = m_sh2_state->sr;
@@ -446,11 +466,13 @@ void sh2_device::sh2_exception_internal(const char *message, int irqline, int ve
m_sh2_state->sr = (m_sh2_state->sr & ~SH_I) | (irqline << 4);
// printf("sh2_exception [%s] irqline %x evec %x save SR %x new SR %x\n", message, irqline, m_sh2_state->evec, m_sh2_state->irqsr, m_sh2_state->sr);
- } else {
+ }
+ else
+ {
m_sh2_state->r[15] -= 4;
- WL( m_sh2_state->r[15], m_sh2_state->sr ); /* push SR onto stack */
+ write_long(m_sh2_state->r[15], m_sh2_state->sr); /* push SR onto stack */
m_sh2_state->r[15] -= 4;
- WL( m_sh2_state->r[15], m_sh2_state->pc ); /* push PC onto stack */
+ write_long(m_sh2_state->r[15], m_sh2_state->pc); /* push PC onto stack */
/* set I flags in SR */
if (irqline > SH2_INT_15)
@@ -459,10 +481,11 @@ void sh2_device::sh2_exception_internal(const char *message, int irqline, int ve
m_sh2_state->sr = (m_sh2_state->sr & ~SH_I) | (irqline << 4);
/* fetch PC */
- m_sh2_state->pc = RL( m_sh2_state->vbr + vector * 4 );
+ m_sh2_state->pc = read_long(m_sh2_state->vbr + vector * 4);
}
- if(m_sh2_state->sleep_mode == 1) { m_sh2_state->sleep_mode = 2; }
+ if (m_sh2_state->sleep_mode == 1)
+ m_sh2_state->sleep_mode = 2;
}
/////////
@@ -475,7 +498,7 @@ const opcode_desc* sh2_device::get_desclist(offs_t pc)
void sh2_device::func_fastirq()
{
- sh2_exception("fastirq",m_sh2_state->irqline);
+ sh2_exception("fastirq", m_sh2_state->irqline);
}
static void cfunc_fastirq(void *param) { ((sh2_device *)param)->func_fastirq(); };
diff --git a/src/devices/cpu/sh/sh2.h b/src/devices/cpu/sh/sh2.h
index 2acd63094a9..a75f1c53f92 100644
--- a/src/devices/cpu/sh/sh2.h
+++ b/src/devices/cpu/sh/sh2.h
@@ -33,6 +33,8 @@ public:
protected:
sh2_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, int cpu_type, address_map_constructor internal_map, int addrlines, uint32_t address_mask);
+ void check_pending_irq(const char *message);
+
// device-level overrides
virtual void device_start() override;
virtual void device_reset() override;
@@ -67,12 +69,13 @@ protected:
int8_t m_nmi_line_state;
private:
- virtual uint8_t RB(offs_t A) override;
- virtual uint16_t RW(offs_t A) override;
- virtual uint32_t RL(offs_t A) override;
- virtual void WB(offs_t A, uint8_t V) override;
- virtual void WW(offs_t A, uint16_t V) override;
- virtual void WL(offs_t A, uint32_t V) override;
+ virtual uint8_t read_byte(offs_t A) override;
+ virtual uint16_t read_word(offs_t A) override;
+ virtual uint32_t read_long(offs_t A) override;
+ virtual uint16_t decrypted_read_word(offs_t offset) override;
+ virtual void write_byte(offs_t A, uint8_t V) override;
+ virtual void write_word(offs_t A, uint16_t V) override;
+ virtual void write_long(offs_t A, uint32_t V) override;
virtual void LDCMSR(const uint16_t opcode) override;
virtual void LDCSR(const uint16_t opcode) override;
diff --git a/src/devices/cpu/sh/sh2fe.cpp b/src/devices/cpu/sh/sh2fe.cpp
index 8db408b4bd3..b21ea334ba0 100644
--- a/src/devices/cpu/sh/sh2fe.cpp
+++ b/src/devices/cpu/sh/sh2fe.cpp
@@ -2,7 +2,7 @@
// copyright-holders:R. Belmont
/***************************************************************************
- sh2fe.c
+ sh2fe.cpp
Front end for SH-2 recompiler
diff --git a/src/devices/cpu/sh/sh3comn.cpp b/src/devices/cpu/sh/sh3comn.cpp
index ebf674fe7de..3ea57709ba4 100644
--- a/src/devices/cpu/sh/sh3comn.cpp
+++ b/src/devices/cpu/sh/sh3comn.cpp
@@ -20,23 +20,23 @@ void sh3_base_device::sh3_internal_high_w(offs_t offset, uint32_t data, uint32_t
case SH3_ICR0_IPRA_ADDR:
if (mem_mask & 0xffff0000)
{
- logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (SH3_ICR0_IPRA_ADDR - ICR0)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask);
+ logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (SH3_ICR0_IPRA_ADDR - ICR0)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + SH3_UPPER_REGBASE, data, mem_mask);
}
if (mem_mask & 0x0000ffff)
{
- logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (SH3_ICR0_IPRA_ADDR - IPRA)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask);
- sh4_handler_ipra_w(data&0xffff,mem_mask&0xffff);
+ logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (SH3_ICR0_IPRA_ADDR - IPRA)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + SH3_UPPER_REGBASE, data, mem_mask);
+ sh4_handler_ipra_w(data & 0xffff, mem_mask & 0xffff);
}
break;
case SH3_IPRB_ADDR:
- logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (SH3_IPRB_ADDR)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask);
+ logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (SH3_IPRB_ADDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + SH3_UPPER_REGBASE, data, mem_mask);
break;
case SH3_TOCR_TSTR_ADDR:
- logerror("'%s' (%08x): TMU internal write to %08x = %08x & %08x (SH3_TOCR_TSTR_ADDR)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask);
+ logerror("'%s' (%08x): TMU internal write to %08x = %08x & %08x (SH3_TOCR_TSTR_ADDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + SH3_UPPER_REGBASE, data, mem_mask);
if (mem_mask&0xff000000)
{
sh4_handle_tocr_addr_w((data>>24)&0xffff, (mem_mask>>24)&0xff);
@@ -62,7 +62,7 @@ void sh3_base_device::sh3_internal_high_w(offs_t offset, uint32_t data, uint32_t
case SH3_TCPR2_ADDR: sh4_handle_tcpr2_addr_w(data, mem_mask);break;
default:
- logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (unk)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask);
+ logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (unk)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + SH3_UPPER_REGBASE, data, mem_mask);
break;
}
@@ -79,11 +79,11 @@ uint32_t sh3_base_device::sh3_internal_high_r(offs_t offset, uint32_t mem_mask)
switch (offset)
{
case SH3_ICR0_IPRA_ADDR:
- logerror("'%s' (%08x): INTC internal read from %08x mask %08x (SH3_ICR0_IPRA_ADDR - %08x)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, m_sh3internal_upper[offset]);
+ logerror("'%s' (%08x): INTC internal read from %08x mask %08x (SH3_ICR0_IPRA_ADDR - %08x)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + SH3_UPPER_REGBASE, mem_mask, m_sh3internal_upper[offset]);
return (m_sh3internal_upper[offset] & 0xffff0000) | (m_SH4_IPRA & 0xffff);
case SH3_IPRB_ADDR:
- logerror("'%s' (%08x): INTC internal read from %08x mask %08x (SH3_IPRB_ADDR - %08x)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, m_sh3internal_upper[offset]);
+ logerror("'%s' (%08x): INTC internal read from %08x mask %08x (SH3_IPRB_ADDR - %08x)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + SH3_UPPER_REGBASE, mem_mask, m_sh3internal_upper[offset]);
return m_sh3internal_upper[offset];
case SH3_TOCR_TSTR_ADDR:
@@ -114,15 +114,15 @@ uint32_t sh3_base_device::sh3_internal_high_r(offs_t offset, uint32_t mem_mask)
case SH3_TRA_ADDR:
- logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SH3 TRA - %08x)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, m_sh3internal_upper[offset]);
+ logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SH3 TRA - %08x)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + SH3_UPPER_REGBASE, mem_mask, m_sh3internal_upper[offset]);
return m_sh3internal_upper[offset];
case SH3_EXPEVT_ADDR:
- logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SH3 EXPEVT - %08x)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, m_sh3internal_upper[offset]);
+ logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SH3 EXPEVT - %08x)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + SH3_UPPER_REGBASE, mem_mask, m_sh3internal_upper[offset]);
return m_sh3internal_upper[offset];
case SH3_INTEVT_ADDR:
- //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SH3 INTEVT - %08x)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, m_sh3internal_upper[offset]);
+ //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SH3 INTEVT - %08x)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + SH3_UPPER_REGBASE, mem_mask, m_sh3internal_upper[offset]);
return m_sh3internal_upper[offset];
case SH3_SCSSR_ADDR:
@@ -131,7 +131,7 @@ uint32_t sh3_base_device::sh3_internal_high_r(offs_t offset, uint32_t mem_mask)
default:
- logerror("'%s' (%08x): unmapped internal read from %08x mask %08x\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask);
+ logerror("'%s' (%08x): unmapped internal read from %08x mask %08x\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + SH3_UPPER_REGBASE, mem_mask);
return m_sh3internal_upper[offset];
}
}
@@ -164,7 +164,7 @@ uint32_t sh3_base_device::sh3_internal_r(offs_t offset, uint32_t mem_mask)
case INTEVT2:
{
- // logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (INTEVT2)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,mem_mask);
+ // logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (INTEVT2)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
return m_sh3internal_lower[offset];
}
@@ -174,17 +174,17 @@ uint32_t sh3_base_device::sh3_internal_r(offs_t offset, uint32_t mem_mask)
{
if (mem_mask & 0xff000000)
{
- logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR0)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,mem_mask);
+ logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR0)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
return m_sh3internal_lower[offset];
}
if (mem_mask & 0x0000ff00)
{
- logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR1)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,mem_mask);
+ logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR1)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
return m_sh3internal_lower[offset];
}
- fatalerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR0/1 unused bits)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,mem_mask);
+ fatalerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR0/1 unused bits)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
}
}
@@ -192,14 +192,14 @@ uint32_t sh3_base_device::sh3_internal_r(offs_t offset, uint32_t mem_mask)
{
if (mem_mask & 0xffff0000)
{
- //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PADR)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,mem_mask);
- return m_io->read_qword(SH3_PORT_A)<<24;
+ //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PADR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
+ return m_io->read_qword(SH3_PORT_A) << 24;
}
if (mem_mask & 0x0000ffff)
{
- //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PBDR)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,mem_mask);
- return m_io->read_qword(SH3_PORT_B)<<8;
+ //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PBDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
+ return m_io->read_qword(SH3_PORT_B) << 8;
}
}
break;
@@ -208,14 +208,14 @@ uint32_t sh3_base_device::sh3_internal_r(offs_t offset, uint32_t mem_mask)
{
if (mem_mask & 0xffff0000)
{
- //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PCDR)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,mem_mask);
- return m_io->read_qword(SH3_PORT_C)<<24;
+ //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PCDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
+ return m_io->read_qword(SH3_PORT_C) << 24;
}
if (mem_mask & 0x0000ffff)
{
- //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PDDR)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,mem_mask);
- return m_io->read_qword(SH3_PORT_D)<<8;
+ //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PDDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
+ return m_io->read_qword(SH3_PORT_D) << 8;
}
}
break;
@@ -224,14 +224,14 @@ uint32_t sh3_base_device::sh3_internal_r(offs_t offset, uint32_t mem_mask)
{
if (mem_mask & 0xffff0000)
{
- //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PEDR)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,mem_mask);
- return m_io->read_qword(SH3_PORT_E)<<24;
+ //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PEDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
+ return m_io->read_qword(SH3_PORT_E) << 24;
}
if (mem_mask & 0x0000ffff)
{
- //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PFDR)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,mem_mask);
- return m_io->read_qword(SH3_PORT_F)<<8;
+ //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PFDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
+ return m_io->read_qword(SH3_PORT_F) << 8;
}
}
break;
@@ -240,14 +240,14 @@ uint32_t sh3_base_device::sh3_internal_r(offs_t offset, uint32_t mem_mask)
{
if (mem_mask & 0xffff0000)
{
- //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PGDR)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,mem_mask);
- return m_io->read_qword(SH3_PORT_G)<<24;
+ //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PGDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
+ return m_io->read_qword(SH3_PORT_G) << 24;
}
if (mem_mask & 0x0000ffff)
{
- //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PHDR)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,mem_mask);
- return m_io->read_qword(SH3_PORT_H)<<8;
+ //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PHDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
+ return m_io->read_qword(SH3_PORT_H) << 8;
}
}
break;
@@ -256,14 +256,14 @@ uint32_t sh3_base_device::sh3_internal_r(offs_t offset, uint32_t mem_mask)
{
if (mem_mask & 0xffff0000)
{
- //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PJDR)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,mem_mask);
- return m_io->read_qword(SH3_PORT_J)<<24;
+ //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PJDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
+ return m_io->read_qword(SH3_PORT_J) << 24;
}
if (mem_mask & 0x0000ffff)
{
- //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PKDR)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,mem_mask);
- return m_io->read_qword(SH3_PORT_K)<<8;
+ //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PKDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
+ return m_io->read_qword(SH3_PORT_K) << 8;
}
}
break;
@@ -272,14 +272,14 @@ uint32_t sh3_base_device::sh3_internal_r(offs_t offset, uint32_t mem_mask)
{
if (mem_mask & 0xffff0000)
{
- //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PLDR)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,mem_mask);
- return m_io->read_qword(SH3_PORT_L)<<24;
+ //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PLDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
+ return m_io->read_qword(SH3_PORT_L) << 24;
}
if (mem_mask & 0x0000ffff)
{
- logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SCPDR)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,mem_mask);
- //return m_io->read_qword(SH3_PORT_K)<<8;
+ logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SCPDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
+ //return m_io->read_qword(SH3_PORT_K) << 8;
}
}
break;
@@ -289,13 +289,13 @@ uint32_t sh3_base_device::sh3_internal_r(offs_t offset, uint32_t mem_mask)
{
if (mem_mask & 0xff000000)
{
- logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCSMR2 - Serial Mode Register 2)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,mem_mask);
+ logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCSMR2 - Serial Mode Register 2)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
return m_sh3internal_lower[offset];
}
if (mem_mask & 0x0000ff00)
{
- logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCBRR2 - Bit Rate Register 2)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,mem_mask);
+ logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCBRR2 - Bit Rate Register 2)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
return m_sh3internal_lower[offset];
}
}
@@ -305,13 +305,13 @@ uint32_t sh3_base_device::sh3_internal_r(offs_t offset, uint32_t mem_mask)
{
if (mem_mask & 0xff000000)
{
- logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCSCR2 - Serial Control Register 2)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,mem_mask);
+ logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCSCR2 - Serial Control Register 2)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
return m_sh3internal_lower[offset];
}
if (mem_mask & 0x0000ff00)
{
- logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFTDR2 - Transmit FIFO Data Register 2)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,mem_mask);
+ logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFTDR2 - Transmit FIFO Data Register 2)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
return m_sh3internal_lower[offset];
}
}
@@ -321,13 +321,13 @@ uint32_t sh3_base_device::sh3_internal_r(offs_t offset, uint32_t mem_mask)
{
if (mem_mask & 0xffff0000)
{
- logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCSSR2 - Serial Status Register 2)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,mem_mask);
+ logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCSSR2 - Serial Status Register 2)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
return m_sh3internal_lower[offset];
}
if (mem_mask & 0x0000ff00)
{
- logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFRDR2 - Receive FIFO Data Register 2)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,mem_mask);
+ logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFRDR2 - Receive FIFO Data Register 2)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
return m_sh3internal_lower[offset];
}
}
@@ -337,13 +337,13 @@ uint32_t sh3_base_device::sh3_internal_r(offs_t offset, uint32_t mem_mask)
{
if (mem_mask & 0xff000000)
{
- logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFCR2 - Fifo Control Register 2)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,mem_mask);
+ logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFCR2 - Fifo Control Register 2)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
return m_sh3internal_lower[offset];
}
if (mem_mask & 0x0000ffff)
{
- logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFDR2 - Fifo Data Count Register 2)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,mem_mask);
+ logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFDR2 - Fifo Data Count Register 2)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, mem_mask);
return m_sh3internal_lower[offset];
}
}
@@ -384,23 +384,23 @@ void sh3_base_device::sh3_internal_w(offs_t offset, uint32_t data, uint32_t mem_
switch (offset)
{
- case SH3_SAR0_ADDR: sh4_handle_sar0_addr_w(data,mem_mask); break;
- case SH3_SAR1_ADDR: sh4_handle_sar1_addr_w(data,mem_mask); break;
- case SH3_SAR2_ADDR: sh4_handle_sar2_addr_w(data,mem_mask); break;
- case SH3_SAR3_ADDR: sh4_handle_sar3_addr_w(data,mem_mask); break;
- case SH3_DAR0_ADDR: sh4_handle_dar0_addr_w(data,mem_mask); break;
- case SH3_DAR1_ADDR: sh4_handle_dar1_addr_w(data,mem_mask); break;
- case SH3_DAR2_ADDR: sh4_handle_dar2_addr_w(data,mem_mask); break;
- case SH3_DAR3_ADDR: sh4_handle_dar3_addr_w(data,mem_mask); break;
- case SH3_DMATCR0_ADDR: sh4_handle_dmatcr0_addr_w(data,mem_mask); break;
- case SH3_DMATCR1_ADDR: sh4_handle_dmatcr1_addr_w(data,mem_mask); break;
- case SH3_DMATCR2_ADDR: sh4_handle_dmatcr2_addr_w(data,mem_mask); break;
- case SH3_DMATCR3_ADDR: sh4_handle_dmatcr3_addr_w(data,mem_mask); break;
- case SH3_CHCR0_ADDR: sh4_handle_chcr0_addr_w(data,mem_mask); break;
- case SH3_CHCR1_ADDR: sh4_handle_chcr1_addr_w(data,mem_mask); break;
- case SH3_CHCR2_ADDR: sh4_handle_chcr2_addr_w(data,mem_mask); break;
- case SH3_CHCR3_ADDR: sh4_handle_chcr3_addr_w(data,mem_mask); break;
- case SH3_DMAOR_ADDR: sh4_handle_dmaor_addr_w(data>>16,mem_mask>>16); break;
+ case SH3_SAR0_ADDR: sh4_handle_sar0_addr_w(data, mem_mask); break;
+ case SH3_SAR1_ADDR: sh4_handle_sar1_addr_w(data, mem_mask); break;
+ case SH3_SAR2_ADDR: sh4_handle_sar2_addr_w(data, mem_mask); break;
+ case SH3_SAR3_ADDR: sh4_handle_sar3_addr_w(data, mem_mask); break;
+ case SH3_DAR0_ADDR: sh4_handle_dar0_addr_w(data, mem_mask); break;
+ case SH3_DAR1_ADDR: sh4_handle_dar1_addr_w(data, mem_mask); break;
+ case SH3_DAR2_ADDR: sh4_handle_dar2_addr_w(data, mem_mask); break;
+ case SH3_DAR3_ADDR: sh4_handle_dar3_addr_w(data, mem_mask); break;
+ case SH3_DMATCR0_ADDR: sh4_handle_dmatcr0_addr_w(data, mem_mask); break;
+ case SH3_DMATCR1_ADDR: sh4_handle_dmatcr1_addr_w(data, mem_mask); break;
+ case SH3_DMATCR2_ADDR: sh4_handle_dmatcr2_addr_w(data, mem_mask); break;
+ case SH3_DMATCR3_ADDR: sh4_handle_dmatcr3_addr_w(data, mem_mask); break;
+ case SH3_CHCR0_ADDR: sh4_handle_chcr0_addr_w(data, mem_mask); break;
+ case SH3_CHCR1_ADDR: sh4_handle_chcr1_addr_w(data, mem_mask); break;
+ case SH3_CHCR2_ADDR: sh4_handle_chcr2_addr_w(data, mem_mask); break;
+ case SH3_CHCR3_ADDR: sh4_handle_chcr3_addr_w(data, mem_mask); break;
+ case SH3_DMAOR_ADDR: sh4_handle_dmaor_addr_w(data >> 16, mem_mask >> 16); break;
case IRR0_IRR1:
@@ -408,7 +408,7 @@ void sh3_base_device::sh3_internal_w(offs_t offset, uint32_t data, uint32_t mem_
{
if (mem_mask & 0xff000000)
{
- logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR0)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,data,mem_mask);
+ logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR0)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
// not sure if this is how we should clear lines in this core...
if (!(data & 0x01000000)) execute_set_input(0, CLEAR_LINE);
if (!(data & 0x02000000)) execute_set_input(1, CLEAR_LINE);
@@ -418,11 +418,11 @@ void sh3_base_device::sh3_internal_w(offs_t offset, uint32_t data, uint32_t mem_
}
if (mem_mask & 0x0000ff00)
{
- logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR1)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,data,mem_mask);
+ logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR1)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
}
if (mem_mask & 0x00ff00ff)
{
- fatalerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR0/1 unused bits)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,data,mem_mask);
+ fatalerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR0/1 unused bits)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
}
}
}
@@ -432,18 +432,18 @@ void sh3_base_device::sh3_internal_w(offs_t offset, uint32_t data, uint32_t mem_
{
if (mem_mask & 0xffff0000)
{
- logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PINTER)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,data,mem_mask);
+ logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PINTER)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
}
if (mem_mask & 0x0000ffff)
{
data &= 0xffff; mem_mask &= 0xffff;
COMBINE_DATA(&m_SH4_IPRC);
- logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (IPRC)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,data,mem_mask);
- m_exception_priority[SH4_INTC_IRL0] = INTPRI((m_SH4_IPRC & 0x000f)>>0, SH4_INTC_IRL0);
- m_exception_priority[SH4_INTC_IRL1] = INTPRI((m_SH4_IPRC & 0x00f0)>>4, SH4_INTC_IRL1);
- m_exception_priority[SH4_INTC_IRL2] = INTPRI((m_SH4_IPRC & 0x0f00)>>8, SH4_INTC_IRL2);
- m_exception_priority[SH4_INTC_IRL3] = INTPRI((m_SH4_IPRC & 0xf000)>>12,SH4_INTC_IRL3);
+ logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (IPRC)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
+ m_exception_priority[SH4_INTC_IRL0] = INTPRI((m_SH4_IPRC & 0x000f) >> 0, SH4_INTC_IRL0);
+ m_exception_priority[SH4_INTC_IRL1] = INTPRI((m_SH4_IPRC & 0x00f0) >> 4, SH4_INTC_IRL1);
+ m_exception_priority[SH4_INTC_IRL2] = INTPRI((m_SH4_IPRC & 0x0f00) >> 8, SH4_INTC_IRL2);
+ m_exception_priority[SH4_INTC_IRL3] = INTPRI((m_SH4_IPRC & 0xf000) >> 12, SH4_INTC_IRL3);
sh4_exception_recompute();
}
}
@@ -453,12 +453,12 @@ void sh3_base_device::sh3_internal_w(offs_t offset, uint32_t data, uint32_t mem_
{
if (mem_mask & 0xffff0000)
{
- logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PCCR)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,data,mem_mask);
+ logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PCCR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
}
if (mem_mask & 0x0000ffff)
{
- logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PDCR)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,data,mem_mask);
+ logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PDCR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
}
}
break;
@@ -467,12 +467,12 @@ void sh3_base_device::sh3_internal_w(offs_t offset, uint32_t data, uint32_t mem_
{
if (mem_mask & 0xffff0000)
{
- logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PECR)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,data,mem_mask);
+ logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PECR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
}
if (mem_mask & 0x0000ffff)
{
- logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PFCR)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,data,mem_mask);
+ logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PFCR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
}
}
break;
@@ -482,12 +482,12 @@ void sh3_base_device::sh3_internal_w(offs_t offset, uint32_t data, uint32_t mem_
{
if (mem_mask & 0xffff0000)
{
- logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PGCR)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,data,mem_mask);
+ logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PGCR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
}
if (mem_mask & 0x0000ffff)
{
- logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PHCR)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,data,mem_mask);
+ logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PHCR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
}
}
break;
@@ -497,12 +497,12 @@ void sh3_base_device::sh3_internal_w(offs_t offset, uint32_t data, uint32_t mem_
{
if (mem_mask & 0xffff0000)
{
- logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PJCR)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,data,mem_mask);
+ logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PJCR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
}
if (mem_mask & 0x0000ffff)
{
- logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PKCR)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,data,mem_mask);
+ logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PKCR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
}
}
break;
@@ -512,12 +512,12 @@ void sh3_base_device::sh3_internal_w(offs_t offset, uint32_t data, uint32_t mem_
{
if (mem_mask & 0xffff0000)
{
- logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PLCR)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,data,mem_mask);
+ logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PLCR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
}
if (mem_mask & 0x0000ffff)
{
- logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (SCPCR)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,data,mem_mask);
+ logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (SCPCR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
}
}
break;
@@ -526,14 +526,14 @@ void sh3_base_device::sh3_internal_w(offs_t offset, uint32_t data, uint32_t mem_
{
if (mem_mask & 0xffff0000)
{
- m_io->write_qword(SH3_PORT_A, (data>>24)&0xff);
- // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PADR)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,data,mem_mask);
+ m_io->write_qword(SH3_PORT_A, (data >> 24) & 0xff);
+ // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PADR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
}
if (mem_mask & 0x0000ffff)
{
- m_io->write_qword(SH3_PORT_B, (data>>8)&0xff);
- // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PBDR)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,data,mem_mask);
+ m_io->write_qword(SH3_PORT_B, (data >> 8) & 0xff);
+ // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PBDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
}
}
break;
@@ -542,14 +542,14 @@ void sh3_base_device::sh3_internal_w(offs_t offset, uint32_t data, uint32_t mem_
{
if (mem_mask & 0xffff0000)
{
- m_io->write_qword(SH3_PORT_C, (data>>24)&0xff);
- // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PADR)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,data,mem_mask);
+ m_io->write_qword(SH3_PORT_C, (data >> 24) & 0xff);
+ // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PADR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
}
if (mem_mask & 0x0000ffff)
{
- m_io->write_qword(SH3_PORT_D, (data>>8)&0xff);
- // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PBDR)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,data,mem_mask);
+ m_io->write_qword(SH3_PORT_D, (data >> 8) & 0xff);
+ // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PBDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
}
}
break;
@@ -557,14 +557,14 @@ void sh3_base_device::sh3_internal_w(offs_t offset, uint32_t data, uint32_t mem_
{
if (mem_mask & 0xffff0000)
{
- m_io->write_qword(SH3_PORT_E, (data>>24)&0xff);
- // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PEDR)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,data,mem_mask);
+ m_io->write_qword(SH3_PORT_E, (data >> 24) & 0xff);
+ // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PEDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
}
if (mem_mask & 0x0000ffff)
{
- m_io->write_qword(SH3_PORT_F, (data>>8)&0xff);
- // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PFDR)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,data,mem_mask);
+ m_io->write_qword(SH3_PORT_F, (data >> 8) & 0xff);
+ // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PFDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
}
}
break;
@@ -573,14 +573,14 @@ void sh3_base_device::sh3_internal_w(offs_t offset, uint32_t data, uint32_t mem_
{
if (mem_mask & 0xffff0000)
{
- m_io->write_qword(SH3_PORT_G, (data>>24)&0xff);
- // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PGDR)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,data,mem_mask);
+ m_io->write_qword(SH3_PORT_G, (data >> 24) & 0xff);
+ // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PGDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
}
if (mem_mask & 0x0000ffff)
{
- m_io->write_qword(SH3_PORT_H, (data>>8)&0xff);
- // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PHDR)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,data,mem_mask);
+ m_io->write_qword(SH3_PORT_H, (data >> 8) & 0xff);
+ // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PHDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
}
}
break;
@@ -590,14 +590,14 @@ void sh3_base_device::sh3_internal_w(offs_t offset, uint32_t data, uint32_t mem_
{
if (mem_mask & 0xffff0000)
{
- m_io->write_qword(SH3_PORT_J, (data>>24)&0xff);
- // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PJDR)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,data,mem_mask);
+ m_io->write_qword(SH3_PORT_J, (data >> 24) & 0xff);
+ // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PJDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
}
if (mem_mask & 0x0000ffff)
{
- m_io->write_qword(SH3_PORT_K, (data>>8)&0xff);
- //logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PKDR)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,data,mem_mask);
+ m_io->write_qword(SH3_PORT_K, (data >> 8) & 0xff);
+ //logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PKDR)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
}
}
break;
@@ -606,12 +606,12 @@ void sh3_base_device::sh3_internal_w(offs_t offset, uint32_t data, uint32_t mem_
{
if (mem_mask & 0xff000000)
{
- logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCSMR2 - Serial Mode Register 2)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,data,mem_mask);
+ logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCSMR2 - Serial Mode Register 2)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
}
if (mem_mask & 0x0000ff00)
{
- logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCBRR2 - Bit Rate Register 2)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,data,mem_mask);
+ logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCBRR2 - Bit Rate Register 2)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
}
}
break;
@@ -620,12 +620,12 @@ void sh3_base_device::sh3_internal_w(offs_t offset, uint32_t data, uint32_t mem_
{
if (mem_mask & 0xff000000)
{
- logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCSCR2 - Serial Control Register 2)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,data,mem_mask);
+ logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCSCR2 - Serial Control Register 2)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
}
if (mem_mask & 0x0000ff00)
{
- logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFTDR2 - Transmit FIFO Data Register 2)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,data,mem_mask);
+ logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFTDR2 - Transmit FIFO Data Register 2)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
}
}
break;
@@ -634,12 +634,12 @@ void sh3_base_device::sh3_internal_w(offs_t offset, uint32_t data, uint32_t mem_
{
if (mem_mask & 0xffff0000)
{
- logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCSSR2 - Serial Status Register 2)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,data,mem_mask);
+ logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCSSR2 - Serial Status Register 2)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
}
if (mem_mask & 0x0000ff00)
{
- logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFRDR2 - Receive FIFO Data Register 2)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,data,mem_mask);
+ logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFRDR2 - Receive FIFO Data Register 2)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
}
}
break;
@@ -648,12 +648,12 @@ void sh3_base_device::sh3_internal_w(offs_t offset, uint32_t data, uint32_t mem_
{
if (mem_mask & 0xff000000)
{
- logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFCR2 - Fifo Control Register 2)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,data,mem_mask);
+ logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFCR2 - Fifo Control Register 2)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
}
if (mem_mask & 0x0000ffff)
{
- logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFDR2 - Fifo Data Count Register 2)\n",tag(), m_sh2_state->pc & SH34_AM,(offset *4)+0x4000000,data,mem_mask);
+ logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFDR2 - Fifo Data Count Register 2)\n", tag(), m_sh2_state->pc & SH34_AM, (offset * 4) + 0x4000000, data, mem_mask);
}
}
break;
diff --git a/src/devices/cpu/sh/sh4.cpp b/src/devices/cpu/sh/sh4.cpp
index 7d64546d741..cb384aa2971 100644
--- a/src/devices/cpu/sh/sh4.cpp
+++ b/src/devices/cpu/sh/sh4.cpp
@@ -2,7 +2,7 @@
// copyright-holders:R. Belmont
/*****************************************************************************
*
- * sh4.c
+ * sh4.cpp
* Portable Hitachi SH-4 (SH7750 family) emulator
*
* By R. Belmont, based on sh2.c by Juergen Buchmueller, Mariusz Wojcieszek,
@@ -83,7 +83,8 @@ sh34_base_device::sh34_base_device(const machine_config &mconfig, device_type ty
device_memory_interface::space_config_vector sh34_base_device::memory_space_config() const
{
- return space_config_vector {
+ return space_config_vector
+ {
std::make_pair(AS_PROGRAM, &m_program_config),
std::make_pair(AS_IO, &m_io_config)
};
@@ -193,14 +194,19 @@ int data_type_of(int n)
uint32_t abs;
abs = m_sh2_state->m_fr[n] & 0x7fffffff;
- if ((m_sh2_state->m_fpscr & PR) == 0) { /* Single-precision */
- if (abs < 0x00800000) {
- if (((m_sh2_state->m_fpscr & DN) == 1) || (abs == 0x00000000)) {
- if (sign_of(n) == 0) {
+ if ((m_sh2_state->m_fpscr & PR) == 0) /* Single-precision */
+ {
+ if (abs < 0x00800000)
+ {
+ if (((m_sh2_state->m_fpscr & DN) == 1) || (abs == 0x00000000))
+ {
+ if (sign_of(n) == 0)
+ {
zero(n, 0);
return(SH4_FPU_PZERO);
}
- else {
+ else
+ {
zero(n, 1);
return(SH4_FPU_NZERO);
}
@@ -212,7 +218,8 @@ int data_type_of(int n)
if (abs < 0x7f800000)
return(SH4_FPU_NORM);
else
- if (abs == 0x7f800000) {
+ if (abs == 0x7f800000)
+ {
if (sign_of(n) == 0)
return(SH4_FPU_PINF);
else
@@ -224,14 +231,19 @@ int data_type_of(int n)
else
return(SH4_FPU_sNaN);
}
- else { /* Double-precision */
- if (abs < 0x00100000) {
- if (((m_sh2_state->m_fpscr & DN) == 1) || ((abs == 0x00000000) && (m_sh2_state->m_fr[n + 1] == 0x00000000))) {
- if (sign_of(n) == 0) {
+ else /* Double-precision */
+ {
+ if (abs < 0x00100000)
+ {
+ if (((m_sh2_state->m_fpscr & DN) == 1) || ((abs == 0x00000000) && (m_sh2_state->m_fr[n + 1] == 0x00000000)))
+ {
+ if (sign_of(n) == 0)
+ {
zero(n, 0);
return(SH4_FPU_PZERO);
}
- else {
+ else
+ {
zero(n, 1);
return(SH4_FPU_NZERO);
}
@@ -243,7 +255,8 @@ int data_type_of(int n)
if (abs < 0x7ff00000)
return(SH4_FPU_NORM);
else
- if ((abs == 0x7ff00000) && (m_sh2_state->m_fr[n + 1] == 0x00000000)) {
+ if ((abs == 0x7ff00000) && (m_sh2_state->m_fr[n + 1] == 0x00000000))
+ {
if (sign_of(n) == 0)
return(SH4_FPU_PINF);
else
@@ -259,149 +272,154 @@ int data_type_of(int n)
}
#endif
-inline uint8_t sh34_base_device::RB(offs_t A)
+inline uint8_t sh34_base_device::read_byte(offs_t offset)
{
- if (A >= 0xe0000000)
- return m_program->read_byte(A);
+ if (offset >= 0xe0000000)
+ return m_program->read_byte(offset);
- if (A >= 0x80000000) // P1/P2/P3 region
+ if (offset >= 0x80000000) // P1/P2/P3 region
{
- return m_program->read_byte(A & SH34_AM);
+ return m_program->read_byte(offset & SH34_AM);
}
else // P0 region
{
if (!m_sh4_mmu_enabled)
{
- return m_program->read_byte(A & SH34_AM);
+ return m_program->read_byte(offset & SH34_AM);
}
else
{
- A = get_remap(A & SH34_AM);
- return m_program->read_byte(A);
+ offset = get_remap(offset & SH34_AM);
+ return m_program->read_byte(offset);
}
}
}
-inline uint16_t sh34_base_device::RW(offs_t A)
+inline uint16_t sh34_base_device::read_word(offs_t offset)
{
- if (A >= 0xe0000000)
- return m_program->read_word(A);
+ if (offset >= 0xe0000000)
+ return m_program->read_word(offset);
- if (A >= 0x80000000) // P1/P2/P3 region
+ if (offset >= 0x80000000) // P1/P2/P3 region
{
- return m_program->read_word(A & SH34_AM);
+ return m_program->read_word(offset & SH34_AM);
}
else
{
if (!m_sh4_mmu_enabled)
{
- return m_program->read_word(A & SH34_AM);
+ return m_program->read_word(offset & SH34_AM);
}
else
{
- A = get_remap(A & SH34_AM);
- return m_program->read_word(A);
+ offset = get_remap(offset & SH34_AM);
+ return m_program->read_word(offset);
}
}
}
-inline uint32_t sh34_base_device::RL(offs_t A)
+inline uint16_t sh34_base_device::decrypted_read_word(offs_t offset)
{
- if (A >= 0xe0000000)
- return m_program->read_dword(A);
+ return read_word(offset);
+}
- if (A >= 0x80000000) // P1/P2/P3 region
+inline uint32_t sh34_base_device::read_long(offs_t offset)
+{
+ if (offset >= 0xe0000000)
+ return m_program->read_dword(offset);
+
+ if (offset >= 0x80000000) // P1/P2/P3 region
{
- return m_program->read_dword(A & SH34_AM);
+ return m_program->read_dword(offset & SH34_AM);
}
else
{
if (!m_sh4_mmu_enabled)
{
- return m_program->read_dword(A & SH34_AM);
+ return m_program->read_dword(offset & SH34_AM);
}
else
{
- A = get_remap(A & SH34_AM);
- return m_program->read_dword(A);
+ offset = get_remap(offset & SH34_AM);
+ return m_program->read_dword(offset);
}
}
}
-inline void sh34_base_device::WB(offs_t A, uint8_t V)
+inline void sh34_base_device::write_byte(offs_t offset, uint8_t data)
{
- if (A >= 0xe0000000)
+ if (offset >= 0xe0000000)
{
- m_program->write_byte(A, V);
+ m_program->write_byte(offset, data);
return;
}
- if (A >= 0x80000000) // P1/P2/P3 region
+ if (offset >= 0x80000000) // P1/P2/P3 region
{
- m_program->write_byte(A & SH34_AM, V);
+ m_program->write_byte(offset & SH34_AM, data);
}
else
{
if (!m_sh4_mmu_enabled)
{
- m_program->write_byte(A & SH34_AM, V);
+ m_program->write_byte(offset & SH34_AM, data);
}
else
{
- A = get_remap(A & SH34_AM);
- m_program->write_byte(A, V);
+ offset = get_remap(offset & SH34_AM);
+ m_program->write_byte(offset, data);
}
}
}
-inline void sh34_base_device::WW(offs_t A, uint16_t V)
+inline void sh34_base_device::write_word(offs_t offset, uint16_t data)
{
- if (A >= 0xe0000000)
+ if (offset >= 0xe0000000)
{
- m_program->write_word(A, V);
+ m_program->write_word(offset, data);
return;
}
- if (A >= 0x80000000) // P1/P2/P3 region
+ if (offset >= 0x80000000) // P1/P2/P3 region
{
- m_program->write_word(A & SH34_AM, V);
+ m_program->write_word(offset & SH34_AM, data);
}
else
{
if (!m_sh4_mmu_enabled)
{
- m_program->write_word(A & SH34_AM, V);
+ m_program->write_word(offset & SH34_AM, data);
}
else
{
- A = get_remap(A & SH34_AM);
- m_program->write_word(A, V);
+ offset = get_remap(offset & SH34_AM);
+ m_program->write_word(offset, data);
}
}
}
-inline void sh34_base_device::WL(offs_t A, uint32_t V)
+inline void sh34_base_device::write_long(offs_t offset, uint32_t data)
{
- if (A >= 0xe0000000)
+ if (offset >= 0xe0000000)
{
- m_program->write_dword(A, V);
+ m_program->write_dword(offset, data);
return;
}
- if (A >= 0x80000000) // P1/P2/P3 region
+ if (offset >= 0x80000000) // P1/P2/P3 region
{
- m_program->write_dword(A & SH34_AM, V);
+ m_program->write_dword(offset & SH34_AM, data);
}
else
{
if (!m_sh4_mmu_enabled)
{
- m_program->write_dword(A & SH34_AM, V);
+ m_program->write_dword(offset & SH34_AM, data);
}
else
{
- A = get_remap(A & SH34_AM);
- m_program->write_dword(A, V);
+ offset = get_remap(offset & SH34_AM);
+ m_program->write_dword(offset, data);
}
}
}
@@ -414,8 +432,8 @@ inline void sh34_base_device::ILLEGAL()
/* MOVCA.L R0,@Rn */
inline void sh34_base_device::MOVCAL(const uint16_t opcode)
{
- m_sh2_state->ea = m_sh2_state->r[Rn];
- WL(m_sh2_state->ea, m_sh2_state->r[0]);
+ m_sh2_state->ea = m_sh2_state->r[REG_N];
+ write_long(m_sh2_state->ea, m_sh2_state->r[0]);
}
inline void sh34_base_device::CLRS(const uint16_t opcode)
@@ -432,13 +450,13 @@ inline void sh34_base_device::SETS(const uint16_t opcode)
inline void sh34_base_device::LDCSR(const uint16_t opcode)
{
// important to store the value now so that it doesn't get affected by the bank change
- uint32_t reg = m_sh2_state->r[Rn];
+ uint32_t reg = m_sh2_state->r[REG_N];
if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0)
sh4_syncronize_register_bank((m_sh2_state->sr & sRB) >> 29);
- if ((m_sh2_state->r[Rn] & sRB) != (m_sh2_state->sr & sRB))
- sh4_change_register_bank(m_sh2_state->r[Rn] & sRB ? 1 : 0);
+ if ((m_sh2_state->r[REG_N] & sRB) != (m_sh2_state->sr & sRB))
+ sh4_change_register_bank(m_sh2_state->r[REG_N] & sRB ? 1 : 0);
m_sh2_state->sr = reg & SH34_FLAGS;
sh4_exception_recompute();
@@ -447,16 +465,14 @@ inline void sh34_base_device::LDCSR(const uint16_t opcode)
/* LDC.L @Rm+,SR */
inline void sh34_base_device::LDCMSR(const uint16_t opcode)
{
- uint32_t old;
-
- old = m_sh2_state->sr;
- m_sh2_state->ea = m_sh2_state->r[Rn];
- m_sh2_state->sr = RL(m_sh2_state->ea) & SH34_FLAGS;
+ uint32_t old = m_sh2_state->sr;
+ m_sh2_state->ea = m_sh2_state->r[REG_N];
+ m_sh2_state->sr = read_long(m_sh2_state->ea) & SH34_FLAGS;
if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0)
sh4_syncronize_register_bank((old & sRB) >> 29);
if ((old & sRB) != (m_sh2_state->sr & sRB))
sh4_change_register_bank(m_sh2_state->sr & sRB ? 1 : 0);
- m_sh2_state->r[Rn] += 4;
+ m_sh2_state->r[REG_N] += 4;
m_sh2_state->icount -= 2;
sh4_exception_recompute();
}
@@ -521,100 +537,99 @@ inline void sh34_base_device::TRAPA(uint32_t i)
/* STCRBANK Rm_BANK,Rn */
inline void sh34_base_device::STCRBANK(const uint16_t opcode)
{
- uint32_t m = Rm;
+ uint32_t m = REG_M;
- m_sh2_state->r[Rn] = m_sh2_state->m_rbnk[m_sh2_state->sr&sRB ? 0 : 1][m & 7];
+ m_sh2_state->r[REG_N] = m_sh2_state->m_rbnk[m_sh2_state->sr&sRB ? 0 : 1][m & 7];
}
/* STCMRBANK Rm_BANK,@-Rn */
inline void sh34_base_device::STCMRBANK(const uint16_t opcode)
{
- uint32_t m = Rm; uint32_t n = Rn;
+ uint32_t m = REG_M;
+ uint32_t n = REG_N;
m_sh2_state->r[n] -= 4;
m_sh2_state->ea = m_sh2_state->r[n];
- WL(m_sh2_state->ea, m_sh2_state->m_rbnk[m_sh2_state->sr&sRB ? 0 : 1][m & 7]);
+ write_long(m_sh2_state->ea, m_sh2_state->m_rbnk[m_sh2_state->sr&sRB ? 0 : 1][m & 7]);
m_sh2_state->icount--;
}
/* STS.L SGR,@-Rn */
inline void sh34_base_device::STCMSGR(const uint16_t opcode)
{
- uint32_t n = Rn;
+ uint32_t n = REG_N;
m_sh2_state->r[n] -= 4;
m_sh2_state->ea = m_sh2_state->r[n];
- WL(m_sh2_state->ea, m_sh2_state->m_sgr);
+ write_long(m_sh2_state->ea, m_sh2_state->m_sgr);
}
/* STS.L FPUL,@-Rn */
inline void sh34_base_device::STSMFPUL(const uint16_t opcode)
{
- uint32_t n = Rn;
+ uint32_t n = REG_N;
m_sh2_state->r[n] -= 4;
m_sh2_state->ea = m_sh2_state->r[n];
- WL(m_sh2_state->ea, m_sh2_state->m_fpul);
+ write_long(m_sh2_state->ea, m_sh2_state->m_fpul);
}
/* STS.L FPSCR,@-Rn */
inline void sh34_base_device::STSMFPSCR(const uint16_t opcode)
{
- uint32_t n = Rn;
+ uint32_t n = REG_N;
m_sh2_state->r[n] -= 4;
m_sh2_state->ea = m_sh2_state->r[n];
- WL(m_sh2_state->ea, m_sh2_state->m_fpscr & 0x003FFFFF);
+ write_long(m_sh2_state->ea, m_sh2_state->m_fpscr & 0x003FFFFF);
}
/* STC.L DBR,@-Rn */
inline void sh34_base_device::STCMDBR(const uint16_t opcode)
{
- uint32_t n = Rn;
+ uint32_t n = REG_N;
m_sh2_state->r[n] -= 4;
m_sh2_state->ea = m_sh2_state->r[n];
- WL(m_sh2_state->ea, m_sh2_state->m_dbr);
+ write_long(m_sh2_state->ea, m_sh2_state->m_dbr);
}
/* STC.L SSR,@-Rn */
inline void sh34_base_device::STCMSSR(const uint16_t opcode)
{
- uint32_t n = Rn;
+ uint32_t n = REG_N;
m_sh2_state->r[n] -= 4;
m_sh2_state->ea = m_sh2_state->r[n];
- WL(m_sh2_state->ea, m_sh2_state->m_ssr);
+ write_long(m_sh2_state->ea, m_sh2_state->m_ssr);
}
/* STC.L SPC,@-Rn */
inline void sh34_base_device::STCMSPC(const uint16_t opcode)
{
- uint32_t n = Rn;
+ uint32_t n = REG_N;
m_sh2_state->r[n] -= 4;
m_sh2_state->ea = m_sh2_state->r[n];
- WL(m_sh2_state->ea, m_sh2_state->m_spc);
+ write_long(m_sh2_state->ea, m_sh2_state->m_spc);
}
/* LDS.L @Rm+,FPUL */
inline void sh34_base_device::LDSMFPUL(const uint16_t opcode)
{
- m_sh2_state->ea = m_sh2_state->r[Rn];
- m_sh2_state->m_fpul = RL(m_sh2_state->ea);
- m_sh2_state->r[Rn] += 4;
+ m_sh2_state->ea = m_sh2_state->r[REG_N];
+ m_sh2_state->m_fpul = read_long(m_sh2_state->ea);
+ m_sh2_state->r[REG_N] += 4;
}
/* LDS.L @Rm+,FPSCR */
inline void sh34_base_device::LDSMFPSCR(const uint16_t opcode)
{
- uint32_t s;
-
- s = m_sh2_state->m_fpscr;
- m_sh2_state->ea = m_sh2_state->r[Rn];
- m_sh2_state->m_fpscr = RL(m_sh2_state->ea);
+ uint32_t s = m_sh2_state->m_fpscr;
+ m_sh2_state->ea = m_sh2_state->r[REG_N];
+ m_sh2_state->m_fpscr = read_long(m_sh2_state->ea);
m_sh2_state->m_fpscr &= 0x003FFFFF;
- m_sh2_state->r[Rn] += 4;
+ m_sh2_state->r[REG_N] += 4;
if ((s & FR) != (m_sh2_state->m_fpscr & FR))
sh4_swap_fp_registers();
#ifdef LSB_FIRST
@@ -628,50 +643,49 @@ inline void sh34_base_device::LDSMFPSCR(const uint16_t opcode)
/* LDC.L @Rm+,DBR */
inline void sh34_base_device::LDCMDBR(const uint16_t opcode)
{
- m_sh2_state->ea = m_sh2_state->r[Rn];
- m_sh2_state->m_dbr = RL(m_sh2_state->ea);
- m_sh2_state->r[Rn] += 4;
+ m_sh2_state->ea = m_sh2_state->r[REG_N];
+ m_sh2_state->m_dbr = read_long(m_sh2_state->ea);
+ m_sh2_state->r[REG_N] += 4;
}
/* LDC.L @Rn+,Rm_BANK */
inline void sh34_base_device::LDCMRBANK(const uint16_t opcode)
{
- uint32_t m = Rm; uint32_t n = Rn;
+ uint32_t m = REG_M;
+ uint32_t n = REG_N;
m_sh2_state->ea = m_sh2_state->r[n];
- m_sh2_state->m_rbnk[m_sh2_state->sr&sRB ? 0 : 1][m & 7] = RL(m_sh2_state->ea);
+ m_sh2_state->m_rbnk[m_sh2_state->sr&sRB ? 0 : 1][m & 7] = read_long(m_sh2_state->ea);
m_sh2_state->r[n] += 4;
}
/* LDC.L @Rm+,SSR */
inline void sh34_base_device::LDCMSSR(const uint16_t opcode)
{
- m_sh2_state->ea = m_sh2_state->r[Rn];
- m_sh2_state->m_ssr = RL(m_sh2_state->ea);
- m_sh2_state->r[Rn] += 4;
+ m_sh2_state->ea = m_sh2_state->r[REG_N];
+ m_sh2_state->m_ssr = read_long(m_sh2_state->ea);
+ m_sh2_state->r[REG_N] += 4;
}
/* LDC.L @Rm+,SPC */
inline void sh34_base_device::LDCMSPC(const uint16_t opcode)
{
- m_sh2_state->ea = m_sh2_state->r[Rn];
- m_sh2_state->m_spc = RL(m_sh2_state->ea);
- m_sh2_state->r[Rn] += 4;
+ m_sh2_state->ea = m_sh2_state->r[REG_N];
+ m_sh2_state->m_spc = read_long(m_sh2_state->ea);
+ m_sh2_state->r[REG_N] += 4;
}
/* LDS Rm,FPUL */
inline void sh34_base_device::LDSFPUL(const uint16_t opcode)
{
- m_sh2_state->m_fpul = m_sh2_state->r[Rn];
+ m_sh2_state->m_fpul = m_sh2_state->r[REG_N];
}
/* LDS Rm,FPSCR */
inline void sh34_base_device::LDSFPSCR(const uint16_t opcode)
{
- uint32_t s;
-
- s = m_sh2_state->m_fpscr;
- m_sh2_state->m_fpscr = m_sh2_state->r[Rn] & 0x003FFFFF;
+ uint32_t s = m_sh2_state->m_fpscr;
+ m_sh2_state->m_fpscr = m_sh2_state->r[REG_N] & 0x003FFFFF;
if ((s & FR) != (m_sh2_state->m_fpscr & FR))
sh4_swap_fp_registers();
#ifdef LSB_FIRST
@@ -685,54 +699,56 @@ inline void sh34_base_device::LDSFPSCR(const uint16_t opcode)
/* LDC Rm,DBR */
inline void sh34_base_device::LDCDBR(const uint16_t opcode)
{
- m_sh2_state->m_dbr = m_sh2_state->r[Rn];
+ m_sh2_state->m_dbr = m_sh2_state->r[REG_N];
}
/* STC SSR,Rn */
inline void sh34_base_device::STCSSR(const uint16_t opcode)
{
- m_sh2_state->r[Rn] = m_sh2_state->m_ssr;
+ m_sh2_state->r[REG_N] = m_sh2_state->m_ssr;
}
/* STC SPC,Rn */
inline void sh34_base_device::STCSPC(const uint16_t opcode)
{
- m_sh2_state->r[Rn] = m_sh2_state->m_spc;
+ m_sh2_state->r[REG_N] = m_sh2_state->m_spc;
}
/* STC SGR,Rn */
inline void sh34_base_device::STCSGR(const uint16_t opcode)
{
- m_sh2_state->r[Rn] = m_sh2_state->m_sgr;
+ m_sh2_state->r[REG_N] = m_sh2_state->m_sgr;
}
/* STS FPUL,Rn */
inline void sh34_base_device::STSFPUL(const uint16_t opcode)
{
- m_sh2_state->r[Rn] = m_sh2_state->m_fpul;
+ m_sh2_state->r[REG_N] = m_sh2_state->m_fpul;
}
/* STS FPSCR,Rn */
inline void sh34_base_device::STSFPSCR(const uint16_t opcode)
{
- m_sh2_state->r[Rn] = m_sh2_state->m_fpscr & 0x003FFFFF;
+ m_sh2_state->r[REG_N] = m_sh2_state->m_fpscr & 0x003FFFFF;
}
/* STC DBR,Rn */
inline void sh34_base_device::STCDBR(const uint16_t opcode)
{
- m_sh2_state->r[Rn] = m_sh2_state->m_dbr;
+ m_sh2_state->r[REG_N] = m_sh2_state->m_dbr;
}
/* SHAD Rm,Rn */
inline void sh34_base_device::SHAD(const uint16_t opcode)
{
- uint32_t m = Rm; uint32_t n = Rn;
+ uint32_t m = REG_M;
+ uint32_t n = REG_N;
if ((m_sh2_state->r[m] & 0x80000000) == 0)
m_sh2_state->r[n] = m_sh2_state->r[n] << (m_sh2_state->r[m] & 0x1F);
- else if ((m_sh2_state->r[m] & 0x1F) == 0) {
+ else if ((m_sh2_state->r[m] & 0x1F) == 0)
+ {
if ((m_sh2_state->r[n] & 0x80000000) == 0)
m_sh2_state->r[n] = 0;
else
@@ -745,7 +761,8 @@ inline void sh34_base_device::SHAD(const uint16_t opcode)
/* SHLD Rm,Rn */
inline void sh34_base_device::SHLD(const uint16_t opcode)
{
- uint32_t m = Rm; uint32_t n = Rn;
+ uint32_t m = REG_M;
+ uint32_t n = REG_N;
if ((m_sh2_state->r[m] & 0x80000000) == 0)
m_sh2_state->r[n] = m_sh2_state->r[n] << (m_sh2_state->r[m] & 0x1F);
@@ -758,32 +775,30 @@ inline void sh34_base_device::SHLD(const uint16_t opcode)
/* LDCRBANK Rn,Rm_BANK */
inline void sh34_base_device::LDCRBANK(const uint16_t opcode)
{
- uint32_t m = Rm;
+ uint32_t m = REG_M;
- m_sh2_state->m_rbnk[m_sh2_state->sr&sRB ? 0 : 1][m & 7] = m_sh2_state->r[Rn];
+ m_sh2_state->m_rbnk[m_sh2_state->sr&sRB ? 0 : 1][m & 7] = m_sh2_state->r[REG_N];
}
/* LDC Rm,SSR */
inline void sh34_base_device::LDCSSR(const uint16_t opcode)
{
- m_sh2_state->m_ssr = m_sh2_state->r[Rn];
+ m_sh2_state->m_ssr = m_sh2_state->r[REG_N];
}
/* LDC Rm,SPC */
inline void sh34_base_device::LDCSPC(const uint16_t opcode)
{
- m_sh2_state->m_spc = m_sh2_state->r[Rn];
+ m_sh2_state->m_spc = m_sh2_state->r[REG_N];
}
/* PREF @Rn */
inline void sh34_base_device::PREFM(const uint16_t opcode)
{
- int a;
- uint32_t addr, dest, sq;
-
- addr = m_sh2_state->r[Rn]; // address
+ uint32_t addr = m_sh2_state->r[REG_N]; // address
if ((addr >= 0xE0000000) && (addr <= 0xE3FFFFFF))
{
+ uint32_t dest;
if (m_sh4_mmu_enabled)
{
addr = addr & 0xFFFFFFE0;
@@ -792,7 +807,7 @@ inline void sh34_base_device::PREFM(const uint16_t opcode)
}
else
{
- sq = (addr & 0x20) >> 5;
+ uint32_t sq = (addr & 0x20) >> 5;
dest = addr & 0x03FFFFE0;
if (sq == 0)
{
@@ -820,7 +835,7 @@ inline void sh34_base_device::PREFM(const uint16_t opcode)
addr = addr & 0xFFFFFFE0;
}
- for (a = 0;a < 4;a++)
+ for (int a = 0; a < 4; a++)
{
// shouldn't be causing a memory read, should store sq writes in registers.
m_program->write_qword(dest, m_program->read_qword(addr));
@@ -842,37 +857,42 @@ inline void sh34_base_device::PREFM(const uint16_t opcode)
/* FMOV @Rm+,XDn PR=1 1111nnn1mmmm1001 */
inline void sh34_base_device::FMOVMRIFR(const uint16_t opcode)
{
- uint32_t m = Rm; uint32_t n = Rn;
+ uint32_t m = REG_M;
+ uint32_t n = REG_N;
- if (m_sh2_state->m_fpu_sz) { /* SZ = 1 */
- if (n & 1) {
+ if (m_sh2_state->m_fpu_sz) /* SZ = 1 */
+ {
+ if (n & 1)
+ {
n &= 14;
#ifdef LSB_FIRST
n ^= m_sh2_state->m_fpu_pr;
#endif
m_sh2_state->ea = m_sh2_state->r[m];
- m_sh2_state->m_xf[n] = RL(m_sh2_state->ea);
+ m_sh2_state->m_xf[n] = read_long(m_sh2_state->ea);
m_sh2_state->r[m] += 4;
- m_sh2_state->m_xf[n ^ 1] = RL(m_sh2_state->ea + 4);
+ m_sh2_state->m_xf[n ^ 1] = read_long(m_sh2_state->ea + 4);
m_sh2_state->r[m] += 4;
}
- else {
+ else
+ {
#ifdef LSB_FIRST
n ^= m_sh2_state->m_fpu_pr;
#endif
m_sh2_state->ea = m_sh2_state->r[m];
- m_sh2_state->m_fr[n] = RL(m_sh2_state->ea);
+ m_sh2_state->m_fr[n] = read_long(m_sh2_state->ea);
m_sh2_state->r[m] += 4;
- m_sh2_state->m_fr[n ^ 1] = RL(m_sh2_state->ea + 4);
+ m_sh2_state->m_fr[n ^ 1] = read_long(m_sh2_state->ea + 4);
m_sh2_state->r[m] += 4;
}
}
- else { /* SZ = 0 */
+ else /* SZ = 0 */
+ {
m_sh2_state->ea = m_sh2_state->r[m];
#ifdef LSB_FIRST
n ^= m_sh2_state->m_fpu_pr;
#endif
- m_sh2_state->m_fr[n] = RL(m_sh2_state->ea);
+ m_sh2_state->m_fr[n] = read_long(m_sh2_state->ea);
m_sh2_state->r[m] += 4;
}
}
@@ -883,33 +903,38 @@ inline void sh34_base_device::FMOVMRIFR(const uint16_t opcode)
/* FMOV XDm,@Rn PR=1 1111nnnnmmm11010 */
inline void sh34_base_device::FMOVFRMR(const uint16_t opcode)
{
- uint32_t m = Rm; uint32_t n = Rn;
+ uint32_t m = REG_M;
+ uint32_t n = REG_N;
- if (m_sh2_state->m_fpu_sz) { /* SZ = 1 */
- if (m & 1) {
+ if (m_sh2_state->m_fpu_sz) /* SZ = 1 */
+ {
+ if (m & 1)
+ {
m &= 14;
#ifdef LSB_FIRST
m ^= m_sh2_state->m_fpu_pr;
#endif
m_sh2_state->ea = m_sh2_state->r[n];
- WL(m_sh2_state->ea, m_sh2_state->m_xf[m]);
- WL(m_sh2_state->ea + 4, m_sh2_state->m_xf[m ^ 1]);
+ write_long(m_sh2_state->ea, m_sh2_state->m_xf[m]);
+ write_long(m_sh2_state->ea + 4, m_sh2_state->m_xf[m ^ 1]);
}
- else {
+ else
+ {
#ifdef LSB_FIRST
m ^= m_sh2_state->m_fpu_pr;
#endif
m_sh2_state->ea = m_sh2_state->r[n];
- WL(m_sh2_state->ea, m_sh2_state->m_fr[m]);
- WL(m_sh2_state->ea + 4, m_sh2_state->m_fr[m ^ 1]);
+ write_long(m_sh2_state->ea, m_sh2_state->m_fr[m]);
+ write_long(m_sh2_state->ea + 4, m_sh2_state->m_fr[m ^ 1]);
}
}
- else { /* SZ = 0 */
+ else /* SZ = 0 */
+ {
m_sh2_state->ea = m_sh2_state->r[n];
#ifdef LSB_FIRST
m ^= m_sh2_state->m_fpu_pr;
#endif
- WL(m_sh2_state->ea, m_sh2_state->m_fr[m]);
+ write_long(m_sh2_state->ea, m_sh2_state->m_fr[m]);
}
}
@@ -919,36 +944,41 @@ inline void sh34_base_device::FMOVFRMR(const uint16_t opcode)
/* FMOV XDm,@-Rn PR=1 1111nnnnmmm11011 */
inline void sh34_base_device::FMOVFRMDR(const uint16_t opcode)
{
- uint32_t m = Rm; uint32_t n = Rn;
+ uint32_t m = REG_M;
+ uint32_t n = REG_N;
- if (m_sh2_state->m_fpu_sz) { /* SZ = 1 */
- if (m & 1) {
+ if (m_sh2_state->m_fpu_sz) /* SZ = 1 */
+ {
+ if (m & 1)
+ {
m &= 14;
#ifdef LSB_FIRST
m ^= m_sh2_state->m_fpu_pr;
#endif
m_sh2_state->r[n] -= 8;
m_sh2_state->ea = m_sh2_state->r[n];
- WL(m_sh2_state->ea, m_sh2_state->m_xf[m]);
- WL(m_sh2_state->ea + 4, m_sh2_state->m_xf[m ^ 1]);
+ write_long(m_sh2_state->ea, m_sh2_state->m_xf[m]);
+ write_long(m_sh2_state->ea + 4, m_sh2_state->m_xf[m ^ 1]);
}
- else {
+ else
+ {
#ifdef LSB_FIRST
m ^= m_sh2_state->m_fpu_pr;
#endif
m_sh2_state->r[n] -= 8;
m_sh2_state->ea = m_sh2_state->r[n];
- WL(m_sh2_state->ea, m_sh2_state->m_fr[m]);
- WL(m_sh2_state->ea + 4, m_sh2_state->m_fr[m ^ 1]);
+ write_long(m_sh2_state->ea, m_sh2_state->m_fr[m]);
+ write_long(m_sh2_state->ea + 4, m_sh2_state->m_fr[m ^ 1]);
}
}
- else { /* SZ = 0 */
+ else /* SZ = 0 */
+ {
m_sh2_state->r[n] -= 4;
m_sh2_state->ea = m_sh2_state->r[n];
#ifdef LSB_FIRST
m ^= m_sh2_state->m_fpu_pr;
#endif
- WL(m_sh2_state->ea, m_sh2_state->m_fr[m]);
+ write_long(m_sh2_state->ea, m_sh2_state->m_fr[m]);
}
}
@@ -958,33 +988,38 @@ inline void sh34_base_device::FMOVFRMDR(const uint16_t opcode)
/* FMOV XDm,@(R0,Rn) PR=1 1111nnnnmmm10111 */
inline void sh34_base_device::FMOVFRS0(const uint16_t opcode)
{
- uint32_t m = Rm; uint32_t n = Rn;
+ uint32_t m = REG_M;
+ uint32_t n = REG_N;
- if (m_sh2_state->m_fpu_sz) { /* SZ = 1 */
- if (m & 1) {
+ if (m_sh2_state->m_fpu_sz) /* SZ = 1 */
+ {
+ if (m & 1)
+ {
m &= 14;
#ifdef LSB_FIRST
m ^= m_sh2_state->m_fpu_pr;
#endif
m_sh2_state->ea = m_sh2_state->r[0] + m_sh2_state->r[n];
- WL(m_sh2_state->ea, m_sh2_state->m_xf[m]);
- WL(m_sh2_state->ea + 4, m_sh2_state->m_xf[m ^ 1]);
+ write_long(m_sh2_state->ea, m_sh2_state->m_xf[m]);
+ write_long(m_sh2_state->ea + 4, m_sh2_state->m_xf[m ^ 1]);
}
- else {
+ else
+ {
#ifdef LSB_FIRST
m ^= m_sh2_state->m_fpu_pr;
#endif
m_sh2_state->ea = m_sh2_state->r[0] + m_sh2_state->r[n];
- WL(m_sh2_state->ea, m_sh2_state->m_fr[m]);
- WL(m_sh2_state->ea + 4, m_sh2_state->m_fr[m ^ 1]);
+ write_long(m_sh2_state->ea, m_sh2_state->m_fr[m]);
+ write_long(m_sh2_state->ea + 4, m_sh2_state->m_fr[m ^ 1]);
}
}
- else { /* SZ = 0 */
+ else /* SZ = 0 */
+ {
m_sh2_state->ea = m_sh2_state->r[0] + m_sh2_state->r[n];
#ifdef LSB_FIRST
m ^= m_sh2_state->m_fpu_pr;
#endif
- WL(m_sh2_state->ea, m_sh2_state->m_fr[m]);
+ write_long(m_sh2_state->ea, m_sh2_state->m_fr[m]);
}
}
@@ -994,33 +1029,38 @@ inline void sh34_base_device::FMOVFRS0(const uint16_t opcode)
/* FMOV @(R0,Rm),XDn PR=1 1111nnn1mmmm0110 */
inline void sh34_base_device::FMOVS0FR(const uint16_t opcode)
{
- uint32_t m = Rm; uint32_t n = Rn;
+ uint32_t m = REG_M;
+ uint32_t n = REG_N;
- if (m_sh2_state->m_fpu_sz) { /* SZ = 1 */
- if (n & 1) {
+ if (m_sh2_state->m_fpu_sz) /* SZ = 1 */
+ {
+ if (n & 1)
+ {
n &= 14;
#ifdef LSB_FIRST
n ^= m_sh2_state->m_fpu_pr;
#endif
m_sh2_state->ea = m_sh2_state->r[0] + m_sh2_state->r[m];
- m_sh2_state->m_xf[n] = RL(m_sh2_state->ea);
- m_sh2_state->m_xf[n ^ 1] = RL(m_sh2_state->ea + 4);
+ m_sh2_state->m_xf[n] = read_long(m_sh2_state->ea);
+ m_sh2_state->m_xf[n ^ 1] = read_long(m_sh2_state->ea + 4);
}
- else {
+ else
+ {
#ifdef LSB_FIRST
n ^= m_sh2_state->m_fpu_pr;
#endif
m_sh2_state->ea = m_sh2_state->r[0] + m_sh2_state->r[m];
- m_sh2_state->m_fr[n] = RL(m_sh2_state->ea);
- m_sh2_state->m_fr[n ^ 1] = RL(m_sh2_state->ea + 4);
+ m_sh2_state->m_fr[n] = read_long(m_sh2_state->ea);
+ m_sh2_state->m_fr[n ^ 1] = read_long(m_sh2_state->ea + 4);
}
}
- else { /* SZ = 0 */
+ else /* SZ = 0 */
+ {
m_sh2_state->ea = m_sh2_state->r[0] + m_sh2_state->r[m];
#ifdef LSB_FIRST
n ^= m_sh2_state->m_fpu_pr;
#endif
- m_sh2_state->m_fr[n] = RL(m_sh2_state->ea);
+ m_sh2_state->m_fr[n] = read_long(m_sh2_state->ea);
}
}
@@ -1031,33 +1071,38 @@ inline void sh34_base_device::FMOVS0FR(const uint16_t opcode)
/* FMOV @Rm,DRn PR=1 1111nnn0mmmm1000 */
inline void sh34_base_device::FMOVMRFR(const uint16_t opcode)
{
- uint32_t m = Rm; uint32_t n = Rn;
+ uint32_t m = REG_M;
+ uint32_t n = REG_N;
- if (m_sh2_state->m_fpu_sz) { /* SZ = 1 */
- if (n & 1) {
+ if (m_sh2_state->m_fpu_sz) /* SZ = 1 */
+ {
+ if (n & 1)
+ {
n &= 14;
#ifdef LSB_FIRST
n ^= m_sh2_state->m_fpu_pr;
#endif
m_sh2_state->ea = m_sh2_state->r[m];
- m_sh2_state->m_xf[n] = RL(m_sh2_state->ea);
- m_sh2_state->m_xf[n ^ 1] = RL(m_sh2_state->ea + 4);
+ m_sh2_state->m_xf[n] = read_long(m_sh2_state->ea);
+ m_sh2_state->m_xf[n ^ 1] = read_long(m_sh2_state->ea + 4);
}
- else {
+ else
+ {
#ifdef LSB_FIRST
n ^= m_sh2_state->m_fpu_pr;
#endif
m_sh2_state->ea = m_sh2_state->r[m];
- m_sh2_state->m_fr[n] = RL(m_sh2_state->ea);
- m_sh2_state->m_fr[n ^ 1] = RL(m_sh2_state->ea + 4);
+ m_sh2_state->m_fr[n] = read_long(m_sh2_state->ea);
+ m_sh2_state->m_fr[n ^ 1] = read_long(m_sh2_state->ea + 4);
}
}
- else { /* SZ = 0 */
+ else /* SZ = 0 */
+ {
m_sh2_state->ea = m_sh2_state->r[m];
#ifdef LSB_FIRST
n ^= m_sh2_state->m_fpu_pr;
#endif
- m_sh2_state->m_fr[n] = RL(m_sh2_state->ea);
+ m_sh2_state->m_fr[n] = read_long(m_sh2_state->ea);
}
}
@@ -1068,32 +1113,41 @@ inline void sh34_base_device::FMOVMRFR(const uint16_t opcode)
/* FMOV XDm,XDn PR=1 XDm -> XDn 1111nnn1mmm11100 */
inline void sh34_base_device::FMOVFR(const uint16_t opcode)
{
- uint32_t m = Rm; uint32_t n = Rn;
+ uint32_t m = REG_M;
+ uint32_t n = REG_N;
- if (m_sh2_state->m_fpu_sz == 0) { /* SZ = 0 */
+ if (m_sh2_state->m_fpu_sz == 0) /* SZ = 0 */
+ {
#ifdef LSB_FIRST
n ^= m_sh2_state->m_fpu_pr;
m ^= m_sh2_state->m_fpu_pr;
#endif
m_sh2_state->m_fr[n] = m_sh2_state->m_fr[m];
}
- else { /* SZ = 1 */
- if (m & 1) {
- if (n & 1) {
+ else /* SZ = 1 */
+ {
+ if (m & 1)
+ {
+ if (n & 1)
+ {
m_sh2_state->m_xf[n & 14] = m_sh2_state->m_xf[m & 14];
m_sh2_state->m_xf[n | 1] = m_sh2_state->m_xf[m | 1];
}
- else {
+ else
+ {
m_sh2_state->m_fr[n] = m_sh2_state->m_xf[m & 14];
m_sh2_state->m_fr[n | 1] = m_sh2_state->m_xf[m | 1];
}
}
- else {
- if (n & 1) {
+ else
+ {
+ if (n & 1)
+ {
m_sh2_state->m_xf[n & 14] = m_sh2_state->m_fr[m];
m_sh2_state->m_xf[n | 1] = m_sh2_state->m_fr[m | 1]; // (a&14)+1 -> a|1
}
- else {
+ else
+ {
m_sh2_state->m_fr[n] = m_sh2_state->m_fr[m];
m_sh2_state->m_fr[n | 1] = m_sh2_state->m_fr[m | 1];
}
@@ -1105,9 +1159,9 @@ inline void sh34_base_device::FMOVFR(const uint16_t opcode)
inline void sh34_base_device::FLDI1(const uint16_t opcode)
{
#ifdef LSB_FIRST
- m_sh2_state->m_fr[Rn ^ m_sh2_state->m_fpu_pr] = 0x3F800000;
+ m_sh2_state->m_fr[REG_N ^ m_sh2_state->m_fpu_pr] = 0x3F800000;
#else
- m_sh2_state->m_fr[Rn] = 0x3F800000;
+ m_sh2_state->m_fr[REG_N] = 0x3F800000;
#endif
}
@@ -1115,9 +1169,9 @@ inline void sh34_base_device::FLDI1(const uint16_t opcode)
inline void sh34_base_device::FLDI0(const uint16_t opcode)
{
#ifdef LSB_FIRST
- m_sh2_state->m_fr[Rn ^ m_sh2_state->m_fpu_pr] = 0;
+ m_sh2_state->m_fr[REG_N ^ m_sh2_state->m_fpu_pr] = 0;
#else
- m_sh2_state->m_fr[Rn] = 0;
+ m_sh2_state->m_fr[REG_N] = 0;
#endif
}
@@ -1125,9 +1179,9 @@ inline void sh34_base_device::FLDI0(const uint16_t opcode)
inline void sh34_base_device::FLDS(const uint16_t opcode)
{
#ifdef LSB_FIRST
- m_sh2_state->m_fpul = m_sh2_state->m_fr[Rn ^ m_sh2_state->m_fpu_pr];
+ m_sh2_state->m_fpul = m_sh2_state->m_fr[REG_N ^ m_sh2_state->m_fpu_pr];
#else
- m_sh2_state->m_fpul = m_sh2_state->m_fr[Rn];
+ m_sh2_state->m_fpul = m_sh2_state->m_fr[REG_N];
#endif
}
@@ -1135,9 +1189,9 @@ inline void sh34_base_device::FLDS(const uint16_t opcode)
inline void sh34_base_device::FSTS(const uint16_t opcode)
{
#ifdef LSB_FIRST
- m_sh2_state->m_fr[Rn ^ m_sh2_state->m_fpu_pr] = m_sh2_state->m_fpul;
+ m_sh2_state->m_fr[REG_N ^ m_sh2_state->m_fpu_pr] = m_sh2_state->m_fpul;
#else
- m_sh2_state->m_fr[Rn] = m_sh2_state->m_fpul;
+ m_sh2_state->m_fr[REG_N] = m_sh2_state->m_fpul;
#endif
}
@@ -1159,17 +1213,19 @@ void sh34_base_device::FSCHG()
/* FTRC DRm,FPUL PR=1 1111mmm000111101 */
inline void sh34_base_device::FTRC(const uint16_t opcode)
{
- uint32_t n = Rn;
+ uint32_t n = REG_N;
- if (m_sh2_state->m_fpu_pr) { /* PR = 1 */
+ if (m_sh2_state->m_fpu_pr) /* PR = 1 */
+ {
if (n & 1)
fatalerror("SH-4: FTRC opcode used with n %d", n);
n = n & 14;
*((int32_t *)&m_sh2_state->m_fpul) = (int32_t)FP_RFD(n);
}
- else { /* PR = 0 */
- /* read m_sh2_state->m_fr[n] as float -> truncate -> fpul(32) */
+ else /* PR = 0 */
+ {
+ /* read m_sh2_state->m_fr[n] as float -> truncate -> fpul(32) */
*((int32_t *)&m_sh2_state->m_fpul) = (int32_t)FP_RFS(n);
}
}
@@ -1178,16 +1234,18 @@ inline void sh34_base_device::FTRC(const uint16_t opcode)
/* FLOAT FPUL,DRn PR=1 1111nnn000101101 */
inline void sh34_base_device::FLOAT(const uint16_t opcode)
{
- uint32_t n = Rn;
+ uint32_t n = REG_N;
- if (m_sh2_state->m_fpu_pr) { /* PR = 1 */
+ if (m_sh2_state->m_fpu_pr) /* PR = 1 */
+ {
if (n & 1)
fatalerror("SH-4: FLOAT opcode used with n %d", n);
n = n & 14;
FP_RFD(n) = (double)*((int32_t *)&m_sh2_state->m_fpul);
}
- else { /* PR = 0 */
+ else /* PR = 0 */
+ {
FP_RFS(n) = (float)*((int32_t *)&m_sh2_state->m_fpul);
}
}
@@ -1196,12 +1254,14 @@ inline void sh34_base_device::FLOAT(const uint16_t opcode)
/* FNEG DRn PR=1 1111nnn001001101 */
inline void sh34_base_device::FNEG(const uint16_t opcode)
{
- uint32_t n = Rn;
+ uint32_t n = REG_N;
- if (m_sh2_state->m_fpu_pr) { /* PR = 1 */
+ if (m_sh2_state->m_fpu_pr) /* PR = 1 */
+ {
FP_RFD(n) = -FP_RFD(n);
}
- else { /* PR = 0 */
+ else /* PR = 0 */
+ {
FP_RFS(n) = -FP_RFS(n);
}
}
@@ -1210,9 +1270,10 @@ inline void sh34_base_device::FNEG(const uint16_t opcode)
/* FABS DRn PR=1 1111nnn001011101 */
inline void sh34_base_device::FABS(const uint16_t opcode)
{
- uint32_t n = Rn;
+ uint32_t n = REG_N;
- if (m_sh2_state->m_fpu_pr) { /* PR = 1 */
+ if (m_sh2_state->m_fpu_pr) /* PR = 1 */
+ {
#ifdef LSB_FIRST
n = n | 1; // n & 14 + 1
m_sh2_state->m_fr[n] = m_sh2_state->m_fr[n] & 0x7fffffff;
@@ -1221,7 +1282,8 @@ inline void sh34_base_device::FABS(const uint16_t opcode)
m_sh2_state->m_fr[n] = m_sh2_state->m_fr[n] & 0x7fffffff;
#endif
}
- else { /* PR = 0 */
+ else /* PR = 0 */
+ {
m_sh2_state->m_fr[n] = m_sh2_state->m_fr[n] & 0x7fffffff;
}
}
@@ -1230,9 +1292,11 @@ inline void sh34_base_device::FABS(const uint16_t opcode)
/* FCMP/EQ DRm,DRn PR=1 1111nnn0mmm00100 */
inline void sh34_base_device::FCMP_EQ(const uint16_t opcode)
{
- uint32_t m = Rm; uint32_t n = Rn;
+ uint32_t m = REG_M;
+ uint32_t n = REG_N;
- if (m_sh2_state->m_fpu_pr) { /* PR = 1 */
+ if (m_sh2_state->m_fpu_pr) /* PR = 1 */
+ {
n = n & 14;
m = m & 14;
if (FP_RFD(n) == FP_RFD(m))
@@ -1240,7 +1304,8 @@ inline void sh34_base_device::FCMP_EQ(const uint16_t opcode)
else
m_sh2_state->sr &= ~SH_T;
}
- else { /* PR = 0 */
+ else /* PR = 0 */
+ {
if (FP_RFS(n) == FP_RFS(m))
m_sh2_state->sr |= SH_T;
else
@@ -1252,9 +1317,11 @@ inline void sh34_base_device::FCMP_EQ(const uint16_t opcode)
/* FCMP/GT DRm,DRn PR=1 1111nnn0mmm00101 */
inline void sh34_base_device::FCMP_GT(const uint16_t opcode)
{
- uint32_t m = Rm; uint32_t n = Rn;
+ uint32_t m = REG_M;
+ uint32_t n = REG_N;
- if (m_sh2_state->m_fpu_pr) { /* PR = 1 */
+ if (m_sh2_state->m_fpu_pr) /* PR = 1 */
+ {
n = n & 14;
m = m & 14;
if (FP_RFD(n) > FP_RFD(m))
@@ -1262,7 +1329,8 @@ inline void sh34_base_device::FCMP_GT(const uint16_t opcode)
else
m_sh2_state->sr &= ~SH_T;
}
- else { /* PR = 0 */
+ else /* PR = 0 */
+ {
if (FP_RFS(n) > FP_RFS(m))
m_sh2_state->sr |= SH_T;
else
@@ -1273,9 +1341,10 @@ inline void sh34_base_device::FCMP_GT(const uint16_t opcode)
/* FCNVDS DRm,FPUL PR=1 1111mmm010111101 */
inline void sh34_base_device::FCNVDS(const uint16_t opcode)
{
- uint32_t n = Rn;
+ uint32_t n = REG_N;
- if (m_sh2_state->m_fpu_pr) { /* PR = 1 */
+ if (m_sh2_state->m_fpu_pr) /* PR = 1 */
+ {
n = n & 14;
if (m_sh2_state->m_fpscr & RM)
m_sh2_state->m_fr[n | NATIVE_ENDIAN_VALUE_LE_BE(0, 1)] &= 0xe0000000; /* round toward zero*/
@@ -1286,9 +1355,10 @@ inline void sh34_base_device::FCNVDS(const uint16_t opcode)
/* FCNVSD FPUL, DRn PR=1 1111nnn010101101 */
inline void sh34_base_device::FCNVSD(const uint16_t opcode)
{
- uint32_t n = Rn;
+ uint32_t n = REG_N;
- if (m_sh2_state->m_fpu_pr) { /* PR = 1 */
+ if (m_sh2_state->m_fpu_pr) /* PR = 1 */
+ {
n = n & 14;
FP_RFD(n) = (double)*((float *)&m_sh2_state->m_fpul);
}
@@ -1298,14 +1368,17 @@ inline void sh34_base_device::FCNVSD(const uint16_t opcode)
/* FADD DRm,DRn PR=1 1111nnn0mmm00000 */
inline void sh34_base_device::FADD(const uint16_t opcode)
{
- uint32_t m = Rm; uint32_t n = Rn;
+ uint32_t m = REG_M;
+ uint32_t n = REG_N;
- if (m_sh2_state->m_fpu_pr) { /* PR = 1 */
+ if (m_sh2_state->m_fpu_pr) /* PR = 1 */
+ {
n = n & 14;
m = m & 14;
FP_RFD(n) = FP_RFD(n) + FP_RFD(m);
}
- else { /* PR = 0 */
+ else /* PR = 0 */
+ {
FP_RFS(n) = FP_RFS(n) + FP_RFS(m);
}
}
@@ -1314,14 +1387,17 @@ inline void sh34_base_device::FADD(const uint16_t opcode)
/* FSUB DRm,DRn PR=1 1111nnn0mmm00001 */
inline void sh34_base_device::FSUB(const uint16_t opcode)
{
- uint32_t m = Rm; uint32_t n = Rn;
+ uint32_t m = REG_M;
+ uint32_t n = REG_N;
- if (m_sh2_state->m_fpu_pr) { /* PR = 1 */
+ if (m_sh2_state->m_fpu_pr) /* PR = 1 */
+ {
n = n & 14;
m = m & 14;
FP_RFD(n) = FP_RFD(n) - FP_RFD(m);
}
- else { /* PR = 0 */
+ else /* PR = 0 */
+ {
FP_RFS(n) = FP_RFS(n) - FP_RFS(m);
}
}
@@ -1331,14 +1407,17 @@ inline void sh34_base_device::FSUB(const uint16_t opcode)
/* FMUL DRm,DRn PR=1 1111nnn0mmm00010 */
inline void sh34_base_device::FMUL(const uint16_t opcode)
{
- uint32_t m = Rm; uint32_t n = Rn;
+ uint32_t m = REG_M;
+ uint32_t n = REG_N;
- if (m_sh2_state->m_fpu_pr) { /* PR = 1 */
+ if (m_sh2_state->m_fpu_pr) /* PR = 1 */
+ {
n = n & 14;
m = m & 14;
FP_RFD(n) = FP_RFD(n) * FP_RFD(m);
}
- else { /* PR = 0 */
+ else /* PR = 0 */
+ {
FP_RFS(n) = FP_RFS(n) * FP_RFS(m);
}
}
@@ -1347,16 +1426,19 @@ inline void sh34_base_device::FMUL(const uint16_t opcode)
/* FDIV DRm,DRn PR=1 1111nnn0mmm00011 */
inline void sh34_base_device::FDIV(const uint16_t opcode)
{
- uint32_t m = Rm; uint32_t n = Rn;
+ uint32_t m = REG_M;
+ uint32_t n = REG_N;
- if (m_sh2_state->m_fpu_pr) { /* PR = 1 */
+ if (m_sh2_state->m_fpu_pr) /* PR = 1 */
+ {
n = n & 14;
m = m & 14;
if (FP_RFD(m) == 0)
return;
FP_RFD(n) = FP_RFD(n) / FP_RFD(m);
}
- else { /* PR = 0 */
+ else /* PR = 0 */
+ {
if (FP_RFS(m) == 0)
return;
FP_RFS(n) = FP_RFS(n) / FP_RFS(m);
@@ -1366,9 +1448,11 @@ inline void sh34_base_device::FDIV(const uint16_t opcode)
/* FMAC FR0,FRm,FRn PR=0 1111nnnnmmmm1110 */
inline void sh34_base_device::FMAC(const uint16_t opcode)
{
- uint32_t m = Rm; uint32_t n = Rn;
+ uint32_t m = REG_M;
+ uint32_t n = REG_N;
- if (m_sh2_state->m_fpu_pr == 0) { /* PR = 0 */
+ if (m_sh2_state->m_fpu_pr == 0) /* PR = 0 */
+ {
FP_RFS(n) = (FP_RFS(0) * FP_RFS(m)) + FP_RFS(n);
}
}
@@ -1377,15 +1461,17 @@ inline void sh34_base_device::FMAC(const uint16_t opcode)
/* FSQRT DRn PR=1 1111nnnn01101101 */
inline void sh34_base_device::FSQRT(const uint16_t opcode)
{
- uint32_t n = Rn;
+ uint32_t n = REG_N;
- if (m_sh2_state->m_fpu_pr) { /* PR = 1 */
+ if (m_sh2_state->m_fpu_pr) /* PR = 1 */
+ {
n = n & 14;
if (FP_RFD(n) < 0)
return;
FP_RFD(n) = sqrtf(FP_RFD(n));
}
- else { /* PR = 0 */
+ else /* PR = 0 */
+ {
if (FP_RFS(n) < 0)
return;
FP_RFS(n) = sqrtf(FP_RFS(n));
@@ -1395,7 +1481,7 @@ inline void sh34_base_device::FSQRT(const uint16_t opcode)
/* FSRRA FRn PR=0 1111nnnn01111101 */
inline void sh34_base_device::FSRRA(const uint16_t opcode)
{
- uint32_t n = Rn;
+ uint32_t n = REG_N;
if (FP_RFS(n) < 0)
return;
@@ -1405,11 +1491,9 @@ inline void sh34_base_device::FSRRA(const uint16_t opcode)
/* FSSCA FPUL,FRn PR=0 1111nnn011111101 */
void sh34_base_device::FSSCA(const uint16_t opcode)
{
- uint32_t n = Rn;
-
- float angle;
+ uint32_t n = REG_N;
- angle = (((float)(m_sh2_state->m_fpul & 0xFFFF)) / 65536.0f) * 2.0f * (float)M_PI;
+ float angle = (((float)(m_sh2_state->m_fpul & 0xFFFF)) / 65536.0f) * 2.0f * (float)M_PI;
FP_RFS(n) = sinf(angle);
FP_RFS(n + 1) = cosf(angle);
}
@@ -1417,15 +1501,12 @@ void sh34_base_device::FSSCA(const uint16_t opcode)
/* FIPR FVm,FVn PR=0 1111nnmm11101101 */
inline void sh34_base_device::FIPR(const uint16_t opcode)
{
- uint32_t n = Rn;
+ uint32_t n = REG_N;
+ uint32_t m = (n & 3) << 2;
+ n = n & 12;
- uint32_t m;
float ml[4];
- int a;
-
- m = (n & 3) << 2;
- n = n & 12;
- for (a = 0;a < 4;a++)
+ for (int a = 0; a < 4; a++)
ml[a] = FP_RFS(n + a) * FP_RFS(m + a);
FP_RFS(n + 3) = ml[0] + ml[1] + ml[2] + ml[3];
}
@@ -1433,25 +1514,26 @@ inline void sh34_base_device::FIPR(const uint16_t opcode)
/* FTRV XMTRX,FVn PR=0 1111nn0111111101 */
void sh34_base_device::FTRV(const uint16_t opcode)
{
- uint32_t n = Rn;
+ uint32_t n = REG_N;
+ n = n & 12;
- int i, j;
float sum[4];
-
- n = n & 12;
- for (i = 0;i < 4;i++) {
+ for (int i = 0; i < 4; i++)
+ {
sum[i] = 0;
- for (j = 0;j < 4;j++)
+ for (int j = 0; j < 4; j++)
sum[i] += FP_XFS((j << 2) + i)*FP_RFS(n + j);
}
- for (i = 0;i < 4;i++)
+ for (int i = 0; i < 4; i++)
FP_RFS(n + i) = sum[i];
}
inline void sh34_base_device::op1111_0xf13(const uint16_t opcode)
{
- if (opcode & 0x100) {
- if (opcode & 0x200) {
+ if (opcode & 0x100)
+ {
+ if (opcode & 0x200)
+ {
switch (opcode & 0xC00)
{
case 0x000:
@@ -1465,11 +1547,13 @@ inline void sh34_base_device::op1111_0xf13(const uint16_t opcode)
break;
}
}
- else {
+ else
+ {
FTRV(opcode);
}
}
- else {
+ else
+ {
FSSCA(opcode);
}
}
@@ -1602,7 +1686,7 @@ void sh34_base_device::device_reset()
m_sh2_state->pc = 0xa0000000;
m_sh2_state->m_ppc = m_sh2_state->pc & SH34_AM;
- m_sh2_state->r[15] = RL(4);
+ m_sh2_state->r[15] = read_long(4);
m_sh2_state->sr = 0x700000f0;
m_sh2_state->m_fpscr = 0x00040001;
m_sh2_state->m_fpu_sz = (m_sh2_state->m_fpscr & SZ) ? 1 : 0;
@@ -1868,7 +1952,7 @@ inline void sh34_base_device::execute_one_f000(const uint16_t opcode)
/* Execute cycles - returns number of cycles actually run */
void sh34_base_device::execute_run()
{
- if ( m_isdrc )
+ if (m_isdrc)
{
execute_run_drc();
return;
@@ -1888,7 +1972,7 @@ void sh34_base_device::execute_run()
uint16_t opcode;
if (!m_sh4_mmu_enabled) opcode = m_pr16(m_sh2_state->pc & SH34_AM);
- else opcode = RW(m_sh2_state->pc); // should probably use a different function as this needs to go through the ITLB
+ else opcode = read_word(m_sh2_state->pc); // should probably use a different function as this needs to go through the ITLB
if (m_sh2_state->m_delay)
{
@@ -1911,7 +1995,7 @@ void sh34_base_device::execute_run()
void sh3be_device::execute_run()
{
- if ( m_isdrc )
+ if (m_isdrc)
{
execute_run_drc();
return;
@@ -1951,7 +2035,7 @@ void sh3be_device::execute_run()
void sh4be_device::execute_run()
{
- if ( m_isdrc )
+ if (m_isdrc)
{
execute_run_drc();
return;
@@ -2232,7 +2316,7 @@ void sh34_base_device::device_start()
state_add(STATE_GENPC, "GENPC", m_debugger_temp).callimport().callexport().noshow();
//state_add(STATE_GENPCBASE, "CURPC", m_sh2_state->m_ppc).noshow();
- state_add( STATE_GENPCBASE, "CURPC", m_sh2_state->pc ).callimport().noshow();
+ state_add(STATE_GENPCBASE, "CURPC", m_sh2_state->pc).callimport().noshow();
for (int regnum = 0; regnum < 16; regnum++)
{
@@ -2916,13 +3000,13 @@ bool sh34_base_device::generate_group_0_STCRBANK(drcuml_block &block, compiler_s
bool sh34_base_device::generate_group_0_STCSSR(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc)
{
- UML_MOV(block, R32(Rn), mem(&m_sh2_state->m_ssr));
+ UML_MOV(block, R32(REG_N), mem(&m_sh2_state->m_ssr));
return true;
}
bool sh34_base_device::generate_group_0_STCSPC(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc)
{
- UML_MOV(block, R32(Rn), mem(&m_sh2_state->m_spc));
+ UML_MOV(block, R32(REG_N), mem(&m_sh2_state->m_spc));
return true;
}
@@ -2940,7 +3024,7 @@ bool sh34_base_device::generate_group_0_PREFM(drcuml_block &block, compiler_stat
bool sh34_base_device::generate_group_0_MOVCAL(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc)
{
- UML_MOV(block, I0, R32(Rn))
+ UML_MOV(block, I0, R32(REG_N))
SETEA(0);
UML_MOV(block, I1, R32(0));
UML_CALLH(block, *m_write32);
@@ -2985,27 +3069,27 @@ bool sh34_base_device::generate_group_0_SETS(drcuml_block &block, compiler_state
bool sh34_base_device::generate_group_0_STCSGR(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc)
{
- UML_MOV(block, R32(Rn), mem(&m_sh2_state->m_sgr));
+ UML_MOV(block, R32(REG_N), mem(&m_sh2_state->m_sgr));
return true;
}
bool sh34_base_device::generate_group_0_STSFPUL(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc)
{
- UML_MOV(block, R32(Rn), mem(&m_sh2_state->m_fpul));
+ UML_MOV(block, R32(REG_N), mem(&m_sh2_state->m_fpul));
return true;
}
bool sh34_base_device::generate_group_0_STSFPSCR(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc)
{
UML_AND(block, I0, 0x003FFFFF, mem(&m_sh2_state->m_fpscr));
- UML_MOV(block, R32(Rn), I0);
+ UML_MOV(block, R32(REG_N), I0);
return true;
}
bool sh34_base_device::generate_group_0_STCDBR(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc)
{
- UML_MOV(block, R32(Rn), mem(&m_sh2_state->m_dbr));
+ UML_MOV(block, R32(REG_N), mem(&m_sh2_state->m_dbr));
return true;
}
@@ -3295,7 +3379,7 @@ bool sh34_base_device::generate_group_4_LDCMSSR(drcuml_block &block, compiler_st
bool sh34_base_device::generate_group_4_LDCSSR(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc)
{
- UML_MOV(block, mem(&m_sh2_state->m_ssr), R32(Rn));
+ UML_MOV(block, mem(&m_sh2_state->m_ssr), R32(REG_N));
return true;
}
@@ -3325,7 +3409,7 @@ bool sh34_base_device::generate_group_4_LDCMSPC(drcuml_block &block, compiler_st
bool sh34_base_device::generate_group_4_LDCSPC(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc)
{
- UML_MOV(block, mem(&m_sh2_state->m_spc), R32(Rn));
+ UML_MOV(block, mem(&m_sh2_state->m_spc), R32(REG_N));
return true;
}
@@ -3355,7 +3439,7 @@ bool sh34_base_device::generate_group_4_LDSMFPUL(drcuml_block &block, compiler_s
bool sh34_base_device::generate_group_4_LDSFPUL(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc)
{
- UML_MOV(block, mem(&m_sh2_state->m_fpul), R32(Rn));
+ UML_MOV(block, mem(&m_sh2_state->m_fpul), R32(REG_N));
return true;
}
@@ -3464,11 +3548,11 @@ bool sh34_base_device::generate_group_15_FADD(drcuml_block &block, compiler_stat
UML_TEST(block, mem(&m_sh2_state->m_fpu_pr), 0);
UML_JMPc(block, COND_Z, compiler.labelnum);
- UML_FDADD(block, FPD32(Rn), FPD32(Rn), FPD32(Rm));
+ UML_FDADD(block, FPD32(REG_N), FPD32(REG_N), FPD32(REG_M));
UML_JMP(block, compiler.labelnum+1);
UML_LABEL(block, compiler.labelnum++); // labelnum:
- UML_FSADD(block, FPS32(Rn), FPS32(Rn), FPS32(Rm));
+ UML_FSADD(block, FPS32(REG_N), FPS32(REG_N), FPS32(REG_M));
UML_LABEL(block, compiler.labelnum++); // labelnum+1:
@@ -3480,11 +3564,11 @@ bool sh34_base_device::generate_group_15_FSUB(drcuml_block &block, compiler_stat
UML_TEST(block, mem(&m_sh2_state->m_fpu_pr), 0);
UML_JMPc(block, COND_Z, compiler.labelnum);
- UML_FDSUB(block, FPD32(Rn), FPD32(Rn), FPD32(Rm));
+ UML_FDSUB(block, FPD32(REG_N), FPD32(REG_N), FPD32(REG_M));
UML_JMP(block, compiler.labelnum+1);
UML_LABEL(block, compiler.labelnum++); // labelnum:
- UML_FSSUB(block, FPS32(Rn), FPS32(Rn), FPS32(Rm));
+ UML_FSSUB(block, FPS32(REG_N), FPS32(REG_N), FPS32(REG_M));
UML_LABEL(block, compiler.labelnum++); // labelnum+1:
@@ -3496,11 +3580,11 @@ bool sh34_base_device::generate_group_15_FMUL(drcuml_block &block, compiler_stat
UML_TEST(block, mem(&m_sh2_state->m_fpu_pr), 0);
UML_JMPc(block, COND_Z, compiler.labelnum);
- UML_FDMUL(block, FPD32(Rn), FPD32(Rn), FPD32(Rm));
+ UML_FDMUL(block, FPD32(REG_N), FPD32(REG_N), FPD32(REG_M));
UML_JMP(block, compiler.labelnum+1);
UML_LABEL(block, compiler.labelnum++); // labelnum:
- UML_FSMUL(block, FPS32(Rn), FPS32(Rn), FPS32(Rm));
+ UML_FSMUL(block, FPS32(REG_N), FPS32(REG_N), FPS32(REG_M));
UML_LABEL(block, compiler.labelnum++); // labelnum+1:
@@ -3512,11 +3596,11 @@ bool sh34_base_device::generate_group_15_FDIV(drcuml_block &block, compiler_stat
UML_TEST(block, mem(&m_sh2_state->m_fpu_pr), 0);
UML_JMPc(block, COND_Z, compiler.labelnum);
- UML_FDDIV(block, FPD32(Rn), FPD32(Rn), FPD32(Rm));
+ UML_FDDIV(block, FPD32(REG_N), FPD32(REG_N), FPD32(REG_M));
UML_JMP(block, compiler.labelnum+1);
UML_LABEL(block, compiler.labelnum++); // labelnum:
- UML_FSDIV(block, FPS32(Rn), FPS32(Rn), FPS32(Rm));
+ UML_FSDIV(block, FPS32(REG_N), FPS32(REG_N), FPS32(REG_M));
UML_LABEL(block, compiler.labelnum++); // labelnum+1:
@@ -3528,7 +3612,7 @@ bool sh34_base_device::generate_group_15_FCMP_EQ(drcuml_block &block, compiler_s
UML_TEST(block, uml::mem(&m_sh2_state->m_fpu_pr), 0);
UML_JMPc(block, COND_Z, compiler.labelnum);
- UML_FDCMP(block, FPD32(Rm & 14), FPD32(Rn & 14));
+ UML_FDCMP(block, FPD32(REG_M & 14), FPD32(REG_N & 14));
UML_SETc(block, COND_Z, I0);
UML_ROLINS(block, uml::mem(&m_sh2_state->sr), I0, T_SHIFT, SH_T);
@@ -3536,7 +3620,7 @@ bool sh34_base_device::generate_group_15_FCMP_EQ(drcuml_block &block, compiler_s
UML_LABEL(block, compiler.labelnum++); // labelnum:
- UML_FSCMP(block, FPS32(Rm), FPS32(Rn));
+ UML_FSCMP(block, FPS32(REG_M), FPS32(REG_N));
UML_SETc(block, COND_Z, I0);
UML_ROLINS(block, uml::mem(&m_sh2_state->sr), I0, T_SHIFT, SH_T);
@@ -3549,7 +3633,7 @@ bool sh34_base_device::generate_group_15_FCMP_GT(drcuml_block &block, compiler_s
UML_TEST(block, uml::mem(&m_sh2_state->m_fpu_pr), 0);
UML_JMPc(block, COND_Z, compiler.labelnum);
- UML_FDCMP(block, FPD32(Rm & 14), FPD32(Rn & 14));
+ UML_FDCMP(block, FPD32(REG_M & 14), FPD32(REG_N & 14));
UML_SETc(block, COND_C, I0);
UML_ROLINS(block, uml::mem(&m_sh2_state->sr), I0, T_SHIFT, SH_T);
@@ -3557,7 +3641,7 @@ bool sh34_base_device::generate_group_15_FCMP_GT(drcuml_block &block, compiler_s
UML_LABEL(block, compiler.labelnum++); // labelnum:
- UML_FSCMP(block, FPS32(Rm), FPS32(Rn));
+ UML_FSCMP(block, FPS32(REG_M), FPS32(REG_N));
UML_SETc(block, COND_C, I0);
UML_ROLINS(block, uml::mem(&m_sh2_state->sr), I0, T_SHIFT, SH_T);
@@ -3654,8 +3738,8 @@ bool sh34_base_device::generate_group_15_FMAC(drcuml_block &block, compiler_stat
UML_TEST(block, mem(&m_sh2_state->m_fpu_pr), 0);
UML_JMPc(block, COND_NZ, compiler.labelnum);
- UML_FSMUL(block, F0, FPS32(0), FPS32(Rm));
- UML_FSADD(block, FPS32(Rn), F0, FPS32(Rn));
+ UML_FSMUL(block, F0, FPS32(0), FPS32(REG_M));
+ UML_FSADD(block, FPS32(REG_N), F0, FPS32(REG_N));
UML_LABEL(block, compiler.labelnum++);
return true;
@@ -3688,10 +3772,10 @@ bool sh34_base_device::generate_group_15_op1111_0x13(drcuml_block &block, compil
bool sh34_base_device::generate_group_15_op1111_0x13_FSTS(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc)
{
#ifdef LSB_FIRST
- UML_XOR(block, I0, Rn, uml::mem(&m_sh2_state->m_fpu_pr));
+ UML_XOR(block, I0, REG_N, uml::mem(&m_sh2_state->m_fpu_pr));
UML_STORE(block, m_sh2_state->m_fr, I0, uml::mem(&m_sh2_state->m_fpul), SIZE_DWORD, SCALE_x4);
#else
- UML_MOV(block, FPS32(Rn), uml::mem(&m_sh2_state->m_fpul));
+ UML_MOV(block, FPS32(REG_N), uml::mem(&m_sh2_state->m_fpul));
#endif
return true;
}
@@ -3713,12 +3797,12 @@ bool sh34_base_device::generate_group_15_op1111_0x13_FLOAT(drcuml_block &block,
UML_TEST(block, uml::mem(&m_sh2_state->m_fpu_pr), 0);
UML_JMPc(block, COND_Z, compiler.labelnum);
- UML_FDFRINT(block, FPD32(Rn & 14), uml::mem(&m_sh2_state->m_fpul), SIZE_DWORD);
+ UML_FDFRINT(block, FPD32(REG_N & 14), uml::mem(&m_sh2_state->m_fpul), SIZE_DWORD);
UML_JMP(block, compiler.labelnum+1);
UML_LABEL(block, compiler.labelnum++); // labelnum:
- UML_FSFRINT(block, FPS32(Rn), uml::mem(&m_sh2_state->m_fpul), SIZE_DWORD);
+ UML_FSFRINT(block, FPS32(REG_N), uml::mem(&m_sh2_state->m_fpul), SIZE_DWORD);
UML_LABEL(block, compiler.labelnum++); // labelnum+1:
@@ -3730,12 +3814,12 @@ bool sh34_base_device::generate_group_15_op1111_0x13_FTRC(drcuml_block &block, c
UML_TEST(block, uml::mem(&m_sh2_state->m_fpu_pr), 0);
UML_JMPc(block, COND_Z, compiler.labelnum);
- UML_FDTOINT(block, uml::mem(&m_sh2_state->m_fpul), FPD32(Rn & 14), SIZE_DWORD, ROUND_TRUNC);
+ UML_FDTOINT(block, uml::mem(&m_sh2_state->m_fpul), FPD32(REG_N & 14), SIZE_DWORD, ROUND_TRUNC);
UML_JMP(block, compiler.labelnum+1);
UML_LABEL(block, compiler.labelnum++); // labelnum:
- UML_FSTOINT(block, uml::mem(&m_sh2_state->m_fpul), FPS32(Rn), SIZE_DWORD, ROUND_TRUNC);
+ UML_FSTOINT(block, uml::mem(&m_sh2_state->m_fpul), FPS32(REG_N), SIZE_DWORD, ROUND_TRUNC);
UML_LABEL(block, compiler.labelnum++); // labelnum+1:
return true;
@@ -3749,14 +3833,14 @@ bool sh34_base_device::generate_group_15_op1111_0x13_FNEG(drcuml_block &block, c
UML_JMPc(block, COND_Z, compiler.labelnum);
UML_FDFRINT(block, F1, I0, SIZE_DWORD);
- UML_FDSUB(block, FPD32(Rn), F1, FPD32(Rn));
+ UML_FDSUB(block, FPD32(REG_N), F1, FPD32(REG_N));
UML_JMP(block, compiler.labelnum+1);
UML_LABEL(block, compiler.labelnum++); // labelnum:
UML_FSFRINT(block, F1, I0, SIZE_DWORD);
- UML_FSSUB(block, FPS32(Rn), F1, FPS32(Rn));
+ UML_FSSUB(block, FPS32(REG_N), F1, FPS32(REG_N));
UML_LABEL(block, compiler.labelnum++); // labelnum+1:
return true;
@@ -3768,16 +3852,16 @@ bool sh34_base_device::generate_group_15_op1111_0x13_FABS(drcuml_block &block, c
UML_JMPc(block, COND_Z, compiler.labelnum);
#ifdef LSB_FIRST
- UML_AND(block, FPS32(((Rn&14)|1)), FPS32(((Rn&14)|1)), 0x7fffffff);
+ UML_AND(block, FPS32(((REG_N & 14) | 1)), FPS32(((REG_N & 14) | 1)), 0x7fffffff);
#else
- UML_AND(block, FPS32(Rn&14), FPS32(Rn&14), 0x7fffffff);
+ UML_AND(block, FPS32(REG_N & 14), FPS32(REG_N & 14), 0x7fffffff);
#endif
- UML_JMP(block, compiler.labelnum+1);
+ UML_JMP(block, compiler.labelnum + 1);
UML_LABEL(block, compiler.labelnum++); // labelnum:
- UML_AND(block, FPS32(Rn), FPS32(Rn), 0x7fffffff);
+ UML_AND(block, FPS32(REG_N), FPS32(REG_N), 0x7fffffff);
UML_LABEL(block, compiler.labelnum++); // labelnum+1:
return true;
@@ -3810,11 +3894,11 @@ bool sh34_base_device::generate_group_15_op1111_0x13_FSRRA(drcuml_block &block,
bool sh34_base_device::generate_group_15_op1111_0x13_FLDI0(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc)
{
#ifdef LSB_FIRST
- UML_MOV(block, I0, Rn);
+ UML_MOV(block, I0, REG_N);
UML_XOR(block, I0, I0, uml::mem(&m_sh2_state->m_fpu_pr));
UML_STORE(block, m_sh2_state->m_fr, I0, 0, SIZE_DWORD, SCALE_x4);
#else
- UML_MOV(block, FP_RFS(Rn), 0);
+ UML_MOV(block, FP_RFS(REG_N), 0);
#endif
return true;
}
@@ -3822,11 +3906,11 @@ bool sh34_base_device::generate_group_15_op1111_0x13_FLDI0(drcuml_block &block,
bool sh34_base_device::generate_group_15_op1111_0x13_FLDI1(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc)
{
#ifdef LSB_FIRST
- UML_MOV(block, I0, Rn);
+ UML_MOV(block, I0, REG_N);
UML_XOR(block, I0, I0, uml::mem(&m_sh2_state->m_fpu_pr));
UML_STORE(block, m_sh2_state->m_fr, I0, 0x3F800000, SIZE_DWORD, SCALE_x4);
#else
- UML_MOV(block, FP_RFS(Rn), 0x3F800000);
+ UML_MOV(block, FP_RFS(REG_N), 0x3F800000);
#endif
return true;
}
@@ -3869,8 +3953,10 @@ bool sh34_base_device::generate_group_15_op1111_0x13_FIPR(drcuml_block &block, c
bool sh34_base_device::generate_group_15_op1111_0x13_op1111_0xf13(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc)
{
- if (opcode & 0x100) {
- if (opcode & 0x200) {
+ if (opcode & 0x100)
+ {
+ if (opcode & 0x200)
+ {
switch (opcode & 0xC00)
{
case 0x000:
@@ -3884,11 +3970,13 @@ bool sh34_base_device::generate_group_15_op1111_0x13_op1111_0xf13(drcuml_block &
break;
}
}
- else {
+ else
+ {
return generate_group_15_op1111_0x13_op1111_0xf13_FTRV(block, compiler, desc, opcode, in_delay_slot, ovrpc); // FTRV(opcode);
}
}
- else {
+ else
+ {
return generate_group_15_op1111_0x13_op1111_0xf13_FSSCA(block, compiler, desc, opcode, in_delay_slot, ovrpc); // FSSCA(opcode);
}
return false;
diff --git a/src/devices/cpu/sh/sh4.h b/src/devices/cpu/sh/sh4.h
index b2c97c9dc16..e344a42385e 100644
--- a/src/devices/cpu/sh/sh4.h
+++ b/src/devices/cpu/sh/sh4.h
@@ -2,7 +2,7 @@
// copyright-holders:R. Belmont
/*****************************************************************************
*
- * sh4->h
+ * sh4.h
* Portable Hitachi SH-4 (SH7750 family) emulator interface
*
* By R. Belmont, based on sh2.c by Juergen Buchmueller, Mariusz Wojcieszek,
@@ -168,10 +168,10 @@ public:
void set_mmu_hacktype(int hacktype) { m_mmuhack = hacktype; }
- TIMER_CALLBACK_MEMBER( sh4_refresh_timer_callback );
- TIMER_CALLBACK_MEMBER( sh4_rtc_timer_callback );
- TIMER_CALLBACK_MEMBER( sh4_timer_callback );
- TIMER_CALLBACK_MEMBER( sh4_dmac_callback );
+ TIMER_CALLBACK_MEMBER(sh4_refresh_timer_callback);
+ TIMER_CALLBACK_MEMBER(sh4_rtc_timer_callback);
+ TIMER_CALLBACK_MEMBER(sh4_timer_callback);
+ TIMER_CALLBACK_MEMBER(sh4_dmac_callback);
virtual void set_frt_input(int state) override;
void sh4_set_irln_input(int value);
@@ -387,13 +387,11 @@ protected:
inline void sh4_check_pending_irq(const char *message) // look for highest priority active exception and handle it
{
- int a,irq,z;
-
m_willjump = 0; // for the DRC
- irq = 0;
- z = -1;
- for (a=0;a <= SH4_INTC_ROVI;a++)
+ int irq = 0;
+ int z = -1;
+ for (int a = 0; a <= SH4_INTC_ROVI; a++)
{
if (m_exception_requesting[a])
{
@@ -493,12 +491,13 @@ protected:
uint32_t sh4_handle_dmaor_addr_r(uint32_t mem_mask) { return m_SH4_DMAOR; }
// memory handlers
- virtual uint8_t RB(offs_t A) override;
- virtual uint16_t RW(offs_t A) override;
- virtual uint32_t RL(offs_t A) override;
- virtual void WB(offs_t A, uint8_t V) override;
- virtual void WW(offs_t A, uint16_t V) override;
- virtual void WL(offs_t A, uint32_t V) override;
+ virtual uint8_t read_byte(offs_t offset) override;
+ virtual uint16_t read_word(offs_t offset) override;
+ virtual uint32_t read_long(offs_t offset) override;
+ virtual uint16_t decrypted_read_word(offs_t offset) override;
+ virtual void write_byte(offs_t offset, uint8_t data) override;
+ virtual void write_word(offs_t offset, uint16_t data) override;
+ virtual void write_long(offs_t offset, uint32_t data) override;
// regular handlers for opcodes which need to differ on sh3/4 due to different interrupt / exception handling and register banking
virtual void LDCSR(const uint16_t opcode) override;
diff --git a/src/devices/cpu/sh/sh4comn.cpp b/src/devices/cpu/sh/sh4comn.cpp
index b43d8b1d5c0..b8c59aa7ee5 100644
--- a/src/devices/cpu/sh/sh4comn.cpp
+++ b/src/devices/cpu/sh/sh4comn.cpp
@@ -2,7 +2,7 @@
// copyright-holders:R. Belmont
/*****************************************************************************
*
- * sh4comn.c
+ * sh4comn.cpp
*
* SH-4 non-specific components
*
@@ -22,33 +22,33 @@ static const int daysmonth[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 3
static const uint32_t exception_priority_default[] = {
- EXPPRI(1,1,0,0), /* Power-on Reset */
- EXPPRI(1,2,0,1), /* Manual Reset */
- EXPPRI(1,1,0,2), /* H-UDI Reset */
- EXPPRI(1,3,0,3), /* Inst TLB Multiple Hit */
- EXPPRI(1,4,0,4), /* Data TLB Multiple Hit */
-
- EXPPRI(2,0,0,5), /* User break Before Instruction */
- EXPPRI(2,1,0,6), /* Inst Address Error */
- EXPPRI(2,2,0,7), /* Inst TLB Miss */
- EXPPRI(2,3,0,8), /* Inst TLB Protection Violation */
- EXPPRI(2,4,0,9), /* Illegal Instruction */
- EXPPRI(2,4,0,10), /* Slot Illegal Instruction */
- EXPPRI(2,4,0,11), /* FPU Disable */
- EXPPRI(2,4,0,12), /* Slot FPU Disable */
- EXPPRI(2,5,0,13), /* Data Address Error (Read) */
- EXPPRI(2,5,0,14), /* Data Address Error (Write) */
- EXPPRI(2,6,0,15), /* Data TBL Miss Read */
- EXPPRI(2,6,0,16), /* Data TBL Miss Write */
- EXPPRI(2,7,0,17), /* Data TBL Protection Violation Read */
- EXPPRI(2,7,0,18), /* Data TBL Protection Violation Write */
- EXPPRI(2,8,0,19), /* FPU Exception */
- EXPPRI(2,9,0,20), /* Initial Page Write exception */
-
- EXPPRI(2,4,0,21), /* Unconditional TRAP */
- EXPPRI(2,10,0,22), /* User break After Instruction */
-
- EXPPRI(3,0,16,SH4_INTC_NMI) /* NMI */
+ EXPPRI(1, 1, 0, 0), /* Power-on Reset */
+ EXPPRI(1, 2, 0, 1), /* Manual Reset */
+ EXPPRI(1, 1, 0, 2), /* H-UDI Reset */
+ EXPPRI(1, 3, 0, 3), /* Inst TLB Multiple Hit */
+ EXPPRI(1, 4, 0, 4), /* Data TLB Multiple Hit */
+
+ EXPPRI(2, 0, 0, 5), /* User break Before Instruction */
+ EXPPRI(2, 1, 0, 6), /* Inst Address Error */
+ EXPPRI(2, 2, 0, 7), /* Inst TLB Miss */
+ EXPPRI(2, 3, 0, 8), /* Inst TLB Protection Violation */
+ EXPPRI(2, 4, 0, 9), /* Illegal Instruction */
+ EXPPRI(2, 4, 0, 10), /* Slot Illegal Instruction */
+ EXPPRI(2, 4, 0, 11), /* FPU Disable */
+ EXPPRI(2, 4, 0, 12), /* Slot FPU Disable */
+ EXPPRI(2, 5, 0, 13), /* Data Address Error (Read) */
+ EXPPRI(2, 5, 0, 14), /* Data Address Error (Write) */
+ EXPPRI(2, 6, 0, 15), /* Data TBL Miss Read */
+ EXPPRI(2, 6, 0, 16), /* Data TBL Miss Write */
+ EXPPRI(2, 7, 0, 17), /* Data TBL Protection Violation Read */
+ EXPPRI(2, 7, 0, 18), /* Data TBL Protection Violation Write */
+ EXPPRI(2, 8, 0, 19), /* FPU Exception */
+ EXPPRI(2, 9, 0, 20), /* Initial Page Write exception */
+
+ EXPPRI(2, 4, 0, 21), /* Unconditional TRAP */
+ EXPPRI(2, 10, 0, 22), /* User break After Instruction */
+
+ EXPPRI(3, 0, 16, SH4_INTC_NMI) /* NMI */
/* This is copied to a table, and the IRQ priorities filled in later */
};
@@ -234,12 +234,9 @@ static const int sh3_intevt2_exception_codes[] =
void sh34_base_device::sh4_swap_fp_registers()
{
- int s;
- uint32_t z;
-
- for (s = 0;s <= 15;s++)
+ for (int s = 0; s <= 15; s++)
{
- z = m_sh2_state->m_fr[s];
+ uint32_t z = m_sh2_state->m_fr[s];
m_sh2_state->m_fr[s] = m_sh2_state->m_xf[s];
m_sh2_state->m_xf[s] = z;
}
@@ -247,14 +244,12 @@ void sh34_base_device::sh4_swap_fp_registers()
void sh34_base_device::sh4_swap_fp_couples()
{
- int s;
- uint32_t z;
-
- for (s = 0;s <= 15;s = s+2)
+ for (int s = 0; s <= 15; s += 2)
{
- z = m_sh2_state->m_fr[s];
+ uint32_t z = m_sh2_state->m_fr[s];
m_sh2_state->m_fr[s] = m_sh2_state->m_fr[s + 1];
m_sh2_state->m_fr[s + 1] = z;
+
z = m_sh2_state->m_xf[s];
m_sh2_state->m_xf[s] = m_sh2_state->m_xf[s + 1];
m_sh2_state->m_xf[s + 1] = z;
@@ -264,11 +259,9 @@ void sh34_base_device::sh4_swap_fp_couples()
void sh34_base_device::sh4_change_register_bank(int to)
{
- int s;
-
if (to) // 0 -> 1
{
- for (s = 0;s < 8;s++)
+ for (int s = 0; s < 8; s++)
{
m_sh2_state->m_rbnk[0][s] = m_sh2_state->r[s];
m_sh2_state->r[s] = m_sh2_state->m_rbnk[1][s];
@@ -276,7 +269,7 @@ void sh34_base_device::sh4_change_register_bank(int to)
}
else // 1 -> 0
{
- for (s = 0;s < 8;s++)
+ for (int s = 0; s < 8; s++)
{
m_sh2_state->m_rbnk[1][s] = m_sh2_state->r[s];
m_sh2_state->r[s] = m_sh2_state->m_rbnk[0][s];
@@ -286,9 +279,7 @@ void sh34_base_device::sh4_change_register_bank(int to)
void sh34_base_device::sh4_syncronize_register_bank(int to)
{
- int s;
-
- for (s = 0;s < 8;s++)
+ for (int s = 0; s < 8; s++)
{
m_sh2_state->m_rbnk[to][s] = m_sh2_state->r[s];
}
@@ -296,34 +287,30 @@ void sh34_base_device::sh4_syncronize_register_bank(int to)
void sh34_base_device::sh4_default_exception_priorities() // setup default priorities for exceptions
{
- int a;
-
- for (a=0;a <= SH4_INTC_NMI;a++)
+ for (int a = 0; a <= SH4_INTC_NMI; a++)
m_exception_priority[a] = exception_priority_default[a];
- for (a=SH4_INTC_IRLn0;a <= SH4_INTC_IRLnE;a++)
- m_exception_priority[a] = INTPRI(15-(a-SH4_INTC_IRLn0), a);
+ for (int a = SH4_INTC_IRLn0; a <= SH4_INTC_IRLnE; a++)
+ m_exception_priority[a] = INTPRI(15-(a - SH4_INTC_IRLn0), a);
m_exception_priority[SH4_INTC_IRL0] = INTPRI(13, SH4_INTC_IRL0);
m_exception_priority[SH4_INTC_IRL1] = INTPRI(10, SH4_INTC_IRL1);
m_exception_priority[SH4_INTC_IRL2] = INTPRI(7, SH4_INTC_IRL2);
m_exception_priority[SH4_INTC_IRL3] = INTPRI(4, SH4_INTC_IRL3);
- for (a=SH4_INTC_HUDI;a <= SH4_INTC_ROVI;a++)
+ for (int a = SH4_INTC_HUDI; a <= SH4_INTC_ROVI; a++)
m_exception_priority[a] = INTPRI(0, a);
}
void sh34_base_device::sh4_exception_recompute() // checks if there is any interrupt with high enough priority
{
- int a,z;
-
m_sh2_state->m_test_irq = 0;
- if ((!m_sh2_state->m_pending_irq) || ((m_sh2_state->sr & BL) && (m_exception_requesting[SH4_INTC_NMI] == 0)))
+ if (!m_sh2_state->m_pending_irq || ((m_sh2_state->sr & BL) && m_exception_requesting[SH4_INTC_NMI] == 0))
return;
- z = (m_sh2_state->sr >> 4) & 15;
- for (a=0;a <= SH4_INTC_ROVI;a++)
+ int z = (m_sh2_state->sr >> 4) & 15;
+ for (int a = 0; a <= SH4_INTC_ROVI; a++)
{
if (m_exception_requesting[a])
{
- int pri = (((int)m_exception_priority[a] >> 8) & 255);
- //logerror("pri is %02x z is %02x\n",pri,z);
+ int pri = ((int)m_exception_priority[a] >> 8) & 255;
+ //logerror("pri is %02x z is %02x\n", pri, z);
if (pri > z)
{
//logerror("will test\n");
@@ -360,8 +347,7 @@ void sh34_base_device::sh4_exception_checkunrequest(int exception)
{
if (exception == SH4_INTC_NMI)
sh4_exception_unrequest(exception);
- if ((exception == SH4_INTC_DMTE0) || (exception == SH4_INTC_DMTE1) ||
- (exception == SH4_INTC_DMTE2) || (exception == SH4_INTC_DMTE3))
+ if (exception == SH4_INTC_DMTE0 || exception == SH4_INTC_DMTE1 || exception == SH4_INTC_DMTE2 || exception == SH4_INTC_DMTE3)
sh4_exception_unrequest(exception);
}
@@ -389,7 +375,10 @@ void sh34_base_device::sh4_exception_process(int exception, uint32_t vector)
m_sh2_state->pc = m_sh2_state->vbr + vector;
m_willjump = 1; // for DRC
/* wake up if a sleep opcode is triggered */
- if(m_sh2_state->sleep_mode == 1) { m_sh2_state->sleep_mode = 2; }
+ if (m_sh2_state->sleep_mode == 1)
+ {
+ m_sh2_state->sleep_mode = 2;
+ }
}
void sh34_base_device::sh4_exception(const char *message, int exception) // handle exception
@@ -400,18 +389,21 @@ void sh34_base_device::sh4_exception(const char *message, int exception) // hand
{
if (exception < SH4_INTC_NMI)
return; // Not yet supported
- if (exception == SH4_INTC_NMI) {
- if ((m_sh2_state->sr & BL) && (!(m_m[ICR] & 0x200)))
+
+ if (exception == SH4_INTC_NMI)
+ {
+ if ((m_sh2_state->sr & BL) && !(m_m[ICR] & 0x200))
return;
m_m[ICR] &= ~0x200;
m_m[INTEVT] = 0x1c0;
-
vector = 0x600;
standard_irq_callback(INPUT_LINE_NMI, m_sh2_state->pc);
- LOG(("SH-4 '%s' nmi exception after [%s]\n", tag(), message));
- } else {
+ LOG("SH-4 '%s' nmi exception after [%s]\n", tag(), message);
+ }
+ else
+ {
// if ((m_m[ICR] & 0x4000) && (m_nmi_line_state == ASSERT_LINE))
// return;
if (m_sh2_state->sr & BL)
@@ -420,11 +412,11 @@ void sh34_base_device::sh4_exception(const char *message, int exception) // hand
return;
m_m[INTEVT] = exception_codes[exception];
vector = 0x600;
- if ((exception >= SH4_INTC_IRL0) && (exception <= SH4_INTC_IRL3))
- standard_irq_callback((exception-SH4_INTC_IRL0)+SH4_IRL0, m_sh2_state->pc);
+ if (exception >= SH4_INTC_IRL0 && exception <= SH4_INTC_IRL3)
+ standard_irq_callback((exception - SH4_INTC_IRL0) + SH4_IRL0, m_sh2_state->pc);
else
- standard_irq_callback(SH4_IRL3+1, m_sh2_state->pc);
- LOG(("SH-4 '%s' interrupt exception #%d after [%s]\n", tag(), exception, message));
+ standard_irq_callback(SH4_IRL3 + 1, m_sh2_state->pc);
+ LOG("SH-4 '%s' interrupt exception #%d after [%s]\n", tag(), exception, message);
}
}
else /* SH3 exceptions */
@@ -444,30 +436,30 @@ void sh34_base_device::sh4_exception(const char *message, int exception) // hand
if (((m_exception_priority[exception] >> 8) & 255) <= ((m_sh2_state->sr >> 4) & 15))
return;
-
vector = 0x600;
- if ((exception >= SH4_INTC_IRL0) && (exception <= SH4_INTC_IRL3))
- standard_irq_callback((exception-SH4_INTC_IRL0)+SH4_IRL0, m_sh2_state->pc);
+ if (exception >= SH4_INTC_IRL0 && exception <= SH4_INTC_IRL3)
+ standard_irq_callback((exception - SH4_INTC_IRL0) + SH4_IRL0, m_sh2_state->pc);
else
- standard_irq_callback(SH4_IRL3+1, m_sh2_state->pc);
+ standard_irq_callback(SH4_IRL3 + 1, m_sh2_state->pc);
- if (sh3_intevt2_exception_codes[exception]==-1)
+ if (sh3_intevt2_exception_codes[exception] == -1)
fatalerror("sh3_intevt2_exception_codes unpopulated for exception %02x\n", exception);
m_sh3internal_lower[INTEVT2] = sh3_intevt2_exception_codes[exception];
m_sh3internal_upper[SH3_EXPEVT_ADDR] = exception_codes[exception];
if (sh3_intevt2_exception_codes[exception] >= 0x600)
- m_sh3internal_upper[SH3_INTEVT_ADDR] = 0x3E0 - ((m_exception_priority[exception] >> 8) & 255) * 0x20;
+ m_sh3internal_upper[SH3_INTEVT_ADDR] = 0x3e0 - ((m_exception_priority[exception] >> 8) & 255) * 0x20;
else
m_sh3internal_upper[SH3_INTEVT_ADDR] = sh3_intevt2_exception_codes[exception];
- LOG(("SH-3 '%s' interrupt exception #%d after [%s]\n", tag(), exception, message));
+ LOG("SH-3 '%s' interrupt exception #%d after [%s]\n", tag(), exception, message);
}
/***** END ASSUME THIS TO BE WRONG FOR NOW *****/
}
+
sh4_exception_process(exception, vector);
}
@@ -477,20 +469,17 @@ uint32_t sh34_base_device::compute_ticks_refresh_timer(emu_timer *timer, int her
// elapsed:total = x : ticks
// x=elapsed*tics/total -> x=elapsed*(double)100000000/rtcnt_div[(m_m[RTCSR] >> 3) & 7]
// ticks/total=ticks / ((rtcnt_div[(m_m[RTCSR] >> 3) & 7] * ticks) / 100000000)=1/((rtcnt_div[(m_m[RTCSR] >> 3) & 7] / 100000000)=100000000/rtcnt_div[(m_m[RTCSR] >> 3) & 7]
- return base + (uint32_t)((timer->elapsed().as_double() * (double)hertz) / (double)divisor);
+ return base + (uint32_t)((timer->elapsed().as_double() * hertz) / divisor);
}
void sh34_base_device::sh4_refresh_timer_recompute()
{
- uint32_t ticks;
-
if (m_cpu_type != CPU_TYPE_SH4)
fatalerror("sh4_refresh_timer_recompute uses m_m[] with SH3\n");
-
//if rtcnt < rtcor then rtcor-rtcnt
//if rtcnt >= rtcor then 256-rtcnt+rtcor=256+rtcor-rtcnt
- ticks = m_m[RTCOR]-m_m[RTCNT];
+ uint32_t ticks = m_m[RTCOR]-m_m[RTCNT];
if (ticks <= 0)
ticks = 256 + ticks;
m_refresh_timer->adjust(attotime::from_hz(m_bus_clock) * rtcnt_div[(m_m[RTCSR] >> 3) & 7] * ticks);
@@ -498,7 +487,7 @@ void sh34_base_device::sh4_refresh_timer_recompute()
}
-TIMER_CALLBACK_MEMBER( sh34_base_device::sh4_refresh_timer_callback )
+TIMER_CALLBACK_MEMBER(sh34_base_device::sh4_refresh_timer_callback)
{
if (m_cpu_type != CPU_TYPE_SH4)
fatalerror("sh4_refresh_timer_callback uses m_m[] with SH3\n");
@@ -509,7 +498,7 @@ TIMER_CALLBACK_MEMBER( sh34_base_device::sh4_refresh_timer_callback )
if ((m_m[MCR] & 4) && !(m_m[MCR] & 2))
{
m_m[RFCR] = (m_m[RFCR] + 1) & 1023;
- if (((m_m[RTCSR] & 1) && (m_m[RFCR] == 512)) || (m_m[RFCR] == 0))
+ if (((m_m[RTCSR] & 1) && m_m[RFCR] == 512) || m_m[RFCR] == 0)
{
m_m[RFCR] = 0;
m_m[RTCSR] |= 4;
@@ -519,11 +508,10 @@ TIMER_CALLBACK_MEMBER( sh34_base_device::sh4_refresh_timer_callback )
void sh34_base_device::increment_rtc_time(int mode)
{
- int carry, year, leap, days;
-
if (m_cpu_type != CPU_TYPE_SH4)
fatalerror("increment_rtc_time uses m_m[] with SH3\n");
+ int carry;
if (mode == 0)
{
carry = 0;
@@ -533,7 +521,7 @@ void sh34_base_device::increment_rtc_time(int mode)
if (m_m[RSECCNT] == 0x60)
{
m_m[RSECCNT] = 0;
- carry=1;
+ carry = 1;
}
else
return;
@@ -544,7 +532,8 @@ void sh34_base_device::increment_rtc_time(int mode)
m_m[RMINCNT] = m_m[RMINCNT] + carry;
if ((m_m[RMINCNT] & 0xf) == 0xa)
m_m[RMINCNT] = m_m[RMINCNT] + 6;
- carry=0;
+ carry = 0;
+
if (m_m[RMINCNT] == 0x60)
{
m_m[RMINCNT] = 0;
@@ -555,6 +544,7 @@ void sh34_base_device::increment_rtc_time(int mode)
if ((m_m[RHRCNT] & 0xf) == 0xa)
m_m[RHRCNT] = m_m[RHRCNT] + 6;
carry = 0;
+
if (m_m[RHRCNT] == 0x24)
{
m_m[RHRCNT] = 0;
@@ -567,26 +557,27 @@ void sh34_base_device::increment_rtc_time(int mode)
m_m[RWKCNT] = 0;
}
- days = 0;
- year = (m_m[RYRCNT] & 0xf) + ((m_m[RYRCNT] & 0xf0) >> 4)*10 + ((m_m[RYRCNT] & 0xf00) >> 8)*100 + ((m_m[RYRCNT] & 0xf000) >> 12)*1000;
- leap = 0;
- if (!(year%100))
+ int days = 0;
+ int year = (m_m[RYRCNT] & 0xf) + ((m_m[RYRCNT] & 0xf0) >> 4) * 10 + ((m_m[RYRCNT] & 0xf00) >> 8) * 100 + ((m_m[RYRCNT] & 0xf000) >> 12) * 1000;
+ int leap = 0;
+ if (!(year % 100))
{
- if (!(year%400))
+ if (!(year % 400))
leap = 1;
}
- else if (!(year%4))
+ else if (!(year % 4))
leap = 1;
if (m_m[RMONCNT] != 2)
leap = 0;
if (m_m[RMONCNT])
- days = daysmonth[(m_m[RMONCNT] & 0xf) + ((m_m[RMONCNT] & 0xf0) >> 4)*10 - 1];
+ days = daysmonth[(m_m[RMONCNT] & 0xf) + ((m_m[RMONCNT] & 0xf0) >> 4) * 10 - 1];
m_m[RDAYCNT] = m_m[RDAYCNT] + carry;
if ((m_m[RDAYCNT] & 0xf) == 0xa)
m_m[RDAYCNT] = m_m[RDAYCNT] + 6;
carry = 0;
- if (m_m[RDAYCNT] > (days+leap))
+
+ if (m_m[RDAYCNT] > (days + leap))
{
m_m[RDAYCNT] = 1;
carry = 1;
@@ -595,7 +586,8 @@ void sh34_base_device::increment_rtc_time(int mode)
m_m[RMONCNT] = m_m[RMONCNT] + carry;
if ((m_m[RMONCNT] & 0xf) == 0xa)
m_m[RMONCNT] = m_m[RMONCNT] + 6;
- carry=0;
+ carry = 0;
+
if (m_m[RMONCNT] == 0x13)
{
m_m[RMONCNT] = 1;
@@ -613,7 +605,7 @@ void sh34_base_device::increment_rtc_time(int mode)
m_m[RYRCNT] = 0;
}
-TIMER_CALLBACK_MEMBER( sh34_base_device::sh4_rtc_timer_callback )
+TIMER_CALLBACK_MEMBER(sh34_base_device::sh4_rtc_timer_callback)
{
if (m_cpu_type != CPU_TYPE_SH4)
{
@@ -622,7 +614,8 @@ TIMER_CALLBACK_MEMBER( sh34_base_device::sh4_rtc_timer_callback )
}
m_rtc_timer->adjust(attotime::from_hz(128));
- m_m[R64CNT] = (m_m[R64CNT]+1) & 0x7f;
+
+ m_m[R64CNT] = (m_m[R64CNT] + 1) & 0x7f;
if (m_m[R64CNT] == 64)
{
m_m[RCR1] |= 0x80;
@@ -674,7 +667,6 @@ void sh34_base_device::sh4_handler_ipra_w(uint32_t data, uint32_t mem_mask)
void sh4_base_device::sh4_internal_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
- int a;
uint32_t addr = (offset << 2) + 0xfe000000;
offset = ((addr & 0xfc) >> 2) | ((addr & 0x1fe0000) >> 11);
@@ -682,11 +674,11 @@ void sh4_base_device::sh4_internal_w(offs_t offset, uint32_t data, uint32_t mem_
fatalerror("sh4_internal_w uses m_m[] with SH3\n");
uint32_t old = m_m[offset];
- COMBINE_DATA(m_m+offset);
+ COMBINE_DATA(m_m + offset);
-// printf("sh4_internal_w: Write %08x (%x), %08x @ %08x\n", 0xfe000000+((offset & 0x3fc0) << 11)+((offset & 0x3f) << 2), offset, data, mem_mask);
+// printf("sh4_internal_w: Write %08x (%x), %08x @ %08x\n", 0xfe000000 + ((offset & 0x3fc0) << 11) + ((offset & 0x3f) << 2), offset, data, mem_mask);
- switch( offset )
+ switch (offset)
{
case PTEH: // for use with LDTLB opcode
m_m[PTEH] &= 0xffffffff;
@@ -698,8 +690,6 @@ void sh4_base_device::sh4_internal_w(offs_t offset, uint32_t data, uint32_t mem_
same as the address table part of the utlb but with 2 unused bits (these are sourced from PTEL instead when LDTLB is called)
*/
-
-
break;
case PTEL:
@@ -744,7 +734,7 @@ void sh4_base_device::sh4_internal_w(offs_t offset, uint32_t data, uint32_t mem_
case MMUCR: // MMU Control
m_m[MMUCR] &= 0xffffffff;
// MMUCR_AT
- m_sh4_mmu_enabled = bool(BIT(data, 0));
+ m_sh4_mmu_enabled = BIT(data, 0);
logerror("%s: MMUCR %08x (enable: %d)\n", machine().describe_context(), data, m_sh4_mmu_enabled);
if (m_sh4_mmu_enabled)
@@ -787,16 +777,15 @@ void sh4_base_device::sh4_internal_w(offs_t offset, uint32_t data, uint32_t mem_
}
}
}
-
break;
- // Memory refresh
+ // Memory refresh
case RTCSR:
m_m[RTCSR] &= 255;
if ((old >> 3) & 7)
m_m[RTCNT] = compute_ticks_refresh_timer(m_refresh_timer, m_bus_clock, m_refresh_timer_base, rtcnt_div[(old >> 3) & 7]) & 0xff;
if ((m_m[RTCSR] >> 3) & 7)
- { // activated
+ { // activated
sh4_refresh_timer_recompute();
}
else
@@ -808,7 +797,7 @@ void sh4_base_device::sh4_internal_w(offs_t offset, uint32_t data, uint32_t mem_
case RTCNT:
m_m[RTCNT] &= 255;
if ((m_m[RTCSR] >> 3) & 7)
- { // active
+ { // active
sh4_refresh_timer_recompute();
}
break;
@@ -816,7 +805,7 @@ void sh4_base_device::sh4_internal_w(offs_t offset, uint32_t data, uint32_t mem_
case RTCOR:
m_m[RTCOR] &= 255;
if ((m_m[RTCSR] >> 3) & 7)
- { // active
+ { // active
m_m[RTCNT] = compute_ticks_refresh_timer(m_refresh_timer, m_bus_clock, m_refresh_timer_base, rtcnt_div[(m_m[RTCSR] >> 3) & 7]) & 0xff;
sh4_refresh_timer_recompute();
}
@@ -826,7 +815,7 @@ void sh4_base_device::sh4_internal_w(offs_t offset, uint32_t data, uint32_t mem_
m_m[RFCR] &= 1023;
break;
- // RTC
+ // RTC
case RCR1:
if ((m_m[RCR1] & 8) && (~old & 8)) // 0 -> 1
m_m[RCR1] ^= 1;
@@ -846,11 +835,11 @@ void sh4_base_device::sh4_internal_w(offs_t offset, uint32_t data, uint32_t mem_
m_m[RSECCNT] = 0;
}
if ((m_m[RCR2] & 8) && (~old & 8))
- { // 0 -> 1
+ { // 0 -> 1
m_rtc_timer->adjust(attotime::from_hz(128));
}
- else if (~(m_m[RCR2]) & 8)
- { // 0
+ else if (~m_m[RCR2] & 8)
+ { // 0
m_rtc_timer->adjust(attotime::never);
}
break;
@@ -858,18 +847,18 @@ void sh4_base_device::sh4_internal_w(offs_t offset, uint32_t data, uint32_t mem_
/*********************************************************************************************************************
TMU (Timer Unit)
*********************************************************************************************************************/
- case SH4_TSTR_ADDR: sh4_handle_tstr_addr_w(data,mem_mask); break;
- case SH4_TCR0_ADDR: sh4_handle_tcr0_addr_w(data,mem_mask); break;
- case SH4_TCR1_ADDR: sh4_handle_tcr1_addr_w(data,mem_mask); break;
- case SH4_TCR2_ADDR: sh4_handle_tcr2_addr_w(data,mem_mask); break;
- case SH4_TCOR0_ADDR: sh4_handle_tcor0_addr_w(data,mem_mask); break;
- case SH4_TCNT0_ADDR: sh4_handle_tcnt0_addr_w(data,mem_mask); break;
- case SH4_TCOR1_ADDR: sh4_handle_tcor1_addr_w(data,mem_mask); break;
- case SH4_TCNT1_ADDR: sh4_handle_tcnt1_addr_w(data,mem_mask); break;
- case SH4_TCOR2_ADDR: sh4_handle_tcor2_addr_w(data,mem_mask); break;
- case SH4_TCNT2_ADDR: sh4_handle_tcnt2_addr_w(data,mem_mask); break;
- case SH4_TOCR_ADDR: sh4_handle_tocr_addr_w(data,mem_mask); break; // not supported
- case SH4_TCPR2_ADDR: sh4_handle_tcpr2_addr_w(data,mem_mask); break; // not supported
+ case SH4_TSTR_ADDR: sh4_handle_tstr_addr_w(data, mem_mask); break;
+ case SH4_TCR0_ADDR: sh4_handle_tcr0_addr_w(data, mem_mask); break;
+ case SH4_TCR1_ADDR: sh4_handle_tcr1_addr_w(data, mem_mask); break;
+ case SH4_TCR2_ADDR: sh4_handle_tcr2_addr_w(data, mem_mask); break;
+ case SH4_TCOR0_ADDR: sh4_handle_tcor0_addr_w(data, mem_mask); break;
+ case SH4_TCNT0_ADDR: sh4_handle_tcnt0_addr_w(data, mem_mask); break;
+ case SH4_TCOR1_ADDR: sh4_handle_tcor1_addr_w(data, mem_mask); break;
+ case SH4_TCNT1_ADDR: sh4_handle_tcnt1_addr_w(data, mem_mask); break;
+ case SH4_TCOR2_ADDR: sh4_handle_tcor2_addr_w(data, mem_mask); break;
+ case SH4_TCNT2_ADDR: sh4_handle_tcnt2_addr_w(data, mem_mask); break;
+ case SH4_TOCR_ADDR: sh4_handle_tocr_addr_w(data, mem_mask); break; // not supported
+ case SH4_TCPR2_ADDR: sh4_handle_tcpr2_addr_w(data, mem_mask); break; // not supported
/*********************************************************************************************************************
INTC (Interrupt Controller)
*********************************************************************************************************************/
@@ -904,23 +893,23 @@ void sh4_base_device::sh4_internal_w(offs_t offset, uint32_t data, uint32_t mem_
/*********************************************************************************************************************
DMAC (DMA Controller)
*********************************************************************************************************************/
- case SH4_SAR0_ADDR: sh4_handle_sar0_addr_w(data,mem_mask); break;
- case SH4_SAR1_ADDR: sh4_handle_sar1_addr_w(data,mem_mask); break;
- case SH4_SAR2_ADDR: sh4_handle_sar2_addr_w(data,mem_mask); break;
- case SH4_SAR3_ADDR: sh4_handle_sar3_addr_w(data,mem_mask); break;
- case SH4_DAR0_ADDR: sh4_handle_dar0_addr_w(data,mem_mask); break;
- case SH4_DAR1_ADDR: sh4_handle_dar1_addr_w(data,mem_mask); break;
- case SH4_DAR2_ADDR: sh4_handle_dar2_addr_w(data,mem_mask); break;
- case SH4_DAR3_ADDR: sh4_handle_dar3_addr_w(data,mem_mask); break;
- case SH4_DMATCR0_ADDR: sh4_handle_dmatcr0_addr_w(data,mem_mask); break;
- case SH4_DMATCR1_ADDR: sh4_handle_dmatcr1_addr_w(data,mem_mask); break;
- case SH4_DMATCR2_ADDR: sh4_handle_dmatcr2_addr_w(data,mem_mask); break;
- case SH4_DMATCR3_ADDR: sh4_handle_dmatcr3_addr_w(data,mem_mask); break;
- case SH4_CHCR0_ADDR: sh4_handle_chcr0_addr_w(data,mem_mask); break;
- case SH4_CHCR1_ADDR: sh4_handle_chcr1_addr_w(data,mem_mask); break;
- case SH4_CHCR2_ADDR: sh4_handle_chcr2_addr_w(data,mem_mask); break;
- case SH4_CHCR3_ADDR: sh4_handle_chcr3_addr_w(data,mem_mask); break;
- case SH4_DMAOR_ADDR: sh4_handle_dmaor_addr_w(data,mem_mask); break;
+ case SH4_SAR0_ADDR: sh4_handle_sar0_addr_w(data, mem_mask); break;
+ case SH4_SAR1_ADDR: sh4_handle_sar1_addr_w(data, mem_mask); break;
+ case SH4_SAR2_ADDR: sh4_handle_sar2_addr_w(data, mem_mask); break;
+ case SH4_SAR3_ADDR: sh4_handle_sar3_addr_w(data, mem_mask); break;
+ case SH4_DAR0_ADDR: sh4_handle_dar0_addr_w(data, mem_mask); break;
+ case SH4_DAR1_ADDR: sh4_handle_dar1_addr_w(data, mem_mask); break;
+ case SH4_DAR2_ADDR: sh4_handle_dar2_addr_w(data, mem_mask); break;
+ case SH4_DAR3_ADDR: sh4_handle_dar3_addr_w(data, mem_mask); break;
+ case SH4_DMATCR0_ADDR: sh4_handle_dmatcr0_addr_w(data, mem_mask); break;
+ case SH4_DMATCR1_ADDR: sh4_handle_dmatcr1_addr_w(data, mem_mask); break;
+ case SH4_DMATCR2_ADDR: sh4_handle_dmatcr2_addr_w(data, mem_mask); break;
+ case SH4_DMATCR3_ADDR: sh4_handle_dmatcr3_addr_w(data, mem_mask); break;
+ case SH4_CHCR0_ADDR: sh4_handle_chcr0_addr_w(data, mem_mask); break;
+ case SH4_CHCR1_ADDR: sh4_handle_chcr1_addr_w(data, mem_mask); break;
+ case SH4_CHCR2_ADDR: sh4_handle_chcr2_addr_w(data, mem_mask); break;
+ case SH4_CHCR3_ADDR: sh4_handle_chcr3_addr_w(data, mem_mask); break;
+ case SH4_DMAOR_ADDR: sh4_handle_dmaor_addr_w(data, mem_mask); break;
/*********************************************************************************************************************
Store Queues
*********************************************************************************************************************/
@@ -933,9 +922,10 @@ void sh4_base_device::sh4_internal_w(offs_t offset, uint32_t data, uint32_t mem_
case PCTRA:
m_ioport16_pullup = 0;
m_ioport16_direction = 0;
- for (a=0;a < 16;a++) {
- m_ioport16_direction |= (m_m[PCTRA] & (1 << (a*2))) >> a;
- m_ioport16_pullup |= (m_m[PCTRA] & (1 << (a*2+1))) >> (a+1);
+ for (int a = 0; a < 16; a++)
+ {
+ m_ioport16_direction |= (m_m[PCTRA] & (1 << (a * 2))) >> a;
+ m_ioport16_pullup |= (m_m[PCTRA] & (1 << (a * 2 + 1))) >> (a + 1);
}
m_ioport16_direction &= 0xffff;
m_ioport16_pullup = (m_ioport16_pullup | m_ioport16_direction) ^ 0xffff;
@@ -949,9 +939,10 @@ void sh4_base_device::sh4_internal_w(offs_t offset, uint32_t data, uint32_t mem_
case PCTRB:
m_ioport4_pullup = 0;
m_ioport4_direction = 0;
- for (a=0;a < 4;a++) {
- m_ioport4_direction |= (m_m[PCTRB] & (1 << (a*2))) >> a;
- m_ioport4_pullup |= (m_m[PCTRB] & (1 << (a*2+1))) >> (a+1);
+ for (int a = 0; a < 4; a++)
+ {
+ m_ioport4_direction |= (m_m[PCTRB] & (1 << (a * 2))) >> a;
+ m_ioport4_pullup |= (m_m[PCTRB] & (1 << (a * 2 + 1))) >> (a + 1);
}
m_ioport4_direction &= 0xf;
m_ioport4_pullup = (m_ioport4_pullup | m_ioport4_direction) ^ 0xf;
@@ -985,7 +976,7 @@ uint32_t sh4_base_device::sh4_internal_r(offs_t offset, uint32_t mem_mask)
// printf("sh4_internal_r: Read %08x (%x) @ %08x\n", 0xfe000000+((offset & 0x3fc0) << 11)+((offset & 0x3f) << 2), offset, mem_mask);
- switch( offset )
+ switch (offset)
{
case VERSION:
return PVR_SH7091; // 0x040205c1, this is what a real SH7091 in a Dreamcast returns - the later Naomi BIOSes check and care!
@@ -1070,7 +1061,8 @@ void sh34_base_device::set_frt_input(int state)
if (m_cpu_type != CPU_TYPE_SH4)
fatalerror("sh4_set_frt_input uses m_m[] with SH3\n");
- if(m_sh2_state->m_frt_input == state) {
+ if (m_sh2_state->m_frt_input == state)
+ {
return;
}
@@ -1078,12 +1070,17 @@ void sh34_base_device::set_frt_input(int state)
if (m_cpu_type == CPU_TYPE_SH4)
{
- if(m_m[5] & 0x8000) {
- if(state == CLEAR_LINE) {
+ if (m_m[5] & 0x8000)
+ {
+ if (state == CLEAR_LINE)
+ {
return;
}
- } else {
- if(state == ASSERT_LINE) {
+ }
+ else
+ {
+ if (state == ASSERT_LINE)
+ {
return;
}
}
@@ -1129,15 +1126,15 @@ void sh34_base_device::execute_set_input(int irqline, int state) // set state of
return;
m_irq_line_state[irqline] = state;
- if( state == CLEAR_LINE )
+ if (state == CLEAR_LINE)
{
- LOG(("SH-4 '%s' cleared external irq IRL%d\n", tag(), irqline));
- sh4_exception_unrequest(SH4_INTC_IRL0+irqline-SH4_IRL0);
+ LOG("SH-4 '%s' cleared external irq IRL%d\n", tag(), irqline);
+ sh4_exception_unrequest(SH4_INTC_IRL0 + irqline - SH4_IRL0);
}
else
{
- LOG(("SH-4 '%s' assert external irq IRL%d\n", tag(), irqline));
- sh4_exception_request(SH4_INTC_IRL0+irqline-SH4_IRL0);
+ LOG("SH-4 '%s' assert external irq IRL%d\n", tag(), irqline);
+ sh4_exception_request(SH4_INTC_IRL0 + irqline - SH4_IRL0);
}
}
@@ -1146,26 +1143,25 @@ void sh34_base_device::execute_set_input(int irqline, int state) // set state of
}
else
{
- int s;
-
if (irqline == INPUT_LINE_NMI)
{
if (m_nmi_line_state == state)
return;
+
if (m_m[ICR] & 0x100)
{
- if ((state == CLEAR_LINE) && (m_nmi_line_state == ASSERT_LINE)) // rising
+ if (state == CLEAR_LINE && m_nmi_line_state == ASSERT_LINE) // rising
{
- LOG(("SH-4 '%s' assert nmi\n", tag()));
+ LOG("SH-4 '%s' assert nmi\n", tag());
sh4_exception_request(SH4_INTC_NMI);
sh4_dmac_nmi();
}
}
else
{
- if ((state == ASSERT_LINE) && (m_nmi_line_state == CLEAR_LINE)) // falling
+ if (state == ASSERT_LINE && m_nmi_line_state == CLEAR_LINE) // falling
{
- LOG(("SH-4 '%s' assert nmi\n", tag()));
+ LOG("SH-4 '%s' assert nmi\n", tag());
sh4_exception_request(SH4_INTC_NMI);
sh4_dmac_nmi();
}
@@ -1186,40 +1182,40 @@ void sh34_base_device::execute_set_input(int irqline, int state) // set state of
return;
m_irq_line_state[irqline] = state;
- if( state == CLEAR_LINE )
+ if (state == CLEAR_LINE)
{
- LOG(("SH-4 '%s' cleared external irq IRL%d\n", tag(), irqline));
- sh4_exception_unrequest(SH4_INTC_IRL0+irqline-SH4_IRL0);
+ LOG("SH-4 '%s' cleared external irq IRL%d\n", tag(), irqline);
+ sh4_exception_unrequest(SH4_INTC_IRL0 + irqline - SH4_IRL0);
}
else
{
- LOG(("SH-4 '%s' assert external irq IRL%d\n", tag(), irqline));
- sh4_exception_request(SH4_INTC_IRL0+irqline-SH4_IRL0);
+ LOG("SH-4 '%s' assert external irq IRL%d\n", tag(), irqline);
+ sh4_exception_request(SH4_INTC_IRL0 + irqline - SH4_IRL0);
}
}
else // level-encoded interrupt
{
if (irqline != SH4_IRLn)
return;
- if ((m_irln > 15) || (m_irln < 0))
+ if (m_irln > 15 || m_irln < 0)
return;
- for (s = 0; s < 15; s++)
- sh4_exception_unrequest(SH4_INTC_IRLn0+s);
+ for (int s = 0; s < 15; s++)
+ sh4_exception_unrequest(SH4_INTC_IRLn0 + s);
if (m_irln < 15)
- sh4_exception_request(SH4_INTC_IRLn0+m_irln);
- LOG(("SH-4 '%s' IRLn0-IRLn3 level #%d\n", tag(), m_irln));
+ sh4_exception_request(SH4_INTC_IRLn0 + m_irln);
+ LOG("SH-4 '%s' IRLn0-IRLn3 level #%d\n", tag(), m_irln);
}
}
- if (m_sh2_state->m_test_irq && (!m_sh2_state->m_delay))
+ if (m_sh2_state->m_test_irq && !m_sh2_state->m_delay)
sh4_check_pending_irq("sh4_set_irq_line");
}
}
void sh34_base_device::sh4_parse_configuration()
{
- if(m_clock > 0)
+ if (m_clock > 0)
{
- switch((m_md[2] << 2) | (m_md[1] << 1) | (m_md[0]))
+ switch ((m_md[2] << 2) | (m_md[1] << 1) | (m_md[0]))
{
case 0:
m_cpu_clock = m_clock;
@@ -1252,7 +1248,7 @@ void sh34_base_device::sh4_parse_configuration()
m_pm_clock = m_clock / 4;
break;
}
- m_is_slave = (~(m_md[7])) & 1;
+ m_is_slave = (~m_md[7]) & 1;
}
else
{
@@ -1274,10 +1270,9 @@ uint32_t sh4_base_device::get_remap(uint32_t address)
return address;
// is this the correct way around?
- int i;
uint32_t topaddr = address&0xfff00000;
- for (i=0;i<64;i++)
+ for (int i = 0; i < 64; i++)
{
if (m_utlb[i].V)
{
@@ -1288,8 +1283,6 @@ uint32_t sh4_base_device::get_remap(uint32_t address)
}
//printf("address not in UTLB? %08x\n", address);
-
-
return address;
}
@@ -1300,18 +1293,17 @@ uint32_t sh34_base_device::sh4_getsqremap(uint32_t address)
uint32_t sh4_base_device::sh4_getsqremap(uint32_t address)
{
- if (!m_sh4_mmu_enabled || (m_mmuhack != 1))
+ if (!m_sh4_mmu_enabled || m_mmuhack != 1)
return address;
else
{
- int i;
- uint32_t topaddr = address&0xfff00000;
+ uint32_t topaddr = address & 0xfff00000;
- for (i=0;i<64;i++)
+ for (int i = 0; i < 64; i++)
{
- uint32_t topcmp = (m_utlb[i].VPN<<10)&0xfff00000;
- if (topcmp==topaddr)
- return (address&0x000fffff) | ((m_utlb[i].PPN<<10)&0xfff00000);
+ uint32_t topcmp = (m_utlb[i].VPN << 10) & 0xfff00000;
+ if (topcmp == topaddr)
+ return (address & 0x000fffff) | ((m_utlb[i].PPN << 10) & 0xfff00000);
}
}
@@ -1333,16 +1325,13 @@ void sh4_base_device::sh4_utlb_address_array_w(offs_t offset, uint64_t data)
A = ASID = Address Space Identifier
*/
- logerror("sh4_utlb_address_array_w %08x %08x\n", offset, data);
- int offs = offset << 3;
-
- uint8_t associative = (offs >> 7) & 1;
+ LOG("sh4_utlb_address_array_w %08x %08x\n", offset, data);
+ const bool associative = BIT(offset, 4);
if (!associative)
{
// non-associative mode
- uint8_t i = (offs >> 8) & 63;
-
+ uint8_t i = (offset >> 5) & 63;
m_utlb[i].VPN = (data & 0xfffffc00) >> 10;
m_utlb[i].D = (data & 0x00000200) >> 9;
m_utlb[i].V = (data & 0x00000100) >> 8;
@@ -1358,13 +1347,8 @@ void sh4_base_device::sh4_utlb_address_array_w(offs_t offset, uint64_t data)
uint64_t sh4_base_device::sh4_utlb_address_array_r(offs_t offset)
{
// associative bit is ignored for reads
- int offs = offset*8;
-
- uint32_t ret = 0;
-
- uint8_t i = (offs >> 8) & 63;
-
- ret |= m_utlb[i].VPN << 10;
+ uint8_t i = (offset >> 5) & 63;
+ uint32_t ret = m_utlb[i].VPN << 10;
ret |= m_utlb[i].D << 9;
ret |= m_utlb[i].V << 8;
ret |= m_utlb[i].ASID << 0;
@@ -1389,11 +1373,8 @@ void sh4_base_device::sh4_utlb_data_array1_w(offs_t offset, uint64_t data)
W = Write through
- = unused (should be 0)
*/
- logerror("sh4_utlb_data_array1_w %08x %08x\n", offset, data);
- int offs = offset*8;
-
- uint8_t i = (offs>>8)&63;
-
+ LOG("sh4_utlb_data_array1_w %08x %08x\n", offset, data);
+ uint8_t i = (offset >> 5) & 63;
m_utlb[i].PPN = (data & 0x1ffffc00) >> 10;
m_utlb[i].V = (data & 0x00000100) >> 8;
m_utlb[i].PSZ = (data & 0x00000080) >> 6;
@@ -1408,12 +1389,8 @@ void sh4_base_device::sh4_utlb_data_array1_w(offs_t offset, uint64_t data)
uint64_t sh4_base_device::sh4_utlb_data_array1_r(offs_t offset)
{
- uint32_t ret = 0;
- int offs = offset*8;
-
- uint8_t i = (offs>>8)&63;
-
- ret |= m_utlb[i].PPN << 10;
+ uint8_t i = (offset >> 5) & 63;
+ uint32_t ret = m_utlb[i].PPN << 10;
ret |= m_utlb[i].V << 8;
ret |= (m_utlb[i].PSZ & 2) << 6;
ret |= (m_utlb[i].PSZ & 1) << 4;
@@ -1439,12 +1416,8 @@ void sh4_base_device::sh4_utlb_data_array2_w(offs_t offset, uint64_t data)
- = unused (should be 0)
*/
-
- logerror("sh4_utlb_data_array2_w %08x %08x\n", offset, data);
- int offs = offset*8;
-
- uint8_t i = (offs>>8)&63;
-
+ LOG("sh4_utlb_data_array2_w %08x %08x\n", offset, data);
+ uint8_t i = (offset >> 5) & 63;
m_utlb[i].TC = (data & 0x00000008) >> 3;
m_utlb[i].SA = (data & 0x00000007) >> 0;
}
@@ -1452,13 +1425,6 @@ void sh4_base_device::sh4_utlb_data_array2_w(offs_t offset, uint64_t data)
uint64_t sh4_base_device::sh4_utlb_data_array2_r(offs_t offset)
{
- uint32_t ret = 0;
- int offs = offset*8;
-
- uint8_t i = (offs>>8)&63;
-
- ret |= m_utlb[i].TC << 3;
- ret |= m_utlb[i].SA << 0;
-
- return ret;
+ uint8_t i = (offset >> 5) & 63;
+ return (m_utlb[i].TC << 3) | (m_utlb[i].SA);
}
diff --git a/src/devices/cpu/sh/sh4comn.h b/src/devices/cpu/sh/sh4comn.h
index 0d856012581..5f02378ed9f 100644
--- a/src/devices/cpu/sh/sh4comn.h
+++ b/src/devices/cpu/sh/sh4comn.h
@@ -15,25 +15,24 @@
#include "sh.h"
-#define VERBOSE 0
+#define VERBOSE (0)
+#include "logmacro.h"
-#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
-
-#define EXPPRI(pl,po,p,n) (((4-(pl)) << 24) | ((15-(po)) << 16) | ((p) << 8) | (255-(n)))
-#define NMIPRI() EXPPRI(3,0,16,SH4_INTC_NMI)
-#define INTPRI(p,n) EXPPRI(4,2,p,n)
+#define EXPPRI(pl, po, p, n) (((4 - (pl)) << 24) | ((15 - (po)) << 16) | ((p) << 8) | (255 - (n)))
+#define NMIPRI() EXPPRI(3, 0, 16, SH4_INTC_NMI)
+#define INTPRI(p, n) EXPPRI(4, 2, p, n)
#define FP_RS(r) m_sh2_state->m_fr[(r)] // binary representation of single precision floating point register r
-#define FP_RFS(r) *( (float *)(m_sh2_state->m_fr+(r)) ) // single precision floating point register r
-#define FP_RFD(r) *( (double *)(m_sh2_state->m_fr+(r)) ) // double precision floating point register r
+#define FP_RFS(r) *( (float *)(m_sh2_state->m_fr + (r)) ) // single precision floating point register r
+#define FP_RFD(r) *( (double *)(m_sh2_state->m_fr + (r)) ) // double precision floating point register r
#define FP_XS(r) m_sh2_state->m_xf[(r)] // binary representation of extended single precision floating point register r
-#define FP_XFS(r) *( (float *)(m_sh2_state->m_xf+(r)) ) // single precision extended floating point register r
-#define FP_XFD(r) *( (double *)(m_sh2_state->m_xf+(r)) ) // double precision extended floating point register r
+#define FP_XFS(r) *( (float *)(m_sh2_state->m_xf + (r)) ) // single precision extended floating point register r
+#define FP_XFD(r) *( (double *)(m_sh2_state->m_xf + (r)) ) // double precision extended floating point register r
#ifdef LSB_FIRST
#define FP_RS2(r) m_sh2_state->m_fr[(r) ^ m_sh2_state->m_fpu_pr]
-#define FP_RFS2(r) *( (float *)(m_sh2_state->m_fr+((r) ^ m_sh2_state->m_fpu_pr)) )
+#define FP_RFS2(r) *( (float *)(m_sh2_state->m_fr + ((r) ^ m_sh2_state->m_fpu_pr)) )
#define FP_XS2(r) m_sh2_state->m_xf[(r) ^ m_sh2_state->m_fpu_pr]
-#define FP_XFS2(r) *( (float *)(m_sh2_state->m_xf+((r) ^ m_sh2_state->m_fpu_pr)) )
+#define FP_XFS2(r) *( (float *)(m_sh2_state->m_xf + ((r) ^ m_sh2_state->m_fpu_pr)) )
#endif
#define FPSCR mem(&m_sh2_state->m_fpscr)
@@ -55,7 +54,7 @@ enum
/* 29 bits */
#define SH34_AM 0x1fffffff
-#define SH34_FLAGS (MD|sRB|BL|FD|SH_M|SH_Q|SH_I|SH_S|SH_T)
+#define SH34_FLAGS (MD | sRB | BL | FD | SH_M | SH_Q | SH_I | SH_S | SH_T)
/* Bits in FPSCR */
#define RM 0x00000003
diff --git a/src/devices/cpu/sh/sh4dmac.cpp b/src/devices/cpu/sh/sh4dmac.cpp
index ae18202ab73..51607032f64 100644
--- a/src/devices/cpu/sh/sh4dmac.cpp
+++ b/src/devices/cpu/sh/sh4dmac.cpp
@@ -16,7 +16,7 @@ TIMER_CALLBACK_MEMBER( sh34_base_device::sh4_dmac_callback )
{
int channel = param;
- LOG(("SH4 '%s': DMA %d complete\n", tag(), channel));
+ LOG("SH4 '%s': DMA %d complete\n", tag(), channel);
m_dma_timer_active[channel] = 0;
switch (channel)
{
@@ -49,12 +49,10 @@ TIMER_CALLBACK_MEMBER( sh34_base_device::sh4_dmac_callback )
int sh34_base_device::sh4_dma_transfer(int channel, int timermode, uint32_t chcr, uint32_t *sar, uint32_t *dar, uint32_t *dmatcr)
{
- int incs, incd, size;
- uint32_t src, dst, count;
-
- incd = (chcr & CHCR_DM) >> 14;
- incs = (chcr & CHCR_SM) >> 12;
+ int incd = (chcr & CHCR_DM) >> 14;
+ int incs = (chcr & CHCR_SM) >> 12;
+ int size;
if (m_cpu_type == CPU_TYPE_SH4)
{
size = dmasize[(chcr & CHCR_TS) >> 4];
@@ -64,18 +62,19 @@ int sh34_base_device::sh4_dma_transfer(int channel, int timermode, uint32_t chcr
size = sh3_dmasize[(chcr >> 3) & 3];
}
- if(incd == 3 || incs == 3)
+ if (incd == 3 || incs == 3)
{
logerror("SH4: DMA: bad increment values (%d, %d, %d, %04x)\n", incd, incs, size, chcr);
return 0;
}
- src = *sar;
- dst = *dar;
- count = *dmatcr;
+
+ uint32_t src = *sar;
+ uint32_t dst = *dar;
+ uint32_t count = *dmatcr;
if (!count)
count = 0x1000000;
- LOG(("SH4: DMA %d start %x, %x, %x, %04x, %d, %d, %d\n", channel, src, dst, count, chcr, incs, incd, size));
+ LOG("SH4: DMA %d start %x, %x, %x, %04x, %d, %d, %d\n", channel, src, dst, count, chcr, incs, incd, size);
if (timermode == 1) // timer actvated after a time based on the number of words to transfer
{
@@ -91,51 +90,51 @@ int sh34_base_device::sh4_dma_transfer(int channel, int timermode, uint32_t chcr
src &= SH34_AM;
dst &= SH34_AM;
- switch(size)
+ switch (size)
{
case 1: // 8 bit
- for(;count > 0; count --)
+ for (;count > 0; count --)
{
- if(incs == 2)
+ if (incs == 2)
src --;
- if(incd == 2)
+ if (incd == 2)
dst --;
m_program->write_byte(dst, m_program->read_byte(src));
- if(incs == 1)
+ if (incs == 1)
src ++;
- if(incd == 1)
+ if (incd == 1)
dst ++;
}
break;
case 2: // 16 bit
src &= ~1;
dst &= ~1;
- for(;count > 0; count --)
+ for (;count > 0; count --)
{
- if(incs == 2)
+ if (incs == 2)
src -= 2;
- if(incd == 2)
+ if (incd == 2)
dst -= 2;
m_program->write_word(dst, m_program->read_word(src));
- if(incs == 1)
+ if (incs == 1)
src += 2;
- if(incd == 1)
+ if (incd == 1)
dst += 2;
}
break;
case 8: // 64 bit
src &= ~7;
dst &= ~7;
- for(;count > 0; count --)
+ for (;count > 0; count --)
{
- if(incs == 2)
+ if (incs == 2)
src -= 8;
- if(incd == 2)
+ if (incd == 2)
dst -= 8;
m_program->write_qword(dst, m_program->read_qword(src));
- if(incs == 1)
+ if (incs == 1)
src += 8;
- if(incd == 1)
+ if (incd == 1)
dst += 8;
}
@@ -143,16 +142,16 @@ int sh34_base_device::sh4_dma_transfer(int channel, int timermode, uint32_t chcr
case 4: // 32 bit
src &= ~3;
dst &= ~3;
- for(;count > 0; count --)
+ for (;count > 0; count --)
{
- if(incs == 2)
+ if (incs == 2)
src -= 4;
- if(incd == 2)
+ if (incd == 2)
dst -= 4;
m_program->write_dword(dst, m_program->read_dword(src));
- if(incs == 1)
+ if (incs == 1)
src += 4;
- if(incd == 1)
+ if (incd == 1)
dst += 4;
}
@@ -160,19 +159,19 @@ int sh34_base_device::sh4_dma_transfer(int channel, int timermode, uint32_t chcr
case 32:
src &= ~31;
dst &= ~31;
- for(;count > 0; count --)
+ for (;count > 0; count --)
{
- if(incs == 2)
+ if (incs == 2)
src -= 32;
- if(incd == 2)
+ if (incd == 2)
dst -= 32;
m_program->write_qword(dst, m_program->read_qword(src));
- m_program->write_qword(dst+8, m_program->read_qword(src+8));
- m_program->write_qword(dst+16, m_program->read_qword(src+16));
- m_program->write_qword(dst+24, m_program->read_qword(src+24));
- if(incs == 1)
+ m_program->write_qword(dst + 8, m_program->read_qword(src + 8));
+ m_program->write_qword(dst + 16, m_program->read_qword(src + 16));
+ m_program->write_qword(dst + 24, m_program->read_qword(src + 24));
+ if (incs == 1)
src += 32;
- if(incd == 1)
+ if (incd == 1)
dst += 32;
}
break;
@@ -185,13 +184,10 @@ int sh34_base_device::sh4_dma_transfer(int channel, int timermode, uint32_t chcr
int sh34_base_device::sh4_dma_transfer_device(int channel, uint32_t chcr, uint32_t *sar, uint32_t *dar, uint32_t *dmatcr)
{
- int incs, incd, size, mod;
- uint32_t src, dst, count;
-
- incd = (chcr & CHCR_DM) >> 14;
- incs = (chcr & CHCR_SM) >> 12;
-
+ int incd = (chcr & CHCR_DM) >> 14;
+ int incs = (chcr & CHCR_SM) >> 12;
+ int size;
if (m_cpu_type == CPU_TYPE_SH4)
{
size = dmasize[(chcr & CHCR_TS) >> 4];
@@ -201,19 +197,20 @@ int sh34_base_device::sh4_dma_transfer_device(int channel, uint32_t chcr, uint32
size = sh3_dmasize[(chcr >> 3) & 3];
}
- mod = ((chcr & CHCR_RS) >> 8);
+ int mod = ((chcr & CHCR_RS) >> 8);
if (incd == 3 || incs == 3)
{
logerror("SH4: DMA: bad increment values (%d, %d, %d, %04x)\n", incd, incs, size, chcr);
return 0;
}
- src = *sar;
- dst = *dar;
- count = *dmatcr;
+
+ uint32_t src = *sar;
+ uint32_t dst = *dar;
+ uint32_t count = *dmatcr;
if (!count)
count = 0x1000000;
- LOG(("SH4: DMA %d start device<->memory %x, %x, %x, %04x, %d, %d, %d\n", channel, src, dst, count, chcr, incs, incd, size));
+ LOG("SH4: DMA %d start device<->memory %x, %x, %x, %04x, %d, %d, %d\n", channel, src, dst, count, chcr, incs, incd, size);
m_dma_timer_active[channel] = 1;
@@ -294,7 +291,6 @@ void sh34_base_device::sh4_dmac_check(int channel)
// called by drivers to transfer data in a cpu<->device dma. 'device' must be a SH4 cpu
int sh34_base_device::sh4_dma_data(struct sh4_device_dma *s)
{
- uint32_t pos, len, siz;
int channel = s->channel;
void *data = s->buffer;
@@ -304,11 +300,12 @@ int sh34_base_device::sh4_dma_data(struct sh4_device_dma *s)
if (m_dma_mode[channel] == 2)
{
// device receives data
- len = m_dma_count[channel];
+ uint32_t len = m_dma_count[channel];
if (s->length < len)
len = s->length;
- siz = m_dma_wordsize[channel];
- for (pos = 0;pos < len;pos++) {
+ uint32_t siz = m_dma_wordsize[channel];
+ for (uint32_t pos = 0; pos < len; pos++)
+ {
switch (siz)
{
case 8:
@@ -362,11 +359,12 @@ int sh34_base_device::sh4_dma_data(struct sh4_device_dma *s)
else if (m_dma_mode[channel] == 3)
{
// device sends data
- len = m_dma_count[channel];
+ uint32_t len = m_dma_count[channel];
if (s->length < len)
len = s->length;
- siz = m_dma_wordsize[channel];
- for (pos = 0;pos < len;pos++) {
+ uint32_t siz = m_dma_wordsize[channel];
+ for (uint32_t pos = 0; pos < len; pos++)
+ {
switch (siz)
{
case 8:
@@ -425,17 +423,13 @@ int sh34_base_device::sh4_dma_data(struct sh4_device_dma *s)
// called by drivers to transfer data in a DDT dma.
void sh34_base_device::sh4_dma_ddt(struct sh4_ddt_dma *s)
{
- uint32_t chcr;
- uint32_t *p32bits;
- uint64_t *p32bytes;
- uint32_t pos,len,siz;
-
if (m_cpu_type != CPU_TYPE_SH4)
fatalerror("sh4_dma_ddt uses m_m[] with SH3\n");
if (m_dma_timer_active[s->channel])
return;
- if (s->mode >= 0) {
+ if (s->mode >= 0)
+ {
switch (s->channel)
{
case 0:
@@ -480,6 +474,8 @@ void sh34_base_device::sh4_dma_ddt(struct sh4_ddt_dma *s)
m_SH4_DAR3 = s->destination;
break;
}
+ uint32_t len;
+ uint32_t chcr;
switch (s->channel)
{
case 0:
@@ -500,13 +496,13 @@ void sh34_base_device::sh4_dma_ddt(struct sh4_ddt_dma *s)
len = m_SH4_DMATCR3;
break;
}
- if ((s->direction) == 0) {
+
+ if (s->direction == 0)
chcr = (chcr & 0xffff3fff) | ((s->mode & 0x30) << 10);
- } else {
+ else
chcr = (chcr & 0xffffcfff) | ((s->mode & 0x30) << 8);
- }
-
+ uint32_t siz = 0;
if (m_cpu_type == CPU_TYPE_SH4)
{
//siz = dmasize[(chcr & CHCR_TS) >> 4];
@@ -518,43 +514,51 @@ void sh34_base_device::sh4_dma_ddt(struct sh4_ddt_dma *s)
}
- if (siz && (s->size))
- if ((len * siz) != (s->length * s->size))
+ if (siz && s->size)
+ if (len * siz != s->length * s->size)
return;
sh4_dma_transfer(s->channel, 0, chcr, &s->source, &s->destination, &len);
- } else {
- if (s->size == 4) {
- if ((s->direction) == 0) {
- len = s->length;
- p32bits = (uint32_t *)(s->buffer);
- for (pos = 0;pos < len;pos++) {
- *p32bits = m_program->read_dword(s->source);
- p32bits++;
+ }
+ else
+ {
+ if (s->size == 4)
+ {
+ if ((s->direction) == 0)
+ {
+ uint32_t *p32bits = (uint32_t *)s->buffer;
+ for (uint32_t pos = 0; pos < s->length; pos++)
+ {
+ *p32bits++ = m_program->read_dword(s->source);
s->source = s->source + 4;
}
- } else {
- len = s->length;
- p32bits = (uint32_t *)(s->buffer);
- for (pos = 0;pos < len;pos++) {
+ }
+ else
+ {
+ uint32_t *p32bits = (uint32_t *)s->buffer;
+ for (uint32_t pos = 0; pos < s->length; pos++)
+ {
m_program->write_dword(s->destination, *p32bits);
p32bits++;
s->destination = s->destination + 4;
}
}
}
- if (s->size == 32) {
- if ((s->direction) == 0) {
- len = s->length * 4;
- p32bytes = (uint64_t *)(s->buffer);
- for (pos = 0;pos < len;pos++) {
- *p32bytes = m_program->read_qword(s->source);
- p32bytes++;
+ if (s->size == 32)
+ {
+ if ((s->direction) == 0)
+ {
+ uint64_t *p32bytes = (uint64_t *)s->buffer;
+ for (uint32_t pos = 0; pos < s->length * 4; pos++)
+ {
+ *p32bytes++ = m_program->read_qword(s->source);
s->destination = s->destination + 8;
}
- } else {
- len = s->length * 4;
- p32bytes = (uint64_t *)(s->buffer);
- for (pos = 0;pos < len;pos++) {
+ }
+ else
+ {
+ uint64_t *p32bytes = (uint64_t *)s->buffer;
+ for (uint32_t pos = 0; pos < s->length * 4; pos++)
+ {
m_program->write_qword(s->destination, *p32bytes);
p32bytes++;
s->destination = s->destination + 8;
diff --git a/src/devices/cpu/sh/sh4fe.cpp b/src/devices/cpu/sh/sh4fe.cpp
index 0f88f98b9ae..61941b7ec26 100644
--- a/src/devices/cpu/sh/sh4fe.cpp
+++ b/src/devices/cpu/sh/sh4fe.cpp
@@ -2,7 +2,7 @@
// copyright-holders:R. Belmont, David Haywood
/***************************************************************************
- sh4fe.c
+ sh4fe.cpp
Front end for SH-4 recompiler
@@ -291,8 +291,10 @@ bool sh4_frontend::describe_op1111_0x13(opcode_desc &desc, const opcode_desc *pr
bool sh4_frontend::describe_op1111_0xf13(opcode_desc &desc, const opcode_desc *prev, uint16_t opcode)
{
- if (opcode & 0x100) {
- if (opcode & 0x200) {
+ if (opcode & 0x100)
+ {
+ if (opcode & 0x200)
+ {
switch (opcode & 0xC00)
{
case 0x000:
@@ -306,11 +308,13 @@ bool sh4_frontend::describe_op1111_0xf13(opcode_desc &desc, const opcode_desc *p
break;
}
}
- else {
+ else
+ {
return true; // FTRV(opcode);
}
}
- else {
+ else
+ {
return true; // FSSCA(opcode);
}
return false;
diff --git a/src/devices/cpu/sh/sh7021.cpp b/src/devices/cpu/sh/sh7021.cpp
index 458e4ff7aac..6b61621cb5c 100644
--- a/src/devices/cpu/sh/sh7021.cpp
+++ b/src/devices/cpu/sh/sh7021.cpp
@@ -1,164 +1,2243 @@
// license:BSD-3-Clause
-// copyright-holders:Angelo Salese
+// copyright-holders:Ryan Holtz
+/*****************************************************************************
+ *
+ * sh7021.cpp
+ * Portable Hitachi SH-1 (model SH7021) emulator
+ *
+ *****************************************************************************/
#include "emu.h"
#include "sh7021.h"
+#include "sh_dasm.h"
-DEFINE_DEVICE_TYPE(SH2A_SH7021, sh2a_sh7021_device, "sh2a_sh7021", "Hitachi SH-2A (SH7021)")
+#define LOG_INTC_RD (1u << 1)
+#define LOG_INTC_WR (1u << 2)
+#define LOG_UBC_RD (1u << 3)
+#define LOG_UBC_WR (1u << 4)
+#define LOG_BSC_RD (1u << 5)
+#define LOG_BSC_WR (1u << 6)
+#define LOG_DMA_RD (1u << 7)
+#define LOG_DMA_WR (1u << 8)
+#define LOG_ITU_RD (1u << 9)
+#define LOG_ITU_WR (1u << 10)
+#define LOG_TPC_RD (1u << 11)
+#define LOG_TPC_WR (1u << 12)
+#define LOG_WDT_RD (1u << 13)
+#define LOG_WDT_WR (1u << 14)
+#define LOG_SCI_RD (1u << 15)
+#define LOG_SCI_WR (1u << 16)
+#define LOG_PFC_RD (1u << 17)
+#define LOG_PFC_WR (1u << 18)
+#define LOG_INTC (LOG_INTC_RD | LOG_INTC_WR)
+#define LOG_UBC (LOG_UBC_RD | LOG_UBC_WR)
+#define LOG_BSC (LOG_BSC_RD | LOG_BSC_WR)
+#define LOG_DMA (LOG_DMA_RD | LOG_DMA_WR)
+#define LOG_ITU (LOG_ITU_RD | LOG_ITU_WR)
+#define LOG_TPC (LOG_TPC_RD | LOG_TPC_WR)
+#define LOG_WDT (LOG_WDT_RD | LOG_WDT_WR)
+#define LOG_SCI (LOG_SCI_RD | LOG_SCI_WR)
+#define LOG_PFC (LOG_PFC_RD | LOG_PFC_WR)
+#define LOG_ALL (LOG_INTC | LOG_UBC | LOG_BSC | LOG_DMA | LOG_ITU | LOG_TPC | LOG_WDT | LOG_SCI | LOG_PFC)
+#define VERBOSE (0)
+#include "logmacro.h"
-sh2a_sh7021_device::sh2a_sh7021_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : sh2_device(mconfig, SH2A_SH7021, tag, owner, clock, CPU_TYPE_SH2, address_map_constructor(FUNC(sh2a_sh7021_device::sh7021_map), this), 28, 0xc7ffffff)
+
+DEFINE_DEVICE_TYPE(SH7021, sh7021_device, "sh7021", "Hitachi SH7021")
+
+/*-------------------------------------------------
+ internal_map - maps SH7021 built-ins
+-------------------------------------------------*/
+
+void sh7021_device::internal_map(address_map &map)
{
+ map(0x00000000, 0x00007fff).rom().region(DEVICE_SELF, 0).mirror(0x00ff8000); // 32KB internal ROM
+
+ map(0x05fffec0, 0x05fffec0).rw(FUNC(sh7021_device::sci_smr_r<0>), FUNC(sh7021_device::sci_smr_w<0>));
+ map(0x05fffec1, 0x05fffec1).rw(FUNC(sh7021_device::sci_brr_r<0>), FUNC(sh7021_device::sci_brr_w<0>));
+ map(0x05fffec2, 0x05fffec2).rw(FUNC(sh7021_device::sci_scr_r<0>), FUNC(sh7021_device::sci_scr_w<0>));
+ map(0x05fffec3, 0x05fffec3).rw(FUNC(sh7021_device::sci_tdr_r<0>), FUNC(sh7021_device::sci_tdr_w<0>));
+ map(0x05fffec4, 0x05fffec4).rw(FUNC(sh7021_device::sci_ssr_r<0>), FUNC(sh7021_device::sci_ssr_w<0>));
+ map(0x05fffec5, 0x05fffec5).r(FUNC(sh7021_device::sci_rdr_r<0>));
+ map(0x05fffec8, 0x05fffec8).rw(FUNC(sh7021_device::sci_smr_r<1>), FUNC(sh7021_device::sci_smr_w<1>));
+ map(0x05fffec9, 0x05fffec9).rw(FUNC(sh7021_device::sci_brr_r<1>), FUNC(sh7021_device::sci_brr_w<1>));
+ map(0x05fffeca, 0x05fffeca).rw(FUNC(sh7021_device::sci_scr_r<1>), FUNC(sh7021_device::sci_scr_w<1>));
+ map(0x05fffecb, 0x05fffecb).rw(FUNC(sh7021_device::sci_tdr_r<1>), FUNC(sh7021_device::sci_tdr_w<1>));
+ map(0x05fffecc, 0x05fffecc).rw(FUNC(sh7021_device::sci_ssr_r<1>), FUNC(sh7021_device::sci_ssr_w<1>));
+ map(0x05fffecd, 0x05fffecd).r(FUNC(sh7021_device::sci_rdr_r<1>));
+
+ map(0x05ffff00, 0x05ffff00).rw(FUNC(sh7021_device::itu_tstr_r), FUNC(sh7021_device::itu_tstr_w));
+ map(0x05ffff01, 0x05ffff01).rw(FUNC(sh7021_device::itu_tsnc_r), FUNC(sh7021_device::itu_tsnc_w));
+ map(0x05ffff02, 0x05ffff02).rw(FUNC(sh7021_device::itu_tmdr_r), FUNC(sh7021_device::itu_tmdr_w));
+ map(0x05ffff03, 0x05ffff03).rw(FUNC(sh7021_device::itu_tfcr_r), FUNC(sh7021_device::itu_tfcr_w));
+ map(0x05ffff31, 0x05ffff31).rw(FUNC(sh7021_device::itu_tocr_r), FUNC(sh7021_device::itu_tocr_w));
+
+ map(0x05ffff04, 0x05ffff04).rw(FUNC(sh7021_device::itu_tcr_r<0>), FUNC(sh7021_device::itu_tcr_w<0>));
+ map(0x05ffff05, 0x05ffff05).rw(FUNC(sh7021_device::itu_tior_r<0>), FUNC(sh7021_device::itu_tior_w<0>));
+ map(0x05ffff06, 0x05ffff06).rw(FUNC(sh7021_device::itu_tier_r<0>), FUNC(sh7021_device::itu_tier_w<0>));
+ map(0x05ffff07, 0x05ffff07).rw(FUNC(sh7021_device::itu_tsr_r<0>), FUNC(sh7021_device::itu_tsr_w<0>));
+ map(0x05ffff08, 0x05ffff09).rw(FUNC(sh7021_device::itu_tcnt_r<0>), FUNC(sh7021_device::itu_tcnt_w<0>));
+ map(0x05ffff0a, 0x05ffff0b).rw(FUNC(sh7021_device::itu_gra_r<0>), FUNC(sh7021_device::itu_gra_w<0>));
+ map(0x05ffff0c, 0x05ffff0d).rw(FUNC(sh7021_device::itu_grb_r<0>), FUNC(sh7021_device::itu_grb_w<0>));
+
+ map(0x05ffff0e, 0x05ffff0e).rw(FUNC(sh7021_device::itu_tcr_r<1>), FUNC(sh7021_device::itu_tcr_w<1>));
+ map(0x05ffff0f, 0x05ffff0f).rw(FUNC(sh7021_device::itu_tior_r<1>), FUNC(sh7021_device::itu_tior_w<1>));
+ map(0x05ffff10, 0x05ffff10).rw(FUNC(sh7021_device::itu_tier_r<1>), FUNC(sh7021_device::itu_tier_w<1>));
+ map(0x05ffff11, 0x05ffff11).rw(FUNC(sh7021_device::itu_tsr_r<1>), FUNC(sh7021_device::itu_tsr_w<1>));
+ map(0x05ffff12, 0x05ffff13).rw(FUNC(sh7021_device::itu_tcnt_r<1>), FUNC(sh7021_device::itu_tcnt_w<1>));
+ map(0x05ffff14, 0x05ffff15).rw(FUNC(sh7021_device::itu_gra_r<1>), FUNC(sh7021_device::itu_gra_w<1>));
+ map(0x05ffff16, 0x05ffff17).rw(FUNC(sh7021_device::itu_grb_r<1>), FUNC(sh7021_device::itu_grb_w<1>));
+
+ map(0x05ffff18, 0x05ffff18).rw(FUNC(sh7021_device::itu_tcr_r<2>), FUNC(sh7021_device::itu_tcr_w<2>));
+ map(0x05ffff19, 0x05ffff19).rw(FUNC(sh7021_device::itu_tior_r<2>), FUNC(sh7021_device::itu_tior_w<2>));
+ map(0x05ffff1a, 0x05ffff1a).rw(FUNC(sh7021_device::itu_tier_r<2>), FUNC(sh7021_device::itu_tier_w<2>));
+ map(0x05ffff1b, 0x05ffff1b).rw(FUNC(sh7021_device::itu_tsr_r<2>), FUNC(sh7021_device::itu_tsr_w<2>));
+ map(0x05ffff1c, 0x05ffff1d).rw(FUNC(sh7021_device::itu_tcnt_r<2>), FUNC(sh7021_device::itu_tcnt_w<2>));
+ map(0x05ffff1e, 0x05ffff1f).rw(FUNC(sh7021_device::itu_gra_r<2>), FUNC(sh7021_device::itu_gra_w<2>));
+ map(0x05ffff20, 0x05ffff21).rw(FUNC(sh7021_device::itu_grb_r<2>), FUNC(sh7021_device::itu_grb_w<2>));
+
+ map(0x05ffff22, 0x05ffff22).rw(FUNC(sh7021_device::itu_tcr_r<3>), FUNC(sh7021_device::itu_tcr_w<3>));
+ map(0x05ffff23, 0x05ffff23).rw(FUNC(sh7021_device::itu_tior_r<3>), FUNC(sh7021_device::itu_tior_w<3>));
+ map(0x05ffff24, 0x05ffff24).rw(FUNC(sh7021_device::itu_tier_r<3>), FUNC(sh7021_device::itu_tier_w<3>));
+ map(0x05ffff25, 0x05ffff25).rw(FUNC(sh7021_device::itu_tsr_r<3>), FUNC(sh7021_device::itu_tsr_w<3>));
+ map(0x05ffff26, 0x05ffff27).rw(FUNC(sh7021_device::itu_tcnt_r<3>), FUNC(sh7021_device::itu_tcnt_w<3>));
+ map(0x05ffff28, 0x05ffff29).rw(FUNC(sh7021_device::itu_gra_r<3>), FUNC(sh7021_device::itu_gra_w<3>));
+ map(0x05ffff2a, 0x05ffff2b).rw(FUNC(sh7021_device::itu_grb_r<3>), FUNC(sh7021_device::itu_grb_w<3>));
+ map(0x05ffff2c, 0x05ffff2d).rw(FUNC(sh7021_device::itu_bra_r<3>), FUNC(sh7021_device::itu_bra_w<3>));
+ map(0x05ffff2e, 0x05ffff2f).rw(FUNC(sh7021_device::itu_brb_r<3>), FUNC(sh7021_device::itu_brb_w<3>));
+
+ map(0x05ffff32, 0x05ffff32).rw(FUNC(sh7021_device::itu_tcr_r<4>), FUNC(sh7021_device::itu_tcr_w<4>));
+ map(0x05ffff33, 0x05ffff33).rw(FUNC(sh7021_device::itu_tior_r<4>), FUNC(sh7021_device::itu_tior_w<4>));
+ map(0x05ffff34, 0x05ffff34).rw(FUNC(sh7021_device::itu_tier_r<4>), FUNC(sh7021_device::itu_tier_w<4>));
+ map(0x05ffff35, 0x05ffff35).rw(FUNC(sh7021_device::itu_tsr_r<4>), FUNC(sh7021_device::itu_tsr_w<4>));
+ map(0x05ffff36, 0x05ffff37).rw(FUNC(sh7021_device::itu_tcnt_r<4>), FUNC(sh7021_device::itu_tcnt_w<4>));
+ map(0x05ffff38, 0x05ffff39).rw(FUNC(sh7021_device::itu_gra_r<4>), FUNC(sh7021_device::itu_gra_w<4>));
+ map(0x05ffff3a, 0x05ffff3b).rw(FUNC(sh7021_device::itu_grb_r<4>), FUNC(sh7021_device::itu_grb_w<4>));
+ map(0x05ffff3c, 0x05ffff3d).rw(FUNC(sh7021_device::itu_bra_r<4>), FUNC(sh7021_device::itu_bra_w<4>));
+ map(0x05ffff3e, 0x05ffff3f).rw(FUNC(sh7021_device::itu_brb_r<4>), FUNC(sh7021_device::itu_brb_w<4>));
+
+ map(0x05ffff40, 0x05ffff43).rw(FUNC(sh7021_device::dma_sar_r<0>), FUNC(sh7021_device::dma_sar_w<0>));
+ map(0x05ffff44, 0x05ffff47).rw(FUNC(sh7021_device::dma_dar_r<0>), FUNC(sh7021_device::dma_dar_w<0>));
+ map(0x05ffff48, 0x05ffff49).rw(FUNC(sh7021_device::dmaor_r), FUNC(sh7021_device::dmaor_w));
+ map(0x05ffff4a, 0x05ffff4b).rw(FUNC(sh7021_device::dma_tcr_r<0>), FUNC(sh7021_device::dma_tcr_w<0>));
+ map(0x05ffff4e, 0x05ffff4f).rw(FUNC(sh7021_device::dma_chcr_r<0>), FUNC(sh7021_device::dma_chcr_w<0>));
+
+ map(0x05ffff50, 0x05ffff53).rw(FUNC(sh7021_device::dma_sar_r<1>), FUNC(sh7021_device::dma_sar_w<1>));
+ map(0x05ffff54, 0x05ffff57).rw(FUNC(sh7021_device::dma_dar_r<1>), FUNC(sh7021_device::dma_dar_w<1>));
+ map(0x05ffff5a, 0x05ffff5b).rw(FUNC(sh7021_device::dma_tcr_r<1>), FUNC(sh7021_device::dma_tcr_w<1>));
+ map(0x05ffff5e, 0x05ffff5f).rw(FUNC(sh7021_device::dma_chcr_r<1>), FUNC(sh7021_device::dma_chcr_w<1>));
+
+ map(0x05ffff60, 0x05ffff63).rw(FUNC(sh7021_device::dma_sar_r<2>), FUNC(sh7021_device::dma_sar_w<2>));
+ map(0x05ffff64, 0x05ffff67).rw(FUNC(sh7021_device::dma_dar_r<2>), FUNC(sh7021_device::dma_dar_w<2>));
+ map(0x05ffff6a, 0x05ffff6b).rw(FUNC(sh7021_device::dma_tcr_r<2>), FUNC(sh7021_device::dma_tcr_w<2>));
+ map(0x05ffff6e, 0x05ffff6f).rw(FUNC(sh7021_device::dma_chcr_r<2>), FUNC(sh7021_device::dma_chcr_w<2>));
+
+ map(0x05ffff70, 0x05ffff73).rw(FUNC(sh7021_device::dma_sar_r<3>), FUNC(sh7021_device::dma_sar_w<3>));
+ map(0x05ffff74, 0x05ffff77).rw(FUNC(sh7021_device::dma_dar_r<3>), FUNC(sh7021_device::dma_dar_w<3>));
+ map(0x05ffff7a, 0x05ffff7b).rw(FUNC(sh7021_device::dma_tcr_r<3>), FUNC(sh7021_device::dma_tcr_w<3>));
+ map(0x05ffff7e, 0x05ffff7f).rw(FUNC(sh7021_device::dma_chcr_r<3>), FUNC(sh7021_device::dma_chcr_w<3>));
+
+ map(0x05ffff84, 0x05ffff85).rw(FUNC(sh7021_device::intc_ipra_r), FUNC(sh7021_device::intc_ipra_w));
+ map(0x05ffff86, 0x05ffff87).rw(FUNC(sh7021_device::intc_iprb_r), FUNC(sh7021_device::intc_iprb_w));
+ map(0x05ffff88, 0x05ffff89).rw(FUNC(sh7021_device::intc_iprc_r), FUNC(sh7021_device::intc_iprc_w));
+ map(0x05ffff8a, 0x05ffff8b).rw(FUNC(sh7021_device::intc_iprd_r), FUNC(sh7021_device::intc_iprd_w));
+ map(0x05ffff8c, 0x05ffff8d).rw(FUNC(sh7021_device::intc_ipre_r), FUNC(sh7021_device::intc_ipre_w));
+ map(0x05ffff8e, 0x05ffff8f).rw(FUNC(sh7021_device::intc_icr_r), FUNC(sh7021_device::intc_icr_w));
+
+ map(0x05ffff90, 0x05ffff91).rw(FUNC(sh7021_device::ubc_barh_r), FUNC(sh7021_device::ubc_barh_w));
+ map(0x05ffff92, 0x05ffff93).rw(FUNC(sh7021_device::ubc_barl_r), FUNC(sh7021_device::ubc_barl_w));
+ map(0x05ffff94, 0x05ffff95).rw(FUNC(sh7021_device::ubc_bamrh_r), FUNC(sh7021_device::ubc_bamrh_w));
+ map(0x05ffff96, 0x05ffff97).rw(FUNC(sh7021_device::ubc_bamrl_r), FUNC(sh7021_device::ubc_bamrl_w));
+ map(0x05ffff98, 0x05ffff99).rw(FUNC(sh7021_device::ubc_bbr_r), FUNC(sh7021_device::ubc_bbr_w));
+
+ map(0x05ffffa0, 0x05ffffa1).rw(FUNC(sh7021_device::bsc_bcr_r), FUNC(sh7021_device::bsc_bcr_w));
+ map(0x05ffffa2, 0x05ffffa3).rw(FUNC(sh7021_device::bsc_wcr1_r), FUNC(sh7021_device::bsc_wcr1_w));
+ map(0x05ffffa4, 0x05ffffa5).rw(FUNC(sh7021_device::bsc_wcr2_r), FUNC(sh7021_device::bsc_wcr2_w));
+ map(0x05ffffa6, 0x05ffffa7).rw(FUNC(sh7021_device::bsc_wcr3_r), FUNC(sh7021_device::bsc_wcr3_w));
+ map(0x05ffffa8, 0x05ffffa9).rw(FUNC(sh7021_device::bsc_dcr_r), FUNC(sh7021_device::bsc_dcr_w));
+ map(0x05ffffaa, 0x05ffffab).rw(FUNC(sh7021_device::bsc_pcr_r), FUNC(sh7021_device::bsc_pcr_w));
+ map(0x05ffffac, 0x05ffffad).rw(FUNC(sh7021_device::bsc_rcr_r), FUNC(sh7021_device::bsc_rcr_w));
+ map(0x05ffffae, 0x05ffffaf).rw(FUNC(sh7021_device::bsc_rtcsr_r), FUNC(sh7021_device::bsc_rtcsr_w));
+ map(0x05ffffb0, 0x05ffffb1).rw(FUNC(sh7021_device::bsc_rtcnt_r), FUNC(sh7021_device::bsc_rtcnt_w));
+ map(0x05ffffb2, 0x05ffffb3).rw(FUNC(sh7021_device::bsc_rtcor_r), FUNC(sh7021_device::bsc_rtcor_w));
+
+ map(0x05ffffb8, 0x05ffffb8).rw(FUNC(sh7021_device::wdt_tcsr_r), FUNC(sh7021_device::wdt_tcsr_w));
+ map(0x05ffffb9, 0x05ffffb9).rw(FUNC(sh7021_device::wdt_tcnt_r), FUNC(sh7021_device::wdt_tcnt_w));
+ map(0x05ffffba, 0x05ffffba).rw(FUNC(sh7021_device::wdt_rstcsr_r), FUNC(sh7021_device::wdt_rstcsr_w));
+
+ map(0x05ffffc0, 0x05ffffc1).rw(FUNC(sh7021_device::pfc_padr_r), FUNC(sh7021_device::pfc_padr_w));
+ map(0x05ffffc2, 0x05ffffc3).rw(FUNC(sh7021_device::pfc_pbdr_r), FUNC(sh7021_device::pfc_pbdr_w));
+ map(0x05ffffc4, 0x05ffffc5).rw(FUNC(sh7021_device::pfc_paior_r), FUNC(sh7021_device::pfc_paior_w));
+ map(0x05ffffc6, 0x05ffffc7).rw(FUNC(sh7021_device::pfc_pbior_r), FUNC(sh7021_device::pfc_pbior_w));
+ map(0x05ffffc8, 0x05ffffc9).rw(FUNC(sh7021_device::pfc_pacr1_r), FUNC(sh7021_device::pfc_pacr1_w));
+ map(0x05ffffca, 0x05ffffcb).rw(FUNC(sh7021_device::pfc_pacr2_r), FUNC(sh7021_device::pfc_pacr2_w));
+ map(0x05ffffcc, 0x05ffffcd).rw(FUNC(sh7021_device::pfc_pbcr1_r), FUNC(sh7021_device::pfc_pbcr1_w));
+ map(0x05ffffce, 0x05ffffcf).rw(FUNC(sh7021_device::pfc_pbcr2_r), FUNC(sh7021_device::pfc_pbcr2_w));
+
+ map(0x05fffff0, 0x05fffff0).rw(FUNC(sh7021_device::tpc_tpmr_r), FUNC(sh7021_device::tpc_tpmr_w));
+ map(0x05fffff1, 0x05fffff1).rw(FUNC(sh7021_device::tpc_tpcr_r), FUNC(sh7021_device::tpc_tpcr_w));
+ map(0x05fffff2, 0x05fffff2).rw(FUNC(sh7021_device::tpc_ndera_r), FUNC(sh7021_device::tpc_ndera_w));
+ map(0x05fffff3, 0x05fffff3).rw(FUNC(sh7021_device::tpc_nderb_r), FUNC(sh7021_device::tpc_nderb_w));
+ map(0x05fffff4, 0x05fffff4).rw(FUNC(sh7021_device::tpc_ndrb_r), FUNC(sh7021_device::tpc_ndrb_w));
+ map(0x05fffff5, 0x05fffff5).rw(FUNC(sh7021_device::tpc_ndra_r), FUNC(sh7021_device::tpc_ndra_w));
+ map(0x05fffff6, 0x05fffff6).rw(FUNC(sh7021_device::tpc_ndrb_alt_r), FUNC(sh7021_device::tpc_ndrb_alt_w));
+ map(0x05fffff7, 0x05fffff7).rw(FUNC(sh7021_device::tpc_ndra_alt_r), FUNC(sh7021_device::tpc_ndra_alt_w));
+
+ map(0x07000000, 0x070003ff).ram().mirror(0x00fffc00); // 1KB internal RAM, actually at 0xf000000
}
-void sh2a_sh7021_device::device_start()
+sh7021_device::sh7021_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+ : sh2_device(mconfig, SH7021, tag, owner, clock, CPU_TYPE_SH2, address_map_constructor(FUNC(sh7021_device::internal_map), this), 28, 0xc7ffffff)
+ , m_pa_out(*this)
+ , m_pb_out(*this)
+ , m_pa_bit_out(*this)
+ , m_pb_bit_out(*this)
+{
+ m_isdrc = false; // FIXME
+}
+
+void sh7021_device::execute_run()
+{
+ int consumed_cycles = 0;
+ do
+ {
+ int icount_before = m_sh2_state->icount;
+ debugger_instruction_hook(m_sh2_state->pc);
+
+ const uint16_t opcode = decrypted_read_word(m_sh2_state->pc >= 0x40000000 ? m_sh2_state->pc : m_sh2_state->pc & m_am);
+
+ if (m_sh2_state->m_delay)
+ {
+ m_sh2_state->pc = m_sh2_state->m_delay;
+ m_sh2_state->m_delay = 0;
+ }
+ else
+ m_sh2_state->pc += 2;
+
+ execute_peripherals(consumed_cycles);
+ execute_one(opcode);
+
+ if (m_test_irq && !m_sh2_state->m_delay)
+ {
+ check_pending_irq("mame_sh2_execute");
+ m_test_irq = 0;
+ }
+ m_sh2_state->icount--;
+ consumed_cycles = icount_before - m_sh2_state->icount;
+ } while (m_sh2_state->icount > 0);
+}
+
+void sh7021_device::device_start()
{
sh2_device::device_start();
- save_item(NAME(m_sh7021_regs));
- save_item(NAME(m_dmaor));
+ m_itu.timer[0].et = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(sh7021_device::sh7021_timer_callback<0>), this));
+ m_itu.timer[1].et = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(sh7021_device::sh7021_timer_callback<1>), this));
+ m_itu.timer[2].et = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(sh7021_device::sh7021_timer_callback<2>), this));
+ m_itu.timer[3].et = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(sh7021_device::sh7021_timer_callback<3>), this));
+ m_itu.timer[4].et = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(sh7021_device::sh7021_timer_callback<4>), this));
+
+ for (uint32_t i = 0; i < 5; ++i)
+ {
+ m_itu.timer[i].et->adjust(attotime::never);
+ }
+
+ m_sci[0].et = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(sh7021_device::sh7021_sci_callback<0>), this));
+ m_sci[1].et = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(sh7021_device::sh7021_sci_callback<1>), this));
+
+ for (uint32_t i = 0; i < 2; ++i)
+ {
+ m_sci[i].et->adjust(attotime::never);
+ }
+
+ // Interrupt Controller (INTC)
+ save_item(NAME(m_iprc));
+ save_item(NAME(m_iprd));
+ save_item(NAME(m_ipre));
+ save_item(NAME(m_icr));
+
+ // User Break Controller (UBC)
+ save_item(STRUCT_MEMBER(m_ubc, barh));
+ save_item(STRUCT_MEMBER(m_ubc, barl));
+ save_item(STRUCT_MEMBER(m_ubc, bamrh));
+ save_item(STRUCT_MEMBER(m_ubc, bamrl));
+ save_item(STRUCT_MEMBER(m_ubc, bbr));
+
+ // Bus State Controller (BSC)
+ save_item(STRUCT_MEMBER(m_bsc, bcr));
+ save_item(STRUCT_MEMBER(m_bsc, wcr1));
+ save_item(STRUCT_MEMBER(m_bsc, wcr2));
+ save_item(STRUCT_MEMBER(m_bsc, wcr3));
+ save_item(STRUCT_MEMBER(m_bsc, dcr));
+ save_item(STRUCT_MEMBER(m_bsc, pcr));
+ save_item(STRUCT_MEMBER(m_bsc, rcr));
+ save_item(STRUCT_MEMBER(m_bsc, rtcsr));
+ save_item(STRUCT_MEMBER(m_bsc, rtcsr_read));
+ save_item(STRUCT_MEMBER(m_bsc, rtcnt));
+ save_item(STRUCT_MEMBER(m_bsc, rtcor));
+
+ // DMA Controller (DMAC)
save_item(STRUCT_MEMBER(m_dma, sar));
save_item(STRUCT_MEMBER(m_dma, dar));
save_item(STRUCT_MEMBER(m_dma, tcr));
save_item(STRUCT_MEMBER(m_dma, chcr));
+ save_item(NAME(m_dma_cycles));
+
+ // 16-Bit Integrated-Timer Pulse Unit (ITU)
+ save_item(STRUCT_MEMBER(m_itu, tstr));
+ save_item(STRUCT_MEMBER(m_itu, tsnc));
+ save_item(STRUCT_MEMBER(m_itu, tmdr));
+ save_item(STRUCT_MEMBER(m_itu, tfcr));
+ save_item(STRUCT_MEMBER(m_itu, tocr));
+ save_item(STRUCT_MEMBER(m_itu.timer, tcr));
+ save_item(STRUCT_MEMBER(m_itu.timer, tior));
+ save_item(STRUCT_MEMBER(m_itu.timer, tier));
+ save_item(STRUCT_MEMBER(m_itu.timer, tsr));
+ save_item(STRUCT_MEMBER(m_itu.timer, tcnt));
+ save_item(STRUCT_MEMBER(m_itu.timer, gra));
+ save_item(STRUCT_MEMBER(m_itu.timer, grb));
+ save_item(STRUCT_MEMBER(m_itu.timer, bra));
+ save_item(STRUCT_MEMBER(m_itu.timer, brb));
+
+ // Programmable Timing Pattern Controller (TPC)
+ save_item(STRUCT_MEMBER(m_tpc, tpmr));
+ save_item(STRUCT_MEMBER(m_tpc, tpcr));
+ save_item(STRUCT_MEMBER(m_tpc, ndera));
+ save_item(STRUCT_MEMBER(m_tpc, nderb));
+ save_item(STRUCT_MEMBER(m_tpc, ndra));
+ save_item(STRUCT_MEMBER(m_tpc, ndrb));
+
+ // Watchdog Timer (WDT)
+ save_item(STRUCT_MEMBER(m_wdt, tcsr));
+ save_item(STRUCT_MEMBER(m_wdt, tcnt));
+ save_item(STRUCT_MEMBER(m_wdt, rstcsr));
+
+ // Serial Communication Interface (SCI)
+ save_item(STRUCT_MEMBER(m_sci, smr));
+ save_item(STRUCT_MEMBER(m_sci, brr));
+ save_item(STRUCT_MEMBER(m_sci, scr));
+ save_item(STRUCT_MEMBER(m_sci, tsr));
+ save_item(STRUCT_MEMBER(m_sci, tdr));
+ save_item(STRUCT_MEMBER(m_sci, ssr));
+ save_item(STRUCT_MEMBER(m_sci, ssr_read));
+ save_item(STRUCT_MEMBER(m_sci, rsr));
+ save_item(STRUCT_MEMBER(m_sci, rdr));
+
+ // Pin Function Controller (PFC)
+ save_item(STRUCT_MEMBER(m_pfc, paior));
+ save_item(STRUCT_MEMBER(m_pfc, pacr1));
+ save_item(STRUCT_MEMBER(m_pfc, pacr2));
+ save_item(STRUCT_MEMBER(m_pfc, pbior));
+ save_item(STRUCT_MEMBER(m_pfc, pbcr1));
+ save_item(STRUCT_MEMBER(m_pfc, pbcr2));
+ save_item(STRUCT_MEMBER(m_pfc, padr));
+ save_item(STRUCT_MEMBER(m_pfc, pbdr));
+ save_item(STRUCT_MEMBER(m_pfc, padr_in));
+ save_item(STRUCT_MEMBER(m_pfc, pbdr_in));
+ save_item(STRUCT_MEMBER(m_pfc, cascr));
+ save_item(STRUCT_MEMBER(m_pfc, pafunc));
+ save_item(STRUCT_MEMBER(m_pfc, pbfunc));
+ save_item(STRUCT_MEMBER(m_pfc, pa_gpio_mask));
+ save_item(STRUCT_MEMBER(m_pfc, pb_gpio_mask));
}
-void sh2a_sh7021_device::device_reset()
+void sh7021_device::device_reset()
{
sh2_device::device_reset();
- std::fill(std::begin(m_sh7021_regs), std::end(m_sh7021_regs), 0);
+ // Interrupt Controller (INTC)
+ m_ipra = 0;
+ m_iprb = 0;
+ m_iprc = 0;
+ m_iprd = 0;
+ m_ipre = 0;
+ m_icr = 0;
- m_dmaor = 0;
+ // User Break Controller (UBC)
+ m_ubc.barh = 0;
+ m_ubc.barl = 0;
+ m_ubc.bamrh = 0;
+ m_ubc.bamrl = 0;
+ m_ubc.bbr = 0;
- for(int i = 0; i < 4; i++)
+ // Bus State Controller (BSC)
+ m_bsc.bcr = 0;
+ m_bsc.wcr1 = 0xffff;
+ m_bsc.wcr2 = 0xffff;
+ m_bsc.wcr3 = 0xf800;
+ m_bsc.dcr = 0;
+ m_bsc.pcr = 0;
+ m_bsc.rcr = 0;
+ m_bsc.rtcsr = 0;
+ m_bsc.rtcsr_read = false;
+ m_bsc.rtcnt = 0;
+ m_bsc.rtcor = 0x00ff;
+
+ // DMA Controller (DMAC)
+ for (uint32_t i = 0; i < 4; i++)
{
m_dma[i].sar = 0;
m_dma[i].dar = 0;
m_dma[i].tcr = 0;
m_dma[i].chcr = 0;
}
+ m_dmaor = 0;
+ m_dma_cycles = 0;
+
+ // 16-Bit Integrated-Timer Pulse Unit (ITU)
+ m_itu.tstr = 0x60;
+ m_itu.tsnc = 0x60;
+ m_itu.tmdr = 0;
+ m_itu.tfcr = 0x40;
+ m_itu.tocr = 0x7f;
+ for (uint32_t i = 0; i < 5; i++)
+ {
+ m_itu.timer[i].tcr = 0;
+ m_itu.timer[i].tior = 0x08;
+ m_itu.timer[i].tier = 0xf8;
+ m_itu.timer[i].tsr = 0xf8;
+ m_itu.timer[i].tcnt = 0;
+ m_itu.timer[i].gra = 0xffff;
+ m_itu.timer[i].grb = 0xffff;
+ m_itu.timer[i].bra = 0xffff;
+ m_itu.timer[i].brb = 0xffff;
+ }
+
+ // Programmable Timing Pattern Controller (TPC)
+ m_tpc.tpmr = 0xf0;
+ m_tpc.tpcr = 0xff;
+ m_tpc.nderb = 0;
+ m_tpc.ndera = 0;
+ m_tpc.ndra = 0;
+ m_tpc.ndrb = 0;
+
+ // Watchdog Timer (WDT)
+ m_wdt.tcsr = 0x18;
+ m_wdt.tcnt = 0;
+ m_wdt.rstcsr = 0x3f;
+
+ // Serial Communication Interface (SCI)
+ for (uint32_t i = 0; i < 2; i++)
+ {
+ m_sci[i].smr = 0;
+ m_sci[i].brr = 0xff;
+ m_sci[i].scr = 0;
+ m_sci[i].tsr = 0;
+ m_sci[i].tdr = 0xff;
+ m_sci[i].ssr = 0x84;
+ m_sci[i].ssr_read = 0;
+ m_sci[i].rsr = 0;
+ m_sci[i].rdr = 0;
+ }
+
+ // Pin Function Controller (PFC)
+ m_pfc.paior = 0;
+ m_pfc.pacr1 = 0x3302;
+ m_pfc.pacr2 = 0xff95;
+ m_pfc.pbior = 0;
+ m_pfc.pbcr1 = 0;
+ m_pfc.pbcr2 = 0;
+ m_pfc.padr = 0;
+ m_pfc.pbdr = 0;
+ m_pfc.padr_in = 0;
+ m_pfc.pbdr_in = 0;
+ m_pfc.cascr = 0x5fff;
+ m_pfc.pa_gpio_mask = 0;
+ m_pfc.pb_gpio_mask = 0xffff;
+
+ static constexpr uint16_t PACR1_W_MASK = 0xfffd;
+ static constexpr uint16_t PACR2_W_MASK = 0x55ff;
+ for (int i = 0; i < 16; i++)
+ {
+ int bit = (i & 7) << 1;
+
+ uint16_t data = (i >= 8 ? (m_pfc.pacr1 & PACR1_W_MASK) : (m_pfc.pacr2 & PACR2_W_MASK));
+ uint8_t func = (data >> bit) & 3;
+ m_pfc.pafunc[i] = (data >> bit) & 3;
+ if (func == 0)
+ m_pfc.pa_gpio_mask |= 1 << i;
+ m_pfc.pbfunc[i] = 0;
+ }
}
-void sh2a_sh7021_device::sh7021_map(address_map &map)
+uint8_t sh7021_device::read_byte(offs_t offset)
{
-// fall-back
- map(0x05fffe00, 0x05ffffff).rw(FUNC(sh2a_sh7021_device::sh7021_r), FUNC(sh2a_sh7021_device::sh7021_w)); // SH-7032H internal i/o
-// overrides
- map(0x05ffff40, 0x05ffff43).rw(FUNC(sh2a_sh7021_device::dma_sar0_r), FUNC(sh2a_sh7021_device::dma_sar0_w));
- map(0x05ffff44, 0x05ffff47).rw(FUNC(sh2a_sh7021_device::dma_dar0_r), FUNC(sh2a_sh7021_device::dma_dar0_w));
- map(0x05ffff48, 0x05ffff49).rw(FUNC(sh2a_sh7021_device::dmaor_r), FUNC(sh2a_sh7021_device::dmaor_w));
- map(0x05ffff4a, 0x05ffff4b).rw(FUNC(sh2a_sh7021_device::dma_tcr0_r), FUNC(sh2a_sh7021_device::dma_tcr0_w));
- map(0x05ffff4e, 0x05ffff4f).rw(FUNC(sh2a_sh7021_device::dma_chcr0_r), FUNC(sh2a_sh7021_device::dma_chcr0_w));
-// map(0x07000000, 0x070003ff).ram().share("oram"); // on-chip RAM, actually at 0xf000000 (1 kb)
-// map(0x0f000000, 0x0f0003ff).ram().share("oram"); // on-chip RAM, actually at 0xf000000 (1 kb)
+ const uint32_t area = (offset >> 24) & 7;
+ if (area == 6)
+ m_sh2_state->icount -= ((m_bsc.wcr3 >> 11) & 3) + 1; // Consume cycles specified by A6LW
+ else if (area == 0 || area == 2)
+ m_sh2_state->icount -= ((m_bsc.wcr3 >> 13) & 3) + 1; // Consume cycles specified by A02LW
+
+ return m_program->read_byte(offset & m_am);
}
-void sh2a_sh7021_device::sh7021_dma_exec(int ch)
+uint16_t sh7021_device::read_word(offs_t offset)
{
- const short dma_word_size[4] = { 0, +1, -1, 0 };
- uint8_t rs = (m_dma[ch].chcr >> 8) & 0xf; /**< Resource Select bits */
- if(rs != 0xc) // Auto-Request
+ const uint32_t area = (offset >> 24) & 7;
+ if (area == 6)
+ m_sh2_state->icount -= ((m_bsc.wcr3 >> 11) & 3) + 1; // Consume cycles specified by A6LW
+ else if (area == 0 || area == 2)
+ m_sh2_state->icount -= ((m_bsc.wcr3 >> 13) & 3) + 1; // Consume cycles specified by A02LW
+
+ return m_program->read_word(offset & m_am);
+}
+
+uint32_t sh7021_device::read_long(offs_t offset)
+{
+ const uint32_t area = (offset >> 24) & 7;
+ if (area == 6)
+ m_sh2_state->icount -= ((m_bsc.wcr3 >> 11) & 3) + 1; // Consume cycles specified by A6LW
+ else if (area == 0 || area == 2)
+ m_sh2_state->icount -= ((m_bsc.wcr3 >> 13) & 3) + 1; // Consume cycles specified by A02LW
+
+ return m_program->read_dword(offset & m_am);
+}
+
+uint16_t sh7021_device::decrypted_read_word(offs_t offset)
+{
+ const uint32_t area = (offset >> 24) & 7;
+ if (area == 6)
+ m_sh2_state->icount -= ((m_bsc.wcr3 >> 11) & 3) + 1; // Consume cycles specified by A6LW
+ else if (area == 0 || area == 2)
+ m_sh2_state->icount -= ((m_bsc.wcr3 >> 13) & 3) + 1; // Consume cycles specified by A02LW
+
+ return m_decrypted_program->read_word(offset);
+}
+
+void sh7021_device::write_byte(offs_t offset, uint8_t data)
+{
+ const uint32_t area = (offset >> 24) & 7;
+ if (area == 6)
+ m_sh2_state->icount -= ((m_bsc.wcr3 >> 11) & 3) + 1; // Consume cycles specified by A6LW
+ else if (area == 0 || area == 2)
+ m_sh2_state->icount -= ((m_bsc.wcr3 >> 13) & 3) + 1; // Consume cycles specified by A02LW
+
+ m_program->write_byte(offset & m_am, data);
+}
+
+void sh7021_device::write_word(offs_t offset, uint16_t data)
+{
+ const uint32_t area = (offset >> 24) & 7;
+ if (area == 6)
+ m_sh2_state->icount -= ((m_bsc.wcr3 >> 11) & 3) + 1; // Consume cycles specified by A6LW
+ else if (area == 0 || area == 2)
+ m_sh2_state->icount -= ((m_bsc.wcr3 >> 13) & 3) + 1; // Consume cycles specified by A02LW
+
+ m_program->write_word(offset & m_am, data);
+}
+
+void sh7021_device::write_long(offs_t offset, uint32_t data)
+{
+ const uint32_t area = (offset >> 24) & 7;
+ if (area == 6)
+ m_sh2_state->icount -= ((m_bsc.wcr3 >> 11) & 3) + 1; // Consume cycles specified by A6LW
+ else if (area == 0 || area == 2)
+ m_sh2_state->icount -= ((m_bsc.wcr3 >> 13) & 3) + 1; // Consume cycles specified by A02LW
+
+ m_program->write_dword(offset & m_am, data);
+}
+
+void sh7021_device::recalc_irq()
+{
+ int irq = 0;
+ int vector = -1;
+
+ // Serial IRQs
+ for (uint32_t i = 0; i < 2; ++i)
+ {
+ int sci_level = (i == 1 ? ((m_ipre >> 12) & 0xf) : (m_iprd & 0xf));
+ if (sci_level == 0)
+ {
+ continue;
+ }
+
+ if (BIT(m_sci[i].scr, 7) && BIT(m_sci[i].ssr, 7))
+ {
+ // TxI
+ irq = sci_level;
+ vector = 102 + i * 4;
+ LOGMASKED(LOG_DMA_WR, "SCI Tx interrupt %d is ready, level %d vector %d\n", i, irq, vector);
+ }
+ else if (BIT(m_sci[i].scr, 2) && BIT(m_sci[i].ssr, 2))
+ {
+ // TEI
+ irq = sci_level;
+ vector = 103 + i * 4;
+ LOGMASKED(LOG_DMA_WR, "SCI TE interrupt %d is ready, level %d vector %d\n", i, irq, vector);
+ }
+ }
+
+ // Timer IRQs
+ for (uint32_t i = 0; i < 5; ++i)
+ {
+ if ((m_itu.timer[i].tier & m_itu.timer[i].tsr) & 7)
+ {
+ int level;
+
+ switch (i)
+ {
+ case 0:
+ level = (m_iprc >> 4) & 0xf;
+ break;
+ case 1:
+ level = (m_iprc >> 0) & 0xf;
+ break;
+ case 2:
+ level = (m_iprd >> 12) & 0xf;
+ break;
+ case 3:
+ level = (m_iprd >> 8) & 0xf;
+ break;
+ case 4:
+ level = (m_iprd >> 4) & 0xf;
+ break;
+ }
+
+ if (level == 0)
+ {
+ continue;
+ }
+
+ for (uint32_t j = 0; j < 3; j++)
+ {
+ if (BIT(m_itu.timer[i].tier & m_itu.timer[i].tsr, j))
+ {
+ irq = level;
+ vector = 80 + i * 4 + j;
+ break;
+ }
+ }
+ }
+ }
+
+ if (vector >= 0)
{
- logerror("Warning: SH7021 DMA enables non auto-request transfer\n");
+ m_sh2_state->internal_irq_level = irq;
+ m_internal_irq_vector = vector;
+ m_test_irq = 1;
+ }
+}
+
+
+// Interrupt Controller (INTC)
+
+uint16_t sh7021_device::intc_ipra_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_INTC_RD, "%s: intc_ipra_r: %04x\n", machine().describe_context(), m_ipra);
+ return m_ipra;
+}
+
+void sh7021_device::intc_ipra_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ LOGMASKED(LOG_INTC_WR, "%s: intc_ipra_w = %04x & %04x\n", machine().describe_context(), data, mem_mask);
+ COMBINE_DATA(&m_ipra);
+}
+
+uint16_t sh7021_device::intc_iprb_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_INTC_RD, "%s: intc_iprb_r: %04x\n", machine().describe_context(), m_iprb);
+ return m_iprb;
+}
+
+void sh7021_device::intc_iprb_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ LOGMASKED(LOG_INTC_WR, "%s: intc_iprb_w = %04x & %04x\n", machine().describe_context(), data, mem_mask);
+ COMBINE_DATA(&m_iprb);
+}
+
+uint16_t sh7021_device::intc_iprc_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_INTC_RD, "%s: intc_iprc_r: %04x\n", machine().describe_context(), m_iprc);
+ return m_iprc;
+}
+
+void sh7021_device::intc_iprc_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ LOGMASKED(LOG_INTC_WR, "%s: intc_iprc_w = %04x & %04x\n", machine().describe_context(), data, mem_mask);
+ COMBINE_DATA(&m_iprc);
+}
+
+uint16_t sh7021_device::intc_iprd_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_INTC_RD, "%s: intc_iprd_r: %04x\n", machine().describe_context(), m_iprd);
+ return m_iprd;
+}
+
+void sh7021_device::intc_iprd_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ LOGMASKED(LOG_INTC_WR, "%s: intc_iprd_w = %04x & %04x\n", machine().describe_context(), data, mem_mask);
+ COMBINE_DATA(&m_iprd);
+}
+
+uint16_t sh7021_device::intc_ipre_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_INTC_RD, "%s: intc_ipre_r: %04x\n", machine().describe_context(), m_ipre);
+ return m_ipre;
+}
+
+void sh7021_device::intc_ipre_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ LOGMASKED(LOG_INTC_WR, "%s: intc_ipre_w = %04x & %04x\n", machine().describe_context(), data, mem_mask);
+ COMBINE_DATA(&m_ipre);
+}
+
+uint16_t sh7021_device::intc_icr_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_INTC_RD, "%s: intc_icr_r: %04x\n", machine().describe_context(), m_ipre);
+ return m_icr;
+}
+
+void sh7021_device::intc_icr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ LOGMASKED(LOG_INTC_WR, "%s: intc_icr_w = %04x & %04x\n", machine().describe_context(), data, mem_mask);
+ COMBINE_DATA(&m_icr);
+}
+
+
+// User Break Controller (UBC)
+
+uint16_t sh7021_device::ubc_barh_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_UBC_RD, "%s: Break Address Register H, ubc_barh_r: %04x\n", machine().describe_context(), m_ubc.barh);
+ return m_ubc.barh;
+}
+
+void sh7021_device::ubc_barh_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ LOGMASKED(LOG_UBC_WR, "%s: Break Address Register H, ubc_barh_w = %04x\n", machine().describe_context(), data);
+ COMBINE_DATA(&m_ubc.barh);
+}
+
+uint16_t sh7021_device::ubc_barl_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_UBC_RD, "%s: Break Address Register L, ubc_barl_r: %04x\n", machine().describe_context(), m_ubc.barl);
+ return m_ubc.barl;
+}
+
+void sh7021_device::ubc_barl_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ LOGMASKED(LOG_UBC_WR, "%s: Break Address Register L, ubc_barl_w = %04x\n", machine().describe_context(), data);
+ COMBINE_DATA(&m_ubc.barl);
+}
+
+uint16_t sh7021_device::ubc_bamrh_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_UBC_RD, "%s: Break Address Mask Register H, ubc_bamrh_r: %04x\n", machine().describe_context(), m_ubc.bamrh);
+ return m_ubc.bamrh;
+}
+
+void sh7021_device::ubc_bamrh_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ LOGMASKED(LOG_UBC_WR, "%s: Break Address Mask Register H, ubc_bmarh_w = %04x\n", machine().describe_context(), data);
+ COMBINE_DATA(&m_ubc.bamrh);
+}
+
+uint16_t sh7021_device::ubc_bamrl_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_UBC_RD, "%s: Break Address Mask Register L, ubc_bamrl_r: %04x\n", machine().describe_context(), m_ubc.bamrl);
+ return m_ubc.bamrl;
+}
+
+void sh7021_device::ubc_bamrl_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ LOGMASKED(LOG_UBC_WR, "%s: Break Address Mask Register L, ubc_bmarl_w = %04x\n", machine().describe_context(), data);
+ COMBINE_DATA(&m_ubc.bamrl);
+}
+
+uint16_t sh7021_device::ubc_bbr_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_UBC_RD, "%s: Break Bus Cycle Register, ubc_bbr_r: %04x\n", machine().describe_context(), m_ubc.bbr);
+ return m_ubc.bbr;
+}
+
+void sh7021_device::ubc_bbr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ static const char *const CPU_DMA_NAMES[4] = { "No break", "Break on CPU cycles", "Break on DMA cycles", "Break on both CPU and DMA cycles" };
+ static const char *const INSN_DATA_NAMES[4] = { "No break", "Break on instruction fetch cycles", "Break on data access cycles", "Break on both instruction and data cycles" };
+ static const char *const READ_WRITE_NAMES[4] = { "No break", "Break on read cycles", "Break on write cycles", "Break on both read and write cycles" };
+ static const char *const SIZE_NAMES[4] = { "No break", "Break on byte access", "Break on word access", "Break on long word access" };
+ LOGMASKED(LOG_UBC_WR, "%s: Break Bus Cycle Register, ubc_bbr_w = %04x\n", machine().describe_context(), data);
+ LOGMASKED(LOG_UBC_WR, "%s: CPU/DMA Cycle Select: %s\n", machine().describe_context(), CPU_DMA_NAMES[(data >> 6) & 3]);
+ LOGMASKED(LOG_UBC_WR, "%s: Instruction/Data Fetch Select: %s\n", machine().describe_context(), INSN_DATA_NAMES[(data >> 4) & 3]);
+ LOGMASKED(LOG_UBC_WR, "%s: Read/Write Select: %s\n", machine().describe_context(), READ_WRITE_NAMES[(data >> 2) & 3]);
+ LOGMASKED(LOG_UBC_WR, "%s: Operand Size Select: %s\n", machine().describe_context(), SIZE_NAMES[data & 3]);
+ COMBINE_DATA(&m_ubc.bbr);
+}
+
+
+// Bus State Controller (BSC)
+
+uint16_t sh7021_device::bsc_bcr_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_BSC_RD, "%s: Bus Control Register, bsc_bcr_r: %04x\n", machine().describe_context(), m_bsc.bcr);
+ return m_bsc.bcr;
+}
+
+void sh7021_device::bsc_bcr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ LOGMASKED(LOG_BSC_WR, "%s: Bus Control Register bsc_bcr_w = %04x & %04x\n", machine().describe_context(), data, mem_mask);
+ LOGMASKED(LOG_BSC_WR, "%s: DRAM Enable: %d\n", machine().describe_context(), BIT(data, 15));
+ LOGMASKED(LOG_BSC_WR, "%s: Multiplexed I/O Enable: %d\n", machine().describe_context(), BIT(data, 14));
+ LOGMASKED(LOG_BSC_WR, "%s: WARP Enable: %d\n", machine().describe_context(), BIT(data, 13));
+ LOGMASKED(LOG_BSC_WR, "%s: /RD High Duty Cycle: %d% of T1 state\n", machine().describe_context(), BIT(data, 12) ? 35 : 50);
+ LOGMASKED(LOG_BSC_WR, "%s: Byte Access Select: %s\n", machine().describe_context(), BIT(data, 11) ? "/LBS, /WR, /HBS enabled" : "/WRH, /WRL, A0 enabled");
+ COMBINE_DATA(&m_bsc.bcr);
+}
+
+uint16_t sh7021_device::bsc_wcr1_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_BSC_RD, "%s: Wait State Control Register 1, bsc_wcr1_r: %04x\n", machine().describe_context(), m_bsc.wcr1);
+ return m_bsc.wcr1;
+}
+
+void sh7021_device::bsc_wcr1_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ LOGMASKED(LOG_BSC_WR, "%s: Wait State Control Register 1, bsc_wcr1_w = %04x\n", machine().describe_context(), data);
+ COMBINE_DATA(&m_bsc.wcr1);
+}
+
+uint16_t sh7021_device::bsc_wcr2_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_BSC_RD, "%s: Wait State Control Register 2, bsc_wcr2_r: %04x\n", machine().describe_context(), m_bsc.wcr2);
+ return m_bsc.wcr2;
+}
+
+void sh7021_device::bsc_wcr2_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ LOGMASKED(LOG_BSC_WR, "%s: Wait State Control Register 2, bsc_wcr2_w = %04x & %04x\n", machine().describe_context(), data, mem_mask);
+ COMBINE_DATA(&m_bsc.wcr2);
+}
+
+uint16_t sh7021_device::bsc_wcr3_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_BSC_RD, "%s: Wait State Control Register 3, bsc_wcr3_r: %04x\n", machine().describe_context(), m_bsc.wcr3);
+ return m_bsc.wcr3;
+}
+
+void sh7021_device::bsc_wcr3_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ LOGMASKED(LOG_BSC_WR, "%s: Wait State Control Register 3, bsc_wcr3_w = %04x & %04x\n", machine().describe_context(), data, mem_mask);
+ COMBINE_DATA(&m_bsc.wcr3);
+}
+
+uint16_t sh7021_device::bsc_dcr_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_BSC_RD, "%s: DRAM Control Register, bsc_dcr_r: %04x\n", machine().describe_context(), m_bsc.dcr);
+ return m_bsc.dcr;
+}
+
+void sh7021_device::bsc_dcr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ LOGMASKED(LOG_BSC_WR, "%s: DRAM Control Register, bsc_dcr_w = %04x & %04x\n", machine().describe_context(), data, mem_mask);
+ LOGMASKED(LOG_BSC_WR, "%s: Dual-WE Mode: %d\n", machine().describe_context(), BIT(data, 15));
+ LOGMASKED(LOG_BSC_WR, "%s: RAS Down Mode: %d\n", machine().describe_context(), BIT(data, 14));
+ LOGMASKED(LOG_BSC_WR, "%s: 2-state Precharge: %d\n", machine().describe_context(), BIT(data, 13));
+ LOGMASKED(LOG_BSC_WR, "%s: Burst Enable: %d\n", machine().describe_context(), BIT(data, 12));
+ LOGMASKED(LOG_BSC_WR, "%s: /CAS High Duty Cycle: %d% of Tc state\n", machine().describe_context(), BIT(data, 11) ? 35 : 50);
+ LOGMASKED(LOG_BSC_WR, "%s: Row/Column Multiplex Enable: %d\n", machine().describe_context(), BIT(data, 10));
+ LOGMASKED(LOG_BSC_WR, "%s: Multiplex Shift Count: %d\n", machine().describe_context(), 8 + ((data >> 8) & 3));
+ COMBINE_DATA(&m_bsc.dcr);
+}
+
+uint16_t sh7021_device::bsc_pcr_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_BSC_RD, "%s: Parity Control Register, bsc_pcr_r: %04x\n", machine().describe_context(), m_bsc.pcr);
+ return m_bsc.pcr;
+}
+
+void sh7021_device::bsc_pcr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ static const char *const PARITY_CHECK_NAMES[4] =
+ {
+ "Don't Check, Don't Generate",
+ "Check and Generate in DRAM",
+ "Check and Generate in DRAM and Area 2",
+ "Reserved",
+ };
+
+ LOGMASKED(LOG_BSC_WR, "%s: Parity Control Register, bsc_pcr_w = %04x & %04x\n", machine().describe_context(), data, mem_mask);
+ LOGMASKED(LOG_BSC_WR, "%s: Parity Error Clear: %d\n", machine().describe_context(), BIT(data, 15));
+ LOGMASKED(LOG_BSC_WR, "%s: Force Parity Error: %d\n", machine().describe_context(), BIT(data, 14));
+ LOGMASKED(LOG_BSC_WR, "%s: Parity Polarity: %s\n", machine().describe_context(), BIT(data, 13) ? "odd" : "even");
+ LOGMASKED(LOG_BSC_WR, "%s: Parity Check Enable: %s\n", machine().describe_context(), PARITY_CHECK_NAMES[(data >> 11) & 3]);
+ LOGMASKED(LOG_BSC_WR, "%s: Parity Error Clear: %d\n", machine().describe_context(), BIT(data, 15));
+ COMBINE_DATA(&m_bsc.pcr);
+}
+
+uint16_t sh7021_device::bsc_rcr_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_BSC_RD, "%s: Refresh Control Register, bsc_rcr_r: %04x\n", machine().describe_context(), m_bsc.rcr);
+ return m_bsc.rcr;
+}
+
+void sh7021_device::bsc_rcr_w(uint16_t data)
+{
+ if ((data >> 8) != 0x5a)
return;
+
+ LOGMASKED(LOG_BSC_WR, "%s: Refresh Control Register, bsc_rcr_w = %02x\n", machine().describe_context(), (uint8_t)data);
+ LOGMASKED(LOG_BSC_WR, "%s: Refresh Control Enable: %d\n", machine().describe_context(), BIT(data, 7));
+ LOGMASKED(LOG_BSC_WR, "%s: Refresh Mode: %s\n", machine().describe_context(), BIT(data, 6) ? "Self-refresh" : "CAS-before-RAS");
+ LOGMASKED(LOG_BSC_WR, "%s: CBR Wait States: %d\n", machine().describe_context(), 1 + ((data >> 4) & 3));
+ m_bsc.rcr = (uint8_t)data;
+}
+
+uint16_t sh7021_device::bsc_rtcsr_r()
+{
+ if (!machine().side_effects_disabled())
+ {
+ LOGMASKED(LOG_BSC_RD, "%s: Refresh Timer Control/Status Register, bsc_rtcsr_r: %04x\n", machine().describe_context(), m_bsc.rtcsr);
+ if (BIT(m_bsc.rtcsr, 7))
+ m_bsc.rtcsr_read = true;
}
+ return m_bsc.rtcsr;
+}
+
+void sh7021_device::bsc_rtcsr_w(uint16_t data)
+{
+ if ((data >> 8) != 0xa5)
+ return;
+
+ static const char *const RTCSR_CKS_NAMES[8] =
+ {
+ "Disabled", "/2", "/8", "/32", "/128", "/512", "/2048", "/4096"
+ };
+
+ LOGMASKED(LOG_BSC_WR, "%s: Refresh Timer Control/Status Register, bsc_rcr_w = %02x\n", machine().describe_context(), (uint8_t)data);
+ LOGMASKED(LOG_BSC_WR, "%s: Refresh Control Enable: %d\n", machine().describe_context(), BIT(data, 7));
+ LOGMASKED(LOG_BSC_WR, "%s: Compare Match Interrupt Enable: %d\n", machine().describe_context(), BIT(data, 6));
+ LOGMASKED(LOG_BSC_WR, "%s: Refresh Timer Counter Prescale: %d\n", machine().describe_context(), RTCSR_CKS_NAMES[(data >> 3) & 7]);
+ m_bsc.rtcsr = (m_bsc.rtcsr & 0x80) | (uint8_t)(data & 0x7f);
+ if (m_bsc.rtcsr_read && !BIT(data, 7))
+ {
+ m_bsc.rtcsr_read = false;
+ m_bsc.rtcsr &= 0x7f;
+ }
+}
+
+uint16_t sh7021_device::bsc_rtcnt_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_BSC_RD, "%s: Refresh Timer Count, bsc_rtcnt_r: %04x\n", machine().describe_context(), m_bsc.rtcnt);
+ return m_bsc.rtcnt;
+}
+
+void sh7021_device::bsc_rtcnt_w(uint16_t data)
+{
+ if ((data >> 8) != 0x69)
+ return;
+
+ LOGMASKED(LOG_BSC_WR, "%s: Refresh Timer Count, bsc_rtcnt_w = %02x\n", machine().describe_context(), (uint8_t)data);
+ m_bsc.rtcnt = (uint8_t)data;
+}
+
+uint16_t sh7021_device::bsc_rtcor_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_BSC_RD, "%s: Refresh Time Constant Register, bsc_rtcor_r: %04x\n", machine().describe_context(), m_bsc.rtcor);
+ return m_bsc.rtcor;
+}
+
+void sh7021_device::bsc_rtcor_w(uint16_t data)
+{
+ if ((data >> 8) != 0x96)
+ return;
+
+ LOGMASKED(LOG_BSC_WR, "%s: Refresh Time Constant Register, bsc_rtcor_w = %02x\n", machine().describe_context(), (uint8_t)data);
+ m_bsc.rtcor = (uint8_t)data;
+}
+
+
+// DMA Controller (DMAC)
+
+template uint32_t sh7021_device::dma_sar_r<0>();
+template uint32_t sh7021_device::dma_sar_r<1>();
+template uint32_t sh7021_device::dma_sar_r<2>();
+template uint32_t sh7021_device::dma_sar_r<3>();
+
+template <int Channel>
+uint32_t sh7021_device::dma_sar_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_DMA_RD, "%s: DMA Source Address Register %d, dma_sar_r: %08x\n", machine().describe_context(), Channel, m_dma[Channel].sar);
+ return m_dma[Channel].sar;
+}
+
+template void sh7021_device::dma_sar_w<0>(offs_t offset, uint32_t data, uint32_t mem_mask);
+template void sh7021_device::dma_sar_w<1>(offs_t offset, uint32_t data, uint32_t mem_mask);
+template void sh7021_device::dma_sar_w<2>(offs_t offset, uint32_t data, uint32_t mem_mask);
+template void sh7021_device::dma_sar_w<3>(offs_t offset, uint32_t data, uint32_t mem_mask);
+
+template <int Channel>
+void sh7021_device::dma_sar_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ LOGMASKED(LOG_DMA_WR, "%s: DMA Source Address Register %d, dma_sar_w = %08x & %08x\n", machine().describe_context(), Channel, data, mem_mask);
+ COMBINE_DATA(&m_dma[Channel].sar);
+}
+
+template uint32_t sh7021_device::dma_dar_r<0>();
+template uint32_t sh7021_device::dma_dar_r<1>();
+template uint32_t sh7021_device::dma_dar_r<2>();
+template uint32_t sh7021_device::dma_dar_r<3>();
+
+template <int Channel>
+uint32_t sh7021_device::dma_dar_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_DMA_RD, "%s: DMA Destination Address Register %d, dma_sar_r: %08x\n", machine().describe_context(), Channel, m_dma[Channel].dar);
+ return m_dma[Channel].dar;
+}
+
+template void sh7021_device::dma_dar_w<0>(offs_t offset, uint32_t data, uint32_t mem_mask);
+template void sh7021_device::dma_dar_w<1>(offs_t offset, uint32_t data, uint32_t mem_mask);
+template void sh7021_device::dma_dar_w<2>(offs_t offset, uint32_t data, uint32_t mem_mask);
+template void sh7021_device::dma_dar_w<3>(offs_t offset, uint32_t data, uint32_t mem_mask);
+
+template <int Channel>
+void sh7021_device::dma_dar_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+{
+ LOGMASKED(LOG_DMA_WR, "%s: DMA Destination Address Register %d, dma_dar_w = %08x & %08x\n", machine().describe_context(), Channel, data, mem_mask);
+ COMBINE_DATA(&m_dma[Channel].dar);
+}
+
+template uint16_t sh7021_device::dma_tcr_r<0>();
+template uint16_t sh7021_device::dma_tcr_r<1>();
+template uint16_t sh7021_device::dma_tcr_r<2>();
+template uint16_t sh7021_device::dma_tcr_r<3>();
+
+template <int Channel>
+uint16_t sh7021_device::dma_tcr_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_DMA_RD, "%s: DMA Transfer Count Register %d, dma_tcr_r: %04x\n", machine().describe_context(), Channel, m_dma[Channel].tcr);
+ return m_dma[Channel].tcr;
+}
+
+template void sh7021_device::dma_tcr_w<0>(offs_t offset, uint16_t data, uint16_t mem_mask);
+template void sh7021_device::dma_tcr_w<1>(offs_t offset, uint16_t data, uint16_t mem_mask);
+template void sh7021_device::dma_tcr_w<2>(offs_t offset, uint16_t data, uint16_t mem_mask);
+template void sh7021_device::dma_tcr_w<3>(offs_t offset, uint16_t data, uint16_t mem_mask);
+
+template <int Channel>
+void sh7021_device::dma_tcr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ LOGMASKED(LOG_DMA_WR, "%s: DMA Transfer Count Register %d, dma_tcr_w = %04x & %04x\n", machine().describe_context(), Channel, data, mem_mask);
+ COMBINE_DATA(&m_dma[Channel].tcr);
+}
+
+
+template uint16_t sh7021_device::dma_chcr_r<0>();
+template uint16_t sh7021_device::dma_chcr_r<1>();
+template uint16_t sh7021_device::dma_chcr_r<2>();
+template uint16_t sh7021_device::dma_chcr_r<3>();
+
+template <int Channel>
+uint16_t sh7021_device::dma_chcr_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_DMA_RD, "%s: DMA Channel Control Register %d, dma_chcr_r: %04x\n", machine().describe_context(), Channel, m_dma[Channel].chcr);
+ return m_dma[Channel].chcr;
+}
+
+template void sh7021_device::dma_chcr_w<0>(offs_t offset, uint16_t data, uint16_t mem_mask);
+template void sh7021_device::dma_chcr_w<1>(offs_t offset, uint16_t data, uint16_t mem_mask);
+template void sh7021_device::dma_chcr_w<2>(offs_t offset, uint16_t data, uint16_t mem_mask);
+template void sh7021_device::dma_chcr_w<3>(offs_t offset, uint16_t data, uint16_t mem_mask);
+
+template <int Channel>
+void sh7021_device::dma_chcr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ static const char *const ADDR_MODE_NAMES[4] =
+ {
+ "Fixed", "Increment", "Decrement", "Reserved"
+ };
+ static const char *const SOURCE_NAMES[16] =
+ {
+ "/DREQ, Dual-Address Mode",
+ "Reserved (1)",
+ "/DREQ, Memory-to-device",
+ "/DREQ, Device-to-memory",
+ "RXI0 (Serial 0 Receive), Dual-Address Mode",
+ "TXI0 (Serial 0 Transmit), Dual-Address Mode",
+ "RXI1 (Serial 1 Receive), Dual-Address Mode",
+ "TXI1 (Serial 1 Transmit), Dual-Address Mode",
+ "IMIA0 (Timer 0 Capture/Compare-Match), Dual-Address Mode",
+ "IMIA1 (Timer 1 Capture/Compare-Match), Dual-Address Mode",
+ "IMIA2 (Timer 2 Capture/Compare-Match), Dual-Address Mode",
+ "IMIA3 (Timer 3 Capture/Compare-Match), Dual-Address Mode",
+ "Auto-Request, Dual-Address Mode",
+ "Reserved (13)",
+ "Reserved (14)",
+ "Reserved (15)"
+ };
+
+ LOGMASKED(LOG_DMA_WR, "%s: DMA Channel Control Register %d, dma_chcr_w = %04x & %04x\n", machine().describe_context(), Channel, data, mem_mask);
+ LOGMASKED(LOG_DMA_WR, "%s: Dest Address Mode: %s\n", machine().describe_context(), ADDR_MODE_NAMES[data >> 14]);
+ LOGMASKED(LOG_DMA_WR, "%s: Source Address Mode: %s\n", machine().describe_context(), ADDR_MODE_NAMES[(data >> 12) & 3]);
+ LOGMASKED(LOG_DMA_WR, "%s: Resource Select: %s\n", machine().describe_context(), SOURCE_NAMES[(data >> 8) & 15]);
+ LOGMASKED(LOG_DMA_WR, "%s: Acknowledge Bit: DACK output in %s cycle\n", machine().describe_context(), BIT(data, 7) ? "write" : "read");
+ LOGMASKED(LOG_DMA_WR, "%s: Acknowledge Level Bit: DACK active %s\n", machine().describe_context(), BIT(data, 6) ? "low" : "high");
+ LOGMASKED(LOG_DMA_WR, "%s: /DREQ Detect Mode: %s\n", machine().describe_context(), BIT(data, 5) ? "Edge" : "Level");
+ LOGMASKED(LOG_DMA_WR, "%s: Transfer Mode: %s\n", machine().describe_context(), BIT(data, 4) ? "Burst Mode" : "Cycle-Steal");
+ LOGMASKED(LOG_DMA_WR, "%s: Transfer Size: %s\n", machine().describe_context(), BIT(data, 3) ? "Word" : "Byte");
+ LOGMASKED(LOG_DMA_WR, "%s: Interrupt Enable: %d\n", machine().describe_context(), BIT(data, 2));
+ LOGMASKED(LOG_DMA_WR, "%s: Transfer End Clear: %d\n", machine().describe_context(), BIT(data, 1));
+ LOGMASKED(LOG_DMA_WR, "%s: Transfer Enable: %d\n", machine().describe_context(), BIT(data, 0));
+ COMBINE_DATA(&m_dma[Channel].chcr);
+ execute_dma(Channel);
+}
+
+uint16_t sh7021_device::dmaor_r()
+{
+ if (!machine().side_effects_disabled())
+ {
+ LOGMASKED(LOG_DMA_RD, "%s: DMA Operation Register, dmaor_r: %04x\n", machine().describe_context(), m_dmaor);
+ LOGMASKED(LOG_DMA_RD, "%s: Address Error Flag: %d\n", machine().describe_context(), BIT(m_dmaor, 2));
+ LOGMASKED(LOG_DMA_RD, "%s: NMI Flag: %d\n", machine().describe_context(), BIT(m_dmaor, 1));
+ LOGMASKED(LOG_DMA_RD, "%s: DMA Master Enable: %d\n", machine().describe_context(), BIT(m_dmaor, 0));
+ }
+ return m_dmaor;
+}
+
+void sh7021_device::dmaor_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ static const char *const PRIORITY_NAMES[4] =
+ {
+ "Fixed Priority (0 -> 3 -> 2 -> 1)",
+ "Fixed Priority (1 -> 3 -> 2 -> 0)",
+ "Round-Robin Priority",
+ "External-Pin Round-Robin Priority"
+ };
+ LOGMASKED(LOG_DMA_WR, "%s: DMA Operation Register, dmaor_w = %04x & %04x\n", machine().describe_context(), data, mem_mask);
+ LOGMASKED(LOG_DMA_WR, "%s: Priority Mode: %s\n", machine().describe_context(), PRIORITY_NAMES[(data >> 8) & 3]);
+ LOGMASKED(LOG_DMA_WR, "%s: Address Error Flag: %d\n", machine().describe_context(), BIT(data, 2));
+ LOGMASKED(LOG_DMA_WR, "%s: NMI Flag: %d\n", machine().describe_context(), BIT(data, 1));
+ LOGMASKED(LOG_DMA_WR, "%s: DMA Master Enable: %d\n", machine().describe_context(), BIT(data, 0));
+ COMBINE_DATA(&m_dmaor);
+}
+
+void sh7021_device::execute_dma(int ch)
+{
+ const short dma_word_size[4] = { 0, +1, -1, 0 };
+ uint8_t rs = (m_dma[ch].chcr >> 8) & 0xf; /**< Resource Select bits */
// channel enable & master enable
- if((m_dma[ch].chcr & 1) == 0 || (m_dmaor & 1) == 0)
+ if ((m_dma[ch].chcr & 1) == 0 || (m_dmaor & 1) == 0)
+ {
return;
+ }
- // printf("%08x %08x %04x\n",m_dma[ch].sar,m_dma[ch].dar,m_dma[ch].chcr);
uint8_t dm = (m_dma[ch].chcr >> 14) & 3; /**< Destination Address Mode bits */
uint8_t sm = (m_dma[ch].chcr >> 12) & 3; /**< Source Address Mode bits */
bool ts = (m_dma[ch].chcr & 8); /**< Transfer Size bit */
- int src_word_size = dma_word_size[sm] * ((ts == true) ? 2 : 1);
- int dst_word_size = dma_word_size[dm] * ((ts == true) ? 2 : 1);
+ int src_word_size = dma_word_size[sm] * (ts ? 2 : 1);
+ int dst_word_size = dma_word_size[dm] * (ts ? 2 : 1);
uint32_t src_addr = m_dma[ch].sar;
uint32_t dst_addr = m_dma[ch].dar;
- uint32_t size_index = m_dma[ch].tcr;
- if(size_index == 0)
- size_index = 0x10000;
+ uint32_t count = m_dma[ch].tcr;
+
+ if (count == 0)
+ {
+ count = 0x10000;
+ }
+
+ if (!ts)
+ {
+ //printf("SH7032: DMA byte mode check\n");
+ //printf("DMA%u: S:%08x D:%08x C:%08x CTRL:%04x\n", ch, m_dma[ch].sar, m_dma[ch].dar, m_dma[ch].tcr, m_dma[ch].chcr);
+ //printf("SRC_INC: %d DST_INC: %d\n", src_word_size, dst_word_size);
+ //printf("MODE: %s\n\n", m_dma[ch].chcr & (1 << 4) ? "BURST" : "STEAL");
+ }
- if(ts == false)
- logerror("SH7021: DMA byte mode check\n");
+ // Fake a a Transmit End Interrupt
+ if (rs == 5 || rs == 7)
+ {
+ int channel = (rs == 5 ? 0 : 1);
+ uint64_t clock_divider = 1 << ((m_sci[channel].smr & 3) << 1);
+ uint64_t char_length = BIT(m_sci[channel].smr, 6) ? 8 : 7;
+ uint64_t stop_bits = BIT(m_sci[channel].smr, 3) ? 2 : 1;
+ attotime transmit_time = attotime::from_ticks(clock_divider * count * (char_length + stop_bits) * (m_sci[channel].brr + 1), clock());
+ m_sci[channel].et->adjust(transmit_time);
+ LOGMASKED(LOG_DMA_WR, "Setting SCI channel %d to elapse in %d ticks (%d * %d * (%d + %d) * %d)\n", channel, clock_divider * count * (char_length + stop_bits) * (m_sci[channel].brr + 1),
+ clock_divider, count, char_length, stop_bits, m_sci[channel].brr + 1);
+ }
- for(int index = size_index;index>-1;index--)
+ for (int i = 0; i < count; ++i)
{
- if(ts == true)
- m_program->write_word(dst_addr,m_program->read_word(src_addr));
+ if (ts)
+ m_program->write_word(dst_addr & m_am, m_program->read_word(src_addr & m_am));
else
- m_program->write_byte(dst_addr,m_program->read_byte(src_addr));
+ m_program->write_byte(dst_addr & m_am, m_program->read_byte(src_addr & m_am));
src_addr += src_word_size;
dst_addr += dst_word_size;
}
- m_dma[ch].chcr &= ~1; /**< @todo non-instant DMA */
- // printf("%02x %02x %02x %1d\n",sm,dm,rs,ts);
+ m_dma[ch].sar = src_addr;
+ m_dma[ch].dar = dst_addr;
+
+ m_dma[ch].chcr |= 2; // Transfer ended
+
+ // TODO: IRQs
}
-uint32_t sh2a_sh7021_device::dma_sar0_r()
+void sh7021_device::execute_peripherals(int peripheral_cycles)
{
- return m_dma[0].sar;
+ m_dma_cycles += peripheral_cycles;
}
-void sh2a_sh7021_device::dma_sar0_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+// 16-Bit Integrated-Timer Pulse Unit (ITU)
+
+template TIMER_CALLBACK_MEMBER(sh7021_device::sh7021_timer_callback<0>);
+template TIMER_CALLBACK_MEMBER(sh7021_device::sh7021_timer_callback<1>);
+template TIMER_CALLBACK_MEMBER(sh7021_device::sh7021_timer_callback<2>);
+template TIMER_CALLBACK_MEMBER(sh7021_device::sh7021_timer_callback<3>);
+template TIMER_CALLBACK_MEMBER(sh7021_device::sh7021_timer_callback<4>);
+
+template<int Which>
+TIMER_CALLBACK_MEMBER(sh7021_device::sh7021_timer_callback)
{
- COMBINE_DATA(&m_dma[0].sar);
+ // TCNT0 and 1 are up-counters
+ //if (Which < 2)
+ {
+ //if (Which == 0)
+ //LOGMASKED(LOG_ITU_WR, "T%d %04x\n", Which, m_itu.timer[Which].tcnt);
+ m_itu.timer[Which].tcnt++;
+
+ if (m_itu.timer[Which].tcnt == 0)
+ {
+ LOGMASKED(LOG_ITU_WR, "Timer %d has overflowed, flagging OVF\n", Which);
+ m_itu.timer[Which].tsr |= 4; // OVF
+ }
+ }
+
+ if (m_itu.timer[Which].tcnt == m_itu.timer[Which].gra)
+ {
+ LOGMASKED(LOG_ITU_WR, "Timer %d count %04x matches GRA %04x, flagging IMFA\n", Which, m_itu.timer[Which].tcnt, m_itu.timer[Which].gra);
+ m_itu.timer[Which].tsr |= 1; // IMFA
+
+ // CCLR[1:0] = 01
+ if (((m_itu.timer[Which].tcr >> 5) & 3) == 1)
+ {
+ LOGMASKED(LOG_ITU_WR, "Timer %d resetting count to 0\n", Which);
+ m_itu.timer[Which].tcnt = 0;
+ }
+ }
+
+ if (m_itu.timer[Which].tcnt == m_itu.timer[Which].grb)
+ {
+ LOGMASKED(LOG_ITU_WR, "Timer %d count %04x matches GRB %04x, flagging IMFB\n", Which, m_itu.timer[Which].tcnt, m_itu.timer[Which].grb);
+ m_itu.timer[Which].tsr |= 2; // IMFB
+
+ // CCLR[1:0] = 10
+ if (((m_itu.timer[Which].tcr >> 5) & 3) == 2)
+ m_itu.timer[Which].tcnt = 0;
+ }
+
+ recalc_irq();
+ //start_timer(Which);
}
-uint32_t sh2a_sh7021_device::dma_dar0_r()
+void sh7021_device::start_timer(int i)
{
- return m_dma[0].dar;
+ if (m_itu.timer[i].tcr & 4)
+ fatalerror("external clock source");
+
+ int prescale = 1 << (m_itu.timer[i].tcr & 3);
+
+// printf("Starting timer %u: TCNT:%x GR:%x TCR:%x TI:%x TICK:%f\n", i, m_itu.timer[i].tcnt, m_itu.timer[i].gra, m_itu.timer[i].tcr & 7, m_itu.timer[i].tier, (double)clock()/psc);
+// printf("%d\n", clock());
+ LOGMASKED(LOG_ITU_WR, "Starting Timer %d, prescale %d, clock %d, current count %04x\n", i, prescale, clock(), m_itu.timer[i].tcnt);
+ attotime period = attotime::from_ticks(prescale, clock());
+ m_itu.timer[i].et->adjust(period, i, period);
}
-void sh2a_sh7021_device::dma_dar0_w(offs_t offset, uint32_t data, uint32_t mem_mask)
+uint8_t sh7021_device::itu_tstr_r()
{
- COMBINE_DATA(&m_dma[0].dar);
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_ITU_RD, "%s: Timer Start Register, itu_tstr_r: %02x\n", machine().describe_context(), m_itu.tstr);
+ return m_itu.tstr | 0x60;
}
-uint16_t sh2a_sh7021_device::dma_tcr0_r()
+void sh7021_device::itu_tstr_w(uint8_t data)
{
- return m_dma[0].tcr;
+ LOGMASKED(LOG_ITU_WR, "%s: Timer Start Register, itu_tstr_w = %02x\n", machine().describe_context(), data);
+
+ // Starts timers
+ const uint8_t newly_enabled = ~m_itu.tstr & data;
+ const uint8_t newly_disabled = m_itu.tstr & ~data;
+ m_itu.tstr = data;
+
+ for (int i = 0; i < 5; ++i)
+ {
+ if (BIT(newly_disabled, i))
+ {
+ LOGMASKED(LOG_ITU_WR, "%s: Timer Start Register, timer %d disabled\n", machine().describe_context(), i);
+ m_itu.timer[i].et->adjust(attotime::never);
+ }
+ else if (BIT(newly_enabled, i))
+ {
+ LOGMASKED(LOG_ITU_WR, "%s: Timer Start Register, timer %d enabled\n", machine().describe_context(), i);
+ start_timer(i);
+ }
+ }
}
-void sh2a_sh7021_device::dma_tcr0_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+uint8_t sh7021_device::itu_tsnc_r()
{
- //printf("%04x\n",data);
- COMBINE_DATA(&m_dma[0].tcr);
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_ITU_RD, "%s: Timer Synchro Register, itu_tsnc_r: %02x\n", machine().describe_context(), m_itu.tsnc);
+ return m_itu.tsnc;
}
-uint16_t sh2a_sh7021_device::dma_chcr0_r()
+void sh7021_device::itu_tsnc_w(uint8_t data)
{
- return m_dma[0].chcr;
+ LOGMASKED(LOG_ITU_WR, "%s: Timer Synchro Register, itu_tsnc_w = %02x\n", machine().describe_context(), data);
+ m_itu.tsnc = data;
}
-void sh2a_sh7021_device::dma_chcr0_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+uint8_t sh7021_device::itu_tmdr_r()
{
- //printf("%04x CHCR0\n",data);
- COMBINE_DATA(&m_dma[0].chcr);
- sh7021_dma_exec(0);
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_ITU_RD, "%s: Timer Mode Register, itu_tmdr_r: %02x\n", machine().describe_context(), m_itu.tmdr);
+ return m_itu.tmdr;
}
-uint16_t sh2a_sh7021_device::dmaor_r()
+void sh7021_device::itu_tmdr_w(uint8_t data)
{
- return m_dmaor;
+ LOGMASKED(LOG_ITU_WR, "%s: Timer Mode Register, itu_tmdr_w = %02x\n", machine().describe_context(), data);
+ LOGMASKED(LOG_ITU_WR, "%s: Channel 2 Phase Counting Mode: %d\n", machine().describe_context(), BIT(data, 6));
+ LOGMASKED(LOG_ITU_WR, "%s: Channel 2 Overflow Behavior: %d\n", machine().describe_context(), BIT(data, 5) ? "Set OVF of TSR2 on TCNT2 overflow" : "Set OVF of TSR2 on TCNT2 overflow and underflow");
+ LOGMASKED(LOG_ITU_WR, "%s: Channel 4 PWM Mode: %d\n", machine().describe_context(), BIT(data, 4));
+ LOGMASKED(LOG_ITU_WR, "%s: Channel 3 PWM Mode: %d\n", machine().describe_context(), BIT(data, 3));
+ LOGMASKED(LOG_ITU_WR, "%s: Channel 2 PWM Mode: %d\n", machine().describe_context(), BIT(data, 2));
+ LOGMASKED(LOG_ITU_WR, "%s: Channel 1 PWM Mode: %d\n", machine().describe_context(), BIT(data, 1));
+ LOGMASKED(LOG_ITU_WR, "%s: Channel 0 PWM Mode: %d\n", machine().describe_context(), BIT(data, 0));
+ m_itu.tmdr = data;
}
-void sh2a_sh7021_device::dmaor_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+uint8_t sh7021_device::itu_tfcr_r()
{
- COMBINE_DATA(&m_dmaor);
- sh7021_dma_exec(0);
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_ITU_RD, "%s: Timer Function Control Register, itu_tfcr_r: %02x\n", machine().describe_context(), m_itu.tfcr);
+ return m_itu.tfcr;
+}
+
+void sh7021_device::itu_tfcr_w(uint8_t data)
+{
+ static const char *const COMBO_MODE_NAMES[4] =
+ {
+ "Channel 3 & 4 Normal (0)",
+ "Channel 3 & 4 Normal (1)",
+ "Channel 3 & 4 Together, Complementary PWM",
+ "Channel 3 & 4 Together, Reset-Synced PWM"
+ };
+ LOGMASKED(LOG_ITU_WR, "%s: Timer Function Control Register, itu_tfcr_w = %02x\n", machine().describe_context(), data);
+ LOGMASKED(LOG_ITU_WR, "%s: Combination Mode: %s\n", machine().describe_context(), COMBO_MODE_NAMES[(data >> 4) & 3]);
+ LOGMASKED(LOG_ITU_WR, "%s: Buffer Mode B4: %s\n", machine().describe_context(), BIT(data, 3) ? "GRB4 and BRB4 buffer mode for Ch.4" : "GRB4 normal for Ch.4");
+ LOGMASKED(LOG_ITU_WR, "%s: Buffer Mode A4: %s\n", machine().describe_context(), BIT(data, 2) ? "GRA4 and BRA4 buffer mode for Ch.4" : "GRA4 normal for Ch.4");
+ LOGMASKED(LOG_ITU_WR, "%s: Buffer Mode B3: %s\n", machine().describe_context(), BIT(data, 1) ? "GRB3 and BRB3 buffer mode for Ch.3" : "GRB3 normal for Ch.3");
+ LOGMASKED(LOG_ITU_WR, "%s: Buffer Mode A3: %s\n", machine().describe_context(), BIT(data, 0) ? "GRA3 and BRA3 buffer mode for Ch.3" : "GRA3 normal for Ch.3");
+ m_itu.tfcr = data;
+}
+
+uint8_t sh7021_device::itu_tocr_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_ITU_RD, "%s: Timer Output Control Register, itu_tfcr_r: %02x\n", machine().describe_context(), m_itu.tocr);
+ return m_itu.tocr | 0x7c;
+}
+
+void sh7021_device::itu_tocr_w(uint8_t data)
+{
+ LOGMASKED(LOG_ITU_WR, "%s: Timer Output Control Register, itu_tocr_w = %02x\n", machine().describe_context(), data);
+ LOGMASKED(LOG_ITU_WR, "%s: Output Level Select Ch.4: %s\n", machine().describe_context(), BIT(data, 1) ? "Direct" : "Inverted");
+ LOGMASKED(LOG_ITU_WR, "%s: Output Level Select Ch.3: %s\n", machine().describe_context(), BIT(data, 0) ? "Direct" : "Inverted");
+ m_itu.tocr = data;
+}
+
+template uint8_t sh7021_device::itu_tcr_r<0>();
+template uint8_t sh7021_device::itu_tcr_r<1>();
+template uint8_t sh7021_device::itu_tcr_r<2>();
+template uint8_t sh7021_device::itu_tcr_r<3>();
+template uint8_t sh7021_device::itu_tcr_r<4>();
+
+template <int Channel>
+uint8_t sh7021_device::itu_tcr_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_ITU_RD, "%s: Timer Control Register %d, itu_tcr_r: %02x\n", machine().describe_context(), Channel, m_itu.timer[Channel].tcr);
+ return m_itu.timer[Channel].tcr;
+}
+
+template void sh7021_device::itu_tcr_w<0>(uint8_t data);
+template void sh7021_device::itu_tcr_w<1>(uint8_t data);
+template void sh7021_device::itu_tcr_w<2>(uint8_t data);
+template void sh7021_device::itu_tcr_w<3>(uint8_t data);
+template void sh7021_device::itu_tcr_w<4>(uint8_t data);
+
+template <int Channel>
+void sh7021_device::itu_tcr_w(uint8_t data)
+{
+ static const char *const CCLR_NAMES[4] =
+ {
+ "Don't clear TCNT", "Clear TCNT on GRA match or input capture", "Clear TCNT on GRB match or input capture", "Synced clear"
+ };
+ static const char *const CKEG_NAMES[4] =
+ {
+ "Count rising edges", "Count falling edges", "Count both edges (2)", "Count both edges (3)"
+ };
+ static const char *const TPSC_NAMES[8] =
+ {
+ "/1", "/2", "/4", "/8", "External clock A", "External clock B", "External clock C", "External clock D"
+ };
+
+ LOGMASKED(LOG_ITU_WR, "%s: Timer Control Register %d, itu_tcr_w = %02x\n", machine().describe_context(), Channel, data);
+ LOGMASKED(LOG_ITU_WR, "%s: Counter Clear Mode: %s\n", machine().describe_context(), CCLR_NAMES[(data >> 5) & 3]);
+ LOGMASKED(LOG_ITU_WR, "%s: External-Clock Edge Mode: %s\n", machine().describe_context(), CKEG_NAMES[(data >> 3) & 3]);
+ LOGMASKED(LOG_ITU_WR, "%s: Timer Prescaler Mode: %s\n", machine().describe_context(), TPSC_NAMES[data & 7]);
+ m_itu.timer[Channel].tcr = data;
+}
+
+template uint8_t sh7021_device::itu_tior_r<0>();
+template uint8_t sh7021_device::itu_tior_r<1>();
+template uint8_t sh7021_device::itu_tior_r<2>();
+template uint8_t sh7021_device::itu_tior_r<3>();
+template uint8_t sh7021_device::itu_tior_r<4>();
+
+template <int Channel>
+uint8_t sh7021_device::itu_tior_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_ITU_RD, "%s: Timer I/O Control Register %d, itu_tior_r: %02x\n", machine().describe_context(), Channel, m_itu.timer[Channel].tior);
+ return m_itu.timer[Channel].tior;
+}
+
+template void sh7021_device::itu_tior_w<0>(uint8_t data);
+template void sh7021_device::itu_tior_w<1>(uint8_t data);
+template void sh7021_device::itu_tior_w<2>(uint8_t data);
+template void sh7021_device::itu_tior_w<3>(uint8_t data);
+template void sh7021_device::itu_tior_w<4>(uint8_t data);
+
+template <int Channel>
+void sh7021_device::itu_tior_w(uint8_t data)
+{
+ static const char *const IOB_NAMES[8] =
+ {
+ "Output compare GRB / Compare Match",
+ "Output compare GRB / 0 output at GRB match",
+ "Output compare GRB / 1 output at GRB match",
+ "Output compare GRB / Toggle at GRB match",
+ "Input capture GRB / Capture rising edge",
+ "Input capture GRB / Capture falling edge",
+ "Input capture GRB / Capture both edges (6)",
+ "Input capture GRB / Capture both edges (7)",
+ };
+ static const char *const IOA_NAMES[8] =
+ {
+ "Output compare GRA / Compare Match",
+ "Output compare GRA / 0 output at GRA match",
+ "Output compare GRA / 1 output at GRA match",
+ "Output compare GRA / Toggle at GRA match",
+ "Input capture GRA / Capture rising edge",
+ "Input capture GRA / Capture falling edge",
+ "Input capture GRA / Capture both edges (6)",
+ "Input capture GRA / Capture both edges (7)",
+ };
+
+ LOGMASKED(LOG_ITU_WR, "%s: Timer I/O Control Register %d, itu_tior_w = %02x\n", machine().describe_context(), Channel, data);
+ LOGMASKED(LOG_ITU_WR, "%s: GRB Function: %s\n", machine().describe_context(), IOB_NAMES[(data >> 4) & 7]);
+ LOGMASKED(LOG_ITU_WR, "%s: GRA Function: %s\n", machine().describe_context(), IOA_NAMES[data & 7]);
+ m_itu.timer[Channel].tior = data;
+}
+
+template uint8_t sh7021_device::itu_tier_r<0>();
+template uint8_t sh7021_device::itu_tier_r<1>();
+template uint8_t sh7021_device::itu_tier_r<2>();
+template uint8_t sh7021_device::itu_tier_r<3>();
+template uint8_t sh7021_device::itu_tier_r<4>();
+
+template <int Channel>
+uint8_t sh7021_device::itu_tier_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_ITU_RD, "%s: Timer Interrupt Enable Register %d, itu_tier_r: %02x\n", machine().describe_context(), Channel, m_itu.timer[Channel].tier);
+ return m_itu.timer[Channel].tier;
+}
+
+template void sh7021_device::itu_tier_w<0>(uint8_t data);
+template void sh7021_device::itu_tier_w<1>(uint8_t data);
+template void sh7021_device::itu_tier_w<2>(uint8_t data);
+template void sh7021_device::itu_tier_w<3>(uint8_t data);
+template void sh7021_device::itu_tier_w<4>(uint8_t data);
+
+template <int Channel>
+void sh7021_device::itu_tier_w(uint8_t data)
+{
+ LOGMASKED(LOG_ITU_WR, "%s: Timer Interrupt Enable Register %d, itu_tier_w = %02x\n", machine().describe_context(), Channel, data);
+ LOGMASKED(LOG_ITU_WR, "%s: Enable Overflow Interrupts: %d\n", machine().describe_context(), BIT(data, 2));
+ LOGMASKED(LOG_ITU_WR, "%s: Enable Capture/Compare B Interrupts: %d\n", machine().describe_context(), BIT(data, 1));
+ LOGMASKED(LOG_ITU_WR, "%s: Enable Capture/Compare A Interrupts: %d\n", machine().describe_context(), BIT(data, 0));
+ m_itu.timer[Channel].tier = data;
+}
+
+template uint8_t sh7021_device::itu_tsr_r<0>();
+template uint8_t sh7021_device::itu_tsr_r<1>();
+template uint8_t sh7021_device::itu_tsr_r<2>();
+template uint8_t sh7021_device::itu_tsr_r<3>();
+template uint8_t sh7021_device::itu_tsr_r<4>();
+
+template <int Channel>
+uint8_t sh7021_device::itu_tsr_r()
+{
+ if (!machine().side_effects_disabled())
+ {
+ LOGMASKED(LOG_ITU_RD, "%s: Timer Status Register %d, itu_tsr_r: %02x\n", machine().describe_context(), Channel, m_itu.timer[Channel].tsr);
+ LOGMASKED(LOG_ITU_RD, "%s: Overflow Flag: %d\n", machine().describe_context(), BIT(m_itu.timer[Channel].tsr, 2));
+ LOGMASKED(LOG_ITU_RD, "%s: Compare/Capture B Flag: %d\n", machine().describe_context(), BIT(m_itu.timer[Channel].tsr, 1));
+ LOGMASKED(LOG_ITU_RD, "%s: Compare/Capture A Flag: %d\n", machine().describe_context(), BIT(m_itu.timer[Channel].tsr, 0));
+ }
+ return m_itu.timer[Channel].tsr;
+}
+
+template void sh7021_device::itu_tsr_w<0>(uint8_t data);
+template void sh7021_device::itu_tsr_w<1>(uint8_t data);
+template void sh7021_device::itu_tsr_w<2>(uint8_t data);
+template void sh7021_device::itu_tsr_w<3>(uint8_t data);
+template void sh7021_device::itu_tsr_w<4>(uint8_t data);
+
+template <int Channel>
+void sh7021_device::itu_tsr_w(uint8_t data)
+{
+ LOGMASKED(LOG_ITU_WR, "%s: Timer Status Register %d, itu_tsr_w = %02x\n", machine().describe_context(), Channel, m_itu.timer[Channel].tsr);
+ if (BIT(m_itu.timer[Channel].tsr, 2) && !BIT(data, 2))
+ LOGMASKED(LOG_ITU_WR, "%s: Overflow Clear\n", machine().describe_context());
+ if (BIT(m_itu.timer[Channel].tsr, 1) && !BIT(data, 1))
+ LOGMASKED(LOG_ITU_WR, "%s: Compare/Capture B Clear\n", machine().describe_context());
+ if (BIT(m_itu.timer[Channel].tsr, 0) && !BIT(data, 0))
+ LOGMASKED(LOG_ITU_WR, "%s: Compare/Capture A Clear\n", machine().describe_context());
+ m_itu.timer[Channel].tsr = data;
+}
+
+template uint16_t sh7021_device::itu_tcnt_r<0>();
+template uint16_t sh7021_device::itu_tcnt_r<1>();
+template uint16_t sh7021_device::itu_tcnt_r<2>();
+template uint16_t sh7021_device::itu_tcnt_r<3>();
+template uint16_t sh7021_device::itu_tcnt_r<4>();
+
+template <int Channel>
+uint16_t sh7021_device::itu_tcnt_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_ITU_RD, "%s: Timer Counter %d, itu_tcnt_r: %04x\n", machine().describe_context(), Channel, m_itu.timer[Channel].tcnt);
+ return m_itu.timer[Channel].tcnt;
+}
+
+template void sh7021_device::itu_tcnt_w<0>(offs_t offset, uint16_t data, uint16_t mem_mask);
+template void sh7021_device::itu_tcnt_w<1>(offs_t offset, uint16_t data, uint16_t mem_mask);
+template void sh7021_device::itu_tcnt_w<2>(offs_t offset, uint16_t data, uint16_t mem_mask);
+template void sh7021_device::itu_tcnt_w<3>(offs_t offset, uint16_t data, uint16_t mem_mask);
+template void sh7021_device::itu_tcnt_w<4>(offs_t offset, uint16_t data, uint16_t mem_mask);
+
+template <int Channel>
+void sh7021_device::itu_tcnt_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ LOGMASKED(LOG_ITU_WR, "%s: Timer Counter %d, itu_tcnt_w = %04x & %04x\n", machine().describe_context(), Channel, data, mem_mask);
+ COMBINE_DATA(&m_itu.timer[Channel].tcnt);
+}
+
+template uint16_t sh7021_device::itu_gra_r<0>();
+template uint16_t sh7021_device::itu_gra_r<1>();
+template uint16_t sh7021_device::itu_gra_r<2>();
+template uint16_t sh7021_device::itu_gra_r<3>();
+template uint16_t sh7021_device::itu_gra_r<4>();
+
+template <int Channel>
+uint16_t sh7021_device::itu_gra_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_ITU_RD, "%s: General Register A %d, itu_gra_r: %04x\n", machine().describe_context(), Channel, m_itu.timer[Channel].gra);
+ return m_itu.timer[Channel].gra;
+}
+
+template void sh7021_device::itu_gra_w<0>(offs_t offset, uint16_t data, uint16_t mem_mask);
+template void sh7021_device::itu_gra_w<1>(offs_t offset, uint16_t data, uint16_t mem_mask);
+template void sh7021_device::itu_gra_w<2>(offs_t offset, uint16_t data, uint16_t mem_mask);
+template void sh7021_device::itu_gra_w<3>(offs_t offset, uint16_t data, uint16_t mem_mask);
+template void sh7021_device::itu_gra_w<4>(offs_t offset, uint16_t data, uint16_t mem_mask);
+
+template <int Channel>
+void sh7021_device::itu_gra_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ LOGMASKED(LOG_ITU_WR, "%s: General Register A %d, itu_gra_w = %04x\n", machine().describe_context(), Channel, data);
+ COMBINE_DATA(&m_itu.timer[Channel].gra);
+}
+
+template uint16_t sh7021_device::itu_grb_r<0>();
+template uint16_t sh7021_device::itu_grb_r<1>();
+template uint16_t sh7021_device::itu_grb_r<2>();
+template uint16_t sh7021_device::itu_grb_r<3>();
+template uint16_t sh7021_device::itu_grb_r<4>();
+
+template <int Channel>
+uint16_t sh7021_device::itu_grb_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_ITU_RD, "%s: General Register B %d, itu_grb_r: %04x\n", machine().describe_context(), Channel, m_itu.timer[Channel].grb);
+ return m_itu.timer[Channel].grb;
+}
+
+template void sh7021_device::itu_grb_w<0>(offs_t offset, uint16_t data, uint16_t mem_mask);
+template void sh7021_device::itu_grb_w<1>(offs_t offset, uint16_t data, uint16_t mem_mask);
+template void sh7021_device::itu_grb_w<2>(offs_t offset, uint16_t data, uint16_t mem_mask);
+template void sh7021_device::itu_grb_w<3>(offs_t offset, uint16_t data, uint16_t mem_mask);
+template void sh7021_device::itu_grb_w<4>(offs_t offset, uint16_t data, uint16_t mem_mask);
+
+template <int Channel>
+void sh7021_device::itu_grb_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ LOGMASKED(LOG_ITU_WR, "%s: General Register B %d, itu_grb_w = %04x\n", machine().describe_context(), Channel, data);
+ COMBINE_DATA(&m_itu.timer[Channel].grb);
+}
+
+template uint16_t sh7021_device::itu_bra_r<3>();
+template uint16_t sh7021_device::itu_bra_r<4>();
+
+template <int Channel>
+uint16_t sh7021_device::itu_bra_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_ITU_RD, "%s: Buffer Register A %d, itu_bra_r: %04x\n", machine().describe_context(), Channel, m_itu.timer[Channel].bra);
+ return m_itu.timer[Channel].bra;
+}
+
+template void sh7021_device::itu_bra_w<3>(offs_t offset, uint16_t data, uint16_t mem_mask);
+template void sh7021_device::itu_bra_w<4>(offs_t offset, uint16_t data, uint16_t mem_mask);
+
+template <int Channel>
+void sh7021_device::itu_bra_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ LOGMASKED(LOG_ITU_WR, "%s: Buffer Register A %d, itu_bra_w = %04x\n", machine().describe_context(), Channel, data);
+ COMBINE_DATA(&m_itu.timer[Channel].bra);
+}
+
+template uint16_t sh7021_device::itu_brb_r<3>();
+template uint16_t sh7021_device::itu_brb_r<4>();
+
+template <int Channel>
+uint16_t sh7021_device::itu_brb_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_ITU_RD, "%s: Buffer Register B %d, itu_brb_r: %04x\n", machine().describe_context(), Channel, m_itu.timer[Channel].brb);
+ return m_itu.timer[Channel].brb;
+}
+
+template void sh7021_device::itu_brb_w<3>(offs_t offset, uint16_t data, uint16_t mem_mask);
+template void sh7021_device::itu_brb_w<4>(offs_t offset, uint16_t data, uint16_t mem_mask);
+
+template <int Channel>
+void sh7021_device::itu_brb_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ LOGMASKED(LOG_ITU_WR, "%s: Buffer Register B %d, itu_brb_w = %04x\n", machine().describe_context(), Channel, data);
+ COMBINE_DATA(&m_itu.timer[Channel].brb);
+}
+
+
+// Programmable Timing Pattern Controller (TPC)
+
+uint8_t sh7021_device::tpc_tpmr_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_TPC_RD, "%s: TPC Output Mode Register, tpc_tpmr_r: %02x\n", machine().describe_context(), m_tpc.tpmr);
+ return m_tpc.tpmr;
+}
+
+void sh7021_device::tpc_tpmr_w(uint8_t data)
+{
+ LOGMASKED(LOG_TPC_WR, "%s: TPC Output Mode Register, tpc_tpmr_w = %02x\n", machine().describe_context(), data);
+ LOGMASKED(LOG_TPC_WR, "%s: TPC Output Group 3 Operation: %s\n", machine().describe_context(), BIT(data, 3) ? "Non-Overlap Mode (1/0 from A/B)" : "Normal (Compare-Match A)");
+ LOGMASKED(LOG_TPC_WR, "%s: TPC Output Group 2 Operation: %s\n", machine().describe_context(), BIT(data, 2) ? "Non-Overlap Mode (1/0 from A/B)" : "Normal (Compare-Match A)");
+ LOGMASKED(LOG_TPC_WR, "%s: TPC Output Group 1 Operation: %s\n", machine().describe_context(), BIT(data, 1) ? "Non-Overlap Mode (1/0 from A/B)" : "Normal (Compare-Match A)");
+ LOGMASKED(LOG_TPC_WR, "%s: TPC Output Group 0 Operation: %s\n", machine().describe_context(), BIT(data, 0) ? "Non-Overlap Mode (1/0 from A/B)" : "Normal (Compare-Match A)");
+ m_tpc.tpmr = data;
+}
+
+uint8_t sh7021_device::tpc_tpcr_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_TPC_RD, "%s: TPC Output Control Register, tpc_tpcr_r: %02x\n", machine().describe_context(), m_tpc.tpcr);
+ return m_tpc.tpcr;
+}
+
+void sh7021_device::tpc_tpcr_w(uint8_t data)
+{
+ LOGMASKED(LOG_TPC_WR, "%s: TPC Output Control Register, tpc_tpcr_w = %02x\n", machine().describe_context(), data);
+ LOGMASKED(LOG_TPC_WR, "%s: TPC Output Group 3 output triggered by compare-match in ITU channel %d\n", machine().describe_context(), (data >> 6) & 3);
+ LOGMASKED(LOG_TPC_WR, "%s: TPC Output Group 2 output triggered by compare-match in ITU channel %d\n", machine().describe_context(), (data >> 4) & 3);
+ LOGMASKED(LOG_TPC_WR, "%s: TPC Output Group 1 output triggered by compare-match in ITU channel %d\n", machine().describe_context(), (data >> 2) & 3);
+ LOGMASKED(LOG_TPC_WR, "%s: TPC Output Group 0 output triggered by compare-match in ITU channel %d\n", machine().describe_context(), data & 3);
+ m_tpc.tpcr = data;
+}
+
+uint8_t sh7021_device::tpc_ndera_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_TPC_RD, "%s: Next Data Enable Register A, tpc_ndera_r (TP7-0): %02x\n", machine().describe_context(), m_tpc.ndera);
+ return m_tpc.ndera;
+}
+
+void sh7021_device::tpc_ndera_w(uint8_t data)
+{
+ LOGMASKED(LOG_TPC_WR, "%s: Next Data Enable Register A, tpc_ndera_w (TP7-0) = %02x\n", machine().describe_context(), data);
+ m_tpc.ndera = data;
+}
+
+uint8_t sh7021_device::tpc_nderb_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_TPC_RD, "%s: Next Data Enable Register B, tpc_nderb_r (TP15-8): %02x\n", machine().describe_context(), m_tpc.nderb);
+ return m_tpc.nderb;
+}
+
+void sh7021_device::tpc_nderb_w(uint8_t data)
+{
+ LOGMASKED(LOG_TPC_WR, "%s: Next Data Enable Register B, tpc_nderb_w (TP15-8) = %02x\n", machine().describe_context(), data);
+ m_tpc.nderb = data;
+}
+
+uint8_t sh7021_device::tpc_ndra_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_TPC_RD, "%s: Next Data Register A, tpc_ndra_r: %02x\n", machine().describe_context(), 0);//m_tpc.ndra);
+ return 0;//m_tpc.ndra;
+}
+
+void sh7021_device::tpc_ndra_w(uint8_t data)
+{
+ LOGMASKED(LOG_TPC_WR, "%s: Next Data Register A, tpc_ndra_w = %02x\n", machine().describe_context(), data);
+}
+
+uint8_t sh7021_device::tpc_ndra_alt_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_TPC_RD, "%s: Next Data Register A (alt. address), tpc_ndra_alt_r: %02x\n", machine().describe_context(), 0);//m_tpc.ndra);
+ return 0;//m_tpc.ndra;
+}
+
+void sh7021_device::tpc_ndra_alt_w(uint8_t data)
+{
+ LOGMASKED(LOG_TPC_WR, "%s: Next Data Register A (alt. address), tpc_ndra_alt_w = %02x\n", machine().describe_context(), data);
+}
+
+uint8_t sh7021_device::tpc_ndrb_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_TPC_RD, "%s: Next Data Register B, tpc_ndrb_r: %02x\n", machine().describe_context(), 0);//m_tpc.ndrb);
+ return 0;//m_tpc.ndrb;
+}
+
+void sh7021_device::tpc_ndrb_w(uint8_t data)
+{
+ LOGMASKED(LOG_TPC_WR, "%s: Next Data Register B, tpc_ndrb_w = %02x\n", machine().describe_context(), data);
+}
+
+uint8_t sh7021_device::tpc_ndrb_alt_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_TPC_RD, "%s: Next Data Register B (alt. address), tpc_ndrb_alt_r: %02x\n", machine().describe_context(), 0);//m_tpc.ndrb);
+ return 0;//m_tpc.ndrb;
+}
+
+void sh7021_device::tpc_ndrb_alt_w(uint8_t data)
+{
+ LOGMASKED(LOG_TPC_WR, "%s: Next Data Register B (alt. address), tpc_ndrb_alt_w = %02x\n", machine().describe_context(), data);
+}
+
+
+// Watchdog Timer (WDT)
+
+uint8_t sh7021_device::wdt_tcsr_r()
+{
+ return m_wdt.tcsr;
+}
+
+void sh7021_device::wdt_tcsr_w(uint8_t data)
+{
+ m_wdt.tcsr = data;
+}
+
+uint8_t sh7021_device::wdt_tcnt_r()
+{
+ return 0;
+}
+
+void sh7021_device::wdt_tcnt_w(uint8_t data)
+{
+}
+
+uint8_t sh7021_device::wdt_rstcsr_r()
+{
+ return 0;
+}
+
+void sh7021_device::wdt_rstcsr_w(uint8_t data)
+{
+
+}
+
+
+// Serial Communication Interface (SCI)
+
+template TIMER_CALLBACK_MEMBER(sh7021_device::sh7021_sci_callback<0>);
+template TIMER_CALLBACK_MEMBER(sh7021_device::sh7021_sci_callback<1>);
+
+template<int Which>
+TIMER_CALLBACK_MEMBER(sh7021_device::sh7021_sci_callback)
+{
+ LOGMASKED(LOG_DMA_WR, "Setting SCI interrupt on channel %d\n", Which);
+ m_sci[Which].ssr |= (1 << 7) | (1 << 2);
+ recalc_irq();
+}
+
+template uint8_t sh7021_device::sci_smr_r<0>();
+template uint8_t sh7021_device::sci_smr_r<1>();
+
+template <int Channel>
+uint8_t sh7021_device::sci_smr_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_SCI_RD, "%s: Serial Mode Register %d, sci_smr_r: %02x\n", machine().describe_context(), Channel, m_sci[Channel].smr);
+ return m_sci[Channel].smr;
+}
+
+template void sh7021_device::sci_smr_w<0>(uint8_t data);
+template void sh7021_device::sci_smr_w<1>(uint8_t data);
+
+template <int Channel>
+void sh7021_device::sci_smr_w(uint8_t data)
+{
+ LOGMASKED(LOG_SCI_WR, "%s: Serial Mode Register %d, sci_smr_w = %02x\n", machine().describe_context(), Channel, data);
+ LOGMASKED(LOG_SCI_WR, "%s: Communication Mode: %s\n", machine().describe_context(), BIT(data, 7) ? "Clocked synchronous" : "Asynchronous");
+ LOGMASKED(LOG_SCI_WR, "%s: Character Length: %d\n", machine().describe_context(), BIT(data, 6) ? 7 : 8);
+ LOGMASKED(LOG_SCI_WR, "%s: Parity Enable: %d\n", machine().describe_context(), BIT(data, 5));
+ LOGMASKED(LOG_SCI_WR, "%s: Parity Mode: %s\n", machine().describe_context(), BIT(data, 4) ? "Odd" : "Even");
+ LOGMASKED(LOG_SCI_WR, "%s: Stop Bits: %d\n", machine().describe_context(), BIT(data, 3) ? 2 : 1);
+ LOGMASKED(LOG_SCI_WR, "%s: Multiprocessor Mode: %d\n", machine().describe_context(), BIT(data, 2));
+ LOGMASKED(LOG_SCI_WR, "%s: Clock Divider: %d\n", machine().describe_context(), 1 << ((data & 3) * 2));
+ m_sci[Channel].smr = data;
+}
+
+template uint8_t sh7021_device::sci_brr_r<0>();
+template uint8_t sh7021_device::sci_brr_r<1>();
+
+template <int Channel>
+uint8_t sh7021_device::sci_brr_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_SCI_RD, "%s: Bit Rate Register %d, sci_brr_r: %02x\n", machine().describe_context(), Channel, m_sci[Channel].brr);
+ return m_sci[Channel].brr;
+}
+
+template void sh7021_device::sci_brr_w<0>(uint8_t data);
+template void sh7021_device::sci_brr_w<1>(uint8_t data);
+
+template <int Channel>
+void sh7021_device::sci_brr_w(uint8_t data)
+{
+ LOGMASKED(LOG_SCI_WR, "%s: Bit Rate Register %d, sci_brr_w = %02x\n", machine().describe_context(), Channel, data);
+ m_sci[Channel].brr = data;
+}
+
+template uint8_t sh7021_device::sci_scr_r<0>();
+template uint8_t sh7021_device::sci_scr_r<1>();
+
+template <int Channel>
+uint8_t sh7021_device::sci_scr_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_SCI_RD, "%s: Serial Control Register %d, sci_scr_r: %02x\n", machine().describe_context(), Channel, m_sci[Channel].scr);
+ return m_sci[Channel].scr;
+}
+
+template void sh7021_device::sci_scr_w<0>(uint8_t data);
+template void sh7021_device::sci_scr_w<1>(uint8_t data);
+
+template <int Channel>
+void sh7021_device::sci_scr_w(uint8_t data)
+{
+ LOGMASKED(LOG_SCI_WR, "%s: Serial Control Register %d, sci_scr_w = %02x\n", machine().describe_context(), Channel, data);
+ LOGMASKED(LOG_SCI_WR, "%s: Transmit-Empty Interrupt Enable: %d\n", machine().describe_context(), BIT(data, 7));
+ LOGMASKED(LOG_SCI_WR, "%s: Receive-Full Interrupt Enable: %d\n", machine().describe_context(), BIT(data, 6));
+ LOGMASKED(LOG_SCI_WR, "%s: Transmit Enable: %d\n", machine().describe_context(), BIT(data, 5));
+ LOGMASKED(LOG_SCI_WR, "%s: Receive Enable: %d\n", machine().describe_context(), BIT(data, 4));
+ LOGMASKED(LOG_SCI_WR, "%s: Multiprocessor Interrupt Enable: %d\n", machine().describe_context(), BIT(data, 3));
+ LOGMASKED(LOG_SCI_WR, "%s: Transmit-End Interrupt Enable: %d\n", machine().describe_context(), BIT(data, 2));
+ LOGMASKED(LOG_SCI_WR, "%s: Clock Enable Mode: %d%d\n", machine().describe_context(), BIT(data, 1), BIT(data, 0));
+ m_sci[Channel].scr = data;
+}
+
+template uint8_t sh7021_device::sci_tdr_r<0>();
+template uint8_t sh7021_device::sci_tdr_r<1>();
+
+template <int Channel>
+uint8_t sh7021_device::sci_tdr_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_SCI_RD, "%s: Transmit Data Register %d, sci_tdr_r: %02x\n", machine().describe_context(), Channel, m_sci[Channel].tdr);
+ return m_sci[Channel].tdr;
+}
+
+template void sh7021_device::sci_tdr_w<0>(uint8_t data);
+template void sh7021_device::sci_tdr_w<1>(uint8_t data);
+
+template <int Channel>
+void sh7021_device::sci_tdr_w(uint8_t data)
+{
+ LOGMASKED(LOG_SCI_WR, "%s: Transmit Data Register %d, sci_tdr_w = %02x\n", machine().describe_context(), Channel, data);
+ m_sci[Channel].tdr = data;
+}
+
+template uint8_t sh7021_device::sci_ssr_r<0>();
+template uint8_t sh7021_device::sci_ssr_r<1>();
+
+template <int Channel>
+uint8_t sh7021_device::sci_ssr_r()
+{
+ if (!machine().side_effects_disabled())
+ {
+ LOGMASKED(LOG_SCI_RD, "%s: Serial Status Register %d, sci_ssr_r: %02x\n", machine().describe_context(), Channel, m_sci[Channel].ssr);
+ LOGMASKED(LOG_SCI_RD, "%s: Transmit Empty Flag: %d\n", machine().describe_context(), Channel, BIT(m_sci[Channel].ssr, 7));
+ LOGMASKED(LOG_SCI_RD, "%s: Receiver Full Flag: %d\n", machine().describe_context(), Channel, BIT(m_sci[Channel].ssr, 6));
+ LOGMASKED(LOG_SCI_RD, "%s: Overrun Error Flag: %d\n", machine().describe_context(), Channel, BIT(m_sci[Channel].ssr, 5));
+ LOGMASKED(LOG_SCI_RD, "%s: Framing Error Flag: %d\n", machine().describe_context(), Channel, BIT(m_sci[Channel].ssr, 4));
+ LOGMASKED(LOG_SCI_RD, "%s: Parity Error Flag: %d\n", machine().describe_context(), Channel, BIT(m_sci[Channel].ssr, 3));
+ LOGMASKED(LOG_SCI_RD, "%s: Transmit End Flag: %d\n", machine().describe_context(), Channel, BIT(m_sci[Channel].ssr, 2));
+ LOGMASKED(LOG_SCI_RD, "%s: Multiprocessor Bit Flag: %d\n", machine().describe_context(), Channel, BIT(m_sci[Channel].ssr, 1));
+ LOGMASKED(LOG_SCI_RD, "%s: Multiprocessor Bit Transfer Flag: %d\n", machine().describe_context(), Channel, BIT(m_sci[Channel].ssr, 0));
+
+ m_sci[Channel].ssr_read |= m_sci[Channel].ssr & 0xf8;
+ }
+
+ return (m_sci[Channel].ssr & 0xf9) | 0x04;
+}
+
+template void sh7021_device::sci_ssr_w<0>(uint8_t data);
+template void sh7021_device::sci_ssr_w<1>(uint8_t data);
+
+template <int Channel>
+void sh7021_device::sci_ssr_w(uint8_t data)
+{
+ LOGMASKED(LOG_SCI_WR, "%s: Serial Status Register %d, sci_ssr_w = %02x\n", machine().describe_context(), Channel, data);
+ if (!BIT(data, 7) && BIT(m_sci[Channel].ssr, 7) && BIT(m_sci[Channel].ssr_read, 7))
+ {
+ // Clear TDR-Empty Flag and Transmit End Flag
+ m_sci[Channel].ssr_read &= ~(1 << 7);
+ m_sci[Channel].ssr &= ~(1 << 7);
+ m_sci[Channel].ssr &= ~(1 << 2);
+ }
+
+ if (!BIT(data, 6) && BIT(m_sci[Channel].ssr, 6) && BIT(m_sci[Channel].ssr_read, 6))
+ {
+ // Clear RDR-Full Flag
+ m_sci[Channel].ssr_read &= ~(1 << 6);
+ m_sci[Channel].ssr &= ~(1 << 6);
+ }
+
+ if (!BIT(data, 5) && BIT(m_sci[Channel].ssr, 5) && BIT(m_sci[Channel].ssr_read, 5))
+ {
+ // Clear Overrun Error Flag
+ m_sci[Channel].ssr_read &= ~(1 << 5);
+ m_sci[Channel].ssr &= ~(1 << 5);
+ }
+
+ if (!BIT(data, 4) && BIT(m_sci[Channel].ssr, 4) && BIT(m_sci[Channel].ssr_read, 4))
+ {
+ // Clear Framing Error Flag
+ m_sci[Channel].ssr_read &= ~(1 << 4);
+ m_sci[Channel].ssr &= ~(1 << 4);
+ }
+
+ if (!BIT(data, 3) && BIT(m_sci[Channel].ssr, 3) && BIT(m_sci[Channel].ssr_read, 3))
+ {
+ // Clear Parity Error Flag
+ m_sci[Channel].ssr_read &= ~(1 << 3);
+ m_sci[Channel].ssr &= ~(1 << 3);
+ }
+
+ m_sci[Channel].ssr &= 0xfe;
+ m_sci[Channel].ssr |= data & 1;
+}
+
+template uint8_t sh7021_device::sci_rdr_r<0>();
+template uint8_t sh7021_device::sci_rdr_r<1>();
+
+template <int Channel>
+uint8_t sh7021_device::sci_rdr_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_SCI_RD, "%s: Receive Data Register %d, sci_rdr_r: %02x\n", machine().describe_context(), Channel, m_sci[Channel].rdr);
+ return m_sci[Channel].rdr;
+}
+
+
+// Pin Function Controller (PFC)
+
+void sh7021_device::write_padr(uint16_t data)
+{
+ LOGMASKED(LOG_PFC_WR, "%s: Port A Input write: write_padr: %04x\n", machine().describe_context(), data);
+ m_pfc.padr_in = data;
+}
+
+void sh7021_device::write_pbdr(uint16_t data)
+{
+ LOGMASKED(LOG_PFC_WR, "%s: Port B Input write: write_pbdr: %04x\n", machine().describe_context(), data);
+ m_pfc.pbdr_in = data;
+}
+
+template void sh7021_device::write_padr_bit< 0>(int state);
+template void sh7021_device::write_padr_bit< 1>(int state);
+template void sh7021_device::write_padr_bit< 2>(int state);
+template void sh7021_device::write_padr_bit< 3>(int state);
+template void sh7021_device::write_padr_bit< 4>(int state);
+template void sh7021_device::write_padr_bit< 5>(int state);
+template void sh7021_device::write_padr_bit< 6>(int state);
+template void sh7021_device::write_padr_bit< 7>(int state);
+template void sh7021_device::write_padr_bit< 8>(int state);
+template void sh7021_device::write_padr_bit< 9>(int state);
+template void sh7021_device::write_padr_bit<10>(int state);
+template void sh7021_device::write_padr_bit<11>(int state);
+template void sh7021_device::write_padr_bit<12>(int state);
+template void sh7021_device::write_padr_bit<13>(int state);
+template void sh7021_device::write_padr_bit<14>(int state);
+template void sh7021_device::write_padr_bit<15>(int state);
+
+template <int Line>
+void sh7021_device::write_padr_bit(int state)
+{
+ LOGMASKED(LOG_PFC_WR, "%s: Port A Bit %d Input write: write_padr_bit: %d\n", machine().describe_context(), Line, state);
+ m_pfc.padr_in = (m_pfc.padr_in & ~(1 << Line)) | (state << Line);
+}
+
+template void sh7021_device::write_pbdr_bit< 0>(int state);
+template void sh7021_device::write_pbdr_bit< 1>(int state);
+template void sh7021_device::write_pbdr_bit< 2>(int state);
+template void sh7021_device::write_pbdr_bit< 3>(int state);
+template void sh7021_device::write_pbdr_bit< 4>(int state);
+template void sh7021_device::write_pbdr_bit< 5>(int state);
+template void sh7021_device::write_pbdr_bit< 6>(int state);
+template void sh7021_device::write_pbdr_bit< 7>(int state);
+template void sh7021_device::write_pbdr_bit< 8>(int state);
+template void sh7021_device::write_pbdr_bit< 9>(int state);
+template void sh7021_device::write_pbdr_bit<10>(int state);
+template void sh7021_device::write_pbdr_bit<11>(int state);
+template void sh7021_device::write_pbdr_bit<12>(int state);
+template void sh7021_device::write_pbdr_bit<13>(int state);
+template void sh7021_device::write_pbdr_bit<14>(int state);
+template void sh7021_device::write_pbdr_bit<15>(int state);
+
+template <int Line>
+void sh7021_device::write_pbdr_bit(int state)
+{
+ LOGMASKED(LOG_PFC_WR, "%s: Port B Bit %d Input write: write_pbdr_bit: %d\n", machine().describe_context(), Line, state);
+ m_pfc.pbdr_in = (m_pfc.pbdr_in & ~(1 << Line)) | (state << Line);
+}
+
+uint16_t sh7021_device::pfc_paior_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_PFC_RD, "%s: Port A I/O (Direction) Register, pfc_paior_r: %04x\n", machine().describe_context(), m_pfc.paior);
+ return m_pfc.paior;
+}
+
+void sh7021_device::pfc_paior_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ LOGMASKED(LOG_PFC_WR, "%s: Port A I/O (Direction) Register, pfc_paior_w = %04x & %04x\n", machine().describe_context(), data, mem_mask);
+ COMBINE_DATA(&m_pfc.paior);
+}
+
+uint16_t sh7021_device::pfc_pacr1_r()
+{
+ static constexpr uint16_t PACR1_R_MASK = 0x0002;
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_PFC_RD, "%s: Port A Control Register 1, pfc_pacr1_r: %04x\n", machine().describe_context(), m_pfc.pacr1);
+ return m_pfc.pacr1 | PACR1_R_MASK;
+}
+
+void sh7021_device::pfc_pacr1_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ static constexpr uint16_t PACR1_W_MASK = 0xfffd;
+ LOGMASKED(LOG_PFC_WR, "%s: Port A Control Register 1, pfc_pacr1_w = %04x & %04x\n", machine().describe_context(), data, mem_mask);
+ COMBINE_DATA(&m_pfc.pacr1);
+ const uint16_t pacr1_masked = m_pfc.pacr1 & PACR1_W_MASK;
+ for (int i = 0; i < 8; i++)
+ {
+ int bit = i << 1;
+ m_pfc.pafunc[8 + i] = (pacr1_masked >> bit) & 3;
+ }
+}
+
+uint16_t sh7021_device::pfc_pacr2_r()
+{
+ static constexpr uint16_t PACR2_R_MASK = 0xaa00;
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_PFC_RD, "%s: Port A Control Register 2, pfc_pacr2_r: %04x\n", machine().describe_context(), m_pfc.pacr2);
+ return m_pfc.pacr2 | PACR2_R_MASK;
+}
+
+void sh7021_device::pfc_pacr2_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ static constexpr uint16_t PACR2_W_MASK = 0x55ff;
+ LOGMASKED(LOG_PFC_WR, "%s: Port A Control Register 2, pfc_pacr2_w = %04x & %04x\n", machine().describe_context(), data, mem_mask);
+ COMBINE_DATA(&m_pfc.pacr2);
+ const uint16_t pacr2_masked = m_pfc.pacr2 & PACR2_W_MASK;
+ for (int i = 0; i < 8; i++)
+ {
+ int bit = i << 1;
+ m_pfc.pafunc[i] = (pacr2_masked >> bit) & 3;
+ }
+}
+
+uint16_t sh7021_device::pfc_pbior_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_PFC_RD, "%s: Port B I/O (Direction) Register, pfc_pbior_r: %04x\n", machine().describe_context(), m_pfc.pbior);
+ return m_pfc.pbior;
+}
+
+void sh7021_device::pfc_pbior_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ LOGMASKED(LOG_PFC_WR, "%s: Port B I/O (Direction) Register, pfc_pbior_w = %04x & %04x\n", machine().describe_context(), data, mem_mask);
+ COMBINE_DATA(&m_pfc.pbior);
+}
+
+uint16_t sh7021_device::pfc_pbcr1_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_PFC_RD, "%s: Port B Control Register 1, pfc_pbcr1_r: %04x\n", machine().describe_context(), m_pfc.pbcr1);
+ return m_pfc.pbcr1;
+}
+
+void sh7021_device::pfc_pbcr1_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ LOGMASKED(LOG_PFC_WR, "%s: Port B Control Register 1, pfc_pbcr1_w = %04x & %04x\n", machine().describe_context(), data, mem_mask);
+ COMBINE_DATA(&m_pfc.pbcr1);
+ for (int i = 0; i < 8; i++)
+ {
+ int bit = i << 1;
+ m_pfc.pbfunc[8 + i] = (m_pfc.pbcr1 >> bit) & 3;
+ }
+}
+
+uint16_t sh7021_device::pfc_pbcr2_r()
+{
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_PFC_RD, "%s: Port B Control Register 2, pfc_pbcr2_r: %04x\n", machine().describe_context(), m_pfc.pbcr2);
+ return m_pfc.pbcr2;
+}
+
+void sh7021_device::pfc_pbcr2_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ LOGMASKED(LOG_PFC_WR, "%s: Port B Control Register 2, pfc_pbcr2_w = %04x & %04x\n", machine().describe_context(), data, mem_mask);
+ COMBINE_DATA(&m_pfc.pbcr2);
+ for (int i = 0; i < 8; i++)
+ {
+ int bit = i << 1;
+ m_pfc.pbfunc[i] = (m_pfc.pbcr2 >> bit) & 3;
+ }
+}
+
+uint16_t sh7021_device::pfc_padr_r()
+{
+ const uint16_t data = ((m_pfc.padr_in & ~m_pfc.paior) | (m_pfc.padr & m_pfc.paior)) & m_pfc.pa_gpio_mask;
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_PFC_RD, "%s: Port A Data Register, pfc_padr_r: %04x ((%04x & ~%04x) | (%04x & %04x)) & %04x\n", machine().describe_context(), data, m_pfc.padr_in, m_pfc.paior, m_pfc.padr, m_pfc.paior, m_pfc.pa_gpio_mask);
+ return data;
+}
+
+void sh7021_device::pfc_padr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ LOGMASKED(LOG_PFC_WR, "%s: Port A Data Register, pfc_padr_w = %04x & %04x\n", machine().describe_context(), data, mem_mask);
+ const uint16_t old = m_pfc.padr;
+ COMBINE_DATA(&m_pfc.padr);
+ const uint16_t changed = m_pfc.padr ^ old;
+
+ uint16_t output_mask = m_pfc.paior & m_pfc.pa_gpio_mask;
+ for (int i = 0; i < 16; i++)
+ {
+ if (BIT(output_mask, i) && BIT(changed, i))
+ {
+ m_pa_bit_out[i](BIT(m_pfc.padr, i));
+ }
+ }
+
+ if (output_mask)
+ {
+ m_pa_out(m_pfc.padr & output_mask, output_mask);
+ }
+}
+
+uint16_t sh7021_device::pfc_pbdr_r()
+{
+ const uint16_t data = ((m_pfc.pbdr_in & ~m_pfc.pbior) | (m_pfc.padr & m_pfc.pbior)) & m_pfc.pa_gpio_mask;
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_PFC_RD, "%s: Port B Data Register, pfc_pbdr_r: %04x\n", machine().describe_context(), data);
+ return data;
+}
+
+void sh7021_device::pfc_pbdr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ LOGMASKED(LOG_PFC_WR, "%s: Port B Data Register, pfc_pbdr_w = %04x & %04x\n", machine().describe_context(), data, mem_mask);
+ const uint16_t old = m_pfc.pbdr;
+ COMBINE_DATA(&m_pfc.pbdr);
+ const uint16_t changed = m_pfc.pbdr ^ old;
+
+ uint16_t output_mask = m_pfc.pbior;
+ for (int i = 0; i < 16; i++)
+ {
+ if (m_pfc.pbfunc[i] != 0)
+ {
+ output_mask &= ~(1 << i);
+ }
+ else if (BIT(changed, i))
+ {
+ m_pb_bit_out[i](BIT(m_pfc.pbdr, i));
+ }
+ }
+
+ if (output_mask)
+ {
+ m_pb_out(m_pfc.pbdr & output_mask, output_mask);
+ }
}
-uint16_t sh2a_sh7021_device::sh7021_r(offs_t offset)
+uint16_t sh7021_device::pfc_cascr_r()
{
- return m_sh7021_regs[offset];
+ if (!machine().side_effects_disabled())
+ LOGMASKED(LOG_PFC_RD, "%s: Column Address Strobe Pin Control Register, pfc_cascr_r: %04x\n", machine().describe_context(), m_pfc.cascr);
+ return m_pfc.cascr;
}
-void sh2a_sh7021_device::sh7021_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+void sh7021_device::pfc_cascr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
- COMBINE_DATA(&m_sh7021_regs[offset]);
+ LOGMASKED(LOG_PFC_WR, "%s: Column Address Strobe Pin Control Register, pfc_cascr_w = %04x & %04x\n", machine().describe_context(), data, mem_mask);
+ COMBINE_DATA(&m_pfc.cascr);
}
diff --git a/src/devices/cpu/sh/sh7021.h b/src/devices/cpu/sh/sh7021.h
index dff35e72eab..8540b2bbb62 100644
--- a/src/devices/cpu/sh/sh7021.h
+++ b/src/devices/cpu/sh/sh7021.h
@@ -1,5 +1,11 @@
// license:BSD-3-Clause
-// copyright-holders:Angelo Salese
+// copyright-holders:Ryan Holtz
+/*****************************************************************************
+ *
+ * sh7021.h
+ * Portable Hitachi SH-1 (model SH7021) emulator
+ *
+ *****************************************************************************/
#ifndef MAME_CPU_SH_SH7021_H
#define MAME_CPU_SH_SH7021_H
@@ -8,45 +14,321 @@
#include "sh2.h"
-class sh2a_sh7021_device : public sh2_device
+class sh7021_device : public sh2_device
{
public:
- sh2a_sh7021_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+ // construction/destruction
+ sh7021_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+ void write_padr(uint16_t data);
+ void write_pbdr(uint16_t data);
+ template <int Line> void write_padr_bit(int state);
+ template <int Line> void write_pbdr_bit(int state);
protected:
virtual void device_start() override;
virtual void device_reset() override;
-private:
- void sh7021_map(address_map &map);
+ virtual void execute_run() override;
+
+ void execute_dma(int ch);
+ void execute_peripherals(int peripheral_cycles);
+
+ // Interrupt Controller (INTC)
+ void intc_ipra_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t intc_ipra_r();
+ void intc_iprb_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t intc_iprb_r();
+ void intc_iprc_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t intc_iprc_r();
+ void intc_iprd_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t intc_iprd_r();
+ void intc_ipre_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t intc_ipre_r();
+ void intc_icr_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t intc_icr_r();
+
+ // User Break Controller (UBC)
+ uint16_t ubc_barh_r();
+ void ubc_barh_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t ubc_barl_r();
+ void ubc_barl_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t ubc_bamrh_r();
+ void ubc_bamrh_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t ubc_bamrl_r();
+ void ubc_bamrl_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t ubc_bbr_r();
+ void ubc_bbr_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+
+ // Bus State Controller (BSC)
+ uint16_t bsc_bcr_r();
+ void bsc_bcr_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t bsc_wcr1_r();
+ void bsc_wcr1_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t bsc_wcr2_r();
+ void bsc_wcr2_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t bsc_wcr3_r();
+ void bsc_wcr3_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t bsc_dcr_r();
+ void bsc_dcr_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t bsc_pcr_r();
+ void bsc_pcr_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t bsc_rcr_r();
+ void bsc_rcr_w(uint16_t data);
+ uint16_t bsc_rtcsr_r();
+ void bsc_rtcsr_w(uint16_t data);
+ uint16_t bsc_rtcnt_r();
+ void bsc_rtcnt_w(uint16_t data);
+ uint16_t bsc_rtcor_r();
+ void bsc_rtcor_w(uint16_t data);
- uint32_t dma_sar0_r();
- void dma_sar0_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
- uint32_t dma_dar0_r();
- void dma_dar0_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
+ // DMA Controller (DMAC)
+ template <int Channel> uint32_t dma_sar_r();
+ template <int Channel> void dma_sar_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0U);
+ template <int Channel> uint32_t dma_dar_r();
+ template <int Channel> void dma_dar_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0U);
+ template <int Channel> uint16_t dma_tcr_r();
+ template <int Channel> void dma_tcr_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ template <int Channel> uint16_t dma_chcr_r();
+ template <int Channel> void dma_chcr_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
uint16_t dmaor_r();
void dmaor_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
- uint16_t dma_tcr0_r();
- void dma_tcr0_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
- uint16_t dma_chcr0_r();
- void dma_chcr0_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
- uint16_t sh7021_r(offs_t offset);
- void sh7021_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
- void sh7021_dma_exec(int ch);
+ // 16-Bit Integrated-Timer Pulse Unit (ITU)
+ uint8_t itu_tstr_r();
+ void itu_tstr_w(uint8_t data);
+ uint8_t itu_tsnc_r();
+ void itu_tsnc_w(uint8_t data);
+ uint8_t itu_tmdr_r();
+ void itu_tmdr_w(uint8_t data);
+ uint8_t itu_tfcr_r();
+ void itu_tfcr_w(uint8_t data);
+ uint8_t itu_tocr_r();
+ void itu_tocr_w(uint8_t data);
+
+ template <int Channel> uint8_t itu_tcr_r();
+ template <int Channel> void itu_tcr_w(uint8_t data);
+ template <int Channel> uint8_t itu_tior_r();
+ template <int Channel> void itu_tior_w(uint8_t data);
+ template <int Channel> uint8_t itu_tier_r();
+ template <int Channel> void itu_tier_w(uint8_t data);
+ template <int Channel> uint8_t itu_tsr_r();
+ template <int Channel> void itu_tsr_w(uint8_t data);
+ template <int Channel> uint16_t itu_tcnt_r();
+ template <int Channel> void itu_tcnt_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ template <int Channel> uint16_t itu_gra_r();
+ template <int Channel> void itu_gra_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ template <int Channel> uint16_t itu_grb_r();
+ template <int Channel> void itu_grb_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ template <int Channel> uint16_t itu_bra_r();
+ template <int Channel> void itu_bra_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ template <int Channel> uint16_t itu_brb_r();
+ template <int Channel> void itu_brb_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+
+ // Programmable Timing Pattern Controller (TPC)
+ uint8_t tpc_tpmr_r();
+ void tpc_tpmr_w(uint8_t data);
+ uint8_t tpc_tpcr_r();
+ void tpc_tpcr_w(uint8_t data);
+ uint8_t tpc_ndera_r();
+ void tpc_ndera_w(uint8_t data);
+ uint8_t tpc_nderb_r();
+ void tpc_nderb_w(uint8_t data);
+ uint8_t tpc_ndra_r();
+ void tpc_ndra_w(uint8_t data);
+ uint8_t tpc_ndra_alt_r();
+ void tpc_ndra_alt_w(uint8_t data);
+ uint8_t tpc_ndrb_r();
+ void tpc_ndrb_w(uint8_t data);
+ uint8_t tpc_ndrb_alt_r();
+ void tpc_ndrb_alt_w(uint8_t data);
+
+ // Watchdog Timer (WDT)
+ uint8_t wdt_tcsr_r(); // TODO: Readable only in 8-bit mode
+ void wdt_tcsr_w(uint8_t data); // TODO: Writable only in 16-bit mode
+ uint8_t wdt_tcnt_r(); // TODO: Readable only in 8-bit mode
+ void wdt_tcnt_w(uint8_t data); // TODO: Writable only in 16-bit mode
+ uint8_t wdt_rstcsr_r();
+ void wdt_rstcsr_w(uint8_t data); // TODO: Writable only in 16-bit mode
+
+ // Serial Communication Interface (SCI)
+ template <int Channel> uint8_t sci_smr_r();
+ template <int Channel> void sci_smr_w(uint8_t data);
+ template <int Channel> uint8_t sci_brr_r();
+ template <int Channel> void sci_brr_w(uint8_t data);
+ template <int Channel> uint8_t sci_scr_r();
+ template <int Channel> void sci_scr_w(uint8_t data);
+ template <int Channel> uint8_t sci_tdr_r();
+ template <int Channel> void sci_tdr_w(uint8_t data);
+ template <int Channel> uint8_t sci_ssr_r();
+ template <int Channel> void sci_ssr_w(uint8_t data);
+ template <int Channel> uint8_t sci_rdr_r();
+
+ // Pin Function Controller (PFC)
+ uint16_t pfc_paior_r();
+ void pfc_paior_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t pfc_pacr1_r();
+ void pfc_pacr1_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t pfc_pacr2_r();
+ void pfc_pacr2_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t pfc_pbior_r();
+ void pfc_pbior_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t pfc_pbcr1_r();
+ void pfc_pbcr1_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t pfc_pbcr2_r();
+ void pfc_pbcr2_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t pfc_padr_r();
+ void pfc_padr_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t pfc_pbdr_r();
+ void pfc_pbdr_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+ uint16_t pfc_cascr_r();
+ void pfc_cascr_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
- uint16_t m_sh7021_regs[0x200];
+ void internal_map(address_map &map);
+
+ void recalc_irq();
+
+ virtual uint8_t read_byte(offs_t offset) override;
+ virtual uint16_t read_word(offs_t offset) override;
+ virtual uint32_t read_long(offs_t offset) override;
+ virtual uint16_t decrypted_read_word(offs_t offset) override;
+ virtual void write_byte(offs_t offset, uint8_t data) override;
+ virtual void write_word(offs_t offset, uint16_t data) override;
+ virtual void write_long(offs_t offset, uint32_t data) override;
+
+ // Interrupt Controller (INTC)
+ uint16_t m_ipra = 0;
+ uint16_t m_iprb = 0;
+ uint16_t m_iprc = 0;
+ uint16_t m_iprd = 0;
+ uint16_t m_ipre = 0;
+ uint16_t m_icr = 0;
+
+ // User Break Controller (UBC)
struct
{
- uint32_t sar; /**< Source Address Register */
- uint32_t dar; /**< Destination Address Register */
- uint16_t tcr; /**< Transfer Count Register */
- uint16_t chcr; /**< Channel Control Register */
+ uint16_t barh = 0;
+ uint16_t barl = 0;
+ uint16_t bamrh = 0;
+ uint16_t bamrl = 0;
+ uint16_t bbr = 0;
+ } m_ubc;
+
+ // Bus State Controller (BSC)
+ struct
+ {
+ uint16_t bcr = 0;
+ uint16_t wcr1 = 0;
+ uint16_t wcr2 = 0;
+ uint16_t wcr3 = 0;
+ uint16_t dcr = 0;
+ uint16_t pcr = 0;
+ uint8_t rcr = 0;
+ uint8_t rtcsr = 0;
+ bool rtcsr_read = false;
+ uint8_t rtcnt = 0;
+ uint8_t rtcor = 0;
+ } m_bsc;
+
+ // DMA Controller (DMAC)
+ struct
+ {
+ uint32_t sar = 0; // Source Address Register
+ uint32_t dar = 0; // Destination Address Register
+ uint16_t tcr = 0; // Transfer Count Register
+ uint16_t chcr = 0; // Channel Control Register
} m_dma[4];
+ uint16_t m_dmaor = 0; // DMA Operation Register (status flags)
+ int m_dma_cycles;
+
+ // 16-Bit Integrated-Timer Pulse Unit (ITU)
+ struct
+ {
+ uint8_t tstr = 0;
+ uint8_t tsnc = 0;
+ uint8_t tmdr = 0;
+ uint8_t tfcr = 0;
+ uint8_t tocr = 0;
+
+ struct
+ {
+ uint8_t tcr = 0;
+ uint8_t tior = 0;
+ uint8_t tier = 0;
+ uint8_t tsr = 0;
+ uint16_t tcnt = 0;
+ uint16_t gra = 0;
+ uint16_t grb = 0;
+ uint16_t bra = 0;
+ uint16_t brb = 0;
+ emu_timer *et = nullptr;
+ } timer[5];
+ } m_itu;
+
+ void start_timer(int i);
+
+ template<int which> TIMER_CALLBACK_MEMBER(sh7021_timer_callback);
+ template<int which> TIMER_CALLBACK_MEMBER(sh7021_sci_callback);
+
+ // Programmable Timing Pattern Controller (TPC)
+ struct
+ {
+ uint8_t tpmr = 0;
+ uint8_t tpcr = 0;
+ uint8_t ndera = 0;
+ uint8_t nderb = 0;
+ uint8_t ndra = 0;
+ uint8_t ndrb = 0;
+ } m_tpc;
- uint16_t m_dmaor; /**< DMA Operation Register (status flags) */
+ // Watchdog Timer (WDT)
+ struct
+ {
+ uint8_t tcsr = 0;
+ uint8_t tcnt = 0;
+ uint8_t rstcsr = 0;
+ } m_wdt;
+
+ // Serial Communication Interface (SCI)
+ struct
+ {
+ uint8_t smr = 0;
+ uint8_t brr = 0;
+ uint8_t scr = 0;
+ uint8_t tsr = 0;
+ uint8_t tdr = 0;
+ uint8_t ssr = 0;
+ uint8_t ssr_read = 0;
+ uint8_t rsr = 0;
+ uint8_t rdr = 0;
+ emu_timer *et = nullptr;
+ } m_sci[2];
+
+ // Pin Function Controller (PFC)
+ struct
+ {
+ uint16_t paior = 0;
+ uint16_t pacr1 = 0;
+ uint16_t pacr2 = 0;
+ uint16_t pbior = 0;
+ uint16_t pbcr1 = 0;
+ uint16_t pbcr2 = 0;
+ uint16_t padr = 0;
+ uint16_t pbdr = 0;
+ uint16_t padr_in = 0;
+ uint16_t pbdr_in = 0;
+ uint16_t cascr = 0;
+ uint8_t pafunc[16];
+ uint8_t pbfunc[16];
+ uint16_t pa_gpio_mask = 0;
+ uint16_t pb_gpio_mask = 0;
+ } m_pfc;
+ devcb_write16 m_pa_out;
+ devcb_write16 m_pb_out;
+ devcb_write_line::array<16> m_pa_bit_out;
+ devcb_write_line::array<16> m_pb_bit_out;
};
-DECLARE_DEVICE_TYPE(SH2A_SH7021, sh2a_sh7021_device)
+DECLARE_DEVICE_TYPE(SH7021, sh7021_device)
#endif // MAME_CPU_SH_SH7021_H
diff --git a/src/devices/cpu/sh/sh7604.cpp b/src/devices/cpu/sh/sh7604.cpp
index af017bc14fa..7da7ef0badd 100644
--- a/src/devices/cpu/sh/sh7604.cpp
+++ b/src/devices/cpu/sh/sh7604.cpp
@@ -2,7 +2,7 @@
// copyright-holders:Juergen Buchmueller, R. Belmont
/*****************************************************************************
*
- * sh2.c
+ * sh7604.cpp
* Portable Hitachi SH-2 (SH7600 family) emulator
*
* This work is based on <tiraniddo@hotmail.com> C/C++ implementation of
@@ -67,7 +67,7 @@ sh2_sh7604_device::sh2_sh7604_device(const machine_config &mconfig, const char *
m_irq_level.frc = m_irq_level.sci = m_irq_level.divu = m_irq_level.dmac = m_irq_level.wdt = 0;
- for(int i = 0; i < 2; i++)
+ for (int i = 0; i < 2; i++)
m_dmac[i].drcr = m_dmac[i].sar = m_dmac[i].dar = m_dmac[i].tcr = m_dmac[i].chcr = 0;
}
@@ -182,7 +182,7 @@ void sh2_sh7604_device::device_reset()
m_frc_base = 0;
m_frt_input = 0;
- for ( int i = 0; i < 2; i++ )
+ for (int i = 0; i < 2; i++)
{
m_dma_timer_active[i] = 0;
m_dma_irq[i] = 0;
@@ -308,7 +308,7 @@ void sh2_sh7604_device::sh2_exception(const char *message, int irqline)
}
else
{
- if(m_vecmd == true)
+ if (m_vecmd)
{
vector = standard_irq_callback(irqline, m_sh2_state->pc);
LOG("SH-2 exception #%d (external vector: $%x) after [%s]\n", irqline, vector, message);
@@ -344,7 +344,7 @@ void sh2_sh7604_device::sh2_timer_resync()
if (add > 0)
{
- if(divider)
+ if (divider)
m_frc += add;
m_frc_base = cur_time;
@@ -354,60 +354,63 @@ void sh2_sh7604_device::sh2_timer_resync()
void sh2_sh7604_device::sh2_timer_activate()
{
int max_delta = 0xfffff;
- uint16_t frc;
m_timer->adjust(attotime::never);
- frc = m_frc;
- if(!(m_ftcsr & OCFA)) {
+ uint16_t frc = m_frc;
+ if (!(m_ftcsr & OCFA))
+ {
uint16_t delta = m_ocra - frc;
- if(delta < max_delta)
+ if (delta < max_delta)
max_delta = delta;
}
- if(!(m_ftcsr & OCFB) && (m_ocra <= m_ocrb || !(m_ftcsr & CCLRA))) {
+ if (!(m_ftcsr & OCFB) && (m_ocra <= m_ocrb || !(m_ftcsr & CCLRA)))
+ {
uint16_t delta = m_ocrb - frc;
- if(delta < max_delta)
+ if (delta < max_delta)
max_delta = delta;
}
- if(!(m_ftcsr & OVF) && !(m_ftcsr & CCLRA)) {
+ if (!(m_ftcsr & OVF) && !(m_ftcsr & CCLRA))
+ {
int delta = 0x10000 - frc;
- if(delta < max_delta)
+ if (delta < max_delta)
max_delta = delta;
}
- if(max_delta != 0xfffff) {
+ if (max_delta != 0xfffff)
+ {
int divider = div_tab[m_frc_tcr & 3];
- if(divider) {
+ if (divider)
+ {
max_delta <<= divider;
m_frc_base = total_cycles();
m_timer->adjust(cycles_to_attotime(max_delta));
- } else {
+ }
+ else
+ {
logerror("SH2.%s: Timer event in %d cycles of external clock", tag(), max_delta);
}
}
}
-TIMER_CALLBACK_MEMBER( sh2_sh7604_device::sh2_timer_callback )
+TIMER_CALLBACK_MEMBER(sh2_sh7604_device::sh2_timer_callback)
{
- uint16_t frc;
-
sh2_timer_resync();
+ uint16_t frc = m_frc;
- frc = m_frc;
-
- if(frc == m_ocrb)
+ if (frc == m_ocrb)
m_ftcsr |= OCFB;
- if(frc == 0x0000)
+ if (frc == 0x0000)
m_ftcsr |= OVF;
- if(frc == m_ocra)
+ if (frc == m_ocra)
{
m_ftcsr |= OCFA;
- if(m_ftcsr & CCLRA)
+ if (m_ftcsr & CCLRA)
m_frc = 0;
}
@@ -472,11 +475,11 @@ void sh2_sh7604_device::sh2_notify_dma_data_available()
for (int dmach=0;dmach<2;dmach++)
{
- //printf("m_dma_timer_active[dmach] %04x\n",m_dma_timer_active[dmach]);
+ //printf("m_dma_timer_active[dmach] %04x\n", m_dma_timer_active[dmach]);
if (m_dma_timer_active[dmach]==2) // 2 = stalled
{
- // printf("resuming stalled dma\n");
+ //printf("resuming stalled dma\n");
m_dma_timer_active[dmach]=1;
m_dma_current_active_timer[dmach]->adjust(attotime::zero, dmach);
}
@@ -486,218 +489,215 @@ void sh2_sh7604_device::sh2_notify_dma_data_available()
void sh2_sh7604_device::sh2_do_dma(int dmach)
{
- uint32_t dmadata;
-
- uint32_t tempsrc, tempdst;
-
if (m_active_dma_count[dmach] > 0)
{
// process current DMA
- switch(m_active_dma_size[dmach])
+ switch (m_active_dma_size[dmach])
{
case 0:
- {
- // we need to know the src / dest ahead of time without changing them
- // to allow for the callback to check if we can process the DMA at this
- // time (we need to know where we're reading / writing to/from)
+ {
+ // we need to know the src / dest ahead of time without changing them
+ // to allow for the callback to check if we can process the DMA at this
+ // time (we need to know where we're reading / writing to/from)
- if(m_active_dma_incs[dmach] == 2)
- tempsrc = m_active_dma_src[dmach] - 1;
- else
- tempsrc = m_active_dma_src[dmach];
+ uint32_t tempsrc = m_active_dma_src[dmach];
+ if (m_active_dma_incs[dmach] == 2)
+ tempsrc--;
- if(m_active_dma_incd[dmach] == 2)
- tempdst = m_active_dma_dst[dmach] - 1;
- else
- tempdst = m_active_dma_dst[dmach];
+ uint32_t tempdst = m_active_dma_dst[dmach];
+ if (m_active_dma_incd[dmach] == 2)
+ tempdst--;
+
+ if (!m_dma_fifo_data_available_cb.isnull())
+ {
+ int available = m_dma_fifo_data_available_cb(tempsrc, tempdst, 0, m_active_dma_size[dmach]);
- if (!m_dma_fifo_data_available_cb.isnull())
+ if (!available)
{
- int available = m_dma_fifo_data_available_cb(tempsrc, tempdst, 0, m_active_dma_size[dmach]);
-
- if (!available)
- {
- //printf("dma stalled\n");
- m_dma_timer_active[dmach]=2;// mark as stalled
- return;
- }
+ //printf("dma stalled\n");
+ m_dma_timer_active[dmach] = 2; // mark as stalled
+ return;
}
+ }
- //schedule next DMA callback
- m_dma_current_active_timer[dmach]->adjust(cycles_to_attotime(2), dmach);
-
- dmadata = m_program->read_byte(tempsrc);
- if (!m_dma_kludge_cb.isnull()) dmadata = m_dma_kludge_cb(tempsrc, tempdst, dmadata, m_active_dma_size[dmach]);
- m_program->write_byte(tempdst, dmadata);
+ //schedule next DMA callback
+ m_dma_current_active_timer[dmach]->adjust(cycles_to_attotime(2), dmach);
- if(m_active_dma_incs[dmach] == 2)
- m_active_dma_src[dmach] --;
- if(m_active_dma_incd[dmach] == 2)
- m_active_dma_dst[dmach] --;
+ uint32_t dmadata = m_program->read_byte(tempsrc);
+ if (!m_dma_kludge_cb.isnull())
+ dmadata = m_dma_kludge_cb(tempsrc, tempdst, dmadata, m_active_dma_size[dmach]);
+ m_program->write_byte(tempdst, dmadata);
+ if (m_active_dma_incs[dmach] == 2)
+ m_active_dma_src[dmach]--;
+ if (m_active_dma_incd[dmach] == 2)
+ m_active_dma_dst[dmach]--;
- if(m_active_dma_incs[dmach] == 1)
- m_active_dma_src[dmach] ++;
- if(m_active_dma_incd[dmach] == 1)
- m_active_dma_dst[dmach] ++;
+ if (m_active_dma_incs[dmach] == 1)
+ m_active_dma_src[dmach]++;
+ if (m_active_dma_incd[dmach] == 1)
+ m_active_dma_dst[dmach]++;
- m_active_dma_count[dmach] --;
- }
+ m_active_dma_count[dmach]--;
break;
+ }
+
case 1:
- {
- if(m_active_dma_incs[dmach] == 2)
- tempsrc = m_active_dma_src[dmach] - 2;
- else
- tempsrc = m_active_dma_src[dmach];
+ {
+ uint32_t tempsrc = m_active_dma_src[dmach];
+ if (m_active_dma_incs[dmach] == 2)
+ tempsrc -= 2;
- if(m_active_dma_incd[dmach] == 2)
- tempdst = m_active_dma_dst[dmach] - 2;
- else
- tempdst = m_active_dma_dst[dmach];
+ uint32_t tempdst = m_active_dma_dst[dmach];
+ if (m_active_dma_incd[dmach] == 2)
+ tempdst -= 2;
- if (!m_dma_fifo_data_available_cb.isnull())
+ if (!m_dma_fifo_data_available_cb.isnull())
+ {
+ int available = m_dma_fifo_data_available_cb(tempsrc, tempdst, 0, m_active_dma_size[dmach]);
+
+ if (!available)
{
- int available = m_dma_fifo_data_available_cb(tempsrc, tempdst, 0, m_active_dma_size[dmach]);
-
- if (!available)
- {
- //printf("dma stalled\n");
- m_dma_timer_active[dmach]=2;// mark as stalled
- return;
- }
+ //printf("dma stalled\n");
+ m_dma_timer_active[dmach] = 2; // mark as stalled
+ return;
}
+ }
- //schedule next DMA callback
- m_dma_current_active_timer[dmach]->adjust(cycles_to_attotime(2), dmach);
+ //schedule next DMA callback
+ m_dma_current_active_timer[dmach]->adjust(cycles_to_attotime(2), dmach);
- // check: should this really be using read_word_32 / write_word_32?
- dmadata = m_program->read_word(tempsrc);
- if (!m_dma_kludge_cb.isnull()) dmadata = m_dma_kludge_cb(tempsrc, tempdst, dmadata, m_active_dma_size[dmach]);
- m_program->write_word(tempdst, dmadata);
+ // check: should this really be using read_word_32 / write_word_32?
+ uint32_t dmadata = m_program->read_word(tempsrc);
+ if (!m_dma_kludge_cb.isnull())
+ dmadata = m_dma_kludge_cb(tempsrc, tempdst, dmadata, m_active_dma_size[dmach]);
+ m_program->write_word(tempdst, dmadata);
- if(m_active_dma_incs[dmach] == 2)
- m_active_dma_src[dmach] -= 2;
- if(m_active_dma_incd[dmach] == 2)
- m_active_dma_dst[dmach] -= 2;
+ if (m_active_dma_incs[dmach] == 2)
+ m_active_dma_src[dmach] -= 2;
+ if (m_active_dma_incd[dmach] == 2)
+ m_active_dma_dst[dmach] -= 2;
- if(m_active_dma_incs[dmach] == 1)
- m_active_dma_src[dmach] += 2;
- if(m_active_dma_incd[dmach] == 1)
- m_active_dma_dst[dmach] += 2;
+ if (m_active_dma_incs[dmach] == 1)
+ m_active_dma_src[dmach] += 2;
+ if (m_active_dma_incd[dmach] == 1)
+ m_active_dma_dst[dmach] += 2;
- m_active_dma_count[dmach] --;
- }
+ m_active_dma_count[dmach]--;
break;
+ }
+
case 2:
- {
- if(m_active_dma_incs[dmach] == 2)
- tempsrc = m_active_dma_src[dmach] - 4;
- else
- tempsrc = m_active_dma_src[dmach];
+ {
+ uint32_t tempsrc = m_active_dma_src[dmach];
+ if (m_active_dma_incs[dmach] == 2)
+ tempsrc -= 4;
+
+ uint32_t tempdst = m_active_dma_dst[dmach];
+ if (m_active_dma_incd[dmach] == 2)
+ tempdst -= 4;
- if(m_active_dma_incd[dmach] == 2)
- tempdst = m_active_dma_dst[dmach] - 4;
- else
- tempdst = m_active_dma_dst[dmach];
+ if (!m_dma_fifo_data_available_cb.isnull())
+ {
+ int available = m_dma_fifo_data_available_cb(tempsrc, tempdst, 0, m_active_dma_size[dmach]);
- if (!m_dma_fifo_data_available_cb.isnull())
+ if (!available)
{
- int available = m_dma_fifo_data_available_cb(tempsrc, tempdst, 0, m_active_dma_size[dmach]);
-
- if (!available)
- {
- //printf("dma stalled\n");
- m_dma_timer_active[dmach]=2;// mark as stalled
- return;
- }
+ //printf("dma stalled\n");
+ m_dma_timer_active[dmach] = 2; // mark as stalled
+ return;
}
+ }
- //schedule next DMA callback
- m_dma_current_active_timer[dmach]->adjust(cycles_to_attotime(2), dmach);
+ //schedule next DMA callback
+ m_dma_current_active_timer[dmach]->adjust(cycles_to_attotime(2), dmach);
- dmadata = m_program->read_dword(tempsrc);
- if (!m_dma_kludge_cb.isnull()) dmadata = m_dma_kludge_cb(tempsrc, tempdst, dmadata, m_active_dma_size[dmach]);
- m_program->write_dword(tempdst, dmadata);
+ uint32_t dmadata = m_program->read_dword(tempsrc);
+ if (!m_dma_kludge_cb.isnull())
+ dmadata = m_dma_kludge_cb(tempsrc, tempdst, dmadata, m_active_dma_size[dmach]);
+ m_program->write_dword(tempdst, dmadata);
- if(m_active_dma_incs[dmach] == 2)
- m_active_dma_src[dmach] -= 4;
- if(m_active_dma_incd[dmach] == 2)
- m_active_dma_dst[dmach] -= 4;
+ if (m_active_dma_incs[dmach] == 2)
+ m_active_dma_src[dmach] -= 4;
+ if (m_active_dma_incd[dmach] == 2)
+ m_active_dma_dst[dmach] -= 4;
- if(m_active_dma_incs[dmach] == 1)
- m_active_dma_src[dmach] += 4;
- if(m_active_dma_incd[dmach] == 1)
- m_active_dma_dst[dmach] += 4;
+ if (m_active_dma_incs[dmach] == 1)
+ m_active_dma_src[dmach] += 4;
+ if (m_active_dma_incd[dmach] == 1)
+ m_active_dma_dst[dmach] += 4;
- m_active_dma_count[dmach] --;
- }
+ m_active_dma_count[dmach]--;
break;
+ }
+
case 3:
- {
- // shouldn't this really be 4 calls here instead?
+ {
+ // shouldn't this really be 4 calls here instead?
- tempsrc = m_active_dma_src[dmach];
+ uint32_t tempsrc = m_active_dma_src[dmach];
- if(m_active_dma_incd[dmach] == 2)
- tempdst = m_active_dma_dst[dmach] - 16;
- else
- tempdst = m_active_dma_dst[dmach];
+ uint32_t tempdst = m_active_dma_dst[dmach];
+ if (m_active_dma_incd[dmach] == 2)
+ tempdst -= 16;
+
+ if (!m_dma_fifo_data_available_cb.isnull())
+ {
+ int available = m_dma_fifo_data_available_cb(tempsrc, tempdst, 0, m_active_dma_size[dmach]);
- if (!m_dma_fifo_data_available_cb.isnull())
+ if (!available)
{
- int available = m_dma_fifo_data_available_cb(tempsrc, tempdst, 0, m_active_dma_size[dmach]);
-
- if (!available)
- {
- //printf("dma stalled\n");
- m_dma_timer_active[dmach]=2;// mark as stalled
- fatalerror("SH2 dma_callback_fifo_data_available == 0 in unsupported mode\n");
- }
+ //printf("dma stalled\n");
+ m_dma_timer_active[dmach] = 2; // mark as stalled
+ fatalerror("SH2 dma_callback_fifo_data_available == 0 in unsupported mode\n");
}
+ }
- //schedule next DMA callback
- m_dma_current_active_timer[dmach]->adjust(cycles_to_attotime(2), dmach);
+ //schedule next DMA callback
+ m_dma_current_active_timer[dmach]->adjust(cycles_to_attotime(2), dmach);
- dmadata = m_program->read_dword(tempsrc);
- if (!m_dma_kludge_cb.isnull()) dmadata = m_dma_kludge_cb(tempsrc, tempdst, dmadata, m_active_dma_size[dmach]);
- m_program->write_dword(tempdst, dmadata);
+ uint32_t dmadata = m_program->read_dword(tempsrc);
+ if (!m_dma_kludge_cb.isnull())
+ dmadata = m_dma_kludge_cb(tempsrc, tempdst, dmadata, m_active_dma_size[dmach]);
+ m_program->write_dword(tempdst, dmadata);
- dmadata = m_program->read_dword(tempsrc+4);
- if (!m_dma_kludge_cb.isnull()) dmadata = m_dma_kludge_cb(tempsrc, tempdst, dmadata, m_active_dma_size[dmach]);
- m_program->write_dword(tempdst+4, dmadata);
+ dmadata = m_program->read_dword(tempsrc + 4);
+ if (!m_dma_kludge_cb.isnull())
+ dmadata = m_dma_kludge_cb(tempsrc, tempdst, dmadata, m_active_dma_size[dmach]);
+ m_program->write_dword(tempdst + 4, dmadata);
- dmadata = m_program->read_dword(tempsrc+8);
- if (!m_dma_kludge_cb.isnull()) dmadata = m_dma_kludge_cb(tempsrc, tempdst, dmadata, m_active_dma_size[dmach]);
- m_program->write_dword(tempdst+8, dmadata);
+ dmadata = m_program->read_dword(tempsrc + 8);
+ if (!m_dma_kludge_cb.isnull())
+ dmadata = m_dma_kludge_cb(tempsrc, tempdst, dmadata, m_active_dma_size[dmach]);
+ m_program->write_dword(tempdst + 8, dmadata);
- dmadata = m_program->read_dword(tempsrc+12);
- if (!m_dma_kludge_cb.isnull()) dmadata = m_dma_kludge_cb(tempsrc, tempdst, dmadata, m_active_dma_size[dmach]);
- m_program->write_dword(tempdst+12, dmadata);
+ dmadata = m_program->read_dword(tempsrc + 12);
+ if (!m_dma_kludge_cb.isnull())
+ dmadata = m_dma_kludge_cb(tempsrc, tempdst, dmadata, m_active_dma_size[dmach]);
+ m_program->write_dword(tempdst + 12, dmadata);
- if(m_active_dma_incd[dmach] == 2)
- m_active_dma_dst[dmach] -= 16;
+ if (m_active_dma_incd[dmach] == 2)
+ m_active_dma_dst[dmach] -= 16;
- m_active_dma_src[dmach] += 16;
- if(m_active_dma_incd[dmach] == 1)
- m_active_dma_dst[dmach] += 16;
+ m_active_dma_src[dmach] += 16;
+ if (m_active_dma_incd[dmach] == 1)
+ m_active_dma_dst[dmach] += 16;
- m_active_dma_count[dmach]-=4;
- }
+ m_active_dma_count[dmach] -= 4;
break;
}
+ }
}
else // the dma is complete
{
- // int dma = param & 1;
+ // int dma = param & 1;
// fever soccer uses cycle-stealing mode, resume the CPU now DMA has finished
if (m_active_dma_steal[dmach])
{
- resume(SUSPEND_REASON_HALT );
+ resume(SUSPEND_REASON_HALT);
}
-
LOG("SH2: DMA %d complete\n", dmach);
m_dmac[dmach].tcr = 0;
m_dmac[dmach].chcr |= 2;
@@ -708,34 +708,32 @@ void sh2_sh7604_device::sh2_do_dma(int dmach)
}
}
-TIMER_CALLBACK_MEMBER( sh2_sh7604_device::sh2_dma_current_active_callback )
+TIMER_CALLBACK_MEMBER(sh2_sh7604_device::sh2_dma_current_active_callback)
{
- int dma = param & 1;
-
- sh2_do_dma(dma);
+ sh2_do_dma(param & 1);
}
void sh2_sh7604_device::sh2_dmac_check(int dmach)
{
- if(m_dmac[dmach].chcr & m_dmaor & 1)
+ if (m_dmac[dmach].chcr & m_dmaor & 1)
{
- if(!m_dma_timer_active[dmach] && !(m_dmac[dmach].chcr & 2))
+ if (!m_dma_timer_active[dmach] && !(m_dmac[dmach].chcr & 2))
{
m_active_dma_incd[dmach] = (m_dmac[dmach].chcr >> 14) & 3;
m_active_dma_incs[dmach] = (m_dmac[dmach].chcr >> 12) & 3;
m_active_dma_size[dmach] = (m_dmac[dmach].chcr >> 10) & 3;
m_active_dma_steal[dmach] = (m_dmac[dmach].chcr & 0x10);
- if(m_active_dma_incd[dmach] == 3 || m_active_dma_incs[dmach] == 3)
+ if (m_active_dma_incd[dmach] == 3 || m_active_dma_incs[dmach] == 3)
{
- logerror("SH2: DMA: bad increment values (%d, %d, %d, %04x)\n", m_active_dma_incd[dmach], m_active_dma_incs[dmach], m_active_dma_size[dmach], m_dmac[dmach].chcr);
+ LOG("SH2: DMA: bad increment values (%d, %d, %d, %04x)\n", m_active_dma_incd[dmach], m_active_dma_incs[dmach], m_active_dma_size[dmach], m_dmac[dmach].chcr);
return;
}
m_active_dma_src[dmach] = m_dmac[dmach].sar;
m_active_dma_dst[dmach] = m_dmac[dmach].dar;
m_active_dma_count[dmach] = m_dmac[dmach].tcr;
- if(!m_active_dma_count[dmach])
+ if (!m_active_dma_count[dmach])
m_active_dma_count[dmach] = 0x1000000;
LOG("SH2: DMA %d start %x, %x, %x, %04x, %d, %d, %d\n", dmach, m_active_dma_src[dmach], m_active_dma_dst[dmach], m_active_dma_count[dmach], m_dmac[dmach].chcr, m_active_dma_incs[dmach], m_active_dma_incd[dmach], m_active_dma_size[dmach]);
@@ -745,7 +743,7 @@ void sh2_sh7604_device::sh2_dmac_check(int dmach)
m_active_dma_src[dmach] &= m_am;
m_active_dma_dst[dmach] &= m_am;
- switch(m_active_dma_size[dmach])
+ switch (m_active_dma_size[dmach])
{
case 0:
break;
@@ -770,7 +768,7 @@ void sh2_sh7604_device::sh2_dmac_check(int dmach)
if (m_active_dma_steal[dmach])
{
//printf("cycle stealing DMA\n");
- suspend(SUSPEND_REASON_HALT, 1 );
+ suspend(SUSPEND_REASON_HALT, 1);
}
m_dma_current_active_timer[dmach]->adjust(cycles_to_attotime(2), dmach);
@@ -778,9 +776,9 @@ void sh2_sh7604_device::sh2_dmac_check(int dmach)
}
else
{
- if(m_dma_timer_active[dmach])
+ if (m_dma_timer_active[dmach])
{
- logerror("SH2: DMA %d cancelled in-flight\n", dmach);
+ LOG("SH2: DMA %d cancelled in-flight\n", dmach);
//m_dma_complete_timer[dmach]->adjust(attotime::never);
m_dma_current_active_timer[dmach]->adjust(attotime::never, dmach);
@@ -832,7 +830,7 @@ uint8_t sh2_sh7604_device::tdr_r()
void sh2_sh7604_device::tdr_w(uint8_t data)
{
m_tdr = data;
- // printf("%c",data & 0xff);
+ //printf("%c", data & 0xff);
}
uint8_t sh2_sh7604_device::ssr_r()
@@ -872,19 +870,18 @@ uint8_t sh2_sh7604_device::ftcsr_r()
{
// TODO: to be tested
if (!m_ftcsr_read_cb.isnull())
- m_ftcsr_read_cb((((m_tier<<24) | (m_ftcsr<<16)) & 0xffff0000) | m_frc);
+ m_ftcsr_read_cb((((m_tier << 24) | (m_ftcsr << 16)) & 0xffff0000) | m_frc);
return m_ftcsr;
}
void sh2_sh7604_device::ftcsr_w(uint8_t data)
{
- uint8_t old;
- old = m_ftcsr;
+ uint8_t old = m_ftcsr;
m_ftcsr = data;
sh2_timer_resync();
- m_ftcsr = (m_ftcsr & ~(ICF|OCFA|OCFB|OVF)) | (old & m_ftcsr & (ICF|OCFA|OCFB|OVF));
+ m_ftcsr = (m_ftcsr & ~(ICF | OCFA | OCFB | OVF)) | (old & m_ftcsr & (ICF | OCFA | OCFB | OVF));
sh2_timer_activate();
sh2_recalc_irq();
}
@@ -911,10 +908,10 @@ uint16_t sh2_sh7604_device::ocra_b_r()
void sh2_sh7604_device::ocra_b_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
sh2_timer_resync();
- if(m_tocr & 0x10)
- m_ocrb = (m_ocrb & (~mem_mask)) | (data & mem_mask);
+ if (m_tocr & 0x10)
+ m_ocrb = (m_ocrb & ~mem_mask) | (data & mem_mask);
else
- m_ocra = (m_ocra & (~mem_mask)) | (data & mem_mask);
+ m_ocra = (m_ocra & ~mem_mask) | (data & mem_mask);
sh2_timer_activate();
sh2_recalc_irq();
}
@@ -959,14 +956,14 @@ uint16_t sh2_sh7604_device::intc_icr_r()
{
// TODO: flip meaning based off NMI edge select bit (NMIE)
uint16_t nmilv = m_nmi_line_state == ASSERT_LINE ? 0 : 0x8000;
- return (nmilv) | (m_intc_icr & 0x0101);
+ return nmilv | (m_intc_icr & 0x0101);
}
void sh2_sh7604_device::intc_icr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_intc_icr);
- m_nmie = bool(BIT(m_intc_icr, 8));
- m_vecmd = bool(BIT(m_intc_icr, 0));
+ m_nmie = BIT(m_intc_icr, 8);
+ m_vecmd = BIT(m_intc_icr, 0);
}
uint16_t sh2_sh7604_device::ipra_r()
@@ -1076,20 +1073,20 @@ void sh2_sh7604_device::vcrdiv_w(offs_t offset, uint32_t data, uint32_t mem_mask
uint32_t sh2_sh7604_device::dvcr_r()
{
- return (m_divu_ovfie == true ? 2 : 0) | (m_divu_ovf == true ? 1 : 0);
+ return (m_divu_ovfie ? 2 : 0) | (m_divu_ovf ? 1 : 0);
}
void sh2_sh7604_device::dvcr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
if (data & 1)
m_divu_ovf = false;
if (data & 2)
{
- m_divu_ovfie = bool(BIT(data, 1));
- if (m_divu_ovfie == true)
- logerror("SH2: unemulated DIVU OVF interrupt enable\n");
+ m_divu_ovfie = BIT(data, 1);
+ if (m_divu_ovfie)
+ LOG("SH2: unemulated DIVU OVF interrupt enable\n");
}
sh2_recalc_irq();
}
@@ -1148,7 +1145,7 @@ void sh2_sh7604_device::dvdnth_w(offs_t offset, uint32_t data, uint32_t mem_mask
void sh2_sh7604_device::dvdntl_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_dvdntl);
- int64_t a = m_dvdntl | ((uint64_t)(m_dvdnth) << 32);
+ int64_t a = m_dvdntl | ((uint64_t)m_dvdnth << 32);
int64_t b = (int32_t)m_dvsr;
LOG("SH2 div64+mod %d/%d\n", a, b);
if (b)
@@ -1358,20 +1355,20 @@ void sh2_sh7604_device::rtcor_w(offs_t offset, uint32_t data, uint32_t mem_mask)
void sh2_sh7604_device::set_frt_input(int state)
{
- if(m_frt_input == state) {
+ if (m_frt_input == state)
return;
- }
m_frt_input = state;
- if(m_frc_tcr & 0x80) {
- if(state == CLEAR_LINE) {
+ if (m_frc_tcr & 0x80)
+ {
+ if (state == CLEAR_LINE)
return;
- }
- } else {
- if(state == ASSERT_LINE) {
+ }
+ else
+ {
+ if (state == ASSERT_LINE)
return;
- }
}
sh2_timer_resync();
@@ -1383,20 +1380,21 @@ void sh2_sh7604_device::set_frt_input(int state)
void sh2_sh7604_device::sh2_recalc_irq()
{
- int irq = 0, vector = -1;
- int level;
+ int irq = 0;
+ int vector = -1;
+ int level;
// Timer irqs
- if (m_tier & m_ftcsr & (ICF|OCFA|OCFB|OVF))
+ if (m_tier & m_ftcsr & (ICF | OCFA | OCFB | OVF))
{
level = (m_irq_level.frc & 15);
if (level > irq)
{
int mask = m_tier & m_ftcsr;
irq = level;
- if(mask & ICF)
+ if (mask & ICF)
vector = m_irq_vector.fic & 0x7f;
- else if(mask & (OCFA|OCFB))
+ else if (mask & (OCFA | OCFB))
vector = m_irq_vector.foc & 0x7f;
else
vector = m_irq_vector.fov & 0x7f;
@@ -1415,17 +1413,21 @@ void sh2_sh7604_device::sh2_recalc_irq()
}
// DMA irqs
- if((m_dmac[0].chcr & 6) == 6 && m_dma_irq[0]) {
+ if ((m_dmac[0].chcr & 6) == 6 && m_dma_irq[0])
+ {
level = m_irq_level.dmac & 15;
- if(level > irq) {
+ if (level > irq)
+ {
irq = level;
m_dma_irq[0] &= ~1;
vector = m_irq_vector.dmac[0] & 0x7f;
}
}
- else if((m_dmac[1].chcr & 6) == 6 && m_dma_irq[1]) {
+ else if ((m_dmac[1].chcr & 6) == 6 && m_dma_irq[1])
+ {
level = m_irq_level.dmac & 15;
- if(level > irq) {
+ if (level > irq)
+ {
irq = level;
m_dma_irq[1] &= ~1;
vector = m_irq_vector.dmac[1] & 0x7f;
@@ -1456,7 +1458,8 @@ void sh2_sh7604_device::vcrdma_w(offs_t offset, uint32_t data, uint32_t mem_mask
}
template <int Channel>
-uint8_t sh2_sh7604_device::drcr_r() {
+uint8_t sh2_sh7604_device::drcr_r()
+{
return m_dmac[Channel].drcr & 3;
}
@@ -1527,10 +1530,9 @@ uint32_t sh2_sh7604_device::dmaor_r()
void sh2_sh7604_device::dmaor_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
- if(ACCESSING_BITS_0_7)
+ if (ACCESSING_BITS_0_7)
{
- uint8_t old;
- old = m_dmaor & 0xf;
+ uint8_t old = m_dmaor & 0xf;
m_dmaor = (data & ~6) | (old & m_dmaor & 6); // TODO: should this be old & data & 6? bug?
sh2_dmac_check(0);
sh2_dmac_check(1);
diff --git a/src/devices/cpu/sh/sh7604.h b/src/devices/cpu/sh/sh7604.h
index deb47dfd24f..587dae5978f 100644
--- a/src/devices/cpu/sh/sh7604.h
+++ b/src/devices/cpu/sh/sh7604.h
@@ -33,7 +33,7 @@ public:
void sh2_notify_dma_data_available();
protected:
- sh2_sh7604_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, int cpu_type,address_map_constructor internal_map, int addrlines);
+ sh2_sh7604_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, int cpu_type, address_map_constructor internal_map, int addrlines);
virtual void device_start() override;
virtual void device_reset() override;
@@ -173,7 +173,8 @@ private:
uint16_t m_ocra, m_ocrb, m_frc_icr;
// INTC
- struct {
+ struct
+ {
uint8_t frc;
uint8_t sci;
uint8_t divu;
@@ -181,7 +182,8 @@ private:
uint8_t wdt;
} m_irq_level;
- struct {
+ struct
+ {
uint8_t fic;
uint8_t foc;
uint8_t fov;
@@ -203,7 +205,8 @@ private:
uint16_t m_wtcw[2];
// DMAC
- struct {
+ struct
+ {
uint8_t drcr;
uint32_t sar;
uint32_t dar;
@@ -242,9 +245,9 @@ private:
dma_fifo_data_available_delegate m_dma_fifo_data_available_cb;
ftcsr_read_delegate m_ftcsr_read_cb;
- TIMER_CALLBACK_MEMBER( sh2_timer_callback );
- TIMER_CALLBACK_MEMBER( sh2_wdtimer_callback );
- TIMER_CALLBACK_MEMBER( sh2_dma_current_active_callback );
+ TIMER_CALLBACK_MEMBER(sh2_timer_callback);
+ TIMER_CALLBACK_MEMBER(sh2_wdtimer_callback);
+ TIMER_CALLBACK_MEMBER(sh2_dma_current_active_callback);
void sh2_timer_resync();
void sh2_timer_activate();
void sh2_wtcnt_recalc();
diff --git a/src/devices/cpu/sh/sh7604_bus.cpp b/src/devices/cpu/sh/sh7604_bus.cpp
index a4b61bddae6..8355ccd247a 100644
--- a/src/devices/cpu/sh/sh7604_bus.cpp
+++ b/src/devices/cpu/sh/sh7604_bus.cpp
@@ -32,31 +32,49 @@ DEFINE_DEVICE_TYPE(SH7604_BUS, sh7604_bus_device, "sh7604bus", "SH7604 BUS Contr
uint16_t sh7604_bus_device::bus_control_1_r()
{
- return (m_bcr1 & 0x1ff7) | (m_is_slave == true ? 0x8000 : 0);
+ return (m_bcr1 & 0x1ff7) | (m_is_slave ? 0x8000 : 0);
}
void sh7604_bus_device::bus_control_1_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_bcr1);
- if(m_bcr1 & 0x1000) // ENDIAN
+ if (m_bcr1 & 0x1000) // ENDIAN
throw emu_fatalerror("%s: enabled little endian for Area 2\n", tag());
- if(m_bcr1 & 0x0800) // PSHR
+ if (m_bcr1 & 0x0800) // PSHR
throw emu_fatalerror("%s: enabled partial space share mode\n", tag());
}
-uint16_t sh7604_bus_device::bus_control_2_r() { return m_bcr2 & 0x00fc; }
+uint16_t sh7604_bus_device::bus_control_2_r()
+{
+ return m_bcr2 & 0x00fc;
+}
+
void sh7604_bus_device::bus_control_2_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_bcr2);
- if(m_bcr2 != 0x00fc)
- throw emu_fatalerror("%s: unexpected bus size register set %04x\n", tag(),data);
+ if (m_bcr2 != 0x00fc)
+ throw emu_fatalerror("%s: unexpected bus size register set %04x\n", tag(), data);
}
-uint16_t sh7604_bus_device::wait_control_r() { return m_wcr; }
-void sh7604_bus_device::wait_control_w(offs_t offset, uint16_t data, uint16_t mem_mask) { COMBINE_DATA(&m_wcr); }
+uint16_t sh7604_bus_device::wait_control_r()
+{
+ return m_wcr;
+}
-uint16_t sh7604_bus_device::memory_control_r() { return m_mcr & 0xfefc; }
-void sh7604_bus_device::memory_control_w(offs_t offset, uint16_t data, uint16_t mem_mask) { COMBINE_DATA(&m_mcr); }
+void sh7604_bus_device::wait_control_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_wcr);
+}
+
+uint16_t sh7604_bus_device::memory_control_r()
+{
+ return m_mcr & 0xfefc;
+}
+
+void sh7604_bus_device::memory_control_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+ COMBINE_DATA(&m_mcr);
+}
uint16_t sh7604_bus_device::refresh_timer_status_r()
{
@@ -67,19 +85,19 @@ void sh7604_bus_device::refresh_timer_control_w(offs_t offset, uint16_t data, ui
{
COMBINE_DATA(&m_rtcsr);
- if(m_rtcsr & 0x40)
- throw emu_fatalerror("%s: enabled timer irq register with clock setting = %02x\n",tag(),data & 0x38);
+ if (m_rtcsr & 0x40)
+ throw emu_fatalerror("%s: enabled timer irq register with clock setting = %02x\n", tag(), data & 0x38);
}
uint16_t sh7604_bus_device::refresh_timer_counter_r()
{
- throw emu_fatalerror("%s: reading timer counter!\n",tag());
+ throw emu_fatalerror("%s: reading timer counter!\n", tag());
return 0;
}
void sh7604_bus_device::refresh_timer_counter_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
- throw emu_fatalerror("%s: writing timer counter %04x\n",tag(),data);
+ throw emu_fatalerror("%s: writing timer counter %04x\n", tag(), data);
//COMBINE_DATA(&m_rtcnt);
}
@@ -152,12 +170,12 @@ void sh7604_bus_device::write(address_space &space, offs_t offset, uint32_t data
{
// TODO: 8 bit access is invalid
// if accessing bits 16-31, one must write ID = 0xa55a
- if(ACCESSING_BITS_16_31)
+ if (ACCESSING_BITS_16_31)
{
// throw fatalerror if something trips it, presumably the write is going to be ignored
- if((data & 0xffff0000) != 0xa55a0000)
- throw emu_fatalerror("%s: making bus write with ID signature = %04x!\n", tag(),data >> 16);
+ if ((data & 0xffff0000) != 0xa55a0000)
+ throw emu_fatalerror("%s: making bus write with ID signature = %04x!\n", tag(), data >> 16);
}
- space.write_word(offset,data & 0xffff);
+ space.write_word(offset, data & 0xffff);
}
diff --git a/src/devices/cpu/sh/sh7604_sci.cpp b/src/devices/cpu/sh/sh7604_sci.cpp
index 5d49eab5c31..ae3ec5f4620 100644
--- a/src/devices/cpu/sh/sh7604_sci.cpp
+++ b/src/devices/cpu/sh/sh7604_sci.cpp
@@ -38,14 +38,14 @@ void sh7604_sci_device::serial_mode_w(uint8_t data)
{
m_smr = data;
- logerror("%s: serial mode set:\n",tag());
- logerror("\tCommunication Mode: %s mode\n",data & 0x80 ? "clocked synchronous" : "asynchronous");
- logerror("\tCharacter Length: %s mode\n",data & 0x40 ? "7-bit" : "8-bit");
- logerror("\tParity Enable: %s\n",data & 0x20 ? "yes" : "no");
- logerror("\tParity Mode: %s\n",data & 0x10 ? "Odd" : "Even");
- logerror("\tStop bits: %s\n",data & 0x08 ? "2" : "1");
- logerror("\tMultiprocessor mode: %s\n",data & 0x04 ? "yes" : "no");
- logerror("\tClock select: clock/%d\n",4 << ((data & 0x03)*2));
+ logerror("%s: serial mode set:\n", tag());
+ logerror("\tCommunication Mode: %s mode\n", data & 0x80 ? "clocked synchronous" : "asynchronous");
+ logerror("\tCharacter Length: %s mode\n", data & 0x40 ? "7-bit" : "8-bit");
+ logerror("\tParity Enable: %s\n", data & 0x20 ? "yes" : "no");
+ logerror("\tParity Mode: %s\n", data & 0x10 ? "Odd" : "Even");
+ logerror("\tStop bits: %s\n", data & 0x08 ? "2" : "1");
+ logerror("\tMultiprocessor mode: %s\n", data & 0x04 ? "yes" : "no");
+ logerror("\tClock select: clock/%d\n", 4 << ((data & 0x03) * 2));
}
uint8_t sh7604_sci_device::serial_control_r()
@@ -57,8 +57,8 @@ void sh7604_sci_device::serial_control_w(uint8_t data)
{
m_scr = data;
- if(data & 0x30)
- throw emu_fatalerror("%s: enabled serial control %02x\n", tag(),data);
+ if (data & 0x30)
+ throw emu_fatalerror("%s: enabled serial control %02x\n", tag(), data);
}
uint8_t sh7604_sci_device::serial_status_r()
@@ -153,5 +153,5 @@ uint8_t sh7604_sci_device::read(address_space &space, offs_t offset)
void sh7604_sci_device::write(address_space &space, offs_t offset, uint8_t data)
{
- space.write_byte(offset,data);
+ space.write_byte(offset, data);
}
diff --git a/src/devices/cpu/sh/sh7604_sci.h b/src/devices/cpu/sh/sh7604_sci.h
index ae4e0155acb..c760ff42588 100644
--- a/src/devices/cpu/sh/sh7604_sci.h
+++ b/src/devices/cpu/sh/sh7604_sci.h
@@ -45,7 +45,8 @@ public:
uint8_t receive_data_r();
protected:
- enum {
+ enum
+ {
STATUS_MPBT = 1 << 0,
STATUS_MPB = 1 << 1,
STATUS_TEND = 1 << 2,
diff --git a/src/devices/cpu/sh/sh7604_wdt.cpp b/src/devices/cpu/sh/sh7604_wdt.cpp
index 2b5ea9eb499..10d7f04c42c 100644
--- a/src/devices/cpu/sh/sh7604_wdt.cpp
+++ b/src/devices/cpu/sh/sh7604_wdt.cpp
@@ -75,10 +75,10 @@ uint8_t sh7604_wdt_device::read(address_space &space, offs_t offset)
void sh7604_wdt_device::write(address_space &space, offs_t offset, uint16_t data)
{
uint8_t id_param = data >> 8;
- switch(id_param)
+ switch (id_param)
{
- case 0xa5: space.write_byte(offset*2+0,data & 0xff); break;
- case 0x5a: space.write_byte(offset*2+1,data & 0xff); break;
- default: throw emu_fatalerror("%s: invalid id param write = %02x\n",tag(),id_param);
+ case 0xa5: space.write_byte(offset * 2 + 0, data & 0xff); break;
+ case 0x5a: space.write_byte(offset * 2 + 1, data & 0xff); break;
+ default: throw emu_fatalerror("%s: invalid id param write = %02x\n", tag(), id_param);
}
}
diff --git a/src/devices/cpu/sh/sh_dasm.cpp b/src/devices/cpu/sh/sh_dasm.cpp
index d504be32eab..26454484e3f 100644
--- a/src/devices/cpu/sh/sh_dasm.cpp
+++ b/src/devices/cpu/sh/sh_dasm.cpp
@@ -6,7 +6,8 @@
#define Rn ((opcode>>8)&15)
#define Rm ((opcode>>4)&15)
-const char *const sh_disassembler::regname[16] = {
+const char *const sh_disassembler::regname[16] =
+{
"R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
"R8", "R9", "R10","R11","R12","R13","R14",
// The old SH2 dasm used 'SP' here, the old SH4 used 'R15'
@@ -17,7 +18,7 @@ const char *const sh_disassembler::regname[16] = {
uint32_t sh_disassembler::op0000(std::ostream &stream, uint32_t pc, uint16_t opcode)
{
uint32_t flags = 0;
- switch(opcode & 0x3f)
+ switch (opcode & 0x3f)
{
case 0x02:
util::stream_format(stream, "STC SR,%s", regname[Rn]);
@@ -73,7 +74,7 @@ uint32_t sh_disassembler::op0000(std::ostream &stream, uint32_t pc, uint16_t opc
flags = STEP_OUT | step_over_extra(1);
break;
default:
- switch(opcode & 15)
+ switch (opcode & 15)
{
case 0:
util::stream_format(stream, "?????? $%04X", opcode);
@@ -249,7 +250,7 @@ uint32_t sh_disassembler::op0011(std::ostream &stream, uint32_t pc, uint16_t opc
uint32_t sh_disassembler::op0100(std::ostream &stream, uint32_t pc, uint16_t opcode)
{
uint32_t flags = 0;
- switch(opcode & 0x3F)
+ switch (opcode & 0x3F)
{
case 0x00:
util::stream_format(stream, "SHLL %s", regname[Rn]);
@@ -384,7 +385,7 @@ uint32_t sh_disassembler::op0101(std::ostream &stream, uint32_t pc, uint16_t opc
uint32_t sh_disassembler::op0110(std::ostream &stream, uint32_t pc, uint16_t opcode)
{
- switch(opcode & 0xF)
+ switch (opcode & 0xF)
{
case 0x00:
util::stream_format(stream, "MOV.B @%s,%s", regname[Rm], regname[Rn]);
@@ -446,7 +447,7 @@ uint32_t sh_disassembler::op0111(std::ostream &stream, uint32_t pc, uint16_t opc
uint32_t sh_disassembler::op1000(std::ostream &stream, uint32_t pc, uint16_t opcode)
{
- switch((opcode >> 8) & 15)
+ switch ((opcode >> 8) & 15)
{
case 0:
util::stream_format(stream, "MOV.B R0,@($%02X,%s)", (opcode & 15), regname[Rm]);
@@ -502,7 +503,7 @@ uint32_t sh_disassembler::op1011(std::ostream &stream, uint32_t pc, uint16_t opc
uint32_t sh_disassembler::op1100(std::ostream &stream, uint32_t pc, uint16_t opcode)
{
uint32_t flags = 0;
- switch((opcode >> 8) & 15)
+ switch ((opcode >> 8) & 15)
{
case 0:
util::stream_format(stream, "MOV.B R0,@($%02X,GBR)", opcode & 0xff);
@@ -589,7 +590,8 @@ uint32_t sh_disassembler::op0000_sh34(std::ostream &stream, uint32_t pc, uint16_
util::stream_format(stream, "?????? $%04X", opcode);
break;
case 0x2:
- if (opcode & 0x80) {
+ if (opcode & 0x80)
+ {
util::stream_format(stream, "STC %s_BANK,%s", regname[(Rm) & 7], regname[Rn]);
return flags;
}
@@ -794,7 +796,8 @@ uint32_t sh_disassembler::op0100_sh34(std::ostream &stream, uint32_t pc, uint16_
}
break;
case 0x3:
- if (opcode & 0x80) {
+ if (opcode & 0x80)
+ {
util::stream_format(stream, "STC.L %s_BANK,@-%s", regname[(Rm) & 7],regname[Rn]);
return flags;
}
@@ -866,7 +869,8 @@ uint32_t sh_disassembler::op0100_sh34(std::ostream &stream, uint32_t pc, uint16_
}
break;
case 0x7:
- if (opcode & 0x80) {
+ if (opcode & 0x80)
+ {
util::stream_format(stream, "LDC.L @%s+,%s_BANK", regname[Rn],regname[(Rm) & 7]);
return flags;
}
@@ -962,7 +966,8 @@ uint32_t sh_disassembler::op0100_sh34(std::ostream &stream, uint32_t pc, uint16_
util::stream_format(stream, "SHLD %s,%s", regname[Rm], regname[Rn]);
break;
case 0xE:
- if (opcode & 0x80) {
+ if (opcode & 0x80)
+ {
util::stream_format(stream, "LDC %s,%s_BANK", regname[Rn],regname[(Rm) & 7]);
return flags;
}
@@ -1079,8 +1084,10 @@ uint32_t sh_disassembler::op1111_sh34(std::ostream &stream, uint32_t pc, uint16_
util::stream_format(stream, "FIPR FV%d, FV%d", (Rn & 3) << 2, Rn & 12);
break;
case 0xF0:
- if (opcode & 0x100) {
- if (opcode & 0x200) {
+ if (opcode & 0x100)
+ {
+ if (opcode & 0x200)
+ {
switch (opcode & 0xC00)
{
case 0x000:
@@ -1093,10 +1100,14 @@ uint32_t sh_disassembler::op1111_sh34(std::ostream &stream, uint32_t pc, uint16_
util::stream_format(stream, "Funknown $%04X", opcode);
break;
}
- } else {
+ }
+ else
+ {
util::stream_format(stream, "FTRV XMTRX, FV%d", Rn & 12);
}
- } else {
+ }
+ else
+ {
util::stream_format(stream, "FSCA FPUL, F%s", regname[Rn & 14]);
}
break;
diff --git a/src/devices/cpu/sh/sh_fe.cpp b/src/devices/cpu/sh/sh_fe.cpp
index 761cd79d342..5e803b8ee00 100644
--- a/src/devices/cpu/sh/sh_fe.cpp
+++ b/src/devices/cpu/sh/sh_fe.cpp
@@ -2,7 +2,7 @@
// copyright-holders:David Haywood, R. Belmont
/***************************************************************************
- sh_fe.c
+ sh_fe.cpp
Front end for SH recompiler
@@ -50,7 +50,7 @@ bool sh_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
return describe_group_0(desc, prev, opcode);
case 1: // MOVLS4
- desc.regin[0] |= REGFLAG_R(Rn) | REGFLAG_R(Rm);
+ desc.regin[0] |= REGFLAG_R(REG_N) | REGFLAG_R(REG_M);
desc.flags |= OPFLAG_WRITES_MEMORY;
return true;
@@ -64,8 +64,8 @@ bool sh_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
return describe_group_4(desc, prev, opcode);
case 5: // MOVLL4
- desc.regin[0] |= REGFLAG_R(Rm);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.flags |= OPFLAG_READS_MEMORY;
return true;
@@ -73,15 +73,15 @@ bool sh_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
return describe_group_6(desc, prev, opcode);
case 7: // ADDI
- desc.regin[0] |= REGFLAG_R(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
+ desc.regout[0] |= REGFLAG_R(REG_N);
return true;
case 8:
return describe_group_8(desc, prev, opcode);
case 9: // MOVWI
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.flags |= OPFLAG_READS_MEMORY;
return true;
@@ -103,12 +103,12 @@ bool sh_frontend::describe(opcode_desc &desc, const opcode_desc *prev)
return describe_group_12(desc, prev, opcode);
case 13: // MOVLI
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.flags |= OPFLAG_READS_MEMORY;
return true;
case 14: // MOVI
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_N);
return true;
case 15: // NOP
@@ -126,7 +126,7 @@ bool sh_frontend::describe_group_2(opcode_desc &desc, const opcode_desc *prev, u
case 0: // MOVBS(Rm, Rn);
case 1: // MOVWS(Rm, Rn);
case 2: // MOVLS(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N);
desc.flags |= OPFLAG_WRITES_MEMORY;
return true;
@@ -137,28 +137,28 @@ bool sh_frontend::describe_group_2(opcode_desc &desc, const opcode_desc *prev, u
case 5: // MOVWM(Rm, Rn);
case 6: // MOVLM(Rm, Rn);
case 13: // XTRCT(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.flags |= OPFLAG_WRITES_MEMORY;
return true;
case 7: // DIV0S(Rm, Rn);
case 8: // TST(Rm, Rn);
case 12: // CMPSTR(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_SR;
return true;
case 9: // AND(Rm, Rn);
case 10: // XOR(Rm, Rn);
case 11: // OR(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N);
+ desc.regout[0] |= REGFLAG_R(REG_N);
return true;
case 14: // MULU(Rm, Rn);
case 15: // MULS(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_MACL | REGFLAG_MACH;
desc.cycles = 2;
return true;
@@ -176,7 +176,7 @@ bool sh_frontend::describe_group_3(opcode_desc &desc, const opcode_desc *prev, u
case 3: // CMPGE(Rm, Rn);
case 6: // CMPHI(Rm, Rn);
case 7: // CMPGT(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_SR;
return true;
@@ -185,31 +185,31 @@ bool sh_frontend::describe_group_3(opcode_desc &desc, const opcode_desc *prev, u
return true;
case 4: // DIV1(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_SR;
return true;
case 5: // DMULU(Rm, Rn);
case 13: // DMULS(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_MACL | REGFLAG_MACH;
desc.cycles = 2;
return true;
case 8: // SUB(Rm, Rn);
case 12: // ADD(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N);
+ desc.regout[0] |= REGFLAG_R(REG_N);
return true;
case 10: // SUBC(Rm, Rn);
case 11: // SUBV(Rm, Rn);
case 14: // ADDC(Rm, Rn);
case 15: // ADDV(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N);
desc.regin[1] |= REGFLAG_SR;
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_SR;
return true;
}
@@ -232,26 +232,26 @@ bool sh_frontend::describe_group_6(opcode_desc &desc, const opcode_desc *prev, u
case 13: // EXTUW(Rm, Rn);
case 14: // EXTSB(Rm, Rn);
case 15: // EXTSW(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M);
+ desc.regout[0] |= REGFLAG_R(REG_N);
return true;
case 4: // MOVBP(Rm, Rn);
case 5: // MOVWP(Rm, Rn);
case 6: // MOVLP(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.flags |= OPFLAG_READS_MEMORY;
return true;
case 8: // SWAPB(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N);
+ desc.regout[0] |= REGFLAG_R(REG_N);
return true;
case 10: // NEGC(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_SR;
return true;
}
@@ -262,46 +262,46 @@ bool sh_frontend::describe_group_8(opcode_desc &desc, const opcode_desc *prev, u
{
int32_t disp;
- switch ( opcode & (15<<8) )
+ switch (opcode & (15 << 8))
{
case 0 << 8: // MOVBS4(opcode & 0x0f, Rm);
case 1 << 8: // MOVWS4(opcode & 0x0f, Rm);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(0);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(0);
desc.flags |= OPFLAG_WRITES_MEMORY;
return true;
- case 2<< 8: // NOP();
- case 3<< 8: // NOP();
- case 6<< 8: // NOP();
- case 7<< 8: // NOP();
- case 10<< 8: // NOP();
- case 12<< 8: // NOP();
- case 14<< 8: // NOP();
+ case 2 << 8: // NOP();
+ case 3 << 8: // NOP();
+ case 6 << 8: // NOP();
+ case 7 << 8: // NOP();
+ case 10 << 8: // NOP();
+ case 12 << 8: // NOP();
+ case 14 << 8: // NOP();
return true;
- case 4<< 8: // MOVBL4(Rm, opcode & 0x0f);
- case 5<< 8: // MOVWL4(Rm, opcode & 0x0f);
- desc.regin[0] |= REGFLAG_R(Rm);
+ case 4 << 8: // MOVBL4(Rm, opcode & 0x0f);
+ case 5 << 8: // MOVWL4(Rm, opcode & 0x0f);
+ desc.regin[0] |= REGFLAG_R(REG_M);
desc.regout[0] |= REGFLAG_R(0);
desc.flags |= OPFLAG_READS_MEMORY;
return true;
- case 8<< 8: // CMPIM(opcode & 0xff);
- desc.regin[0] |= REGFLAG_R(Rm);
+ case 8 << 8: // CMPIM(opcode & 0xff);
+ desc.regin[0] |= REGFLAG_R(REG_M);
desc.regin[1] |= REGFLAG_SR;
desc.regout[1] |= REGFLAG_SR;
return true;
- case 9<< 8: // BT(opcode & 0xff);
- case 11<< 8: // BF(opcode & 0xff);
+ case 9 << 8: // BT(opcode & 0xff);
+ case 11 << 8: // BF(opcode & 0xff);
desc.flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
desc.cycles = 3;
disp = util::sext(opcode, 8);
desc.targetpc = (desc.pc + 2) + disp * 2 + 2;
return true;
- case 13<< 8: // BTS(opcode & 0xff);
- case 15<< 8: // BFS(opcode & 0xff);
+ case 13 << 8: // BTS(opcode & 0xff);
+ case 15 << 8: // BFS(opcode & 0xff);
desc.flags |= OPFLAG_IS_CONDITIONAL_BRANCH;
desc.cycles = 2;
disp = util::sext(opcode, 8);
@@ -317,14 +317,14 @@ bool sh_frontend::describe_group_12(opcode_desc &desc, const opcode_desc *prev,
{
switch (opcode & (15<<8))
{
- case 0<<8: // MOVBSG(opcode & 0xff);
- case 1<<8: // MOVWSG(opcode & 0xff);
- case 2<<8: // MOVLSG(opcode & 0xff);
+ case 0 << 8: // MOVBSG(opcode & 0xff);
+ case 1 << 8: // MOVWSG(opcode & 0xff);
+ case 2 << 8: // MOVLSG(opcode & 0xff);
desc.regin[0] |= REGFLAG_R(0);
desc.flags |= OPFLAG_WRITES_MEMORY;
return true;
- case 3<<8: // TRAPA(opcode & 0xff);
+ case 3 << 8: // TRAPA(opcode & 0xff);
desc.regin[0] |= REGFLAG_R(15);
desc.regin[1] |= REGFLAG_VBR;
desc.regout[0] |= REGFLAG_R(15);
@@ -333,31 +333,31 @@ bool sh_frontend::describe_group_12(opcode_desc &desc, const opcode_desc *prev,
desc.flags |= OPFLAG_READS_MEMORY | OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
return true;
- case 4<<8: // MOVBLG(opcode & 0xff);
- case 5<<8: // MOVWLG(opcode & 0xff);
- case 6<<8: // MOVLLG(opcode & 0xff);
- case 7<<8: // MOVA(opcode & 0xff);
+ case 4 << 8: // MOVBLG(opcode & 0xff);
+ case 5 << 8: // MOVWLG(opcode & 0xff);
+ case 6 << 8: // MOVLLG(opcode & 0xff);
+ case 7 << 8: // MOVA(opcode & 0xff);
desc.regout[0] |= REGFLAG_R(0);
desc.flags |= OPFLAG_READS_MEMORY;
return true;
- case 8<<8: // TSTI(opcode & 0xff);
+ case 8 << 8: // TSTI(opcode & 0xff);
desc.regin[0] |= REGFLAG_R(0);
desc.regin[1] |= REGFLAG_SR;
desc.regout[1] |= REGFLAG_SR;
return true;
- case 9<<8: // ANDI(opcode & 0xff);
- case 10<<8: // XORI(opcode & 0xff);
- case 11<<8: // ORI(opcode & 0xff);
+ case 9 << 8: // ANDI(opcode & 0xff);
+ case 10 << 8: // XORI(opcode & 0xff);
+ case 11 << 8: // ORI(opcode & 0xff);
desc.regin[0] |= REGFLAG_R(0);
desc.regout[0] |= REGFLAG_R(0);
return true;
- case 12<<8: // TSTM(opcode & 0xff);
- case 13<<8: // ANDM(opcode & 0xff);
- case 14<<8: // XORM(opcode & 0xff);
- case 15<<8: // ORM(opcode & 0xff);
+ case 12 << 8: // TSTM(opcode & 0xff);
+ case 13 << 8: // ANDM(opcode & 0xff);
+ case 14 << 8: // XORM(opcode & 0xff);
+ case 15 << 8: // ORM(opcode & 0xff);
desc.regin[0] |= REGFLAG_R(0);
desc.regin[1] |= REGFLAG_SR | REGFLAG_GBR;
desc.regout[1] |= REGFLAG_SR;
@@ -393,7 +393,7 @@ bool sh_frontend::describe_group_0(opcode_desc &desc, const opcode_desc *prev, u
return true;
case 0x02: // STCSR(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_N);
return true;
case 0x03: // BSRF(Rn);
@@ -417,7 +417,7 @@ bool sh_frontend::describe_group_0(opcode_desc &desc, const opcode_desc *prev, u
case 0x34: // MOVBS0(Rm, Rn);
case 0x35: // MOVWS0(Rm, Rn);
case 0x36: // MOVLS0(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn) | REGFLAG_R(0);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N) | REGFLAG_R(0);
desc.flags |= OPFLAG_READS_MEMORY;
return true;
@@ -425,7 +425,7 @@ bool sh_frontend::describe_group_0(opcode_desc &desc, const opcode_desc *prev, u
case 0x17: // MULL(Rm, Rn);
case 0x27: // MULL(Rm, Rn);
case 0x37: // MULL(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rn) | REGFLAG_R(Rm);
+ desc.regin[0] |= REGFLAG_R(REG_N) | REGFLAG_R(REG_M);
desc.regout[1] |= REGFLAG_MACL;
desc.cycles = 2;
return true;
@@ -435,7 +435,7 @@ bool sh_frontend::describe_group_0(opcode_desc &desc, const opcode_desc *prev, u
return true;
case 0x0a: // STSMACH(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_MACH;
return true;
@@ -461,8 +461,8 @@ bool sh_frontend::describe_group_0(opcode_desc &desc, const opcode_desc *prev, u
case 0x3c: // MOVBL0(Rm, Rn);
case 0x3d: // MOVWL0(Rm, Rn);
case 0x3e: // MOVLL0(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(0);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(0);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.flags |= OPFLAG_READS_MEMORY;
return true;
@@ -470,13 +470,13 @@ bool sh_frontend::describe_group_0(opcode_desc &desc, const opcode_desc *prev, u
case 0x1f: // MAC_L(Rm, Rn);
case 0x2f: // MAC_L(Rm, Rn);
case 0x3f: // MAC_L(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_MACL | REGFLAG_MACH;
desc.cycles = 3;
return true;
case 0x12: // STCGBR(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.regin[1] |= REGFLAG_GBR;
return true;
@@ -490,7 +490,7 @@ bool sh_frontend::describe_group_0(opcode_desc &desc, const opcode_desc *prev, u
case 0x1a: // STSMACL(Rn);
desc.regin[1] |= REGFLAG_MACL;
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_N);
return true;
case 0x1b: // SLEEP();
@@ -498,12 +498,12 @@ bool sh_frontend::describe_group_0(opcode_desc &desc, const opcode_desc *prev, u
return true;
case 0x22: // STCVBR(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_VBR;
return true;
case 0x23: // BRAF(Rn);
- desc.regin[0] |= REGFLAG_R(Rm);
+ desc.regin[0] |= REGFLAG_R(REG_M);
desc.flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
desc.targetpc = BRANCH_TARGET_DYNAMIC;
desc.delayslots = 1;
@@ -516,12 +516,12 @@ bool sh_frontend::describe_group_0(opcode_desc &desc, const opcode_desc *prev, u
case 0x29: // MOVT(Rn);
desc.regin[1] |= REGFLAG_SR;
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_N);
return true;
case 0x2a: // STSPR(Rn);
desc.regin[1] |= REGFLAG_PR;
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_N);
return true;
case 0x2b: // RTE();
@@ -548,35 +548,35 @@ bool sh_frontend::describe_group_4(opcode_desc &desc, const opcode_desc *prev, u
case 0x01: // SHLR(Rn);
case 0x04: // ROTL(Rn);
case 0x05: // ROTR(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_SR;
return true;
case 0x02: // STSMMACH(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
desc.regin[1] |= REGFLAG_MACH;
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.flags |= OPFLAG_WRITES_MEMORY;
return true;
case 0x03: // STCMSR(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.cycles = 2;
desc.flags |= OPFLAG_WRITES_MEMORY;
return true;
case 0x06: // LDSMMACH(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_MACH;
desc.flags |= OPFLAG_READS_MEMORY;
return true;
case 0x07: // LDCMSR(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_SR;
desc.cycles = 3;
desc.flags |= OPFLAG_READS_MEMORY | OPFLAG_CAN_EXPOSE_EXTERNAL_INT | OPFLAG_END_SEQUENCE;
@@ -588,17 +588,17 @@ bool sh_frontend::describe_group_4(opcode_desc &desc, const opcode_desc *prev, u
case 0x19: // SHLR8(Rn);
case 0x28: // SHLL16(Rn);
case 0x29: // SHLR16(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
+ desc.regout[0] |= REGFLAG_R(REG_N);
return true;
case 0x0a: // LDSMACH(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_MACH;
return true;
case 0x0b: // JSR(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_PR;
desc.flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
desc.targetpc = BRANCH_TARGET_DYNAMIC;
@@ -606,7 +606,7 @@ bool sh_frontend::describe_group_4(opcode_desc &desc, const opcode_desc *prev, u
return true;
case 0x0e: // LDCSR(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_SR;
desc.flags |= OPFLAG_CAN_EXPOSE_EXTERNAL_INT | OPFLAG_END_SEQUENCE;
return true;
@@ -615,62 +615,62 @@ bool sh_frontend::describe_group_4(opcode_desc &desc, const opcode_desc *prev, u
case 0x1f: // MAC_W(Rm, Rn);
case 0x2f: // MAC_W(Rm, Rn);
case 0x3f: // MAC_W(Rm, Rn);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N);
desc.regin[1] |= REGFLAG_MACL | REGFLAG_MACH;
- desc.regout[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_MACL | REGFLAG_MACH;
desc.cycles = 3;
return true;
case 0x10: // DT(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
desc.regin[1] |= REGFLAG_SR;
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_SR;
return true;
case 0x11: // CMPPZ(Rn);
case 0x15: // CMPPL(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
desc.regin[1] |= REGFLAG_SR;
desc.regout[1] |= REGFLAG_SR;
return true;
case 0x12: // STSMMACL(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
desc.regin[1] |= REGFLAG_MACL;
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.flags |= OPFLAG_WRITES_MEMORY;
return true;
case 0x13: // STCMGBR(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
desc.regin[1] |= REGFLAG_GBR;
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.flags |= OPFLAG_WRITES_MEMORY;
return true;
case 0x16: // LDSMMACL(Rn);
- desc.regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
- desc.regout[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N);
+ desc.regout[0] |= REGFLAG_R(REG_M) | REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_MACL;
desc.flags |= OPFLAG_READS_MEMORY;
return true;
case 0x17: // LDCMGBR(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_GBR;
desc.flags |= OPFLAG_READS_MEMORY;
return true;
case 0x1a: // LDSMACL(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_MACL;
return true;
case 0x1b: // TAS(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
desc.regin[1] |= REGFLAG_SR;
desc.regout[1] |= REGFLAG_SR;
desc.cycles = 4;
@@ -678,67 +678,67 @@ bool sh_frontend::describe_group_4(opcode_desc &desc, const opcode_desc *prev, u
return true;
case 0x1e: // LDCGBR(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_GBR;
return true;
case 0x20: // SHAL(Rn);
case 0x21: // SHAR(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_SR;
return true;
case 0x22: // STSMPR(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
desc.regin[1] |= REGFLAG_PR;
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.flags |= OPFLAG_WRITES_MEMORY;
return true;
case 0x23: // STCMVBR(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
desc.regin[1] |= REGFLAG_VBR;
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.flags |= OPFLAG_WRITES_MEMORY;
return true;
case 0x24: // ROTCL(Rn);
case 0x25: // ROTCR(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
desc.regin[1] |= REGFLAG_SR;
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_SR;
return true;
case 0x26: // LDSMPR(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_PR;
desc.flags |= OPFLAG_READS_MEMORY;
return true;
case 0x27: // LDCMVBR(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
- desc.regout[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
+ desc.regout[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_VBR;
desc.flags |= OPFLAG_READS_MEMORY;
return true;
case 0x2a: // LDSPR(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_PR;
return true;
case 0x2b: // JMP(Rm);
- desc.regin[0] |= REGFLAG_R(Rm);
+ desc.regin[0] |= REGFLAG_R(REG_M);
desc.flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
desc.targetpc = BRANCH_TARGET_DYNAMIC;
desc.delayslots = 1;
return true;
case 0x2e: // LDCVBR(Rn);
- desc.regin[0] |= REGFLAG_R(Rn);
+ desc.regin[0] |= REGFLAG_R(REG_N);
desc.regout[1] |= REGFLAG_VBR;
return true;