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Diffstat (limited to 'src/devices/cpu/sh/sh.cpp')
-rw-r--r--src/devices/cpu/sh/sh.cpp1540
1 files changed, 727 insertions, 813 deletions
diff --git a/src/devices/cpu/sh/sh.cpp b/src/devices/cpu/sh/sh.cpp
index 03fecd135ac..08054e047fe 100644
--- a/src/devices/cpu/sh/sh.cpp
+++ b/src/devices/cpu/sh/sh.cpp
@@ -77,7 +77,7 @@ void sh_common_execution::device_start()
state_add(SH4_R15, "R15", m_sh2_state->r[15]).formatstr("%08X");
state_add(SH4_EA, "EA", m_sh2_state->ea).formatstr("%08X");
- state_add(STATE_GENSP, "GENSP", m_sh2_state->r[15]).noshow();
+ state_add(SH4_SP, "SP", m_sh2_state->r[15]).noshow();
state_add(STATE_GENFLAGS, "GENFLAGS", m_sh2_state->sr).formatstr("%20s").noshow();
set_icountptr(m_sh2_state->icount);
@@ -169,7 +169,7 @@ void sh_common_execution::ADD(uint32_t m, uint32_t n)
*/
void sh_common_execution::ADDI(uint32_t i, uint32_t n)
{
- m_sh2_state->r[n] += (int32_t)(int16_t)(int8_t)i;
+ m_sh2_state->r[n] += util::sext(i, 8);
}
/* code cycles t-bit
@@ -197,24 +197,16 @@ void sh_common_execution::ADDC(uint32_t m, uint32_t n)
*/
void sh_common_execution::ADDV(uint32_t m, uint32_t n)
{
- int32_t dest, src, ans;
-
- if ((int32_t) m_sh2_state->r[n] >= 0)
- dest = 0;
- else
- dest = 1;
- if ((int32_t) m_sh2_state->r[m] >= 0)
- src = 0;
- else
- src = 1;
+ int32_t dest = BIT(m_sh2_state->r[n], 31);
+ int32_t src = BIT(m_sh2_state->r[m], 31);
src += dest;
+
m_sh2_state->r[n] += m_sh2_state->r[m];
- if ((int32_t) m_sh2_state->r[n] >= 0)
- ans = 0;
- else
- ans = 1;
+
+ int32_t ans = BIT(m_sh2_state->r[n], 31);
ans += dest;
- if (src == 0 || src == 2)
+
+ if (src != 1)
{
if (ans == 1)
m_sh2_state->sr |= SH_T;
@@ -249,11 +241,9 @@ void sh_common_execution::ANDI(uint32_t i)
*/
void sh_common_execution::ANDM(uint32_t i)
{
- uint32_t temp;
-
m_sh2_state->ea = m_sh2_state->gbr + m_sh2_state->r[0];
- temp = i & RB( m_sh2_state->ea );
- WB( m_sh2_state->ea, temp );
+ uint32_t temp = i & read_byte(m_sh2_state->ea);
+ write_byte(m_sh2_state->ea, temp);
m_sh2_state->icount -= 2;
}
@@ -265,7 +255,7 @@ void sh_common_execution::BF(uint32_t d)
{
if ((m_sh2_state->sr & SH_T) == 0)
{
- int32_t disp = ((int32_t)d << 24) >> 24;
+ int32_t disp = util::sext(d, 8);
m_sh2_state->pc = m_sh2_state->ea = m_sh2_state->pc + disp * 2 + 2;
m_sh2_state->icount -= 2;
}
@@ -279,7 +269,7 @@ void sh_common_execution::BFS(uint32_t d)
{
if ((m_sh2_state->sr & SH_T) == 0)
{
- int32_t disp = ((int32_t)d << 24) >> 24;
+ int32_t disp = util::sext(d, 8);
m_sh2_state->m_delay = m_sh2_state->ea = m_sh2_state->pc + disp * 2 + 2;
m_sh2_state->icount--;
}
@@ -291,12 +281,12 @@ void sh_common_execution::BFS(uint32_t d)
*/
void sh_common_execution::BRA(uint32_t d)
{
- int32_t disp = ((int32_t)d << 20) >> 20;
+ int32_t disp = util::sext(d, 12);
#if BUSY_LOOP_HACKS
if (disp == -2)
{
- uint32_t next_opcode = RW(m_sh2_state->pc & AM);
+ uint32_t next_opcode = read_word(m_sh2_state->pc & m_am);
/* BRA $
* NOP
*/
@@ -324,7 +314,7 @@ void sh_common_execution::BRAF(uint32_t m)
*/
void sh_common_execution::BSR(uint32_t d)
{
- int32_t disp = ((int32_t)d << 20) >> 20;
+ int32_t disp = util::sext(d, 12);
m_sh2_state->pr = m_sh2_state->pc + 2;
m_sh2_state->m_delay = m_sh2_state->ea = m_sh2_state->pc + disp * 2 + 2;
@@ -350,7 +340,7 @@ void sh_common_execution::BT(uint32_t d)
{
if ((m_sh2_state->sr & SH_T) != 0)
{
- int32_t disp = ((int32_t)d << 24) >> 24;
+ int32_t disp = util::sext(d, 8);
m_sh2_state->pc = m_sh2_state->ea = m_sh2_state->pc + disp * 2 + 2;
m_sh2_state->icount -= 2;
}
@@ -364,7 +354,7 @@ void sh_common_execution::BTS(uint32_t d)
{
if ((m_sh2_state->sr & SH_T) != 0)
{
- int32_t disp = ((int32_t)d << 24) >> 24;
+ int32_t disp = util::sext(d, 8);
m_sh2_state->m_delay = m_sh2_state->ea = m_sh2_state->pc + disp * 2 + 2;
m_sh2_state->icount--;
}
@@ -407,7 +397,7 @@ void sh_common_execution::CMPEQ(uint32_t m, uint32_t n)
*/
void sh_common_execution::CMPGE(uint32_t m, uint32_t n)
{
- if ((int32_t) m_sh2_state->r[n] >= (int32_t) m_sh2_state->r[m])
+ if ((int32_t)m_sh2_state->r[n] >= (int32_t)m_sh2_state->r[m])
m_sh2_state->sr |= SH_T;
else
m_sh2_state->sr &= ~SH_T;
@@ -419,7 +409,7 @@ void sh_common_execution::CMPGE(uint32_t m, uint32_t n)
*/
void sh_common_execution::CMPGT(uint32_t m, uint32_t n)
{
- if ((int32_t) m_sh2_state->r[n] > (int32_t) m_sh2_state->r[m])
+ if ((int32_t)m_sh2_state->r[n] > (int32_t)m_sh2_state->r[m])
m_sh2_state->sr |= SH_T;
else
m_sh2_state->sr &= ~SH_T;
@@ -431,7 +421,7 @@ void sh_common_execution::CMPGT(uint32_t m, uint32_t n)
*/
void sh_common_execution::CMPHI(uint32_t m, uint32_t n)
{
- if ((uint32_t) m_sh2_state->r[n] > (uint32_t) m_sh2_state->r[m])
+ if (m_sh2_state->r[n] > m_sh2_state->r[m])
m_sh2_state->sr |= SH_T;
else
m_sh2_state->sr &= ~SH_T;
@@ -443,7 +433,7 @@ void sh_common_execution::CMPHI(uint32_t m, uint32_t n)
*/
void sh_common_execution::CMPHS(uint32_t m, uint32_t n)
{
- if ((uint32_t) m_sh2_state->r[n] >= (uint32_t) m_sh2_state->r[m])
+ if (m_sh2_state->r[n] >= m_sh2_state->r[m])
m_sh2_state->sr |= SH_T;
else
m_sh2_state->sr &= ~SH_T;
@@ -455,7 +445,7 @@ void sh_common_execution::CMPHS(uint32_t m, uint32_t n)
*/
void sh_common_execution::CMPPL(uint32_t n)
{
- if ((int32_t) m_sh2_state->r[n] > 0)
+ if ((int32_t)m_sh2_state->r[n] > 0)
m_sh2_state->sr |= SH_T;
else
m_sh2_state->sr &= ~SH_T;
@@ -467,7 +457,7 @@ void sh_common_execution::CMPPL(uint32_t n)
*/
void sh_common_execution::CMPPZ(uint32_t n)
{
- if ((int32_t) m_sh2_state->r[n] >= 0)
+ if ((int32_t)m_sh2_state->r[n] >= 0)
m_sh2_state->sr |= SH_T;
else
m_sh2_state->sr &= ~SH_T;
@@ -479,14 +469,12 @@ void sh_common_execution::CMPPZ(uint32_t n)
*/
void sh_common_execution::CMPSTR(uint32_t m, uint32_t n)
{
- uint32_t temp;
- int32_t HH, HL, LH, LL;
- temp = m_sh2_state->r[n] ^ m_sh2_state->r[m];
- HH = (temp >> 24) & 0xff;
- HL = (temp >> 16) & 0xff;
- LH = (temp >> 8) & 0xff;
- LL = temp & 0xff;
- if (HH && HL && LH && LL)
+ uint32_t temp = m_sh2_state->r[n] ^ m_sh2_state->r[m];
+ uint8_t upper_byte = (temp >> 24) & 0xff;
+ uint8_t mid_upper_byte = (temp >> 16) & 0xff;
+ uint8_t mid_lower_byte = (temp >> 8) & 0xff;
+ uint8_t lower_byte = temp & 0xff;
+ if (upper_byte && mid_upper_byte && mid_lower_byte && lower_byte)
m_sh2_state->sr &= ~SH_T;
else
m_sh2_state->sr |= SH_T;
@@ -498,7 +486,7 @@ void sh_common_execution::CMPSTR(uint32_t m, uint32_t n)
*/
void sh_common_execution::CMPIM(uint32_t i)
{
- uint32_t imm = (uint32_t)(int32_t)(int16_t)(int8_t)i;
+ uint32_t imm = (uint32_t)util::sext(i, 8);
if (m_sh2_state->r[0] == imm)
m_sh2_state->sr |= SH_T;
@@ -512,15 +500,17 @@ void sh_common_execution::CMPIM(uint32_t i)
*/
void sh_common_execution::DIV0S(uint32_t m, uint32_t n)
{
- if ((m_sh2_state->r[n] & 0x80000000) == 0)
+ if (!BIT(m_sh2_state->r[n], 31))
m_sh2_state->sr &= ~SH_Q;
else
m_sh2_state->sr |= SH_Q;
- if ((m_sh2_state->r[m] & 0x80000000) == 0)
+
+ if (!BIT(m_sh2_state->r[m], 31))
m_sh2_state->sr &= ~SH_M;
else
m_sh2_state->sr |= SH_M;
- if ((m_sh2_state->r[m] ^ m_sh2_state->r[n]) & 0x80000000)
+
+ if (BIT(m_sh2_state->r[m] ^ m_sh2_state->r[n], 31))
m_sh2_state->sr |= SH_T;
else
m_sh2_state->sr &= ~SH_T;
@@ -541,10 +531,7 @@ void sh_common_execution::DIV0U()
*/
void sh_common_execution::DIV1(uint32_t m, uint32_t n)
{
- uint32_t tmp0;
- uint32_t old_q;
-
- old_q = m_sh2_state->sr & SH_Q;
+ uint32_t old_q = m_sh2_state->sr & SH_Q;
if (0x80000000 & m_sh2_state->r[n])
m_sh2_state->sr |= SH_Q;
else
@@ -556,33 +543,33 @@ void sh_common_execution::DIV1(uint32_t m, uint32_t n)
{
if (!(m_sh2_state->sr & SH_M))
{
- tmp0 = m_sh2_state->r[n];
+ uint32_t tmp = m_sh2_state->r[n];
m_sh2_state->r[n] -= m_sh2_state->r[m];
- if(!(m_sh2_state->sr & SH_Q))
- if(m_sh2_state->r[n] > tmp0)
+ if (!(m_sh2_state->sr & SH_Q))
+ if (m_sh2_state->r[n] > tmp)
m_sh2_state->sr |= SH_Q;
else
m_sh2_state->sr &= ~SH_Q;
else
- if(m_sh2_state->r[n] > tmp0)
+ if (m_sh2_state->r[n] > tmp)
m_sh2_state->sr &= ~SH_Q;
else
m_sh2_state->sr |= SH_Q;
}
else
{
- tmp0 = m_sh2_state->r[n];
+ uint32_t tmp = m_sh2_state->r[n];
m_sh2_state->r[n] += m_sh2_state->r[m];
- if(!(m_sh2_state->sr & SH_Q))
+ if (!(m_sh2_state->sr & SH_Q))
{
- if(m_sh2_state->r[n] < tmp0)
+ if (m_sh2_state->r[n] < tmp)
m_sh2_state->sr &= ~SH_Q;
else
m_sh2_state->sr |= SH_Q;
}
else
{
- if(m_sh2_state->r[n] < tmp0)
+ if (m_sh2_state->r[n] < tmp)
m_sh2_state->sr |= SH_Q;
else
m_sh2_state->sr &= ~SH_Q;
@@ -593,38 +580,38 @@ void sh_common_execution::DIV1(uint32_t m, uint32_t n)
{
if (!(m_sh2_state->sr & SH_M))
{
- tmp0 = m_sh2_state->r[n];
+ uint32_t tmp = m_sh2_state->r[n];
m_sh2_state->r[n] += m_sh2_state->r[m];
- if(!(m_sh2_state->sr & SH_Q))
- if(m_sh2_state->r[n] < tmp0)
+ if (!(m_sh2_state->sr & SH_Q))
+ if (m_sh2_state->r[n] < tmp)
m_sh2_state->sr |= SH_Q;
else
m_sh2_state->sr &= ~SH_Q;
else
- if(m_sh2_state->r[n] < tmp0)
+ if (m_sh2_state->r[n] < tmp)
m_sh2_state->sr &= ~SH_Q;
else
m_sh2_state->sr |= SH_Q;
}
else
{
- tmp0 = m_sh2_state->r[n];
+ uint32_t tmp = m_sh2_state->r[n];
m_sh2_state->r[n] -= m_sh2_state->r[m];
- if(!(m_sh2_state->sr & SH_Q))
- if(m_sh2_state->r[n] > tmp0)
+ if (!(m_sh2_state->sr & SH_Q))
+ if (m_sh2_state->r[n] > tmp)
m_sh2_state->sr &= ~SH_Q;
else
m_sh2_state->sr |= SH_Q;
else
- if(m_sh2_state->r[n] > tmp0)
+ if (m_sh2_state->r[n] > tmp)
m_sh2_state->sr |= SH_Q;
else
m_sh2_state->sr &= ~SH_Q;
}
}
- tmp0 = (m_sh2_state->sr & (SH_Q | SH_M));
- if((!tmp0) || (tmp0 == 0x300)) /* if Q == M set T else clear T */
+ uint32_t tmp = (m_sh2_state->sr & (SH_Q | SH_M));
+ if (tmp == 0 || tmp == 0x300) /* if Q == M set T else clear T */
m_sh2_state->sr |= SH_T;
else
m_sh2_state->sr &= ~SH_T;
@@ -633,77 +620,77 @@ void sh_common_execution::DIV1(uint32_t m, uint32_t n)
/* DMULS.L Rm,Rn */
void sh_common_execution::DMULS(uint32_t m, uint32_t n)
{
- uint32_t RnL, RnH, RmL, RmH, Res0, Res1, Res2;
- uint32_t temp0, temp1, temp2, temp3;
- int32_t tempm, tempn, fnLmL;
+ int32_t tempn = (int32_t)m_sh2_state->r[n];
+ int32_t tempm = (int32_t)m_sh2_state->r[m];
+ bool fnlml = (bool)BIT(tempn ^ tempm, 31);
- tempn = (int32_t) m_sh2_state->r[n];
- tempm = (int32_t) m_sh2_state->r[m];
if (tempn < 0)
tempn = 0 - tempn;
if (tempm < 0)
tempm = 0 - tempm;
- if ((int32_t) (m_sh2_state->r[n] ^ m_sh2_state->r[m]) < 0)
- fnLmL = -1;
- else
- fnLmL = 0;
- temp1 = (uint32_t) tempn;
- temp2 = (uint32_t) tempm;
- RnL = temp1 & 0x0000ffff;
- RnH = (temp1 >> 16) & 0x0000ffff;
- RmL = temp2 & 0x0000ffff;
- RmH = (temp2 >> 16) & 0x0000ffff;
- temp0 = RmL * RnL;
- temp1 = RmH * RnL;
- temp2 = RmL * RnH;
- temp3 = RmH * RnH;
- Res2 = 0;
- Res1 = temp1 + temp2;
- if (Res1 < temp1)
- Res2 += 0x00010000;
- temp1 = (Res1 << 16) & 0xffff0000;
- Res0 = temp0 + temp1;
- if (Res0 < temp0)
- Res2++;
- Res2 = Res2 + ((Res1 >> 16) & 0x0000ffff) + temp3;
- if (fnLmL < 0)
+
+ uint32_t rn_l = (uint32_t)tempn & 0x0000ffff;
+ uint32_t rn_h = (uint32_t)tempn >> 16;
+ uint32_t rm_l = (uint32_t)tempm & 0x0000ffff;
+ uint32_t rm_h = (uint32_t)tempm >> 16;
+
+ uint32_t temp0 = rm_l * rn_l;
+ uint32_t temp1 = rm_h * rn_l;
+ uint32_t temp2 = rm_l * rn_h;
+ uint32_t temp3 = rm_h * rn_h;
+
+ uint32_t res2 = 0;
+ uint32_t res1 = temp1 + temp2;
+ if (res1 < temp1)
+ res2 += 0x00010000;
+ temp1 = res1 << 16;
+
+ uint32_t res0 = temp0 + temp1;
+ if (res0 < temp0)
+ res2++;
+ res2 = res2 + (res1 >> 16) + temp3;
+
+ if (fnlml)
{
- Res2 = ~Res2;
- if (Res0 == 0)
- Res2++;
+ res2 = ~res2;
+ if (res0 == 0)
+ res2++;
else
- Res0 = (~Res0) + 1;
+ res0 = (~res0) + 1;
}
- m_sh2_state->mach = Res2;
- m_sh2_state->macl = Res0;
+
+ m_sh2_state->mach = res2;
+ m_sh2_state->macl = res0;
m_sh2_state->icount--;
}
/* DMULU.L Rm,Rn */
void sh_common_execution::DMULU(uint32_t m, uint32_t n)
{
- uint32_t RnL, RnH, RmL, RmH, Res0, Res1, Res2;
- uint32_t temp0, temp1, temp2, temp3;
-
- RnL = m_sh2_state->r[n] & 0x0000ffff;
- RnH = (m_sh2_state->r[n] >> 16) & 0x0000ffff;
- RmL = m_sh2_state->r[m] & 0x0000ffff;
- RmH = (m_sh2_state->r[m] >> 16) & 0x0000ffff;
- temp0 = RmL * RnL;
- temp1 = RmH * RnL;
- temp2 = RmL * RnH;
- temp3 = RmH * RnH;
- Res2 = 0;
- Res1 = temp1 + temp2;
- if (Res1 < temp1)
- Res2 += 0x00010000;
- temp1 = (Res1 << 16) & 0xffff0000;
- Res0 = temp0 + temp1;
- if (Res0 < temp0)
- Res2++;
- Res2 = Res2 + ((Res1 >> 16) & 0x0000ffff) + temp3;
- m_sh2_state->mach = Res2;
- m_sh2_state->macl = Res0;
+ uint32_t rn_l = m_sh2_state->r[n] & 0x0000ffff;
+ uint32_t rn_h = m_sh2_state->r[n] >> 16;
+ uint32_t rm_l = m_sh2_state->r[m] & 0x0000ffff;
+ uint32_t rm_h = m_sh2_state->r[m] >> 16;
+
+ uint32_t temp0 = rm_l * rn_l;
+ uint32_t temp1 = rm_h * rn_l;
+ uint32_t temp2 = rm_l * rn_h;
+ uint32_t temp3 = rm_h * rn_h;
+
+ uint32_t res2 = 0;
+ uint32_t res1 = temp1 + temp2;
+ if (res1 < temp1)
+ res2 += 0x00010000;
+
+ temp1 = res1 << 16;
+ uint32_t res0 = temp0 + temp1;
+ if (res0 < temp0)
+ res2++;
+
+ res2 = res2 + (res1 >> 16) + temp3;
+
+ m_sh2_state->mach = res2;
+ m_sh2_state->macl = res0;
m_sh2_state->icount--;
}
@@ -717,7 +704,7 @@ void sh_common_execution::DT(uint32_t n)
m_sh2_state->sr &= ~SH_T;
#if BUSY_LOOP_HACKS
{
- uint32_t next_opcode = RW(m_sh2_state->pc & AM);
+ uint32_t next_opcode = read_word(m_sh2_state->pc & AM);
/* DT Rn
* BF $-2
*/
@@ -736,13 +723,13 @@ void sh_common_execution::DT(uint32_t n)
/* EXTS.B Rm,Rn */
void sh_common_execution::EXTSB(uint32_t m, uint32_t n)
{
- m_sh2_state->r[n] = ((int32_t)m_sh2_state->r[m] << 24) >> 24;
+ m_sh2_state->r[n] = util::sext(m_sh2_state->r[m], 8);
}
/* EXTS.W Rm,Rn */
void sh_common_execution::EXTSW(uint32_t m, uint32_t n)
{
- m_sh2_state->r[n] = ((int32_t)m_sh2_state->r[m] << 16) >> 16;
+ m_sh2_state->r[n] = util::sext(m_sh2_state->r[m], 16);
}
/* EXTU.B Rm,Rn */
@@ -788,7 +775,7 @@ void sh_common_execution::LDCVBR(uint32_t m)
void sh_common_execution::LDCMGBR(uint32_t m)
{
m_sh2_state->ea = m_sh2_state->r[m];
- m_sh2_state->gbr = RL( m_sh2_state->ea );
+ m_sh2_state->gbr = read_long(m_sh2_state->ea);
m_sh2_state->r[m] += 4;
m_sh2_state->icount -= 2;
}
@@ -797,7 +784,7 @@ void sh_common_execution::LDCMGBR(uint32_t m)
void sh_common_execution::LDCMVBR(uint32_t m)
{
m_sh2_state->ea = m_sh2_state->r[m];
- m_sh2_state->vbr = RL( m_sh2_state->ea );
+ m_sh2_state->vbr = read_long(m_sh2_state->ea);
m_sh2_state->r[m] += 4;
m_sh2_state->icount -= 2;
}
@@ -824,7 +811,7 @@ void sh_common_execution::LDSPR(uint32_t m)
void sh_common_execution::LDSMMACH(uint32_t m)
{
m_sh2_state->ea = m_sh2_state->r[m];
- m_sh2_state->mach = RL( m_sh2_state->ea );
+ m_sh2_state->mach = read_long(m_sh2_state->ea);
m_sh2_state->r[m] += 4;
}
@@ -832,7 +819,7 @@ void sh_common_execution::LDSMMACH(uint32_t m)
void sh_common_execution::LDSMMACL(uint32_t m)
{
m_sh2_state->ea = m_sh2_state->r[m];
- m_sh2_state->macl = RL( m_sh2_state->ea );
+ m_sh2_state->macl = read_long(m_sh2_state->ea);
m_sh2_state->r[m] += 4;
}
@@ -840,83 +827,83 @@ void sh_common_execution::LDSMMACL(uint32_t m)
void sh_common_execution::LDSMPR(uint32_t m)
{
m_sh2_state->ea = m_sh2_state->r[m];
- m_sh2_state->pr = RL( m_sh2_state->ea );
+ m_sh2_state->pr = read_long(m_sh2_state->ea);
m_sh2_state->r[m] += 4;
}
/* MAC.L @Rm+,@Rn+ */
void sh_common_execution::MAC_L(uint32_t m, uint32_t n)
{
- uint32_t RnL, RnH, RmL, RmH, Res0, Res1, Res2;
- uint32_t temp0, temp1, temp2, temp3;
- int32_t tempm, tempn, fnLmL;
-
- tempn = (int32_t) RL( m_sh2_state->r[n] );
+ int32_t tempn = (int32_t)read_long(m_sh2_state->r[n]);
m_sh2_state->r[n] += 4;
- tempm = (int32_t) RL( m_sh2_state->r[m] );
+
+ int32_t tempm = (int32_t)read_long(m_sh2_state->r[m]);
m_sh2_state->r[m] += 4;
- if ((int32_t) (tempn ^ tempm) < 0)
- fnLmL = -1;
- else
- fnLmL = 0;
+
+ bool fnlml = BIT(tempn ^ tempm, 31);
+
if (tempn < 0)
tempn = 0 - tempn;
if (tempm < 0)
tempm = 0 - tempm;
- temp1 = (uint32_t) tempn;
- temp2 = (uint32_t) tempm;
- RnL = temp1 & 0x0000ffff;
- RnH = (temp1 >> 16) & 0x0000ffff;
- RmL = temp2 & 0x0000ffff;
- RmH = (temp2 >> 16) & 0x0000ffff;
- temp0 = RmL * RnL;
- temp1 = RmH * RnL;
- temp2 = RmL * RnH;
- temp3 = RmH * RnH;
- Res2 = 0;
- Res1 = temp1 + temp2;
- if (Res1 < temp1)
- Res2 += 0x00010000;
- temp1 = (Res1 << 16) & 0xffff0000;
- Res0 = temp0 + temp1;
- if (Res0 < temp0)
- Res2++;
- Res2 = Res2 + ((Res1 >> 16) & 0x0000ffff) + temp3;
- if (fnLmL < 0)
+
+ uint32_t rn_l = (uint32_t)tempn & 0x0000ffff;
+ uint32_t rn_h = (uint32_t)tempn >> 16;
+ uint32_t rm_l = (uint32_t)tempm & 0x0000ffff;
+ uint32_t rm_h = (uint32_t)tempm >> 16;
+
+ uint32_t temp0 = rm_l * rn_l;
+ uint32_t temp1 = rm_h * rn_l;
+ uint32_t temp2 = rm_l * rn_h;
+ uint32_t temp3 = rm_h * rn_h;
+
+ uint32_t res2 = 0;
+ uint32_t res1 = temp1 + temp2;
+ if (res1 < temp1)
+ res2 += 0x00010000;
+ temp1 = res1 << 16;
+
+ uint32_t res0 = temp0 + temp1;
+ if (res0 < temp0)
+ res2++;
+ res2 = res2 + (res1 >> 16) + temp3;
+
+ if (fnlml)
{
- Res2 = ~Res2;
- if (Res0 == 0)
- Res2++;
+ res2 = ~res2;
+ if (res0 == 0)
+ res2++;
else
- Res0 = (~Res0) + 1;
+ res0 = (~res0) + 1;
}
+
if (m_sh2_state->sr & SH_S)
{
- Res0 = m_sh2_state->macl + Res0;
- if (m_sh2_state->macl > Res0)
- Res2++;
- Res2 += (m_sh2_state->mach & 0x0000ffff);
- if (((int32_t) Res2 < 0) && (Res2 < 0xffff8000))
+ res0 = m_sh2_state->macl + res0;
+ if (m_sh2_state->macl > res0)
+ res2++;
+ res2 += m_sh2_state->mach & 0x0000ffff;
+ if ((int32_t)res2 < 0 && res2 < 0xffff8000)
{
- Res2 = 0x00008000;
- Res0 = 0x00000000;
+ res2 = 0x00008000;
+ res0 = 0x00000000;
}
- else if (((int32_t) Res2 > 0) && (Res2 > 0x00007fff))
+ else if ((int32_t)res2 > 0 && res2 > 0x00007fff)
{
- Res2 = 0x00007fff;
- Res0 = 0xffffffff;
+ res2 = 0x00007fff;
+ res0 = 0xffffffff;
}
- m_sh2_state->mach = Res2;
- m_sh2_state->macl = Res0;
+ m_sh2_state->mach = res2;
+ m_sh2_state->macl = res0;
}
else
{
- Res0 = m_sh2_state->macl + Res0;
- if (m_sh2_state->macl > Res0)
- Res2++;
- Res2 += m_sh2_state->mach;
- m_sh2_state->mach = Res2;
- m_sh2_state->macl = Res0;
+ res0 = m_sh2_state->macl + res0;
+ if (m_sh2_state->macl > res0)
+ res2++;
+ res2 += m_sh2_state->mach;
+ m_sh2_state->mach = res2;
+ m_sh2_state->macl = res0;
}
m_sh2_state->icount -= 2;
}
@@ -924,45 +911,32 @@ void sh_common_execution::MAC_L(uint32_t m, uint32_t n)
/* MAC.W @Rm+,@Rn+ */
void sh_common_execution::MAC_W(uint32_t m, uint32_t n)
{
- int32_t tempm, tempn, dest, src, ans;
- uint32_t templ;
-
- tempn = (int32_t) RW( m_sh2_state->r[n] );
+ int32_t tempn = (int32_t)(int16_t)read_word(m_sh2_state->r[n]);
m_sh2_state->r[n] += 2;
- tempm = (int32_t) RW( m_sh2_state->r[m] );
+
+ int32_t tempm = (int32_t)(int16_t)read_word(m_sh2_state->r[m]);
m_sh2_state->r[m] += 2;
- templ = m_sh2_state->macl;
- tempm = ((int32_t) (short) tempn * (int32_t) (short) tempm);
- if ((int32_t) m_sh2_state->macl >= 0)
- dest = 0;
- else
- dest = 1;
- if ((int32_t) tempm >= 0)
- {
- src = 0;
- tempn = 0;
- }
- else
- {
- src = 1;
- tempn = 0xffffffff;
- }
- src += dest;
+
+ uint32_t templ = m_sh2_state->macl;
+ tempm *= tempn;
+
+ int32_t dest = BIT(m_sh2_state->macl, 31);
+ int32_t src = BIT(tempm, 31) + dest;
+ tempn = BIT(tempm, 31) ? -1 : 0;
+
m_sh2_state->macl += tempm;
- if ((int32_t) m_sh2_state->macl >= 0)
- ans = 0;
- else
- ans = 1;
- ans += dest;
+
+ int32_t ans = BIT(m_sh2_state->macl, 31) + dest;
+
if (m_sh2_state->sr & SH_S)
{
if (ans == 1)
- {
- if (src == 0)
- m_sh2_state->macl = 0x7fffffff;
- if (src == 2)
- m_sh2_state->macl = 0x80000000;
- }
+ {
+ if (src == 0)
+ m_sh2_state->macl = 0x7fffffff;
+ else if (src == 2)
+ m_sh2_state->macl = 0x80000000;
+ }
}
else
{
@@ -983,61 +957,60 @@ void sh_common_execution::MOV(uint32_t m, uint32_t n)
void sh_common_execution::MOVBS(uint32_t m, uint32_t n)
{
m_sh2_state->ea = m_sh2_state->r[n];
- WB( m_sh2_state->ea, m_sh2_state->r[m] & 0x000000ff);
+ write_byte(m_sh2_state->ea, m_sh2_state->r[m] & 0x000000ff);
}
/* MOV.W Rm,@Rn */
void sh_common_execution::MOVWS(uint32_t m, uint32_t n)
{
m_sh2_state->ea = m_sh2_state->r[n];
- WW( m_sh2_state->ea, m_sh2_state->r[m] & 0x0000ffff);
+ write_word(m_sh2_state->ea, m_sh2_state->r[m] & 0x0000ffff);
}
/* MOV.L Rm,@Rn */
void sh_common_execution::MOVLS(uint32_t m, uint32_t n)
{
m_sh2_state->ea = m_sh2_state->r[n];
- WL( m_sh2_state->ea, m_sh2_state->r[m] );
+ write_long(m_sh2_state->ea, m_sh2_state->r[m]);
}
/* MOV.B @Rm,Rn */
void sh_common_execution::MOVBL(uint32_t m, uint32_t n)
{
m_sh2_state->ea = m_sh2_state->r[m];
- m_sh2_state->r[n] = (uint32_t)(int32_t)(int16_t)(int8_t) RB( m_sh2_state->ea );
+ m_sh2_state->r[n] = (uint32_t)util::sext(read_byte(m_sh2_state->ea), 8);
}
/* MOV.W @Rm,Rn */
void sh_common_execution::MOVWL(uint32_t m, uint32_t n)
{
m_sh2_state->ea = m_sh2_state->r[m];
- m_sh2_state->r[n] = (uint32_t)(int32_t)(int16_t) RW( m_sh2_state->ea );
+ m_sh2_state->r[n] = (uint32_t)util::sext(read_word(m_sh2_state->ea), 16);
}
/* MOV.L @Rm,Rn */
void sh_common_execution::MOVLL(uint32_t m, uint32_t n)
{
m_sh2_state->ea = m_sh2_state->r[m];
- m_sh2_state->r[n] = RL( m_sh2_state->ea );
+ m_sh2_state->r[n] = read_long(m_sh2_state->ea);
}
/* MOV.B Rm,@-Rn */
void sh_common_execution::MOVBM(uint32_t m, uint32_t n)
{
- /* SMG : bug fix, was reading m_sh2_state->r[n] */
- uint32_t data = m_sh2_state->r[m] & 0x000000ff;
+ uint8_t data(m_sh2_state->r[m]);
m_sh2_state->r[n] -= 1;
- WB( m_sh2_state->r[n], data );
+ write_byte(m_sh2_state->r[n], data);
}
/* MOV.W Rm,@-Rn */
void sh_common_execution::MOVWM(uint32_t m, uint32_t n)
{
- uint32_t data = m_sh2_state->r[m] & 0x0000ffff;
+ uint16_t data(m_sh2_state->r[m]);
m_sh2_state->r[n] -= 2;
- WW( m_sh2_state->r[n], data );
+ write_word(m_sh2_state->r[n], data);
}
/* MOV.L Rm,@-Rn */
@@ -1046,13 +1019,13 @@ void sh_common_execution::MOVLM(uint32_t m, uint32_t n)
uint32_t data = m_sh2_state->r[m];
m_sh2_state->r[n] -= 4;
- WL( m_sh2_state->r[n], data );
+ write_long(m_sh2_state->r[n], data);
}
/* MOV.B @Rm+,Rn */
void sh_common_execution::MOVBP(uint32_t m, uint32_t n)
{
- m_sh2_state->r[n] = (uint32_t)(int32_t)(int16_t)(int8_t) RB( m_sh2_state->r[m] );
+ m_sh2_state->r[n] = (uint32_t)util::sext(read_byte(m_sh2_state->r[m]), 8);
if (n != m)
m_sh2_state->r[m] += 1;
}
@@ -1060,7 +1033,7 @@ void sh_common_execution::MOVBP(uint32_t m, uint32_t n)
/* MOV.W @Rm+,Rn */
void sh_common_execution::MOVWP(uint32_t m, uint32_t n)
{
- m_sh2_state->r[n] = (uint32_t)(int32_t)(int16_t) RW( m_sh2_state->r[m] );
+ m_sh2_state->r[n] = (uint32_t)util::sext(read_word(m_sh2_state->r[m]), 16);
if (n != m)
m_sh2_state->r[m] += 2;
}
@@ -1068,7 +1041,7 @@ void sh_common_execution::MOVWP(uint32_t m, uint32_t n)
/* MOV.L @Rm+,Rn */
void sh_common_execution::MOVLP(uint32_t m, uint32_t n)
{
- m_sh2_state->r[n] = RL( m_sh2_state->r[m] );
+ m_sh2_state->r[n] = read_long(m_sh2_state->r[m]);
if (n != m)
m_sh2_state->r[m] += 4;
}
@@ -1077,48 +1050,48 @@ void sh_common_execution::MOVLP(uint32_t m, uint32_t n)
void sh_common_execution::MOVBS0(uint32_t m, uint32_t n)
{
m_sh2_state->ea = m_sh2_state->r[n] + m_sh2_state->r[0];
- WB( m_sh2_state->ea, m_sh2_state->r[m] & 0x000000ff );
+ write_byte(m_sh2_state->ea, (uint8_t)m_sh2_state->r[m]);
}
/* MOV.W Rm,@(R0,Rn) */
void sh_common_execution::MOVWS0(uint32_t m, uint32_t n)
{
m_sh2_state->ea = m_sh2_state->r[n] + m_sh2_state->r[0];
- WW( m_sh2_state->ea, m_sh2_state->r[m] & 0x0000ffff );
+ write_word(m_sh2_state->ea, (uint16_t)m_sh2_state->r[m]);
}
/* MOV.L Rm,@(R0,Rn) */
void sh_common_execution::MOVLS0(uint32_t m, uint32_t n)
{
m_sh2_state->ea = m_sh2_state->r[n] + m_sh2_state->r[0];
- WL( m_sh2_state->ea, m_sh2_state->r[m] );
+ write_long(m_sh2_state->ea, m_sh2_state->r[m]);
}
/* MOV.B @(R0,Rm),Rn */
void sh_common_execution::MOVBL0(uint32_t m, uint32_t n)
{
m_sh2_state->ea = m_sh2_state->r[m] + m_sh2_state->r[0];
- m_sh2_state->r[n] = (uint32_t)(int32_t)(int16_t)(int8_t) RB( m_sh2_state->ea );
+ m_sh2_state->r[n] = (uint32_t)util::sext(read_byte(m_sh2_state->ea), 8);
}
/* MOV.W @(R0,Rm),Rn */
void sh_common_execution::MOVWL0(uint32_t m, uint32_t n)
{
m_sh2_state->ea = m_sh2_state->r[m] + m_sh2_state->r[0];
- m_sh2_state->r[n] = (uint32_t)(int32_t)(int16_t) RW( m_sh2_state->ea );
+ m_sh2_state->r[n] = (uint32_t)util::sext(read_word(m_sh2_state->ea), 16);
}
/* MOV.L @(R0,Rm),Rn */
void sh_common_execution::MOVLL0(uint32_t m, uint32_t n)
{
m_sh2_state->ea = m_sh2_state->r[m] + m_sh2_state->r[0];
- m_sh2_state->r[n] = RL( m_sh2_state->ea );
+ m_sh2_state->r[n] = read_long(m_sh2_state->ea);
}
/* MOV #imm,Rn */
void sh_common_execution::MOVI(uint32_t i, uint32_t n)
{
- m_sh2_state->r[n] = (uint32_t)(int32_t)(int16_t)(int8_t) i;
+ m_sh2_state->r[n] = (uint32_t)util::sext(i, 8);
}
/* MOV.W @(disp8,PC),Rn */
@@ -1126,7 +1099,7 @@ void sh_common_execution::MOVWI(uint32_t d, uint32_t n)
{
uint32_t disp = d & 0xff;
m_sh2_state->ea = m_sh2_state->pc + disp * 2 + 2;
- m_sh2_state->r[n] = (uint32_t)(int32_t)(int16_t) RW( m_sh2_state->ea );
+ m_sh2_state->r[n] = (uint32_t)util::sext(read_word(m_sh2_state->ea), 16);
}
/* MOV.L @(disp8,PC),Rn */
@@ -1134,7 +1107,7 @@ void sh_common_execution::MOVLI(uint32_t d, uint32_t n)
{
uint32_t disp = d & 0xff;
m_sh2_state->ea = ((m_sh2_state->pc + 2) & ~3) + disp * 4;
- m_sh2_state->r[n] = RL( m_sh2_state->ea );
+ m_sh2_state->r[n] = read_long(m_sh2_state->ea);
}
/* MOV.B @(disp8,GBR),R0 */
@@ -1142,7 +1115,7 @@ void sh_common_execution::MOVBLG(uint32_t d)
{
uint32_t disp = d & 0xff;
m_sh2_state->ea = m_sh2_state->gbr + disp;
- m_sh2_state->r[0] = (uint32_t)(int32_t)(int16_t)(int8_t) RB( m_sh2_state->ea );
+ m_sh2_state->r[0] = (uint32_t)util::sext(read_byte(m_sh2_state->ea), 8);
}
/* MOV.W @(disp8,GBR),R0 */
@@ -1150,7 +1123,7 @@ void sh_common_execution::MOVWLG(uint32_t d)
{
uint32_t disp = d & 0xff;
m_sh2_state->ea = m_sh2_state->gbr + disp * 2;
- m_sh2_state->r[0] = (int32_t)(int16_t) RW( m_sh2_state->ea );
+ m_sh2_state->r[0] = (int32_t)util::sext(read_word(m_sh2_state->ea), 16);
}
/* MOV.L @(disp8,GBR),R0 */
@@ -1158,7 +1131,7 @@ void sh_common_execution::MOVLLG(uint32_t d)
{
uint32_t disp = d & 0xff;
m_sh2_state->ea = m_sh2_state->gbr + disp * 4;
- m_sh2_state->r[0] = RL( m_sh2_state->ea );
+ m_sh2_state->r[0] = read_long(m_sh2_state->ea);
}
/* MOV.B R0,@(disp8,GBR) */
@@ -1166,7 +1139,7 @@ void sh_common_execution::MOVBSG(uint32_t d)
{
uint32_t disp = d & 0xff;
m_sh2_state->ea = m_sh2_state->gbr + disp;
- WB( m_sh2_state->ea, m_sh2_state->r[0] & 0x000000ff );
+ write_byte(m_sh2_state->ea, (uint8_t)m_sh2_state->r[0]);
}
/* MOV.W R0,@(disp8,GBR) */
@@ -1174,7 +1147,7 @@ void sh_common_execution::MOVWSG(uint32_t d)
{
uint32_t disp = d & 0xff;
m_sh2_state->ea = m_sh2_state->gbr + disp * 2;
- WW( m_sh2_state->ea, m_sh2_state->r[0] & 0x0000ffff );
+ write_word(m_sh2_state->ea, (uint16_t)m_sh2_state->r[0]);
}
/* MOV.L R0,@(disp8,GBR) */
@@ -1182,7 +1155,7 @@ void sh_common_execution::MOVLSG(uint32_t d)
{
uint32_t disp = d & 0xff;
m_sh2_state->ea = m_sh2_state->gbr + disp * 4;
- WL( m_sh2_state->ea, m_sh2_state->r[0] );
+ write_long(m_sh2_state->ea, m_sh2_state->r[0]);
}
/* MOV.B R0,@(disp4,Rn) */
@@ -1190,7 +1163,7 @@ void sh_common_execution::MOVBS4(uint32_t d, uint32_t n)
{
uint32_t disp = d & 0x0f;
m_sh2_state->ea = m_sh2_state->r[n] + disp;
- WB( m_sh2_state->ea, m_sh2_state->r[0] & 0x000000ff );
+ write_byte(m_sh2_state->ea, (uint8_t)m_sh2_state->r[0]);
}
/* MOV.W R0,@(disp4,Rn) */
@@ -1198,7 +1171,7 @@ void sh_common_execution::MOVWS4(uint32_t d, uint32_t n)
{
uint32_t disp = d & 0x0f;
m_sh2_state->ea = m_sh2_state->r[n] + disp * 2;
- WW( m_sh2_state->ea, m_sh2_state->r[0] & 0x0000ffff );
+ write_word(m_sh2_state->ea, (uint16_t)m_sh2_state->r[0]);
}
/* MOV.L Rm,@(disp4,Rn) */
@@ -1206,7 +1179,7 @@ void sh_common_execution::MOVLS4(uint32_t m, uint32_t d, uint32_t n)
{
uint32_t disp = d & 0x0f;
m_sh2_state->ea = m_sh2_state->r[n] + disp * 4;
- WL( m_sh2_state->ea, m_sh2_state->r[m] );
+ write_long(m_sh2_state->ea, m_sh2_state->r[m]);
}
/* MOV.B @(disp4,Rm),R0 */
@@ -1214,7 +1187,7 @@ void sh_common_execution::MOVBL4(uint32_t m, uint32_t d)
{
uint32_t disp = d & 0x0f;
m_sh2_state->ea = m_sh2_state->r[m] + disp;
- m_sh2_state->r[0] = (uint32_t)(int32_t)(int16_t)(int8_t) RB( m_sh2_state->ea );
+ m_sh2_state->r[0] = (uint32_t)util::sext(read_byte(m_sh2_state->ea), 8);
}
/* MOV.W @(disp4,Rm),R0 */
@@ -1222,7 +1195,7 @@ void sh_common_execution::MOVWL4(uint32_t m, uint32_t d)
{
uint32_t disp = d & 0x0f;
m_sh2_state->ea = m_sh2_state->r[m] + disp * 2;
- m_sh2_state->r[0] = (uint32_t)(int32_t)(int16_t) RW( m_sh2_state->ea );
+ m_sh2_state->r[0] = (uint32_t)util::sext(read_word(m_sh2_state->ea), 16);
}
/* MOV.L @(disp4,Rm),Rn */
@@ -1230,7 +1203,7 @@ void sh_common_execution::MOVLL4(uint32_t m, uint32_t d, uint32_t n)
{
uint32_t disp = d & 0x0f;
m_sh2_state->ea = m_sh2_state->r[m] + disp * 4;
- m_sh2_state->r[n] = RL( m_sh2_state->ea );
+ m_sh2_state->r[n] = read_long(m_sh2_state->ea);
}
/* MOVA @(disp8,PC),R0 */
@@ -1257,13 +1230,13 @@ void sh_common_execution::MULL(uint32_t m, uint32_t n)
/* MULS Rm,Rn */
void sh_common_execution::MULS(uint32_t m, uint32_t n)
{
- m_sh2_state->macl = (int16_t) m_sh2_state->r[n] * (int16_t) m_sh2_state->r[m];
+ m_sh2_state->macl = (int16_t)m_sh2_state->r[n] * (int16_t)m_sh2_state->r[m];
}
/* MULU Rm,Rn */
void sh_common_execution::MULU(uint32_t m, uint32_t n)
{
- m_sh2_state->macl = (uint16_t) m_sh2_state->r[n] * (uint16_t) m_sh2_state->r[m];
+ m_sh2_state->macl = (uint16_t)m_sh2_state->r[n] * (uint16_t)m_sh2_state->r[m];
}
/* NEG Rm,Rn */
@@ -1275,9 +1248,7 @@ void sh_common_execution::NEG(uint32_t m, uint32_t n)
/* NEGC Rm,Rn */
void sh_common_execution::NEGC(uint32_t m, uint32_t n)
{
- uint32_t temp;
-
- temp = m_sh2_state->r[m];
+ uint32_t temp = m_sh2_state->r[m];
m_sh2_state->r[n] = -temp - (m_sh2_state->sr & SH_T);
if (temp || (m_sh2_state->sr & SH_T))
m_sh2_state->sr |= SH_T;
@@ -1306,27 +1277,20 @@ void sh_common_execution::OR(uint32_t m, uint32_t n)
void sh_common_execution::ORI(uint32_t i)
{
m_sh2_state->r[0] |= i;
- m_sh2_state->icount -= 2; // not in SH2 implementation?
+ m_sh2_state->icount -= 2;
}
/* OR.B #imm,@(R0,GBR) */
void sh_common_execution::ORM(uint32_t i)
{
- uint32_t temp;
-
m_sh2_state->ea = m_sh2_state->gbr + m_sh2_state->r[0];
- temp = RB( m_sh2_state->ea );
- temp |= i;
- WB( m_sh2_state->ea, temp );
- //m_sh2_state->icount -= 2; // not in SH4 implementation?
+ write_byte(m_sh2_state->ea, read_byte(m_sh2_state->ea) | (uint8_t)i);
}
/* ROTCL Rn */
void sh_common_execution::ROTCL(uint32_t n)
{
- uint32_t temp;
-
- temp = (m_sh2_state->r[n] >> 31) & SH_T;
+ uint32_t temp = (m_sh2_state->r[n] >> 31) & SH_T;
m_sh2_state->r[n] = (m_sh2_state->r[n] << 1) | (m_sh2_state->sr & SH_T);
m_sh2_state->sr = (m_sh2_state->sr & ~SH_T) | temp;
}
@@ -1334,8 +1298,7 @@ void sh_common_execution::ROTCL(uint32_t n)
/* ROTCR Rn */
void sh_common_execution::ROTCR(uint32_t n)
{
- uint32_t temp;
- temp = (m_sh2_state->sr & SH_T) << 31;
+ uint32_t temp = (m_sh2_state->sr & SH_T) << 31;
if (m_sh2_state->r[n] & SH_T)
m_sh2_state->sr |= SH_T;
else
@@ -1347,14 +1310,14 @@ void sh_common_execution::ROTCR(uint32_t n)
void sh_common_execution::ROTL(uint32_t n)
{
m_sh2_state->sr = (m_sh2_state->sr & ~SH_T) | ((m_sh2_state->r[n] >> 31) & SH_T);
- m_sh2_state->r[n] = (m_sh2_state->r[n] << 1) | (m_sh2_state->r[n] >> 31);
+ m_sh2_state->r[n] = rotl_32(m_sh2_state->r[n], 1);
}
/* ROTR Rn */
void sh_common_execution::ROTR(uint32_t n)
{
m_sh2_state->sr = (m_sh2_state->sr & ~SH_T) | (m_sh2_state->r[n] & SH_T);
- m_sh2_state->r[n] = (m_sh2_state->r[n] >> 1) | (m_sh2_state->r[n] << 31);
+ m_sh2_state->r[n] = rotr_32(m_sh2_state->r[n], 1);
}
/* RTS */
@@ -1458,7 +1421,7 @@ void sh_common_execution::STCMSR(uint32_t n)
{
m_sh2_state->r[n] -= 4;
m_sh2_state->ea = m_sh2_state->r[n];
- WL( m_sh2_state->ea, m_sh2_state->sr );
+ write_long(m_sh2_state->ea, m_sh2_state->sr);
m_sh2_state->icount--;
}
@@ -1467,7 +1430,7 @@ void sh_common_execution::STCMGBR(uint32_t n)
{
m_sh2_state->r[n] -= 4;
m_sh2_state->ea = m_sh2_state->r[n];
- WL( m_sh2_state->ea, m_sh2_state->gbr );
+ write_long(m_sh2_state->ea, m_sh2_state->gbr);
m_sh2_state->icount--;
}
@@ -1476,7 +1439,7 @@ void sh_common_execution::STCMVBR(uint32_t n)
{
m_sh2_state->r[n] -= 4;
m_sh2_state->ea = m_sh2_state->r[n];
- WL( m_sh2_state->ea, m_sh2_state->vbr );
+ write_long(m_sh2_state->ea, m_sh2_state->vbr);
m_sh2_state->icount--;
}
@@ -1503,7 +1466,7 @@ void sh_common_execution::STSMMACH(uint32_t n)
{
m_sh2_state->r[n] -= 4;
m_sh2_state->ea = m_sh2_state->r[n];
- WL( m_sh2_state->ea, m_sh2_state->mach );
+ write_long(m_sh2_state->ea, m_sh2_state->mach);
}
/* STS.L MACL,@-Rn */
@@ -1511,7 +1474,7 @@ void sh_common_execution::STSMMACL(uint32_t n)
{
m_sh2_state->r[n] -= 4;
m_sh2_state->ea = m_sh2_state->r[n];
- WL( m_sh2_state->ea, m_sh2_state->macl );
+ write_long(m_sh2_state->ea, m_sh2_state->macl);
}
/* STS.L PR,@-Rn */
@@ -1519,7 +1482,7 @@ void sh_common_execution::STSMPR(uint32_t n)
{
m_sh2_state->r[n] -= 4;
m_sh2_state->ea = m_sh2_state->r[n];
- WL( m_sh2_state->ea, m_sh2_state->pr );
+ write_long(m_sh2_state->ea, m_sh2_state->pr);
}
/* SUB Rm,Rn */
@@ -1531,10 +1494,8 @@ void sh_common_execution::SUB(uint32_t m, uint32_t n)
/* SUBC Rm,Rn */
void sh_common_execution::SUBC(uint32_t m, uint32_t n)
{
- uint32_t tmp0, tmp1;
-
- tmp1 = m_sh2_state->r[n] - m_sh2_state->r[m];
- tmp0 = m_sh2_state->r[n];
+ uint32_t tmp1 = m_sh2_state->r[n] - m_sh2_state->r[m];
+ uint32_t tmp0 = m_sh2_state->r[n];
m_sh2_state->r[n] = tmp1 - (m_sh2_state->sr & SH_T);
if (tmp0 < tmp1)
m_sh2_state->sr |= SH_T;
@@ -1547,30 +1508,17 @@ void sh_common_execution::SUBC(uint32_t m, uint32_t n)
/* SUBV Rm,Rn */
void sh_common_execution::SUBV(uint32_t m, uint32_t n)
{
- int32_t dest, src, ans;
-
- if ((int32_t) m_sh2_state->r[n] >= 0)
- dest = 0;
- else
- dest = 1;
- if ((int32_t) m_sh2_state->r[m] >= 0)
- src = 0;
- else
- src = 1;
+ int32_t dest = BIT(m_sh2_state->r[n], 31);
+ int32_t src = BIT(m_sh2_state->r[m], 31);
src += dest;
+
m_sh2_state->r[n] -= m_sh2_state->r[m];
- if ((int32_t) m_sh2_state->r[n] >= 0)
- ans = 0;
- else
- ans = 1;
+
+ int32_t ans = BIT(m_sh2_state->r[n], 31);
ans += dest;
- if (src == 1)
- {
- if (ans == 1)
- m_sh2_state->sr |= SH_T;
- else
- m_sh2_state->sr &= ~SH_T;
- }
+
+ if (src == 1 && ans == 1)
+ m_sh2_state->sr |= SH_T;
else
m_sh2_state->sr &= ~SH_T;
}
@@ -1578,37 +1526,33 @@ void sh_common_execution::SUBV(uint32_t m, uint32_t n)
/* SWAP.B Rm,Rn */
void sh_common_execution::SWAPB(uint32_t m, uint32_t n)
{
- uint32_t temp0, temp1;
-
- temp0 = m_sh2_state->r[m] & 0xffff0000;
- temp1 = (m_sh2_state->r[m] & 0x000000ff) << 8;
- m_sh2_state->r[n] = (m_sh2_state->r[m] >> 8) & 0x000000ff;
- m_sh2_state->r[n] = m_sh2_state->r[n] | temp1 | temp0;
+ uint32_t temp = m_sh2_state->r[m] & 0xffff0000;
+ temp |= (m_sh2_state->r[m] & 0x000000ff) << 8;
+ m_sh2_state->r[n] = (uint8_t)(m_sh2_state->r[m] >> 8);
+ m_sh2_state->r[n] = m_sh2_state->r[n] | temp;
}
/* SWAP.W Rm,Rn */
void sh_common_execution::SWAPW(uint32_t m, uint32_t n)
{
- uint32_t temp;
-
- temp = (m_sh2_state->r[m] >> 16) & 0x0000ffff;
+ uint32_t temp = m_sh2_state->r[m] >> 16;
m_sh2_state->r[n] = (m_sh2_state->r[m] << 16) | temp;
}
/* TAS.B @Rn */
void sh_common_execution::TAS(uint32_t n)
{
- uint32_t temp;
m_sh2_state->ea = m_sh2_state->r[n];
+
/* Bus Lock enable */
- temp = RB( m_sh2_state->ea );
+ uint32_t temp = read_byte(m_sh2_state->ea);
if (temp == 0)
m_sh2_state->sr |= SH_T;
else
m_sh2_state->sr &= ~SH_T;
temp |= 0x80;
/* Bus Lock disable */
- WB( m_sh2_state->ea, temp );
+ write_byte(m_sh2_state->ea, temp);
m_sh2_state->icount -= 3;
}
@@ -1638,7 +1582,7 @@ void sh_common_execution::TSTM(uint32_t i)
uint32_t imm = i & 0xff;
m_sh2_state->ea = m_sh2_state->gbr + m_sh2_state->r[0];
- if ((imm & RB( m_sh2_state->ea )) == 0)
+ if ((imm & read_byte(m_sh2_state->ea)) == 0)
m_sh2_state->sr |= SH_T;
else
m_sh2_state->sr &= ~SH_T;
@@ -1654,31 +1598,21 @@ void sh_common_execution::XOR(uint32_t m, uint32_t n)
/* XOR #imm,R0 */
void sh_common_execution::XORI(uint32_t i)
{
- uint32_t imm = i & 0xff;
- m_sh2_state->r[0] ^= imm;
+ m_sh2_state->r[0] ^= i & 0x000000ff;
}
/* XOR.B #imm,@(R0,GBR) */
void sh_common_execution::XORM(uint32_t i)
{
- uint32_t imm = i & 0xff;
- uint32_t temp;
-
m_sh2_state->ea = m_sh2_state->gbr + m_sh2_state->r[0];
- temp = RB( m_sh2_state->ea );
- temp ^= imm;
- WB( m_sh2_state->ea, temp );
+ write_byte(m_sh2_state->ea, read_byte(m_sh2_state->ea) ^ (uint8_t)i);
m_sh2_state->icount -= 2;
}
/* XTRCT Rm,Rn */
void sh_common_execution::XTRCT(uint32_t m, uint32_t n)
{
- uint32_t temp;
-
- temp = (m_sh2_state->r[m] << 16) & 0xffff0000;
- m_sh2_state->r[n] = (m_sh2_state->r[n] >> 16) & 0x0000ffff;
- m_sh2_state->r[n] |= temp;
+ m_sh2_state->r[n] = (m_sh2_state->r[n] >> 16) | (m_sh2_state->r[m] << 16);
}
/* SLEEP */
@@ -1687,13 +1621,13 @@ void sh_common_execution::SLEEP()
/* 0 = normal mode */
/* 1 = enters into power-down mode */
/* 2 = go out the power-down mode after an exception */
- if(m_sh2_state->sleep_mode != 2)
+ if (m_sh2_state->sleep_mode != 2)
m_sh2_state->pc -= 2;
m_sh2_state->icount -= 2;
/* Wait_for_exception; */
- if(m_sh2_state->sleep_mode == 0)
+ if (m_sh2_state->sleep_mode == 0)
m_sh2_state->sleep_mode = 1;
- else if(m_sh2_state->sleep_mode == 2)
+ else if (m_sh2_state->sleep_mode == 2)
m_sh2_state->sleep_mode = 0;
}
@@ -1703,22 +1637,22 @@ void sh_common_execution::op0010(uint16_t opcode)
{
switch (opcode & 15)
{
- case 0: MOVBS(Rm, Rn); break;
- case 1: MOVWS(Rm, Rn); break;
- case 2: MOVLS(Rm, Rn); break;
- case 3: ILLEGAL(); break;
- case 4: MOVBM(Rm, Rn); break;
- case 5: MOVWM(Rm, Rn); break;
- case 6: MOVLM(Rm, Rn); break;
- case 7: DIV0S(Rm, Rn); break;
- case 8: TST(Rm, Rn); break;
- case 9: AND(Rm, Rn); break;
- case 10: XOR(Rm, Rn); break;
- case 11: OR(Rm, Rn); break;
- case 12: CMPSTR(Rm, Rn); break;
- case 13: XTRCT(Rm, Rn); break;
- case 14: MULU(Rm, Rn); break;
- case 15: MULS(Rm, Rn); break;
+ case 0: MOVBS(REG_M, REG_N); break;
+ case 1: MOVWS(REG_M, REG_N); break;
+ case 2: MOVLS(REG_M, REG_N); break;
+ case 3: ILLEGAL(); break;
+ case 4: MOVBM(REG_M, REG_N); break;
+ case 5: MOVWM(REG_M, REG_N); break;
+ case 6: MOVLM(REG_M, REG_N); break;
+ case 7: DIV0S(REG_M, REG_N); break;
+ case 8: TST(REG_M, REG_N); break;
+ case 9: AND(REG_M, REG_N); break;
+ case 10: XOR(REG_M, REG_N); break;
+ case 11: OR(REG_M, REG_N); break;
+ case 12: CMPSTR(REG_M, REG_N); break;
+ case 13: XTRCT(REG_M, REG_N); break;
+ case 14: MULU(REG_M, REG_N); break;
+ case 15: MULS(REG_M, REG_N); break;
}
}
@@ -1726,22 +1660,22 @@ void sh_common_execution::op0011(uint16_t opcode)
{
switch (opcode & 15)
{
- case 0: CMPEQ(Rm, Rn); break;
- case 1: ILLEGAL(); break;
- case 2: CMPHS(Rm, Rn); break;
- case 3: CMPGE(Rm, Rn); break;
- case 4: DIV1(Rm, Rn); break;
- case 5: DMULU(Rm, Rn); break;
- case 6: CMPHI(Rm, Rn); break;
- case 7: CMPGT(Rm, Rn); break;
- case 8: SUB(Rm, Rn); break;
- case 9: ILLEGAL(); break;
- case 10: SUBC(Rm, Rn); break;
- case 11: SUBV(Rm, Rn); break;
- case 12: ADD(Rm, Rn); break;
- case 13: DMULS(Rm, Rn); break;
- case 14: ADDC(Rm, Rn); break;
- case 15: ADDV(Rm, Rn); break;
+ case 0: CMPEQ(REG_M, REG_N); break;
+ case 1: ILLEGAL(); break;
+ case 2: CMPHS(REG_M, REG_N); break;
+ case 3: CMPGE(REG_M, REG_N); break;
+ case 4: DIV1(REG_M, REG_N); break;
+ case 5: DMULU(REG_M, REG_N); break;
+ case 6: CMPHI(REG_M, REG_N); break;
+ case 7: CMPGT(REG_M, REG_N); break;
+ case 8: SUB(REG_M, REG_N); break;
+ case 9: ILLEGAL(); break;
+ case 10: SUBC(REG_M, REG_N); break;
+ case 11: SUBV(REG_M, REG_N); break;
+ case 12: ADD(REG_M, REG_N); break;
+ case 13: DMULS(REG_M, REG_N); break;
+ case 14: ADDC(REG_M, REG_N); break;
+ case 15: ADDV(REG_M, REG_N); break;
}
}
@@ -1749,69 +1683,69 @@ void sh_common_execution::op0110(uint16_t opcode)
{
switch (opcode & 15)
{
- case 0: MOVBL(Rm, Rn); break;
- case 1: MOVWL(Rm, Rn); break;
- case 2: MOVLL(Rm, Rn); break;
- case 3: MOV(Rm, Rn); break;
- case 4: MOVBP(Rm, Rn); break;
- case 5: MOVWP(Rm, Rn); break;
- case 6: MOVLP(Rm, Rn); break;
- case 7: NOT(Rm, Rn); break;
- case 8: SWAPB(Rm, Rn); break;
- case 9: SWAPW(Rm, Rn); break;
- case 10: NEGC(Rm, Rn); break;
- case 11: NEG(Rm, Rn); break;
- case 12: EXTUB(Rm, Rn); break;
- case 13: EXTUW(Rm, Rn); break;
- case 14: EXTSB(Rm, Rn); break;
- case 15: EXTSW(Rm, Rn); break;
+ case 0: MOVBL(REG_M, REG_N); break;
+ case 1: MOVWL(REG_M, REG_N); break;
+ case 2: MOVLL(REG_M, REG_N); break;
+ case 3: MOV(REG_M, REG_N); break;
+ case 4: MOVBP(REG_M, REG_N); break;
+ case 5: MOVWP(REG_M, REG_N); break;
+ case 6: MOVLP(REG_M, REG_N); break;
+ case 7: NOT(REG_M, REG_N); break;
+ case 8: SWAPB(REG_M, REG_N); break;
+ case 9: SWAPW(REG_M, REG_N); break;
+ case 10: NEGC(REG_M, REG_N); break;
+ case 11: NEG(REG_M, REG_N); break;
+ case 12: EXTUB(REG_M, REG_N); break;
+ case 13: EXTUW(REG_M, REG_N); break;
+ case 14: EXTSB(REG_M, REG_N); break;
+ case 15: EXTSW(REG_M, REG_N); break;
}
}
void sh_common_execution::op1000(uint16_t opcode)
{
- switch ( opcode & (15<<8) )
+ switch ((opcode >> 8) & 15)
{
- case 0 << 8: MOVBS4(opcode & 0x0f, Rm); break;
- case 1 << 8: MOVWS4(opcode & 0x0f, Rm); break;
- case 2<< 8: ILLEGAL(); break;
- case 3<< 8: ILLEGAL(); break;
- case 4<< 8: MOVBL4(Rm, opcode & 0x0f); break;
- case 5<< 8: MOVWL4(Rm, opcode & 0x0f); break;
- case 6<< 8: ILLEGAL(); break;
- case 7<< 8: ILLEGAL(); break;
- case 8<< 8: CMPIM(opcode & 0xff); break;
- case 9<< 8: BT(opcode & 0xff); break;
- case 10<< 8: ILLEGAL(); break;
- case 11<< 8: BF(opcode & 0xff); break;
- case 12<< 8: ILLEGAL(); break;
- case 13<< 8: BTS(opcode & 0xff); break;
- case 14<< 8: ILLEGAL(); break;
- case 15<< 8: BFS(opcode & 0xff); break;
+ case 0: MOVBS4(opcode & 0x0f, REG_M); break;
+ case 1: MOVWS4(opcode & 0x0f, REG_M); break;
+ case 2: ILLEGAL(); break;
+ case 3: ILLEGAL(); break;
+ case 4: MOVBL4(REG_M, opcode & 0x0f); break;
+ case 5: MOVWL4(REG_M, opcode & 0x0f); break;
+ case 6: ILLEGAL(); break;
+ case 7: ILLEGAL(); break;
+ case 8: CMPIM(opcode & 0xff); break;
+ case 9: BT(opcode & 0xff); break;
+ case 10: ILLEGAL(); break;
+ case 11: BF(opcode & 0xff); break;
+ case 12: ILLEGAL(); break;
+ case 13: BTS(opcode & 0xff); break;
+ case 14: ILLEGAL(); break;
+ case 15: BFS(opcode & 0xff); break;
}
}
void sh_common_execution::op1100(uint16_t opcode)
{
- switch (opcode & (15<<8))
+ switch ((opcode >> 8) & 15)
{
- case 0<<8: MOVBSG(opcode & 0xff); break;
- case 1<<8: MOVWSG(opcode & 0xff); break;
- case 2<<8: MOVLSG(opcode & 0xff); break;
- case 3<<8: TRAPA(opcode & 0xff); break; // sh2/4 differ
- case 4<<8: MOVBLG(opcode & 0xff); break;
- case 5<<8: MOVWLG(opcode & 0xff); break;
- case 6<<8: MOVLLG(opcode & 0xff); break;
- case 7<<8: MOVA(opcode & 0xff); break;
- case 8<<8: TSTI(opcode & 0xff); break;
- case 9<<8: ANDI(opcode & 0xff); break;
- case 10<<8: XORI(opcode & 0xff); break;
- case 11<<8: ORI(opcode & 0xff); break;
- case 12<<8: TSTM(opcode & 0xff); break;
- case 13<<8: ANDM(opcode & 0xff); break;
- case 14<<8: XORM(opcode & 0xff); break;
- case 15<<8: ORM(opcode & 0xff); break;
+ case 0: MOVBSG(opcode & 0xff); break;
+ case 1: MOVWSG(opcode & 0xff); break;
+ case 2: MOVLSG(opcode & 0xff); break;
+ case 3: TRAPA(opcode & 0xff); break; // sh2/4 differ
+ case 4: MOVBLG(opcode & 0xff); break;
+ case 5: MOVWLG(opcode & 0xff); break;
+ case 6: MOVLLG(opcode & 0xff); break;
+ case 7: MOVA(opcode & 0xff); break;
+ case 8: TSTI(opcode & 0xff); break;
+ case 9: ANDI(opcode & 0xff); break;
+ case 10: XORI(opcode & 0xff); break;
+ case 11: ORI(opcode & 0xff); break;
+ case 12: TSTM(opcode & 0xff); break;
+ case 13: ANDM(opcode & 0xff); break;
+ case 14: XORM(opcode & 0xff); break;
+ case 15: ORM(opcode & 0xff); break;
}
}
@@ -1820,75 +1754,75 @@ void sh_common_execution::execute_one_0000(uint16_t opcode)
{
// 04,05,06,07 always the same, 0c,0d,0e,0f always the same, other change based on upper bits
- switch (opcode & 0x3F)
+ switch (opcode & 0x3f)
{
- case 0x00: ILLEGAL(); break;
- case 0x01: ILLEGAL(); break;
- case 0x02: STCSR(Rn); break;
- case 0x03: BSRF(Rn); break;
- case 0x04: MOVBS0(Rm, Rn); break;
- case 0x05: MOVWS0(Rm, Rn); break;
- case 0x06: MOVLS0(Rm, Rn); break;
- case 0x07: MULL(Rm, Rn); break;
- case 0x08: CLRT(); break;
- case 0x09: NOP(); break;
- case 0x0a: STSMACH(Rn); break;
- case 0x0b: RTS(); break;
- case 0x0c: MOVBL0(Rm, Rn); break;
- case 0x0d: MOVWL0(Rm, Rn); break;
- case 0x0e: MOVLL0(Rm, Rn); break;
- case 0x0f: MAC_L(Rm, Rn); break;
-
- case 0x10: ILLEGAL(); break;
- case 0x11: ILLEGAL(); break;
- case 0x12: STCGBR(Rn); break;
- case 0x13: ILLEGAL(); break;
- case 0x14: MOVBS0(Rm, Rn); break;
- case 0x15: MOVWS0(Rm, Rn); break;
- case 0x16: MOVLS0(Rm, Rn); break;
- case 0x17: MULL(Rm, Rn); break;
- case 0x18: SETT(); break;
- case 0x19: DIV0U(); break;
- case 0x1a: STSMACL(Rn); break;
- case 0x1b: SLEEP(); break;
- case 0x1c: MOVBL0(Rm, Rn); break;
- case 0x1d: MOVWL0(Rm, Rn); break;
- case 0x1e: MOVLL0(Rm, Rn); break;
- case 0x1f: MAC_L(Rm, Rn); break;
-
- case 0x20: ILLEGAL(); break;
- case 0x21: ILLEGAL(); break;
- case 0x22: STCVBR(Rn); break;
- case 0x23: BRAF(Rn); break;
- case 0x24: MOVBS0(Rm, Rn); break;
- case 0x25: MOVWS0(Rm, Rn); break;
- case 0x26: MOVLS0(Rm, Rn); break;
- case 0x27: MULL(Rm, Rn); break;
- case 0x28: CLRMAC(); break;
- case 0x29: MOVT(Rn); break;
- case 0x2a: STSPR(Rn); break;
- case 0x2b: RTE(); break;
- case 0x2c: MOVBL0(Rm, Rn); break;
- case 0x2d: MOVWL0(Rm, Rn); break;
- case 0x2e: MOVLL0(Rm, Rn); break;
- case 0x2f: MAC_L(Rm, Rn); break;
-
- case 0x30: ILLEGAL(); break;
- case 0x31: ILLEGAL(); break;
- case 0x32: ILLEGAL(); break;
- case 0x33: ILLEGAL(); break;
- case 0x34: MOVBS0(Rm, Rn); break;
- case 0x35: MOVWS0(Rm, Rn); break;
- case 0x36: MOVLS0(Rm, Rn); break;
- case 0x37: MULL(Rm, Rn); break;
- case 0x38: ILLEGAL(); break;
- case 0x39: ILLEGAL(); break;
- case 0x3a: ILLEGAL(); break;
- case 0x3b: ILLEGAL(); break;
- case 0x3c: MOVBL0(Rm, Rn); break;
- case 0x3d: MOVWL0(Rm, Rn); break;
- case 0x3e: MOVLL0(Rm, Rn); break;
- case 0x3f: MAC_L(Rm, Rn); break;
+ case 0x00: ILLEGAL(); break;
+ case 0x01: ILLEGAL(); break;
+ case 0x02: STCSR(REG_N); break;
+ case 0x03: BSRF(REG_N); break;
+ case 0x04: MOVBS0(REG_M, REG_N); break;
+ case 0x05: MOVWS0(REG_M, REG_N); break;
+ case 0x06: MOVLS0(REG_M, REG_N); break;
+ case 0x07: MULL(REG_M, REG_N); break;
+ case 0x08: CLRT(); break;
+ case 0x09: NOP(); break;
+ case 0x0a: STSMACH(REG_N); break;
+ case 0x0b: RTS(); break;
+ case 0x0c: MOVBL0(REG_M, REG_N); break;
+ case 0x0d: MOVWL0(REG_M, REG_N); break;
+ case 0x0e: MOVLL0(REG_M, REG_N); break;
+ case 0x0f: MAC_L(REG_M, REG_N); break;
+
+ case 0x10: ILLEGAL(); break;
+ case 0x11: ILLEGAL(); break;
+ case 0x12: STCGBR(REG_N); break;
+ case 0x13: ILLEGAL(); break;
+ case 0x14: MOVBS0(REG_M, REG_N); break;
+ case 0x15: MOVWS0(REG_M, REG_N); break;
+ case 0x16: MOVLS0(REG_M, REG_N); break;
+ case 0x17: MULL(REG_M, REG_N); break;
+ case 0x18: SETT(); break;
+ case 0x19: DIV0U(); break;
+ case 0x1a: STSMACL(REG_N); break;
+ case 0x1b: SLEEP(); break;
+ case 0x1c: MOVBL0(REG_M, REG_N); break;
+ case 0x1d: MOVWL0(REG_M, REG_N); break;
+ case 0x1e: MOVLL0(REG_M, REG_N); break;
+ case 0x1f: MAC_L(REG_M, REG_N); break;
+
+ case 0x20: ILLEGAL(); break;
+ case 0x21: ILLEGAL(); break;
+ case 0x22: STCVBR(REG_N); break;
+ case 0x23: BRAF(REG_N); break;
+ case 0x24: MOVBS0(REG_M, REG_N); break;
+ case 0x25: MOVWS0(REG_M, REG_N); break;
+ case 0x26: MOVLS0(REG_M, REG_N); break;
+ case 0x27: MULL(REG_M, REG_N); break;
+ case 0x28: CLRMAC(); break;
+ case 0x29: MOVT(REG_N); break;
+ case 0x2a: STSPR(REG_N); break;
+ case 0x2b: RTE(); break;
+ case 0x2c: MOVBL0(REG_M, REG_N); break;
+ case 0x2d: MOVWL0(REG_M, REG_N); break;
+ case 0x2e: MOVLL0(REG_M, REG_N); break;
+ case 0x2f: MAC_L(REG_M, REG_N); break;
+
+ case 0x30: ILLEGAL(); break;
+ case 0x31: ILLEGAL(); break;
+ case 0x32: ILLEGAL(); break;
+ case 0x33: ILLEGAL(); break;
+ case 0x34: MOVBS0(REG_M, REG_N); break;
+ case 0x35: MOVWS0(REG_M, REG_N); break;
+ case 0x36: MOVLS0(REG_M, REG_N); break;
+ case 0x37: MULL(REG_M, REG_N); break;
+ case 0x38: ILLEGAL(); break;
+ case 0x39: ILLEGAL(); break;
+ case 0x3a: ILLEGAL(); break;
+ case 0x3b: ILLEGAL(); break;
+ case 0x3c: MOVBL0(REG_M, REG_N); break;
+ case 0x3d: MOVWL0(REG_M, REG_N); break;
+ case 0x3e: MOVLL0(REG_M, REG_N); break;
+ case 0x3f: MAC_L(REG_M, REG_N); break;
}
}
@@ -1897,99 +1831,99 @@ void sh_common_execution::execute_one_4000(uint16_t opcode)
{
// 0f always the same, others differ
- switch (opcode & 0x3F)
+ switch (opcode & 0x3f)
{
- case 0x00: SHLL(Rn); break;
- case 0x01: SHLR(Rn); break;
- case 0x02: STSMMACH(Rn); break;
- case 0x03: STCMSR(Rn); break;
- case 0x04: ROTL(Rn); break;
- case 0x05: ROTR(Rn); break;
- case 0x06: LDSMMACH(Rn); break;
- case 0x07: LDCMSR(opcode); break;
- case 0x08: SHLL2(Rn); break;
- case 0x09: SHLR2(Rn); break;
- case 0x0a: LDSMACH(Rn); break;
- case 0x0b: JSR(Rn); break;
- case 0x0c: ILLEGAL(); break;
- case 0x0d: ILLEGAL(); break;
- case 0x0e: LDCSR(opcode); break;
- case 0x0f: MAC_W(Rm, Rn); break;
-
- case 0x10: DT(Rn); break;
- case 0x11: CMPPZ(Rn); break;
- case 0x12: STSMMACL(Rn); break;
- case 0x13: STCMGBR(Rn); break;
- case 0x14: ILLEGAL(); break;
- case 0x15: CMPPL(Rn); break;
- case 0x16: LDSMMACL(Rn); break;
- case 0x17: LDCMGBR(Rn); break;
- case 0x18: SHLL8(Rn); break;
- case 0x19: SHLR8(Rn); break;
- case 0x1a: LDSMACL(Rn); break;
- case 0x1b: TAS(Rn); break;
- case 0x1c: ILLEGAL(); break;
- case 0x1d: ILLEGAL(); break;
- case 0x1e: LDCGBR(Rn); break;
- case 0x1f: MAC_W(Rm, Rn); break;
-
- case 0x20: SHAL(Rn); break;
- case 0x21: SHAR(Rn); break;
- case 0x22: STSMPR(Rn); break;
- case 0x23: STCMVBR(Rn); break;
- case 0x24: ROTCL(Rn); break;
- case 0x25: ROTCR(Rn); break;
- case 0x26: LDSMPR(Rn); break;
- case 0x27: LDCMVBR(Rn); break;
- case 0x28: SHLL16(Rn); break;
- case 0x29: SHLR16(Rn); break;
- case 0x2a: LDSPR(Rn); break;
- case 0x2b: JMP(Rn); break;
- case 0x2c: ILLEGAL(); break;
- case 0x2d: ILLEGAL(); break;
- case 0x2e: LDCVBR(Rn); break;
- case 0x2f: MAC_W(Rm, Rn); break;
-
- case 0x30: ILLEGAL(); break;
- case 0x31: ILLEGAL(); break;
- case 0x32: ILLEGAL(); break;
- case 0x33: ILLEGAL(); break;
- case 0x34: ILLEGAL(); break;
- case 0x35: ILLEGAL(); break;
- case 0x36: ILLEGAL(); break;
- case 0x37: ILLEGAL(); break;
- case 0x38: ILLEGAL(); break;
- case 0x39: ILLEGAL(); break;
- case 0x3a: ILLEGAL(); break;
- case 0x3b: ILLEGAL(); break;
- case 0x3c: ILLEGAL(); break;
- case 0x3d: ILLEGAL(); break;
- case 0x3e: ILLEGAL(); break;
- case 0x3f: MAC_W(Rm, Rn); break;
+ case 0x00: SHLL(REG_N); break;
+ case 0x01: SHLR(REG_N); break;
+ case 0x02: STSMMACH(REG_N); break;
+ case 0x03: STCMSR(REG_N); break;
+ case 0x04: ROTL(REG_N); break;
+ case 0x05: ROTR(REG_N); break;
+ case 0x06: LDSMMACH(REG_N); break;
+ case 0x07: LDCMSR(opcode); break;
+ case 0x08: SHLL2(REG_N); break;
+ case 0x09: SHLR2(REG_N); break;
+ case 0x0a: LDSMACH(REG_N); break;
+ case 0x0b: JSR(REG_N); break;
+ case 0x0c: ILLEGAL(); break;
+ case 0x0d: ILLEGAL(); break;
+ case 0x0e: LDCSR(opcode); break;
+ case 0x0f: MAC_W(REG_M, REG_N); break;
+
+ case 0x10: DT(REG_N); break;
+ case 0x11: CMPPZ(REG_N); break;
+ case 0x12: STSMMACL(REG_N); break;
+ case 0x13: STCMGBR(REG_N); break;
+ case 0x14: ILLEGAL(); break;
+ case 0x15: CMPPL(REG_N); break;
+ case 0x16: LDSMMACL(REG_N); break;
+ case 0x17: LDCMGBR(REG_N); break;
+ case 0x18: SHLL8(REG_N); break;
+ case 0x19: SHLR8(REG_N); break;
+ case 0x1a: LDSMACL(REG_N); break;
+ case 0x1b: TAS(REG_N); break;
+ case 0x1c: ILLEGAL(); break;
+ case 0x1d: ILLEGAL(); break;
+ case 0x1e: LDCGBR(REG_N); break;
+ case 0x1f: MAC_W(REG_M, REG_N); break;
+
+ case 0x20: SHAL(REG_N); break;
+ case 0x21: SHAR(REG_N); break;
+ case 0x22: STSMPR(REG_N); break;
+ case 0x23: STCMVBR(REG_N); break;
+ case 0x24: ROTCL(REG_N); break;
+ case 0x25: ROTCR(REG_N); break;
+ case 0x26: LDSMPR(REG_N); break;
+ case 0x27: LDCMVBR(REG_N); break;
+ case 0x28: SHLL16(REG_N); break;
+ case 0x29: SHLR16(REG_N); break;
+ case 0x2a: LDSPR(REG_N); break;
+ case 0x2b: JMP(REG_N); break;
+ case 0x2c: ILLEGAL(); break;
+ case 0x2d: ILLEGAL(); break;
+ case 0x2e: LDCVBR(REG_N); break;
+ case 0x2f: MAC_W(REG_M, REG_N); break;
+
+ case 0x30: ILLEGAL(); break;
+ case 0x31: ILLEGAL(); break;
+ case 0x32: ILLEGAL(); break;
+ case 0x33: ILLEGAL(); break;
+ case 0x34: ILLEGAL(); break;
+ case 0x35: ILLEGAL(); break;
+ case 0x36: ILLEGAL(); break;
+ case 0x37: ILLEGAL(); break;
+ case 0x38: ILLEGAL(); break;
+ case 0x39: ILLEGAL(); break;
+ case 0x3a: ILLEGAL(); break;
+ case 0x3b: ILLEGAL(); break;
+ case 0x3c: ILLEGAL(); break;
+ case 0x3d: ILLEGAL(); break;
+ case 0x3e: ILLEGAL(); break;
+ case 0x3f: MAC_W(REG_M, REG_N); break;
}
}
void sh_common_execution::execute_one(const uint16_t opcode)
{
- switch(opcode & 0xf000)
+ switch ((opcode >> 12) & 15)
{
- case 0x0000: execute_one_0000(opcode); break;
- case 0x1000: MOVLS4(Rm, opcode & 0x0f, Rn); break;
- case 0x2000: op0010(opcode); break;
- case 0x3000: op0011(opcode); break;
- case 0x4000: execute_one_4000(opcode); break;
- case 0x5000: MOVLL4(Rm, opcode & 0x0f, Rn); break;
- case 0x6000: op0110(opcode); break;
- case 0x7000: ADDI(opcode & 0xff, Rn); break;
- case 0x8000: op1000(opcode); break;
- case 0x9000: MOVWI(opcode & 0xff, Rn); break;
- case 0xa000: BRA(opcode & 0xfff); break;
- case 0xb000: BSR(opcode & 0xfff); break;
- case 0xc000: op1100(opcode); break;
- case 0xd000: MOVLI(opcode & 0xff, Rn); break;
- case 0xe000: MOVI(opcode & 0xff, Rn); break;
- case 0xf000: execute_one_f000(opcode); break;
+ case 0: execute_one_0000(opcode); break;
+ case 1: MOVLS4(REG_M, opcode & 0xf, REG_N); break;
+ case 2: op0010(opcode); break;
+ case 3: op0011(opcode); break;
+ case 4: execute_one_4000(opcode); break;
+ case 5: MOVLL4(REG_M, opcode & 0x0f, REG_N); break;
+ case 6: op0110(opcode); break;
+ case 7: ADDI(opcode & 0xff, REG_N); break;
+ case 8: op1000(opcode); break;
+ case 9: MOVWI(opcode & 0xff, REG_N); break;
+ case 10: BRA(opcode & 0xfff); break;
+ case 11: BSR(opcode & 0xfff); break;
+ case 12: op1100(opcode); break;
+ case 13: MOVLI(opcode & 0xff, REG_N); break;
+ case 14: MOVI(opcode & 0xff, REG_N); break;
+ case 15: execute_one_f000(opcode); break;
}
}
@@ -2009,7 +1943,7 @@ void cfunc_printf_probe(void *param) { ((sh_common_execution *)param)->func_prin
void sh_common_execution::sh2drc_add_fastram(offs_t start, offs_t end, uint8_t readonly, void *base)
{
- if (m_fastram_select < ARRAY_LENGTH(m_fastram))
+ if (m_fastram_select < std::size(m_fastram))
{
m_fastram[m_fastram_select].start = start;
m_fastram[m_fastram_select].end = end;
@@ -2051,7 +1985,7 @@ void sh_common_execution::alloc_handle(uml::code_handle *&handleptr, const char
void sh_common_execution::load_fast_iregs(drcuml_block &block)
{
- for (int regnum = 0; regnum < ARRAY_LENGTH(m_regmap); regnum++)
+ for (int regnum = 0; regnum < std::size(m_regmap); regnum++)
{
if (m_regmap[regnum].is_int_register())
{
@@ -2068,7 +2002,7 @@ void sh_common_execution::load_fast_iregs(drcuml_block &block)
void sh_common_execution::save_fast_iregs(drcuml_block &block)
{
- for (int regnum = 0; regnum < ARRAY_LENGTH(m_regmap); regnum++)
+ for (int regnum = 0; regnum < std::size(m_regmap); regnum++)
{
if (m_regmap[regnum].is_int_register())
{
@@ -2343,7 +2277,7 @@ void sh_common_execution::code_compile_block(uint8_t mode, offs_t pc)
const opcode_desc *desclist;
bool override = false;
- g_profiler.start(PROFILER_DRC_COMPILE);
+ auto profile = g_profiler.start(PROFILER_DRC_COMPILE);
/* get a description of this sequence */
desclist = get_desclist(pc);
@@ -2436,7 +2370,6 @@ void sh_common_execution::code_compile_block(uint8_t mode, offs_t pc)
/* end the sequence */
block.end();
- g_profiler.stop();
succeeded = true;
}
catch (drcuml_block::abort_compilation &)
@@ -2569,7 +2502,7 @@ void sh_common_execution::generate_sequence_instruction(drcuml_block &block, com
}
/* if we are debugging, call the debugger */
- if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0)
+ if (debugger_enabled())
{
UML_MOV(block, mem(&m_sh2_state->pc), desc->pc); // mov [pc],desc->pc
save_fast_iregs(block);
@@ -2643,7 +2576,7 @@ void sh_common_execution::generate_delay_slot(drcuml_block &block, compiler_stat
void sh_common_execution::func_unimplemented()
{
// set up an invalid opcode exception
- m_sh2_state->evec = RL( m_sh2_state->vbr + 4 * 4 );
+ m_sh2_state->evec = read_long(m_sh2_state->vbr + 4 * 4);
m_sh2_state->evec &= m_am;
m_sh2_state->irqsr = m_sh2_state->sr;
// claim it's an NMI, because it pretty much is
@@ -2652,15 +2585,12 @@ void sh_common_execution::func_unimplemented()
void sh_common_execution::func_MAC_W()
{
- uint16_t opcode;
- int n, m;
-
// recover the opcode
- opcode = m_sh2_state->arg0;
+ uint32_t opcode = m_sh2_state->arg0;
// extract the operands
- n = Rn;
- m = Rm;
+ uint32_t n = REG_N;
+ uint32_t m = REG_M;
MAC_W(m, n);
}
@@ -2668,15 +2598,12 @@ void sh_common_execution::func_MAC_W()
void sh_common_execution::func_MAC_L()
{
- uint16_t opcode;
- int n, m;
-
// recover the opcode
- opcode = m_sh2_state->arg0;
+ uint32_t opcode = m_sh2_state->arg0;
// extract the operands
- n = Rn;
- m = Rm;
+ uint32_t n = REG_N;
+ uint32_t m = REG_M;
MAC_L(m, n);
}
@@ -2684,15 +2611,12 @@ void sh_common_execution::func_MAC_L()
void sh_common_execution::func_DIV1()
{
- uint16_t opcode;
- int n, m;
-
// recover the opcode
- opcode = m_sh2_state->arg0;
+ uint32_t opcode = m_sh2_state->arg0;
// extract the operands
- n = Rn;
- m = Rm;
+ uint32_t n = REG_N;
+ uint32_t m = REG_M;
DIV1(m, n);
}
@@ -2700,15 +2624,12 @@ void sh_common_execution::func_DIV1()
void sh_common_execution::func_ADDV()
{
- uint16_t opcode;
- int n, m;
-
// recover the opcode
- opcode = m_sh2_state->arg0;
+ uint32_t opcode = m_sh2_state->arg0;
// extract the operands
- n = Rn;
- m = Rm;
+ uint32_t n = REG_N;
+ uint32_t m = REG_M;
ADDV(m, n);
}
@@ -2716,15 +2637,12 @@ void sh_common_execution::func_ADDV()
void sh_common_execution::func_SUBV()
{
- uint16_t opcode;
- int n, m;
-
// recover the opcode
- opcode = m_sh2_state->arg0;
+ uint32_t opcode = m_sh2_state->arg0;
// extract the operands
- n = Rn;
- m = Rm;
+ uint32_t n = REG_N;
+ uint32_t m = REG_M;
SUBV(m, n);
}
@@ -2786,8 +2704,8 @@ bool sh_common_execution::generate_opcode(drcuml_block &block, compiler_state &c
case 1: // MOVLS4
scratch = (opcode & 0x0f) * 4;
- UML_ADD(block, I0, R32(Rn), scratch); // add r0, Rn, scratch
- UML_MOV(block, I1, R32(Rm)); // mov r1, Rm
+ UML_ADD(block, I0, R32(REG_N), scratch); // add r0, Rn, scratch
+ UML_MOV(block, I1, R32(REG_M)); // mov r1, Rm
SETEA(0); // set ea for debug
UML_CALLH(block, *m_write32);
@@ -2804,10 +2722,10 @@ bool sh_common_execution::generate_opcode(drcuml_block &block, compiler_state &c
case 5: // MOVLL4
scratch = (opcode & 0x0f) * 4;
- UML_ADD(block, I0, R32(Rm), scratch); // add r0, Rm, scratch
+ UML_ADD(block, I0, R32(REG_M), scratch); // add r0, Rm, scratch
SETEA(0); // set ea for debug
UML_CALLH(block, *m_read32); // call read32
- UML_MOV(block, R32(Rn), I0); // mov Rn, r0
+ UML_MOV(block, R32(REG_N), I0); // mov Rn, r0
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 2, true);
@@ -2819,7 +2737,7 @@ bool sh_common_execution::generate_opcode(drcuml_block &block, compiler_state &c
case 7: // ADDI
scratch = opcode & 0xff;
scratch2 = (uint32_t)(int32_t)(int16_t)(int8_t)scratch;
- UML_ADD(block, R32(Rn), R32(Rn), scratch2); // add Rn, Rn, scratch2
+ UML_ADD(block, R32(REG_N), R32(REG_N), scratch2); // add Rn, Rn, scratch2
return true;
case 8:
@@ -2827,25 +2745,21 @@ bool sh_common_execution::generate_opcode(drcuml_block &block, compiler_state &c
case 9: // MOVWI
if (ovrpc == 0xffffffff)
- {
scratch = (desc->pc + 2) + ((opcode & 0xff) * 2) + 2;
- }
else
- {
scratch = (ovrpc + 2) + ((opcode & 0xff) * 2) + 2;
- }
if (m_drcoptions & SH2DRC_STRICT_PCREL)
{
UML_MOV(block, I0, scratch); // mov r0, scratch
SETEA(0); // set ea for debug
UML_CALLH(block, *m_read16); // read16(r0, r1)
- UML_SEXT(block, R32(Rn), I0, SIZE_WORD); // sext Rn, r0, WORD
+ UML_SEXT(block, R32(REG_N), I0, SIZE_WORD); // sext Rn, r0, WORD
}
else
{
- scratch2 = (uint32_t)(int32_t)(int16_t) RW(scratch);
- UML_MOV(block, R32(Rn), scratch2); // mov Rn, scratch2
+ scratch2 = (uint32_t)util::sext(read_word(scratch), 16);
+ UML_MOV(block, R32(REG_N), scratch2); // mov Rn, scratch2
}
if (!in_delay_slot)
@@ -2853,7 +2767,7 @@ bool sh_common_execution::generate_opcode(drcuml_block &block, compiler_state &c
return true;
case 10: // BRA
- disp = ((int32_t)opcode << 20) >> 20;
+ disp = util::sext(opcode, 12);
m_sh2_state->ea = (desc->pc + 2) + disp * 2 + 2; // m_sh2_state->ea = pc+4 + disp*2 + 2
generate_delay_slot(block, compiler, desc, m_sh2_state->ea-2);
@@ -2867,7 +2781,7 @@ bool sh_common_execution::generate_opcode(drcuml_block &block, compiler_state &c
// do this before running the delay slot
UML_ADD(block, mem(&m_sh2_state->pr), desc->pc, 4); // add m_pr, desc->pc, #4 (skip the current insn & delay slot)
- disp = ((int32_t)opcode << 20) >> 20;
+ disp = util::sext(opcode, 12);
m_sh2_state->ea = (desc->pc + 2) + disp * 2 + 2; // m_sh2_state->ea = pc+4 + disp*2 + 2
generate_delay_slot(block, compiler, desc, m_sh2_state->ea-2);
@@ -2893,12 +2807,12 @@ bool sh_common_execution::generate_opcode(drcuml_block &block, compiler_state &c
{
UML_MOV(block, I0, scratch); // mov r0, scratch
UML_CALLH(block, *m_read32); // read32(r0, r1)
- UML_MOV(block, R32(Rn), I0); // mov Rn, r0
+ UML_MOV(block, R32(REG_N), I0); // mov Rn, r0
}
else
{
- scratch2 = RL(scratch);
- UML_MOV(block, R32(Rn), scratch2); // mov Rn, scratch2
+ scratch2 = read_long(scratch);
+ UML_MOV(block, R32(REG_N), scratch2); // mov Rn, scratch2
}
if (!in_delay_slot)
@@ -2908,7 +2822,7 @@ bool sh_common_execution::generate_opcode(drcuml_block &block, compiler_state &c
case 14: // MOVI
scratch = opcode & 0xff;
scratch2 = (uint32_t)(int32_t)(int16_t)(int8_t)scratch;
- UML_MOV(block, R32(Rn), scratch2);
+ UML_MOV(block, R32(REG_N), scratch2);
return true;
case 15:
@@ -2929,8 +2843,8 @@ bool sh_common_execution::generate_group_2(drcuml_block &block, compiler_state &
switch (opcode & 15)
{
case 0: // MOVBS(Rm, Rn);
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
- UML_AND(block, I1, R32(Rm), 0xff); // and r1, Rm, 0xff
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
+ UML_AND(block, I1, R32(REG_M), 0xff); // and r1, Rm, 0xff
UML_CALLH(block, *m_write8);
if (!in_delay_slot)
@@ -2938,8 +2852,8 @@ bool sh_common_execution::generate_group_2(drcuml_block &block, compiler_state &
return true;
case 1: // MOVWS(Rm, Rn);
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
- UML_AND(block, I1, R32(Rm), 0xffff); // and r1, Rm, 0xffff
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
+ UML_AND(block, I1, R32(REG_M), 0xffff); // and r1, Rm, 0xffff
UML_CALLH(block, *m_write16);
if (!in_delay_slot)
@@ -2947,8 +2861,8 @@ bool sh_common_execution::generate_group_2(drcuml_block &block, compiler_state &
return true;
case 2: // MOVLS(Rm, Rn);
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
- UML_MOV(block, I1, R32(Rm)); // mov r1, Rm
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
+ UML_MOV(block, I1, R32(REG_M)); // mov r1, Rm
UML_CALLH(block, *m_write32);
if (!in_delay_slot)
@@ -2959,9 +2873,9 @@ bool sh_common_execution::generate_group_2(drcuml_block &block, compiler_state &
return false;
case 4: // MOVBM(Rm, Rn);
- UML_MOV(block, I1, R32(Rm)); // mov r1, Rm
- UML_SUB(block, R32(Rn), R32(Rn), 1); // sub Rn, Rn, 1
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_MOV(block, I1, R32(REG_M)); // mov r1, Rm
+ UML_SUB(block, R32(REG_N), R32(REG_N), 1); // sub Rn, Rn, 1
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
UML_CALLH(block, *m_write8); // call write8
if (!in_delay_slot)
@@ -2969,9 +2883,9 @@ bool sh_common_execution::generate_group_2(drcuml_block &block, compiler_state &
return true;
case 5: // MOVWM(Rm, Rn);
- UML_MOV(block, I1, R32(Rm)); // mov r1, Rm
- UML_SUB(block, R32(Rn), R32(Rn), 2); // sub Rn, Rn, 2
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_MOV(block, I1, R32(REG_M)); // mov r1, Rm
+ UML_SUB(block, R32(REG_N), R32(REG_N), 2); // sub Rn, Rn, 2
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
UML_CALLH(block, *m_write16); // call write16
if (!in_delay_slot)
@@ -2979,9 +2893,9 @@ bool sh_common_execution::generate_group_2(drcuml_block &block, compiler_state &
return true;
case 6: // MOVLM(Rm, Rn);
- UML_MOV(block, I1, R32(Rm)); // mov r1, Rm
- UML_SUB(block, R32(Rn), R32(Rn), 4); // sub Rn, Rn, 4
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_MOV(block, I1, R32(REG_M)); // mov r1, Rm
+ UML_SUB(block, R32(REG_N), R32(REG_N), 4); // sub Rn, Rn, 4
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
UML_CALLH(block, *m_write32); // call write32
if (!in_delay_slot)
@@ -2989,32 +2903,32 @@ bool sh_common_execution::generate_group_2(drcuml_block &block, compiler_state &
return true;
case 13: // XTRCT(Rm, Rn);
- UML_SHL(block, I0, R32(Rm), 16); // shl r0, Rm, #16
+ UML_SHL(block, I0, R32(REG_M), 16); // shl r0, Rm, #16
UML_AND(block, I0, I0, 0xffff0000); // and r0, r0, #0xffff0000
- UML_SHR(block, I1, R32(Rn), 16); // shr, r1, Rn, #16
+ UML_SHR(block, I1, R32(REG_N), 16); // shr, r1, Rn, #16
UML_AND(block, I1, I1, 0xffff); // and r1, r1, #0x0000ffff
- UML_OR(block, R32(Rn), I0, I1); // or Rn, r0, r1
+ UML_OR(block, R32(REG_N), I0, I1); // or Rn, r0, r1
return true;
case 7: // DIV0S(Rm, Rn);
UML_MOV(block, I0, mem(&m_sh2_state->sr)); // move r0, sr
UML_AND(block, I0, I0, ~(SH_Q|SH_M|SH_T)); // and r0, r0, ~(Q|M|T) (clear the Q,M, and T bits)
- UML_TEST(block, R32(Rn), 0x80000000); // test Rn, #0x80000000
+ UML_TEST(block, R32(REG_N), 0x80000000); // test Rn, #0x80000000
UML_JMPc(block, COND_Z, compiler.labelnum); // jz labelnum
UML_OR(block, I0, I0, SH_Q); // or r0, r0, Q
UML_LABEL(block, compiler.labelnum++); // labelnum:
- UML_TEST(block, R32(Rm), 0x80000000); // test Rm, #0x80000000
+ UML_TEST(block, R32(REG_M), 0x80000000); // test Rm, #0x80000000
UML_JMPc(block, COND_Z, compiler.labelnum); // jz labelnum
UML_OR(block, I0, I0, SH_M); // or r0, r0, M
UML_LABEL(block, compiler.labelnum++); // labelnum:
- UML_XOR(block, I1, R32(Rn), R32(Rm)); // xor r1, Rn, Rm
+ UML_XOR(block, I1, R32(REG_N), R32(REG_M)); // xor r1, Rn, Rm
UML_TEST(block, I1, 0x80000000); // test r1, #0x80000000
UML_JMPc(block, COND_Z, compiler.labelnum); // jz labelnum
@@ -3025,7 +2939,7 @@ bool sh_common_execution::generate_group_2(drcuml_block &block, compiler_state &
case 8: // TST(Rm, Rn);
UML_AND(block, I0, mem(&m_sh2_state->sr), ~SH_T); // and r0, sr, ~T (clear the T bit)
- UML_TEST(block, R32(Rm), R32(Rn)); // test Rm, Rn
+ UML_TEST(block, R32(REG_M), R32(REG_N)); // test Rm, Rn
UML_JMPc(block, COND_NZ, compiler.labelnum); // jnz compiler.labelnum
UML_OR(block, I0, I0, SH_T); // or r0, r0, T
@@ -3035,7 +2949,7 @@ bool sh_common_execution::generate_group_2(drcuml_block &block, compiler_state &
return true;
case 12: // CMPSTR(Rm, Rn);
- UML_XOR(block, I0, R32(Rn), R32(Rm)); // xor r0, Rn, Rm (temp)
+ UML_XOR(block, I0, R32(REG_N), R32(REG_M)); // xor r0, Rn, Rm (temp)
UML_SHR(block, I1, I0, 24); // shr r1, r0, #24 (HH)
UML_AND(block, I1, I1, 0xff); // and r1, r1, #0xff
@@ -3066,26 +2980,26 @@ bool sh_common_execution::generate_group_2(drcuml_block &block, compiler_state &
return true;
case 9: // AND(Rm, Rn);
- UML_AND(block, R32(Rn), R32(Rn), R32(Rm)); // and Rn, Rn, Rm
+ UML_AND(block, R32(REG_N), R32(REG_N), R32(REG_M)); // and Rn, Rn, Rm
return true;
case 10: // XOR(Rm, Rn);
- UML_XOR(block, R32(Rn), R32(Rn), R32(Rm)); // xor Rn, Rn, Rm
+ UML_XOR(block, R32(REG_N), R32(REG_N), R32(REG_M)); // xor Rn, Rn, Rm
return true;
case 11: // OR(Rm, Rn);
- UML_OR(block, R32(Rn), R32(Rn), R32(Rm)); // or Rn, Rn, Rm
+ UML_OR(block, R32(REG_N), R32(REG_N), R32(REG_M)); // or Rn, Rn, Rm
return true;
case 14: // MULU(Rm, Rn);
- UML_AND(block, I0, R32(Rm), 0xffff); // and r0, Rm, 0xffff
- UML_AND(block, I1, R32(Rn), 0xffff); // and r1, Rn, 0xffff
+ UML_AND(block, I0, R32(REG_M), 0xffff); // and r0, Rm, 0xffff
+ UML_AND(block, I1, R32(REG_N), 0xffff); // and r1, Rn, 0xffff
UML_MULU(block, mem(&m_sh2_state->macl), mem(&m_sh2_state->ea), I0, I1); // mulu macl, ea, r0, r1
return true;
case 15: // MULS(Rm, Rn);
- UML_SEXT(block, I0, R32(Rm), SIZE_WORD); // sext r0, Rm
- UML_SEXT(block, I1, R32(Rn), SIZE_WORD); // sext r1, Rn
+ UML_SEXT(block, I0, R32(REG_M), SIZE_WORD); // sext r0, Rm
+ UML_SEXT(block, I1, R32(REG_N), SIZE_WORD); // sext r1, Rn
UML_MULS(block, mem(&m_sh2_state->macl), mem(&m_sh2_state->ea), I0, I1); // muls macl, ea, r0, r1
return true;
}
@@ -3099,31 +3013,31 @@ bool sh_common_execution::generate_group_3(drcuml_block &block, compiler_state &
switch (opcode & 15)
{
case 0: // CMPEQ(Rm, Rn); (equality)
- UML_CMP(block, R32(Rn), R32(Rm)); // cmp Rn, Rm
+ UML_CMP(block, R32(REG_N), R32(REG_M)); // cmp Rn, Rm
UML_SETc(block, COND_E, I0); // set E, r0
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, 1); // rolins sr, r0, 0, 1
return true;
case 2: // CMPHS(Rm, Rn); (unsigned greater than or equal)
- UML_CMP(block, R32(Rn), R32(Rm)); // cmp Rn, Rm
+ UML_CMP(block, R32(REG_N), R32(REG_M)); // cmp Rn, Rm
UML_SETc(block, COND_AE, I0); // set AE, r0
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, 1); // rolins sr, r0, 0, 1
return true;
case 3: // CMPGE(Rm, Rn); (signed greater than or equal)
- UML_CMP(block, R32(Rn), R32(Rm)); // cmp Rn, Rm
+ UML_CMP(block, R32(REG_N), R32(REG_M)); // cmp Rn, Rm
UML_SETc(block, COND_GE, I0); // set GE, r0
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, 1); // rolins sr, r0, 0, 1
return true;
case 6: // CMPHI(Rm, Rn); (unsigned greater than)
- UML_CMP(block, R32(Rn), R32(Rm)); // cmp Rn, Rm
+ UML_CMP(block, R32(REG_N), R32(REG_M)); // cmp Rn, Rm
UML_SETc(block, COND_A, I0); // set A, r0
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, 1); // rolins sr, r0, 0, 1
return true;
case 7: // CMPGT(Rm, Rn); (signed greater than)
- UML_CMP(block, R32(Rn), R32(Rm)); // cmp Rn, Rm
+ UML_CMP(block, R32(REG_N), R32(REG_M)); // cmp Rn, Rm
UML_SETc(block, COND_G, I0); // set G, r0
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, 1); // rolins sr, r0, 0, 1
return true;
@@ -3142,7 +3056,7 @@ bool sh_common_execution::generate_group_3(drcuml_block &block, compiler_state &
case 5: // DMULU(Rm, Rn);
if (m_cpu_type > CPU_TYPE_SH1)
{
- UML_MULU(block, mem(&m_sh2_state->macl), mem(&m_sh2_state->mach), R32(Rn), R32(Rm));
+ UML_MULU(block, mem(&m_sh2_state->macl), mem(&m_sh2_state->mach), R32(REG_N), R32(REG_M));
return true;
}
break;
@@ -3150,22 +3064,22 @@ bool sh_common_execution::generate_group_3(drcuml_block &block, compiler_state &
case 13: // DMULS(Rm, Rn);
if (m_cpu_type > CPU_TYPE_SH1)
{
- UML_MULS(block, mem(&m_sh2_state->macl), mem(&m_sh2_state->mach), R32(Rn), R32(Rm));
+ UML_MULS(block, mem(&m_sh2_state->macl), mem(&m_sh2_state->mach), R32(REG_N), R32(REG_M));
return true;
}
break;
case 8: // SUB(Rm, Rn);
- UML_SUB(block, R32(Rn), R32(Rn), R32(Rm)); // sub Rn, Rn, Rm
+ UML_SUB(block, R32(REG_N), R32(REG_N), R32(REG_M)); // sub Rn, Rn, Rm
return true;
case 12: // ADD(Rm, Rn);
- UML_ADD(block, R32(Rn), R32(Rn), R32(Rm)); // add Rn, Rn, Rm
+ UML_ADD(block, R32(REG_N), R32(REG_N), R32(REG_M)); // add Rn, Rn, Rm
return true;
case 10: // SUBC(Rm, Rn);
UML_CARRY(block, mem(&m_sh2_state->sr), 0); // carry = T (T is bit 0 of SR)
- UML_SUBB(block, R32(Rn), R32(Rn), R32(Rm)); // addc Rn, Rn, Rm
+ UML_SUBB(block, R32(REG_N), R32(REG_N), R32(REG_M)); // addc Rn, Rn, Rm
UML_SETc(block, COND_C, I0); // setc i0, C
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, SH_T); // rolins sr,i0,0,T
return true;
@@ -3179,7 +3093,7 @@ bool sh_common_execution::generate_group_3(drcuml_block &block, compiler_state &
case 14: // ADDC(Rm, Rn);
UML_CARRY(block, mem(&m_sh2_state->sr), 0); // carry = T (T is bit 0 of SR)
- UML_ADDC(block, R32(Rn), R32(Rn), R32(Rm)); // addc Rn, Rn, Rm
+ UML_ADDC(block, R32(REG_N), R32(REG_N), R32(REG_M)); // addc Rn, Rn, Rm
UML_SETc(block, COND_C, I0); // setc i0, C
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, SH_T); // rolins sr,i0,0,T
return true;
@@ -3200,118 +3114,118 @@ bool sh_common_execution::generate_group_6(drcuml_block &block, compiler_state &
switch (opcode & 15)
{
case 0: // MOVBL(Rm, Rn);
- UML_MOV(block, I0, R32(Rm)); // mov r0, Rm
+ UML_MOV(block, I0, R32(REG_M)); // mov r0, Rm
SETEA(0); // debug: ea = r0
UML_CALLH(block, *m_read8); // call read8
- UML_SEXT(block, R32(Rn), I0, SIZE_BYTE); // sext Rn, r0, BYTE
+ UML_SEXT(block, R32(REG_N), I0, SIZE_BYTE); // sext Rn, r0, BYTE
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
case 1: // MOVWL(Rm, Rn);
- UML_MOV(block, I0, R32(Rm)); // mov r0, Rm
+ UML_MOV(block, I0, R32(REG_M)); // mov r0, Rm
SETEA(0); // debug: ea = r0
UML_CALLH(block, *m_read16); // call read16
- UML_SEXT(block, R32(Rn), I0, SIZE_WORD); // sext Rn, r0, WORD
+ UML_SEXT(block, R32(REG_N), I0, SIZE_WORD); // sext Rn, r0, WORD
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
case 2: // MOVLL(Rm, Rn);
- UML_MOV(block, I0, R32(Rm)); // mov r0, Rm
+ UML_MOV(block, I0, R32(REG_M)); // mov r0, Rm
SETEA(0); // debug: ea = r0
UML_CALLH(block, *m_read32); // call read32
- UML_MOV(block, R32(Rn), I0); // mov Rn, r0
+ UML_MOV(block, R32(REG_N), I0); // mov Rn, r0
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
case 3: // MOV(Rm, Rn);
- UML_MOV(block, R32(Rn), R32(Rm)); // mov Rn, Rm
+ UML_MOV(block, R32(REG_N), R32(REG_M)); // mov Rn, Rm
return true;
case 7: // NOT(Rm, Rn);
- UML_XOR(block, R32(Rn), R32(Rm), 0xffffffff); // xor Rn, Rm, 0xffffffff
+ UML_XOR(block, R32(REG_N), R32(REG_M), 0xffffffff); // xor Rn, Rm, 0xffffffff
return true;
case 9: // SWAPW(Rm, Rn);
- UML_ROL(block, R32(Rn), R32(Rm), 16); // rol Rn, Rm, 16
+ UML_ROL(block, R32(REG_N), R32(REG_M), 16); // rol Rn, Rm, 16
return true;
case 11: // NEG(Rm, Rn);
- UML_SUB(block, R32(Rn), 0, R32(Rm)); // sub Rn, 0, Rm
+ UML_SUB(block, R32(REG_N), 0, R32(REG_M)); // sub Rn, 0, Rm
return true;
case 12: // EXTUB(Rm, Rn);
- UML_AND(block, R32(Rn), R32(Rm), 0x000000ff); // and Rn, Rm, 0xff
+ UML_AND(block, R32(REG_N), R32(REG_M), 0x000000ff); // and Rn, Rm, 0xff
return true;
case 13: // EXTUW(Rm, Rn);
- UML_AND(block, R32(Rn), R32(Rm), 0x0000ffff); // and Rn, Rm, 0xffff
+ UML_AND(block, R32(REG_N), R32(REG_M), 0x0000ffff); // and Rn, Rm, 0xffff
return true;
case 14: // EXTSB(Rm, Rn);
- UML_SEXT(block, R32(Rn), R32(Rm), SIZE_BYTE); // sext Rn, Rm, BYTE
+ UML_SEXT(block, R32(REG_N), R32(REG_M), SIZE_BYTE); // sext Rn, Rm, BYTE
return true;
case 15: // EXTSW(Rm, Rn);
- UML_SEXT(block, R32(Rn), R32(Rm), SIZE_WORD); // sext Rn, Rm, WORD
+ UML_SEXT(block, R32(REG_N), R32(REG_M), SIZE_WORD); // sext Rn, Rm, WORD
return true;
case 4: // MOVBP(Rm, Rn);
- UML_MOV(block, I0, R32(Rm)); // mov r0, Rm
+ UML_MOV(block, I0, R32(REG_M)); // mov r0, Rm
UML_CALLH(block, *m_read8); // call read8
- UML_SEXT(block, R32(Rn), I0, SIZE_BYTE); // sext Rn, r0, BYTE
+ UML_SEXT(block, R32(REG_N), I0, SIZE_BYTE); // sext Rn, r0, BYTE
- if (Rm != Rn)
- UML_ADD(block, R32(Rm), R32(Rm), 1); // add Rm, Rm, #1
+ if (REG_M != REG_N)
+ UML_ADD(block, R32(REG_M), R32(REG_M), 1); // add Rm, Rm, #1
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
case 5: // MOVWP(Rm, Rn);
- UML_MOV(block, I0, R32(Rm)); // mov r0, Rm
+ UML_MOV(block, I0, R32(REG_M)); // mov r0, Rm
UML_CALLH(block, *m_read16); // call read16
- UML_SEXT(block, R32(Rn), I0, SIZE_WORD); // sext Rn, r0, WORD
+ UML_SEXT(block, R32(REG_N), I0, SIZE_WORD); // sext Rn, r0, WORD
- if (Rm != Rn)
- UML_ADD(block, R32(Rm), R32(Rm), 2); // add Rm, Rm, #2
+ if (REG_M != REG_N)
+ UML_ADD(block, R32(REG_M), R32(REG_M), 2); // add Rm, Rm, #2
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
case 6: // MOVLP(Rm, Rn);
- UML_MOV(block, I0, R32(Rm)); // mov r0, Rm
+ UML_MOV(block, I0, R32(REG_M)); // mov r0, Rm
UML_CALLH(block, *m_read32); // call read32
- UML_MOV(block, R32(Rn), I0); // mov Rn, r0
+ UML_MOV(block, R32(REG_N), I0); // mov Rn, r0
- if (Rm != Rn)
- UML_ADD(block, R32(Rm), R32(Rm), 4); // add Rm, Rm, #4
+ if (REG_M != REG_N)
+ UML_ADD(block, R32(REG_M), R32(REG_M), 4); // add Rm, Rm, #4
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
case 8: // SWAPB(Rm, Rn);
- UML_AND(block, I0, R32(Rm), 0xffff0000); // and r0, Rm, #0xffff0000
- UML_AND(block, I1, R32(Rm), 0x000000ff); // and r0, Rm, #0x000000ff
- UML_AND(block, I2, R32(Rm), 0x0000ff00); // and r0, Rm, #0x0000ff00
+ UML_AND(block, I0, R32(REG_M), 0xffff0000); // and r0, Rm, #0xffff0000
+ UML_AND(block, I1, R32(REG_M), 0x000000ff); // and r0, Rm, #0x000000ff
+ UML_AND(block, I2, R32(REG_M), 0x0000ff00); // and r0, Rm, #0x0000ff00
UML_SHL(block, I1, I1, 8); // shl r1, r1, #8
UML_SHR(block, I2, I2, 8); // shr r2, r2, #8
UML_OR(block, I0, I0, I1); // or r0, r0, r1
- UML_OR(block, R32(Rn), I0, I2); // or Rn, r0, r2
+ UML_OR(block, R32(REG_N), I0, I2); // or Rn, r0, r2
return true;
case 10: // NEGC(Rm, Rn);
UML_MOV(block, I0, mem(&m_sh2_state->sr)); // mov r0, sr (save SR)
UML_AND(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), ~SH_T); // and sr, sr, ~T (clear the T bit)
UML_CARRY(block, I0, 0); // carry = T (T is bit 0 of SR)
- UML_SUBB(block, R32(Rn), 0, R32(Rm)); // subb Rn, #0, Rm
+ UML_SUBB(block, R32(REG_N), 0, R32(REG_M)); // subb Rn, #0, Rm
UML_JMPc(block, COND_NC, compiler.labelnum); // jnc labelnum
@@ -3331,11 +3245,11 @@ bool sh_common_execution::generate_group_8(drcuml_block &block, compiler_state &
uint32_t udisp;
uml::code_label templabel;
- switch ( opcode & (15<<8) )
+ switch ((opcode >> 8) & 15)
{
- case 0 << 8: // MOVBS4(opcode & 0x0f, Rm);
+ case 0: // MOVBS4(opcode & 0x0f, Rm);
udisp = (opcode & 0x0f);
- UML_ADD(block, I0, R32(Rm), udisp); // add r0, Rm, udisp
+ UML_ADD(block, I0, R32(REG_M), udisp); // add r0, Rm, udisp
UML_MOV(block, I1, R32(0)); // mov r1, R0
UML_CALLH(block, *m_write8); // call write8
@@ -3343,9 +3257,9 @@ bool sh_common_execution::generate_group_8(drcuml_block &block, compiler_state &
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
- case 1 << 8: // MOVWS4(opcode & 0x0f, Rm);
+ case 1: // MOVWS4(opcode & 0x0f, Rm);
udisp = (opcode & 0x0f) * 2;
- UML_ADD(block, I0, R32(Rm), udisp); // add r0, Rm, udisp
+ UML_ADD(block, I0, R32(REG_M), udisp); // add r0, Rm, udisp
UML_MOV(block, I1, R32(0)); // mov r1, R0
UML_CALLH(block, *m_write16); // call write16
@@ -3353,18 +3267,18 @@ bool sh_common_execution::generate_group_8(drcuml_block &block, compiler_state &
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
- case 2<< 8:
- case 3<< 8:
- case 6<< 8:
- case 7<< 8:
- case 10<< 8:
- case 12<< 8:
- case 14<< 8:
+ case 2:
+ case 3:
+ case 6:
+ case 7:
+ case 10:
+ case 12:
+ case 14:
return false;
- case 4<< 8: // MOVBL4(Rm, opcode & 0x0f);
+ case 4: // MOVBL4(Rm, opcode & 0x0f);
udisp = opcode & 0x0f;
- UML_ADD(block, I0, R32(Rm), udisp); // add r0, Rm, udisp
+ UML_ADD(block, I0, R32(REG_M), udisp); // add r0, Rm, udisp
SETEA(0);
UML_CALLH(block, *m_read8); // call read8
UML_SEXT(block, R32(0), I0, SIZE_BYTE); // sext R0, r0, BYTE
@@ -3373,9 +3287,9 @@ bool sh_common_execution::generate_group_8(drcuml_block &block, compiler_state &
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
- case 5<< 8: // MOVWL4(Rm, opcode & 0x0f);
+ case 5: // MOVWL4(Rm, opcode & 0x0f);
udisp = (opcode & 0x0f)*2;
- UML_ADD(block, I0, R32(Rm), udisp); // add r0, Rm, udisp
+ UML_ADD(block, I0, R32(REG_M), udisp); // add r0, Rm, udisp
SETEA(0);
UML_CALLH(block, *m_read16); // call read16
UML_SEXT(block, R32(0), I0, SIZE_WORD); // sext R0, r0, WORD
@@ -3384,7 +3298,7 @@ bool sh_common_execution::generate_group_8(drcuml_block &block, compiler_state &
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
- case 8<< 8: // CMPIM(opcode & 0xff);
+ case 8: // CMPIM(opcode & 0xff);
UML_AND(block, I0, mem(&m_sh2_state->sr), ~SH_T); // and r0, sr, ~T (clear the T bit)
UML_SEXT(block, I1, opcode&0xff, SIZE_BYTE); // sext r1, opcode&0xff, BYTE
@@ -3397,11 +3311,11 @@ bool sh_common_execution::generate_group_8(drcuml_block &block, compiler_state &
UML_MOV(block, mem(&m_sh2_state->sr), I0); // mov m_sh2_state->sr, r0
return true;
- case 9<< 8: // BT(opcode & 0xff);
+ case 9: // BT(opcode & 0xff);
UML_TEST(block, mem(&m_sh2_state->sr), SH_T); // test m_sh2_state->sr, T
UML_JMPc(block, COND_Z, compiler.labelnum); // jz compiler.labelnum
- disp = ((int32_t)opcode << 24) >> 24;
+ disp = util::sext(opcode, 8);
m_sh2_state->ea = (desc->pc + 2) + disp * 2 + 2; // m_sh2_state->ea = destination
generate_update_cycles(block, compiler, m_sh2_state->ea, true); // <subtract cycles>
@@ -3410,11 +3324,11 @@ bool sh_common_execution::generate_group_8(drcuml_block &block, compiler_state &
UML_LABEL(block, compiler.labelnum++); // labelnum:
return true;
- case 11<< 8: // BF(opcode & 0xff);
+ case 11: // BF(opcode & 0xff);
UML_TEST(block, mem(&m_sh2_state->sr), SH_T); // test m_sh2_state->sr, T
UML_JMPc(block, COND_NZ, compiler.labelnum); // jnz compiler.labelnum
- disp = ((int32_t)opcode << 24) >> 24;
+ disp = util::sext(opcode, 8);
m_sh2_state->ea = (desc->pc + 2) + disp * 2 + 2; // m_sh2_state->ea = destination
generate_update_cycles(block, compiler, m_sh2_state->ea, true); // <subtract cycles>
@@ -3423,13 +3337,13 @@ bool sh_common_execution::generate_group_8(drcuml_block &block, compiler_state &
UML_LABEL(block, compiler.labelnum++); // labelnum:
return true;
- case 13<< 8: // BTS(opcode & 0xff);
+ case 13: // BTS(opcode & 0xff);
if (m_cpu_type > CPU_TYPE_SH1)
{
UML_TEST(block, mem(&m_sh2_state->sr), SH_T); // test m_sh2_state->sr, T
UML_JMPc(block, COND_Z, compiler.labelnum); // jz compiler.labelnum
- disp = ((int32_t)opcode << 24) >> 24;
+ disp = util::sext(opcode, 8);
m_sh2_state->ea = (desc->pc + 2) + disp * 2 + 2; // m_sh2_state->ea = destination
templabel = compiler.labelnum; // save our label
@@ -3444,13 +3358,13 @@ bool sh_common_execution::generate_group_8(drcuml_block &block, compiler_state &
}
break;
- case 15<< 8: // BFS(opcode & 0xff);
+ case 15: // BFS(opcode & 0xff);
if (m_cpu_type > CPU_TYPE_SH1)
{
UML_TEST(block, mem(&m_sh2_state->sr), SH_T); // test m_sh2_state->sr, T
UML_JMPc(block, COND_NZ, compiler.labelnum); // jnz compiler.labelnum
- disp = ((int32_t)opcode << 24) >> 24;
+ disp = util::sext(opcode, 8);
m_sh2_state->ea = (desc->pc + 2) + disp * 2 + 2; // m_sh2_state->ea = destination
templabel = compiler.labelnum; // save our label
@@ -3495,9 +3409,9 @@ bool sh_common_execution::generate_group_12(drcuml_block &block, compiler_state
{
uint32_t scratch;
- switch (opcode & (15<<8))
+ switch ((opcode >> 8) & 15)
{
- case 0<<8: // MOVBSG(opcode & 0xff);
+ case 0: // MOVBSG(opcode & 0xff);
scratch = (opcode & 0xff);
UML_ADD(block, I0, mem(&m_sh2_state->gbr), scratch); // add r0, gbr, scratch
UML_AND(block, I1, R32(0), 0xff); // and r1, R0, 0xff
@@ -3507,7 +3421,7 @@ bool sh_common_execution::generate_group_12(drcuml_block &block, compiler_state
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
- case 1<<8: // MOVWSG(opcode & 0xff);
+ case 1: // MOVWSG(opcode & 0xff);
scratch = (opcode & 0xff) * 2;
UML_ADD(block, I0, mem(&m_sh2_state->gbr), scratch); // add r0, gbr, scratch
UML_AND(block, I1, R32(0), 0xffff); // and r1, R0, 0xffff
@@ -3517,7 +3431,7 @@ bool sh_common_execution::generate_group_12(drcuml_block &block, compiler_state
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
- case 2<<8: // MOVLSG(opcode & 0xff);
+ case 2: // MOVLSG(opcode & 0xff);
scratch = (opcode & 0xff) * 4;
UML_ADD(block, I0, mem(&m_sh2_state->gbr), scratch); // add r0, gbr, scratch
UML_MOV(block, I1, R32(0)); // mov r1, R0
@@ -3527,10 +3441,10 @@ bool sh_common_execution::generate_group_12(drcuml_block &block, compiler_state
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
- case 3<<8: // TRAPA(opcode & 0xff);
+ case 3: // TRAPA(opcode & 0xff);
return generate_group_12_TRAPA(block, compiler, desc, opcode, in_delay_slot, ovrpc);
- case 4<<8: // MOVBLG(opcode & 0xff);
+ case 4: // MOVBLG(opcode & 0xff);
scratch = (opcode & 0xff);
UML_ADD(block, I0, mem(&m_sh2_state->gbr), scratch); // add r0, gbr, scratch
UML_CALLH(block, *m_read8); // call read16
@@ -3540,7 +3454,7 @@ bool sh_common_execution::generate_group_12(drcuml_block &block, compiler_state
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
- case 5<<8: // MOVWLG(opcode & 0xff);
+ case 5: // MOVWLG(opcode & 0xff);
scratch = (opcode & 0xff) * 2;
UML_ADD(block, I0, mem(&m_sh2_state->gbr), scratch); // add r0, gbr, scratch
UML_CALLH(block, *m_read16); // call read16
@@ -3550,7 +3464,7 @@ bool sh_common_execution::generate_group_12(drcuml_block &block, compiler_state
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
- case 6<<8: // MOVLLG(opcode & 0xff);
+ case 6: // MOVLLG(opcode & 0xff);
scratch = (opcode & 0xff) * 4;
UML_ADD(block, I0, mem(&m_sh2_state->gbr), scratch); // add r0, gbr, scratch
UML_CALLH(block, *m_read32); // call read32
@@ -3560,14 +3474,14 @@ bool sh_common_execution::generate_group_12(drcuml_block &block, compiler_state
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
- case 7<<8: // MOVA(opcode & 0xff);
+ case 7: // MOVA(opcode & 0xff);
scratch = (opcode & 0xff) * 4;
scratch += ((desc->pc + 4) & ~3);
UML_MOV(block, R32(0), scratch); // mov R0, scratch
return true;
- case 8<<8: // TSTI(opcode & 0xff);
+ case 8: // TSTI(opcode & 0xff);
scratch = opcode & 0xff;
UML_AND(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), ~SH_T); // and sr, sr, ~T (clear the T bit)
@@ -3580,19 +3494,19 @@ bool sh_common_execution::generate_group_12(drcuml_block &block, compiler_state
UML_LABEL(block, compiler.labelnum++); // labelnum:
return true;
- case 9<<8: // ANDI(opcode & 0xff);
+ case 9: // ANDI(opcode & 0xff);
UML_AND(block, R32(0), R32(0), opcode & 0xff); // and r0, r0, opcode & 0xff
return true;
- case 10<<8: // XORI(opcode & 0xff);
+ case 10: // XORI(opcode & 0xff);
UML_XOR(block, R32(0), R32(0), opcode & 0xff); // xor r0, r0, opcode & 0xff
return true;
- case 11<<8: // ORI(opcode & 0xff);
+ case 11: // ORI(opcode & 0xff);
UML_OR(block, R32(0), R32(0), opcode & 0xff); // or r0, r0, opcode & 0xff
return true;
- case 12<<8: // TSTM(opcode & 0xff);
+ case 12: // TSTM(opcode & 0xff);
UML_AND(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), ~SH_T); // and sr, sr, ~T (clear the T bit)
UML_ADD(block, I0, R32(0), mem(&m_sh2_state->gbr)); // add r0, R0, gbr
UML_CALLH(block, *m_read8); // read8
@@ -3606,7 +3520,7 @@ bool sh_common_execution::generate_group_12(drcuml_block &block, compiler_state
UML_LABEL(block, compiler.labelnum++); // labelnum:
return true;
- case 13<<8: // ANDM(opcode & 0xff);
+ case 13: // ANDM(opcode & 0xff);
UML_ADD(block, I0, R32(0), mem(&m_sh2_state->gbr)); // add r0, R0, gbr
UML_CALLH(block, *m_read8); // read8
@@ -3616,7 +3530,7 @@ bool sh_common_execution::generate_group_12(drcuml_block &block, compiler_state
UML_CALLH(block, *m_write8); // write8
return true;
- case 14<<8: // XORM(opcode & 0xff);
+ case 14: // XORM(opcode & 0xff);
UML_ADD(block, I0, R32(0), mem(&m_sh2_state->gbr)); // add r0, R0, gbr
UML_CALLH(block, *m_read8); // read8
@@ -3626,7 +3540,7 @@ bool sh_common_execution::generate_group_12(drcuml_block &block, compiler_state
UML_CALLH(block, *m_write8); // write8
return true;
- case 15<<8: // ORM(opcode & 0xff);
+ case 15: // ORM(opcode & 0xff);
UML_ADD(block, I0, R32(0), mem(&m_sh2_state->gbr)); // add r0, R0, gbr
UML_CALLH(block, *m_read8); // read8
@@ -3688,13 +3602,13 @@ bool sh_common_execution::generate_group_0(drcuml_block &block, compiler_state &
return true;
case 0x02: // STCSR(Rn);
- UML_MOV(block, R32(Rn), mem(&m_sh2_state->sr));
+ UML_MOV(block, R32(REG_N), mem(&m_sh2_state->sr));
return true;
case 0x03: // BSRF(Rn);
if (m_cpu_type > CPU_TYPE_SH1)
{
- UML_ADD(block, mem(&m_sh2_state->target), R32(Rn), 4); // add target, Rm, #4
+ UML_ADD(block, mem(&m_sh2_state->target), R32(REG_N), 4); // add target, Rm, #4
UML_ADD(block, mem(&m_sh2_state->target), mem(&m_sh2_state->target), desc->pc); // add target, target, pc
// 32x Cosmic Carnage @ 6002cb0 relies on the delay slot
@@ -3713,8 +3627,8 @@ bool sh_common_execution::generate_group_0(drcuml_block &block, compiler_state &
case 0x14: // MOVBS0(Rm, Rn);
case 0x24: // MOVBS0(Rm, Rn);
case 0x34: // MOVBS0(Rm, Rn);
- UML_ADD(block, I0, R32(0), R32(Rn)); // add r0, R0, Rn
- UML_AND(block, I1, R32(Rm), 0x000000ff); // and r1, Rm, 0xff
+ UML_ADD(block, I0, R32(0), R32(REG_N)); // add r0, R0, Rn
+ UML_AND(block, I1, R32(REG_M), 0x000000ff); // and r1, Rm, 0xff
UML_CALLH(block, *m_write8); // call write8
if (!in_delay_slot)
@@ -3725,8 +3639,8 @@ bool sh_common_execution::generate_group_0(drcuml_block &block, compiler_state &
case 0x15: // MOVWS0(Rm, Rn);
case 0x25: // MOVWS0(Rm, Rn);
case 0x35: // MOVWS0(Rm, Rn);
- UML_ADD(block, I0, R32(0), R32(Rn)); // add r0, R0, Rn
- UML_AND(block, I1, R32(Rm), 0x0000ffff); // and r1, Rm, 0xffff
+ UML_ADD(block, I0, R32(0), R32(REG_N)); // add r0, R0, Rn
+ UML_AND(block, I1, R32(REG_M), 0x0000ffff); // and r1, Rm, 0xffff
UML_CALLH(block, *m_write16); // call write16
if (!in_delay_slot)
@@ -3737,8 +3651,8 @@ bool sh_common_execution::generate_group_0(drcuml_block &block, compiler_state &
case 0x16: // MOVLS0(Rm, Rn);
case 0x26: // MOVLS0(Rm, Rn);
case 0x36: // MOVLS0(Rm, Rn);
- UML_ADD(block, I0, R32(0), R32(Rn)); // add r0, R0, Rn
- UML_MOV(block, I1, R32(Rm)); // mov r1, Rm
+ UML_ADD(block, I0, R32(0), R32(REG_N)); // add r0, R0, Rn
+ UML_MOV(block, I1, R32(REG_M)); // mov r1, Rm
UML_CALLH(block, *m_write32); // call write32
if (!in_delay_slot)
@@ -3751,7 +3665,7 @@ bool sh_common_execution::generate_group_0(drcuml_block &block, compiler_state &
case 0x37: // MULL(Rm, Rn);
if (m_cpu_type > CPU_TYPE_SH1)
{
- UML_MULU(block, mem(&m_sh2_state->macl), mem(&m_sh2_state->ea), R32(Rn), R32(Rm)); // mulu macl, ea, Rn, Rm
+ UML_MULU(block, mem(&m_sh2_state->macl), mem(&m_sh2_state->ea), R32(REG_N), R32(REG_M)); // mulu macl, ea, Rn, Rm
return true;
}
break;
@@ -3761,7 +3675,7 @@ bool sh_common_execution::generate_group_0(drcuml_block &block, compiler_state &
return true;
case 0x0a: // STSMACH(Rn);
- UML_MOV(block, R32(Rn), mem(&m_sh2_state->mach)); // mov Rn, mach
+ UML_MOV(block, R32(REG_N), mem(&m_sh2_state->mach)); // mov Rn, mach
return true;
case 0x0b: // RTS();
@@ -3777,9 +3691,9 @@ bool sh_common_execution::generate_group_0(drcuml_block &block, compiler_state &
case 0x1c: // MOVBL0(Rm, Rn);
case 0x2c: // MOVBL0(Rm, Rn);
case 0x3c: // MOVBL0(Rm, Rn);
- UML_ADD(block, I0, R32(0), R32(Rm)); // add r0, R0, Rm
+ UML_ADD(block, I0, R32(0), R32(REG_M)); // add r0, R0, Rm
UML_CALLH(block, *m_read8); // call read8
- UML_SEXT(block, R32(Rn), I0, SIZE_BYTE); // sext Rn, r0, BYTE
+ UML_SEXT(block, R32(REG_N), I0, SIZE_BYTE); // sext Rn, r0, BYTE
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 2, true);
@@ -3789,9 +3703,9 @@ bool sh_common_execution::generate_group_0(drcuml_block &block, compiler_state &
case 0x1d: // MOVWL0(Rm, Rn);
case 0x2d: // MOVWL0(Rm, Rn);
case 0x3d: // MOVWL0(Rm, Rn);
- UML_ADD(block, I0, R32(0), R32(Rm)); // add r0, R0, Rm
+ UML_ADD(block, I0, R32(0), R32(REG_M)); // add r0, R0, Rm
UML_CALLH(block, *m_read16); // call read16
- UML_SEXT(block, R32(Rn), I0, SIZE_WORD); // sext Rn, r0, WORD
+ UML_SEXT(block, R32(REG_N), I0, SIZE_WORD); // sext Rn, r0, WORD
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 2, true);
@@ -3801,9 +3715,9 @@ bool sh_common_execution::generate_group_0(drcuml_block &block, compiler_state &
case 0x1e: // MOVLL0(Rm, Rn);
case 0x2e: // MOVLL0(Rm, Rn);
case 0x3e: // MOVLL0(Rm, Rn);
- UML_ADD(block, I0, R32(0), R32(Rm)); // add r0, R0, Rm
+ UML_ADD(block, I0, R32(0), R32(REG_M)); // add r0, R0, Rm
UML_CALLH(block, *m_read32); // call read32
- UML_MOV(block, R32(Rn), I0); // mov Rn, r0
+ UML_MOV(block, R32(REG_N), I0); // mov Rn, r0
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 2, true);
@@ -3824,7 +3738,7 @@ bool sh_common_execution::generate_group_0(drcuml_block &block, compiler_state &
break;
case 0x12: // STCGBR(Rn);
- UML_MOV(block, R32(Rn), mem(&m_sh2_state->gbr)); // mov Rn, gbr
+ UML_MOV(block, R32(REG_N), mem(&m_sh2_state->gbr)); // mov Rn, gbr
return true;
case 0x18: // SETT();
@@ -3836,7 +3750,7 @@ bool sh_common_execution::generate_group_0(drcuml_block &block, compiler_state &
return true;
case 0x1a: // STSMACL(Rn);
- UML_MOV(block, R32(Rn), mem(&m_sh2_state->macl)); // mov Rn, macl
+ UML_MOV(block, R32(REG_N), mem(&m_sh2_state->macl)); // mov Rn, macl
return true;
case 0x1b: // SLEEP();
@@ -3857,13 +3771,13 @@ bool sh_common_execution::generate_group_0(drcuml_block &block, compiler_state &
return true;
case 0x22: // STCVBR(Rn);
- UML_MOV(block, R32(Rn), mem(&m_sh2_state->vbr)); // mov Rn, vbr
+ UML_MOV(block, R32(REG_N), mem(&m_sh2_state->vbr)); // mov Rn, vbr
return true;
case 0x23: // BRAF(Rn);
if (m_cpu_type > CPU_TYPE_SH1)
{
- UML_ADD(block, mem(&m_sh2_state->target), R32(Rn), desc->pc+4); // add target, Rn, pc+4
+ UML_ADD(block, mem(&m_sh2_state->target), R32(REG_N), desc->pc+4); // add target, Rn, pc+4
generate_delay_slot(block, compiler, desc, m_sh2_state->target);
@@ -3879,11 +3793,11 @@ bool sh_common_execution::generate_group_0(drcuml_block &block, compiler_state &
return true;
case 0x29: // MOVT(Rn);
- UML_AND(block, R32(Rn), mem(&m_sh2_state->sr), SH_T); // and Rn, sr, T
+ UML_AND(block, R32(REG_N), mem(&m_sh2_state->sr), SH_T); // and Rn, sr, T
return true;
case 0x2a: // STSPR(Rn);
- UML_MOV(block, R32(Rn), mem(&m_sh2_state->pr)); // mov Rn, pr
+ UML_MOV(block, R32(REG_N), mem(&m_sh2_state->pr)); // mov Rn, pr
return true;
case 0x2b: // RTE();
@@ -3896,7 +3810,7 @@ bool sh_common_execution::generate_group_0(drcuml_block &block, compiler_state &
bool sh_common_execution::generate_group_4_LDCSR(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc)
{
// needs to be different on SH2 / 4
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
UML_AND(block, I0, I0, SH_FLAGS); // and r0, r0, FLAGS
UML_MOV(block, mem(&m_sh2_state->sr), I0);
@@ -3906,10 +3820,10 @@ bool sh_common_execution::generate_group_4_LDCSR(drcuml_block &block, compiler_s
bool sh_common_execution::generate_group_4_LDCMSR(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc, uint16_t opcode, int in_delay_slot, uint32_t ovrpc)
{
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
SETEA(0);
UML_CALLH(block, *m_read32); // call read32
- UML_ADD(block, R32(Rn), R32(Rn), 4); // add Rn, #4
+ UML_ADD(block, R32(REG_N), R32(REG_N), 4); // add Rn, #4
UML_MOV(block, mem(&m_sh2_state->sr), I0); // mov sr, r0
compiler.checkints = true;
@@ -3923,32 +3837,32 @@ bool sh_common_execution::generate_group_4(drcuml_block &block, compiler_state &
switch (opcode & 0x3F)
{
case 0x00: // SHLL(Rn);
- UML_SHL(block, R32(Rn), R32(Rn), 1); // shl Rn, Rn, 1
+ UML_SHL(block, R32(REG_N), R32(REG_N), 1); // shl Rn, Rn, 1
UML_SETc(block, COND_C, I0); // set i0,C
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, SH_T); // rolins [sr],i0,0,T
return true;
case 0x01: // SHLR(Rn);
- UML_SHR(block, R32(Rn), R32(Rn), 1); // shr Rn, Rn, 1
+ UML_SHR(block, R32(REG_N), R32(REG_N), 1); // shr Rn, Rn, 1
UML_SETc(block, COND_C, I0); // set i0,C
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, SH_T); // rolins [sr],i0,0,T
return true;
case 0x04: // ROTL(Rn);
- UML_ROL(block, R32(Rn), R32(Rn), 1); // rol Rn, Rn, 1
+ UML_ROL(block, R32(REG_N), R32(REG_N), 1); // rol Rn, Rn, 1
UML_SETc(block, COND_C, I0); // set i0,C
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, SH_T); // rolins [sr],i0,0,T
return true;
case 0x05: // ROTR(Rn);
- UML_ROR(block, R32(Rn), R32(Rn), 1); // ror Rn, Rn, 1
+ UML_ROR(block, R32(REG_N), R32(REG_N), 1); // ror Rn, Rn, 1
UML_SETc(block, COND_C, I0); // set i0,C
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, SH_T); // rolins [sr],i0,0,T
return true;
case 0x02: // STSMMACH(Rn);
- UML_SUB(block, R32(Rn), R32(Rn), 4); // sub Rn, Rn, #4
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_SUB(block, R32(REG_N), R32(REG_N), 4); // sub Rn, Rn, #4
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
UML_MOV(block, I1, mem(&m_sh2_state->mach)); // mov r1, mach
SETEA(0); // set ea for debug
UML_CALLH(block, *m_write32); // call write32
@@ -3958,8 +3872,8 @@ bool sh_common_execution::generate_group_4(drcuml_block &block, compiler_state &
return true;
case 0x03: // STCMSR(Rn);
- UML_SUB(block, R32(Rn), R32(Rn), 4); // sub Rn, Rn, #4
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_SUB(block, R32(REG_N), R32(REG_N), 4); // sub Rn, Rn, #4
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
UML_MOV(block, I1, mem(&m_sh2_state->sr)); // mov r1, sr
SETEA(0); // set ea for debug
UML_CALLH(block, *m_write32); // call write32
@@ -3969,10 +3883,10 @@ bool sh_common_execution::generate_group_4(drcuml_block &block, compiler_state &
return true;
case 0x06: // LDSMMACH(Rn);
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
SETEA(0);
UML_CALLH(block, *m_read32); // call read32
- UML_ADD(block, R32(Rn), R32(Rn), 4); // add Rn, #4
+ UML_ADD(block, R32(REG_N), R32(REG_N), 4); // add Rn, #4
UML_MOV(block, mem(&m_sh2_state->mach), I0); // mov mach, r0
if (!in_delay_slot)
@@ -3983,35 +3897,35 @@ bool sh_common_execution::generate_group_4(drcuml_block &block, compiler_state &
return generate_group_4_LDCMSR(block, compiler, desc, opcode, in_delay_slot, ovrpc);
case 0x08: // SHLL2(Rn);
- UML_SHL(block, R32(Rn), R32(Rn), 2);
+ UML_SHL(block, R32(REG_N), R32(REG_N), 2);
return true;
case 0x09: // SHLR2(Rn);
- UML_SHR(block, R32(Rn), R32(Rn), 2);
+ UML_SHR(block, R32(REG_N), R32(REG_N), 2);
return true;
case 0x18: // SHLL8(Rn);
- UML_SHL(block, R32(Rn), R32(Rn), 8);
+ UML_SHL(block, R32(REG_N), R32(REG_N), 8);
return true;
case 0x19: // SHLR8(Rn);
- UML_SHR(block, R32(Rn), R32(Rn), 8);
+ UML_SHR(block, R32(REG_N), R32(REG_N), 8);
return true;
case 0x28: // SHLL16(Rn);
- UML_SHL(block, R32(Rn), R32(Rn), 16);
+ UML_SHL(block, R32(REG_N), R32(REG_N), 16);
return true;
case 0x29: // SHLR16(Rn);
- UML_SHR(block, R32(Rn), R32(Rn), 16);
+ UML_SHR(block, R32(REG_N), R32(REG_N), 16);
return true;
case 0x0a: // LDSMACH(Rn);
- UML_MOV(block, mem(&m_sh2_state->mach), R32(Rn)); // mov mach, Rn
+ UML_MOV(block, mem(&m_sh2_state->mach), R32(REG_N)); // mov mach, Rn
return true;
case 0x0b: // JSR(Rn);
- UML_MOV(block, mem(&m_sh2_state->target), R32(Rn)); // mov target, Rn
+ UML_MOV(block, mem(&m_sh2_state->target), R32(REG_N)); // mov target, Rn
UML_ADD(block, mem(&m_sh2_state->pr), desc->pc, 4); // add m_pr, desc->pc, #4 (skip the current insn & delay slot)
@@ -4038,7 +3952,7 @@ bool sh_common_execution::generate_group_4(drcuml_block &block, compiler_state &
if (m_cpu_type > CPU_TYPE_SH1)
{
UML_AND(block, I0, mem(&m_sh2_state->sr), ~SH_T); // and r0, sr, ~T (clear the T bit)
- UML_SUB(block, R32(Rn), R32(Rn), 1); // sub Rn, Rn, 1
+ UML_SUB(block, R32(REG_N), R32(REG_N), 1); // sub Rn, Rn, 1
UML_JMPc(block, COND_NZ, compiler.labelnum); // jz compiler.labelnum
UML_OR(block, I0, I0, SH_T); // or r0, r0, T
@@ -4052,7 +3966,7 @@ bool sh_common_execution::generate_group_4(drcuml_block &block, compiler_state &
case 0x11: // CMPPZ(Rn);
UML_AND(block, I0, mem(&m_sh2_state->sr), ~SH_T); // and r0, sr, ~T (clear the T bit)
- UML_CMP(block, R32(Rn), 0); // cmp Rn, 0
+ UML_CMP(block, R32(REG_N), 0); // cmp Rn, 0
UML_JMPc(block, COND_S, compiler.labelnum); // js compiler.labelnum (if negative)
UML_OR(block, I0, I0, SH_T); // or r0, r0, T
@@ -4064,7 +3978,7 @@ bool sh_common_execution::generate_group_4(drcuml_block &block, compiler_state &
case 0x15: // CMPPL(Rn);
UML_AND(block, I0, mem(&m_sh2_state->sr), ~SH_T); // and r0, sr, ~T (clear the T bit)
- UML_CMP(block, R32(Rn), 0); // cmp Rn, 0
+ UML_CMP(block, R32(REG_N), 0); // cmp Rn, 0
UML_JMPc(block, COND_S, compiler.labelnum); // js compiler.labelnum (if negative)
UML_JMPc(block, COND_Z, compiler.labelnum); // jz compiler.labelnum (if zero)
@@ -4076,8 +3990,8 @@ bool sh_common_execution::generate_group_4(drcuml_block &block, compiler_state &
return true;
case 0x12: // STSMMACL(Rn);
- UML_SUB(block, R32(Rn), R32(Rn), 4); // sub Rn, Rn, #4
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_SUB(block, R32(REG_N), R32(REG_N), 4); // sub Rn, Rn, #4
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
UML_MOV(block, I1, mem(&m_sh2_state->macl)); // mov r1, macl
SETEA(0); // set ea for debug
UML_CALLH(block, *m_write32); // call write32
@@ -4087,8 +4001,8 @@ bool sh_common_execution::generate_group_4(drcuml_block &block, compiler_state &
return true;
case 0x13: // STCMGBR(Rn);
- UML_SUB(block, R32(Rn), R32(Rn), 4); // sub Rn, Rn, #4
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_SUB(block, R32(REG_N), R32(REG_N), 4); // sub Rn, Rn, #4
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
UML_MOV(block, I1, mem(&m_sh2_state->gbr)); // mov r1, gbr
SETEA(0); // set ea for debug
UML_CALLH(block, *m_write32); // call write32
@@ -4098,10 +4012,10 @@ bool sh_common_execution::generate_group_4(drcuml_block &block, compiler_state &
return true;
case 0x16: // LDSMMACL(Rn);
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
SETEA(0);
UML_CALLH(block, *m_read32); // call read32
- UML_ADD(block, R32(Rn), R32(Rn), 4); // add Rn, #4
+ UML_ADD(block, R32(REG_N), R32(REG_N), 4); // add Rn, #4
UML_MOV(block, mem(&m_sh2_state->macl), I0); // mov macl, r0
if (!in_delay_slot)
@@ -4109,10 +4023,10 @@ bool sh_common_execution::generate_group_4(drcuml_block &block, compiler_state &
return true;
case 0x17: // LDCMGBR(Rn);
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
SETEA(0);
UML_CALLH(block, *m_read32); // call read32
- UML_ADD(block, R32(Rn), R32(Rn), 4); // add Rn, #4
+ UML_ADD(block, R32(REG_N), R32(REG_N), 4); // add Rn, #4
UML_MOV(block, mem(&m_sh2_state->gbr), I0); // mov gbr, r0
if (!in_delay_slot)
@@ -4120,11 +4034,11 @@ bool sh_common_execution::generate_group_4(drcuml_block &block, compiler_state &
return true;
case 0x1a: // LDSMACL(Rn);
- UML_MOV(block, mem(&m_sh2_state->macl), R32(Rn)); // mov macl, Rn
+ UML_MOV(block, mem(&m_sh2_state->macl), R32(REG_N)); // mov macl, Rn
return true;
case 0x1b: // TAS(Rn);
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
SETEA(0);
UML_CALLH(block, *m_read8); // call read8
@@ -4139,7 +4053,7 @@ bool sh_common_execution::generate_group_4(drcuml_block &block, compiler_state &
UML_OR(block, I1, I0, 0x80); // or r1, r0, #0x80
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
UML_CALLH(block, *m_write8); // write the value back
if (!in_delay_slot)
@@ -4147,27 +4061,27 @@ bool sh_common_execution::generate_group_4(drcuml_block &block, compiler_state &
return true;
case 0x1e: // LDCGBR(Rn);
- UML_MOV(block, mem(&m_sh2_state->gbr), R32(Rn)); // mov gbr, Rn
+ UML_MOV(block, mem(&m_sh2_state->gbr), R32(REG_N)); // mov gbr, Rn
return true;
case 0x20: // SHAL(Rn);
UML_AND(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), ~SH_T); // and sr, sr, ~T
- UML_SHR(block, I0, R32(Rn), 31); // shr r0, Rn, 31
+ UML_SHR(block, I0, R32(REG_N), 31); // shr r0, Rn, 31
UML_AND(block, I0, I0, SH_T); // and r0, r0, T
UML_OR(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), I0); // or sr, sr, r0
- UML_SHL(block, R32(Rn), R32(Rn), 1); // shl Rn, Rn, 1
+ UML_SHL(block, R32(REG_N), R32(REG_N), 1); // shl Rn, Rn, 1
return true;
case 0x21: // SHAR(Rn);
UML_AND(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), ~SH_T); // and sr, sr, ~T
- UML_AND(block, I0, R32(Rn), SH_T); // and r0, Rn, T
+ UML_AND(block, I0, R32(REG_N), SH_T); // and r0, Rn, T
UML_OR(block, mem(&m_sh2_state->sr), mem(&m_sh2_state->sr), I0); // or sr, sr, r0
- UML_SAR(block, R32(Rn), R32(Rn), 1); // sar Rn, Rn, 1
+ UML_SAR(block, R32(REG_N), R32(REG_N), 1); // sar Rn, Rn, 1
return true;
case 0x22: // STSMPR(Rn);
- UML_SUB(block, R32(Rn), R32(Rn), 4); // sub Rn, Rn, 4
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_SUB(block, R32(REG_N), R32(REG_N), 4); // sub Rn, Rn, 4
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
SETEA(0);
UML_MOV(block, I1, mem(&m_sh2_state->pr)); // mov r1, pr
UML_CALLH(block, *m_write32); // call write32
@@ -4177,8 +4091,8 @@ bool sh_common_execution::generate_group_4(drcuml_block &block, compiler_state &
return true;
case 0x23: // STCMVBR(Rn);
- UML_SUB(block, R32(Rn), R32(Rn), 4); // sub Rn, Rn, 4
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_SUB(block, R32(REG_N), R32(REG_N), 4); // sub Rn, Rn, 4
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
SETEA(0);
UML_MOV(block, I1, mem(&m_sh2_state->vbr)); // mov r1, vbr
UML_CALLH(block, *m_write32); // call write32
@@ -4189,46 +4103,46 @@ bool sh_common_execution::generate_group_4(drcuml_block &block, compiler_state &
case 0x24: // ROTCL(Rn);
UML_CARRY(block, mem(&m_sh2_state->sr), 0); // carry sr,0
- UML_ROLC(block, R32(Rn), R32(Rn), 1); // rolc Rn,Rn,1
+ UML_ROLC(block, R32(REG_N), R32(REG_N), 1); // rolc Rn,Rn,1
UML_SETc(block, COND_C, I0); // set i0,C
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, SH_T); // rolins sr,i0,0,T
return true;
case 0x25: // ROTCR(Rn);
UML_CARRY(block, mem(&m_sh2_state->sr), 0); // carry sr,0
- UML_RORC(block, R32(Rn), R32(Rn), 1); // rorc Rn,Rn,1
+ UML_RORC(block, R32(REG_N), R32(REG_N), 1); // rorc Rn,Rn,1
UML_SETc(block, COND_C, I0); // set i0,C
UML_ROLINS(block, mem(&m_sh2_state->sr), I0, 0, SH_T); // rolins sr,i0,0,T
return true;
case 0x26: // LDSMPR(Rn);
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
SETEA(0);
UML_CALLH(block, *m_read32); // call read32
UML_MOV(block, mem(&m_sh2_state->pr), I0); // mov m_pr, r0
- UML_ADD(block, R32(Rn), R32(Rn), 4); // add Rn, Rn, #4
+ UML_ADD(block, R32(REG_N), R32(REG_N), 4); // add Rn, Rn, #4
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
case 0x27: // LDCMVBR(Rn);
- UML_MOV(block, I0, R32(Rn)); // mov r0, Rn
+ UML_MOV(block, I0, R32(REG_N)); // mov r0, Rn
SETEA(0);
UML_CALLH(block, *m_read32); // call read32
UML_MOV(block, mem(&m_sh2_state->vbr), I0); // mov m_sh2_state->vbr, r0
- UML_ADD(block, R32(Rn), R32(Rn), 4); // add Rn, Rn, #4
+ UML_ADD(block, R32(REG_N), R32(REG_N), 4); // add Rn, Rn, #4
if (!in_delay_slot)
generate_update_cycles(block, compiler, desc->pc + 2, true);
return true;
case 0x2a: // LDSPR(Rn);
- UML_MOV(block, mem(&m_sh2_state->pr), R32(Rn)); // mov m_pr, Rn
+ UML_MOV(block, mem(&m_sh2_state->pr), R32(REG_N)); // mov m_pr, Rn
return true;
case 0x2b: // JMP(Rn);
- UML_MOV(block, mem(&m_sh2_state->target), R32(Rn)); // mov target, Rn
+ UML_MOV(block, mem(&m_sh2_state->target), R32(REG_N)); // mov target, Rn
generate_delay_slot(block, compiler, desc, m_sh2_state->target);
@@ -4237,7 +4151,7 @@ bool sh_common_execution::generate_group_4(drcuml_block &block, compiler_state &
return true;
case 0x2e: // LDCVBR(Rn);
- UML_MOV(block, mem(&m_sh2_state->vbr), R32(Rn)); // mov vbr, Rn
+ UML_MOV(block, mem(&m_sh2_state->vbr), R32(REG_N)); // mov vbr, Rn
return true;
case 0x0c:
@@ -4293,6 +4207,6 @@ void sh_common_execution::sh2drc_add_pcflush(offs_t address)
{
if (!allow_drc()) return;
- if (m_pcfsel < ARRAY_LENGTH(m_pcflushes))
+ if (m_pcfsel < std::size(m_pcflushes))
m_pcflushes[m_pcfsel++] = address;
}