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Diffstat (limited to 'src/devices/cpu/powerpc/ppccom.h')
-rw-r--r--src/devices/cpu/powerpc/ppccom.h12
1 files changed, 10 insertions, 2 deletions
diff --git a/src/devices/cpu/powerpc/ppccom.h b/src/devices/cpu/powerpc/ppccom.h
index 918ca62a4c4..da12935a5cc 100644
--- a/src/devices/cpu/powerpc/ppccom.h
+++ b/src/devices/cpu/powerpc/ppccom.h
@@ -64,7 +64,8 @@
#define PPCCAP_MFIOC 0x40 /* TRUE if we have memory-forced I/O controller interface accesses */
#define PPCCAP_601BAT 0x80 /* TRUE if we're doing 601-style BATs (unified I/D, different bit layout) */
#define PPCCAP_604_MMU 0x100 /* TRUE if we have 604-class MMU features */
-
+#define PPCCAP_750_TLB 0x200 /* TRUE if we have the extended 740/750 series TLB */
+#define PPCCAP_LEGACY_POWER 0x400 /* TRUE if we support the legacy POWER instructions */
/* exception types */
enum
@@ -171,6 +172,14 @@ enum
SPR4XX_PBL2 = 0x3fe, /* R/W 403GA 406GA Protection Bound Lower 2 */
SPR4XX_PBU2 = 0x3ff, /* R/W 403GA 406GA Protection Bound Upper 2 */
+ /* PowerPC 601 POWER back compatibility SPR indexes */
+ SPR601_MQ = 0x000, /* R/W Muliplicand/Quotient for 601 POWER instructions */
+ SPR601_RTCUR_PWR = 0x004, /* R Counts up number set in SPR 20 once per second, POWER only */
+ SPR601_RTCLR_PWR = 0x005, /* R Number of nanoseconds between the seconds counted in SPR 4 */
+ SPR601_PWRDEC = 0x006, /* R Decrementer register mirror for POWER compatibilty */
+ SPR601_RTCUW_PWR = 0x014, /* W Seconds counter, set here and read SPR 4 */
+ SPR601_RTCLW_PWR = 0x015, /* W Nanoseconds counter, not clear what writing here does */
+
/* PowerPC 602 SPR register indexes */
SPR602_TCR = 0x3d8, /* 602 */
SPR602_IBR = 0x3da, /* 602 */
@@ -198,7 +207,6 @@ enum
SPR603_HID2 = 0x3f3 /* R/W 603 */
};
-
/* PowerPC 4XX DCR register indexes */
enum
{