summaryrefslogtreecommitdiffstatshomepage
path: root/src/devices/cpu/nec/v25sfr.cpp
diff options
context:
space:
mode:
Diffstat (limited to 'src/devices/cpu/nec/v25sfr.cpp')
-rw-r--r--src/devices/cpu/nec/v25sfr.cpp247
1 files changed, 234 insertions, 13 deletions
diff --git a/src/devices/cpu/nec/v25sfr.cpp b/src/devices/cpu/nec/v25sfr.cpp
index 7c606a82afd..44d01e77999 100644
--- a/src/devices/cpu/nec/v25sfr.cpp
+++ b/src/devices/cpu/nec/v25sfr.cpp
@@ -8,7 +8,7 @@
#include "emu.h"
#include "v25.h"
-#include "v25priv.h"
+#include "v25priv.ipp"
void v25_common_device::ida_sfr_map(address_map &map)
{
@@ -31,11 +31,19 @@ void v25_common_device::ida_sfr_map(address_map &map)
map(0x14e, 0x14e).rw(FUNC(v25_common_device::exic2_r), FUNC(v25_common_device::exic2_w));
map(0x165, 0x165).rw(FUNC(v25_common_device::srms0_r), FUNC(v25_common_device::srms0_w));
map(0x166, 0x166).rw(FUNC(v25_common_device::stms0_r), FUNC(v25_common_device::stms0_w));
+ map(0x168, 0x168).rw(FUNC(v25_common_device::scm0_r), FUNC(v25_common_device::scm0_w));
+ map(0x169, 0x169).rw(FUNC(v25_common_device::scc0_r), FUNC(v25_common_device::scc0_w));
+ map(0x16a, 0x16a).rw(FUNC(v25_common_device::brg0_r), FUNC(v25_common_device::brg0_w));
+ map(0x16b, 0x16b).r(FUNC(v25_common_device::sce0_r));
map(0x16c, 0x16c).rw(FUNC(v25_common_device::seic0_r), FUNC(v25_common_device::seic0_w));
map(0x16d, 0x16d).rw(FUNC(v25_common_device::sric0_r), FUNC(v25_common_device::sric0_w));
map(0x16e, 0x16e).rw(FUNC(v25_common_device::stic0_r), FUNC(v25_common_device::stic0_w));
map(0x175, 0x175).rw(FUNC(v25_common_device::srms1_r), FUNC(v25_common_device::srms1_w));
map(0x176, 0x176).rw(FUNC(v25_common_device::stms1_r), FUNC(v25_common_device::stms1_w));
+ map(0x178, 0x178).rw(FUNC(v25_common_device::scm1_r), FUNC(v25_common_device::scm1_w));
+ map(0x179, 0x179).rw(FUNC(v25_common_device::scc1_r), FUNC(v25_common_device::scc1_w));
+ map(0x17a, 0x17a).rw(FUNC(v25_common_device::brg1_r), FUNC(v25_common_device::brg1_w));
+ map(0x17b, 0x17b).r(FUNC(v25_common_device::sce1_r));
map(0x17c, 0x17c).rw(FUNC(v25_common_device::seic1_r), FUNC(v25_common_device::seic1_w));
map(0x17d, 0x17d).rw(FUNC(v25_common_device::sric1_r), FUNC(v25_common_device::sric1_w));
map(0x17e, 0x17e).rw(FUNC(v25_common_device::stic1_r), FUNC(v25_common_device::stic1_w));
@@ -49,6 +57,12 @@ void v25_common_device::ida_sfr_map(address_map &map)
map(0x19c, 0x19c).rw(FUNC(v25_common_device::tmic0_r), FUNC(v25_common_device::tmic0_w));
map(0x19d, 0x19d).rw(FUNC(v25_common_device::tmic1_r), FUNC(v25_common_device::tmic1_w));
map(0x19e, 0x19e).rw(FUNC(v25_common_device::tmic2_r), FUNC(v25_common_device::tmic2_w));
+ map(0x1a0, 0x1a0).rw(FUNC(v25_common_device::dmac0_r), FUNC(v25_common_device::dmac0_w));
+ map(0x1a1, 0x1a1).rw(FUNC(v25_common_device::dmam0_r), FUNC(v25_common_device::dmam0_w));
+ map(0x1a2, 0x1a2).rw(FUNC(v25_common_device::dmac1_r), FUNC(v25_common_device::dmac1_w));
+ map(0x1a3, 0x1a3).rw(FUNC(v25_common_device::dmam1_r), FUNC(v25_common_device::dmam1_w));
+ map(0x1ac, 0x1ac).rw(FUNC(v25_common_device::dic0_r), FUNC(v25_common_device::dic0_w));
+ map(0x1ad, 0x1ad).rw(FUNC(v25_common_device::dic1_r), FUNC(v25_common_device::dic1_w));
map(0x1e1, 0x1e1).rw(FUNC(v25_common_device::rfm_r), FUNC(v25_common_device::rfm_w));
map(0x1e8, 0x1e9).rw(FUNC(v25_common_device::wtc_r), FUNC(v25_common_device::wtc_w));
map(0x1ea, 0x1ea).rw(FUNC(v25_common_device::flag_r), FUNC(v25_common_device::flag_w));
@@ -246,6 +260,46 @@ void v25_common_device::stms0_w(uint8_t d)
m_stms[0] = d & 0xf7;
}
+uint8_t v25_common_device::scm0_r()
+{
+ return m_scm[0];
+}
+
+void v25_common_device::scm0_w(uint8_t d)
+{
+ logerror("%06x: SCM0 set to %02x\n", PC(), d);
+ m_scm[0] = d;
+}
+
+uint8_t v25_common_device::scc0_r()
+{
+ return m_scc[0];
+}
+
+void v25_common_device::scc0_w(uint8_t d)
+{
+ logerror("%06x: SCC0 prescaler set to %d\n", PC(), 2 << (d & 0x0f));
+ m_scc[0] = d & 0x0f;
+}
+
+uint8_t v25_common_device::brg0_r()
+{
+ return m_brg[0];
+}
+
+void v25_common_device::brg0_w(uint8_t d)
+{
+ logerror("%06x: BRG0 divider set to %u\n", PC(), d);
+ m_brg[0] = d;
+}
+
+uint8_t v25_common_device::sce0_r()
+{
+ if (!machine().side_effects_disabled())
+ logerror("%06x: Warning: read back SCE0\n",PC());
+ return m_sce[0];
+}
+
uint8_t v25_common_device::seic0_r()
{
return read_irqcontrol(INTSER0, m_priority_ints0);
@@ -302,6 +356,46 @@ void v25_common_device::stms1_w(uint8_t d)
m_stms[1] = d & 0xf7;
}
+uint8_t v25_common_device::scm1_r()
+{
+ return m_scm[1];
+}
+
+void v25_common_device::scm1_w(uint8_t d)
+{
+ logerror("%06x: SCM1 set to %02x\n", PC(), d);
+ m_scm[1] = d;
+}
+
+uint8_t v25_common_device::scc1_r()
+{
+ return m_scc[1];
+}
+
+void v25_common_device::scc1_w(uint8_t d)
+{
+ logerror("%06x: SCC1 prescaler set to %d\n", PC(), 2 << (d & 0x0f));
+ m_scc[1] = d & 0x0f;
+}
+
+uint8_t v25_common_device::brg1_r()
+{
+ return m_brg[1];
+}
+
+void v25_common_device::brg1_w(uint8_t d)
+{
+ logerror("%06x: BRG1 divider set to %u\n", PC(), d);
+ m_brg[1] = d;
+}
+
+uint8_t v25_common_device::sce1_r()
+{
+ if (!machine().side_effects_disabled())
+ logerror("%06x: Warning: read back SCE1\n",PC());
+ return m_sce[1];
+}
+
uint8_t v25_common_device::seic1_r()
{
return read_irqcontrol(INTSER1, m_priority_ints1);
@@ -381,7 +475,13 @@ uint16_t v25_common_device::md1_r()
void v25_common_device::md1_w(uint16_t d)
{
- m_MD1 = d;
+ if (m_MD1 == 0 && d != 0)
+ {
+ m_MD1 = d;
+ tmc1_w(m_TMC1); // HACK: start timer if necessary
+ }
+ else
+ m_MD1 = d;
}
void v25_common_device::tmc0_w(uint8_t d)
@@ -389,7 +489,7 @@ void v25_common_device::tmc0_w(uint8_t d)
m_TMC0 = d;
if (BIT(d, 0)) // oneshot mode
{
- if (BIT(d, 7))
+ if (BIT(d, 7) && m_TM0 != 0)
{
unsigned tmp = m_PCK * m_TM0 * (BIT(d, 6) ? 128 : 12);
attotime time = clocks_to_attotime(tmp);
@@ -398,7 +498,7 @@ void v25_common_device::tmc0_w(uint8_t d)
else
m_timers[0]->adjust(attotime::never);
- if (BIT(d, 5))
+ if (BIT(d, 5) && m_MD0 != 0)
{
unsigned tmp = m_PCK * m_MD0 * (BIT(d, 4) ? 128 : 12);
attotime time = clocks_to_attotime(tmp);
@@ -409,7 +509,7 @@ void v25_common_device::tmc0_w(uint8_t d)
}
else // interval mode
{
- if (BIT(d, 7))
+ if (BIT(d, 7) && m_MD0 != 0)
{
unsigned tmp = m_PCK * m_MD0 * (BIT(d, 6) ? 128 : 6);
attotime time = clocks_to_attotime(tmp);
@@ -428,11 +528,11 @@ void v25_common_device::tmc0_w(uint8_t d)
void v25_common_device::tmc1_w(uint8_t d)
{
m_TMC1 = d & 0xC0;
- if (BIT(d, 7))
+ if (BIT(d, 7) && m_MD1 != 0)
{
unsigned tmp = m_PCK * m_MD1 * (BIT(d, 6) ? 128 : 6);
attotime time = clocks_to_attotime(tmp);
- m_timers[2]->adjust(time, INTTU2, time);
+ m_timers[2]->adjust(time, INTTU1 | INTTU2, time);
m_TM1 = m_MD1;
}
else
@@ -481,6 +581,115 @@ void v25_common_device::tmic2_w(uint8_t d)
write_irqcontrol(INTTU2, d);
}
+uint8_t v25_common_device::dmac0_r()
+{
+ return m_dmac[0];
+}
+
+void v25_common_device::dmac0_w(uint8_t d)
+{
+ logerror("%06x: DMAC0 set to %02x\n", PC(), d);
+ logerror(" SAR0 %s after each transfer\n", (d & 0x03) == 0x01 ? "incremented" : (d & 0x03) == 0x02 ? "decremented" : "unmodified");
+ logerror(" DAR0 %s after each transfer\n", (d & 0x30) == 0x10 ? "incremented" : (d & 0x30) == 0x20 ? "decremented" : "unmodified");
+ m_dmac[0] = d & 0x33;
+}
+
+uint8_t v25_common_device::dmam0_r()
+{
+ return m_dmam[0];
+}
+
+void v25_common_device::dmam0_w(uint8_t d)
+{
+ logerror("%06x: DMAM0 set to %02x\n", PC(), d);
+ if ((d & 0x60) == 0)
+ logerror(" %s mode, memory to memory, %s\n", BIT(d, 7) ? "Single step" : "Burst", BIT(d, 4) ? "words" : "bytes");
+ else if ((d & 0x60) != 0x60)
+ logerror(" %s mode, %s to %s, %s\n", BIT(d, 7) ? "Single transfer" : "Demand release",
+ BIT(d, 5) ? "I/O" : "memory",
+ BIT(d, 6) ? "I/O" : "memory",
+ BIT(d, 4) ? "words" : "bytes");
+ if (BIT(d, 2))
+ {
+ uint16_t sar = m_internal_ram[0];
+ uint16_t dar = m_internal_ram[1];
+ uint16_t sarh_darh = m_internal_ram[2];
+ uint16_t tc = m_internal_ram[3];
+ logerror(" DMA enabled%s (%04x:%04x -> %04x:%04x, %u %s)\n", BIT(d, 3) ? " and triggered" : "",
+ sarh_darh & 0xff00, sar,
+ (sarh_darh & 0x00ff) << 8, dar,
+ tc, BIT(d, 4) ? "words" : "bytes");
+ }
+ else
+ logerror(" DMA not enabled\n");
+ m_dmam[0] = d & 0xfc;
+}
+
+uint8_t v25_common_device::dmac1_r()
+{
+ return m_dmac[1];
+}
+
+void v25_common_device::dmac1_w(uint8_t d)
+{
+ logerror("%06x: DMAC1 set to %02x\n", PC(), d);
+ logerror(" SAR1 %s after each transfer\n", (d & 0x03) == 0x01 ? "incremented" : (d & 0x03) == 0x02 ? "decremented" : "unmodified");
+ logerror(" DAR1 %s after each transfer\n", (d & 0x30) == 0x10 ? "incremented" : (d & 0x30) == 0x20 ? "decremented" : "unmodified");
+ m_dmac[1] = d & 0x33;
+}
+
+uint8_t v25_common_device::dmam1_r()
+{
+ return m_dmam[1];
+}
+
+void v25_common_device::dmam1_w(uint8_t d)
+{
+ logerror("%06x: DMAM1 set to %02x\n", PC(), d);
+ if ((d & 0x60) == 0)
+ logerror(" %s mode, memory to memory, %s\n", BIT(d, 7) ? "Single step" : "Burst", BIT(d, 4) ? "words" : "bytes");
+ else if ((d & 0x60) != 0x60)
+ logerror(" %s mode, %s to %s, %s\n", BIT(d, 7) ? "Single transfer" : "Demand release",
+ BIT(d, 5) ? "I/O" : "memory",
+ BIT(d, 6) ? "I/O" : "memory",
+ BIT(d, 4) ? "words" : "bytes");
+ if (BIT(d, 2))
+ {
+ uint16_t sar = m_internal_ram[4];
+ uint16_t dar = m_internal_ram[5];
+ uint16_t sarh_darh = m_internal_ram[6];
+ uint16_t tc = m_internal_ram[7];
+ logerror(" DMA enabled%s (%04x:%04x -> %04x:%04x, %u %s)\n", BIT(d, 3) ? " and triggered" : "",
+ sarh_darh & 0xff00, sar,
+ (sarh_darh & 0x00ff) << 8, dar,
+ tc, BIT(d, 4) ? "words" : "bytes");
+ }
+ else
+ logerror(" DMA not enabled\n");
+ m_dmam[1] = d & 0xfc;
+}
+
+uint8_t v25_common_device::dic0_r()
+{
+ return read_irqcontrol(INTD0, m_priority_intd);
+}
+
+void v25_common_device::dic0_w(uint8_t d)
+{
+ write_irqcontrol(INTD0, d);
+ m_priority_intd = d & 0x7;
+}
+
+uint8_t v25_common_device::dic1_r()
+{
+ return read_irqcontrol(INTD1, 7);
+}
+
+void v25_common_device::dic1_w(uint8_t d)
+{
+ write_irqcontrol(INTD1, d);
+}
+
uint8_t v25_common_device::rfm_r()
{
return m_RFM;
@@ -605,7 +814,7 @@ void v25_common_device::idb_w(uint8_t d)
uint8_t v25_common_device::v25_read_byte(unsigned a)
{
if (((a & 0xffe00) == m_IDB && (m_RAMEN || BIT(a, 8))) || a == 0xfffff)
- return m_data->read_byte(a & 0x1ff);
+ return m_data.read_byte(a & 0x1ff);
else
return m_program->read_byte(a);
}
@@ -617,9 +826,9 @@ uint16_t v25_common_device::v25_read_word(unsigned a)
// not sure about this - manual says FFFFC-FFFFE are "reserved"
if (a == 0xffffe)
- return (m_program->read_byte(a) | (m_data->read_byte(0x1ff) << 8));
+ return (m_program->read_byte(a) | (m_data.read_byte(0x1ff) << 8));
else if ((a & 0xffe00) == m_IDB && (m_RAMEN || BIT(a, 8)))
- return m_data->read_word(a & 0x1ff);
+ return m_data.read_word(a & 0x1ff);
else
return m_program->read_word(a);
}
@@ -627,7 +836,7 @@ uint16_t v25_common_device::v25_read_word(unsigned a)
void v25_common_device::v25_write_byte(unsigned a, uint8_t d)
{
if (((a & 0xffe00) == m_IDB && (m_RAMEN || BIT(a, 8))) || a == 0xfffff)
- m_data->write_byte(a & 0x1ff, d);
+ m_data.write_byte(a & 0x1ff, d);
else
m_program->write_byte(a, d);
}
@@ -645,10 +854,22 @@ void v25_common_device::v25_write_word(unsigned a, uint16_t d)
if (a == 0xffffe)
{
m_program->write_byte(a, d);
- m_data->write_byte(0x1ff, d >> 8);
+ m_data.write_byte(0x1ff, d >> 8);
}
else if ((a & 0xffe00) == m_IDB && (m_RAMEN || BIT(a, 8)))
- m_data->write_word(a & 0x1ff, d);
+ m_data.write_word(a & 0x1ff, d);
else
m_program->write_word(a, d);
}
+
+bool v25_common_device::memory_translate(int spacenum, int intention, offs_t &address, address_space *&target_space)
+{
+ if (spacenum == AS_PROGRAM && intention != TR_FETCH && (((address & 0xffe00) == m_IDB && (m_RAMEN || BIT(address, 8))) || address == 0xfffff))
+ {
+ address &= 0x1ff;
+ target_space = &m_data.space();
+ }
+ else
+ target_space = &space(spacenum);
+ return true;
+}