diff options
Diffstat (limited to 'src/devices/cpu/mcs51/mcs51dasm.cpp')
-rw-r--r-- | src/devices/cpu/mcs51/mcs51dasm.cpp | 492 |
1 files changed, 459 insertions, 33 deletions
diff --git a/src/devices/cpu/mcs51/mcs51dasm.cpp b/src/devices/cpu/mcs51/mcs51dasm.cpp index ebd77aece33..ab3489d928f 100644 --- a/src/devices/cpu/mcs51/mcs51dasm.cpp +++ b/src/devices/cpu/mcs51/mcs51dasm.cpp @@ -2,31 +2,19 @@ // copyright-holders:Steve Ellenoff /***************************************************************************** * - * i8051dasm.c - * Portable MCS-51 Family Emulator + * Portable MCS-51 Family Disassembler + * Copyright Steve Ellenoff * - * Chips in the family: - * 8051 Product Line (8031,8051,8751) - * 8052 Product Line (8032,8052,8752) - * 8054 Product Line (8054) - * 8058 Product Line (8058) - * - * Copyright Steve Ellenoff, all rights reserved. - * - * This work is based on: - * #1) 'Intel(tm) MC51 Microcontroller Family Users Manual' and - * #2) 8051 simulator by Travis Marlatte - * #3) Portable UPI-41/8041/8741/8042/8742 emulator V0.1 by Juergen Buchmueller (MAME CORE) - * - ***************************************************************************** * Symbol Memory Name Tables borrowed from: * D52 8052 Disassembler - Copyright Jeffery L. Post + * *****************************************************************************/ #include "emu.h" #include "mcs51dasm.h" // Note: addresses >= 0x100 are bit addresses +// Note: place default_names last in constructors to allow other names to override it const mcs51_disassembler::mem_info mcs51_disassembler::default_names[] = { { 0x00, "rb0r0" }, @@ -226,7 +214,7 @@ const mcs51_disassembler::mem_info mcs51_disassembler::i8xc51gb_names[] = { { 0xd4, "ad5" }, { 0xe4, "ad6" }, { 0xf4, "ad7" }, - { 0x85, "acon" }, + { 0x97, "acon" }, { 0xc7, "acmp" }, { 0xe8, "c1con" }, @@ -319,16 +307,16 @@ const mcs51_disassembler::mem_info mcs51_disassembler::i8xc751_names[] = { { 0x98, "i2con" }, { 0x99, "i2dat" }, { 0xd8, "i2cfg" }, - { 0xf8, "i2sta" }, /* read only */ + { 0xf8, "i2sta" }, // read only - { 0x198, "xstp" }, /* read: no function */ - { 0x199, "xstr" }, /* read: MASTER */ - { 0x19a, "cstp" }, /* read: STP */ - { 0x19b, "cstr" }, /* read: STR */ - { 0x19c, "carl" }, /* read: ARL */ - { 0x19d, "cdr" }, /* read: DRDY */ - { 0x19e, "idle" }, /* read: ATN */ - { 0x19f, "cxa" }, /* read: RDAT */ + { 0x198, "xstp" }, // read: no function + { 0x199, "xstr" }, // read: MASTER + { 0x19a, "cstp" }, // read: STP + { 0x19b, "cstr" }, // read: STR + { 0x19c, "carl" }, // read: ARL + { 0x19d, "cdr" }, // read: DRDY + { 0x19e, "idle" }, // read: ATN + { 0x19f, "cxa" }, // read: RDAT { 0x1ac, "ei2" }, @@ -360,6 +348,409 @@ const mcs51_disassembler::mem_info mcs51_disassembler::i8xc751_names[] = { { -1 } }; +const mcs51_disassembler::mem_info mcs51_disassembler::ds80c320_names[] = { + { 0x84, "dpl1" }, + { 0x85, "dph1" }, + { 0x86, "dps" }, + { 0x8e, "ckcon" }, + { 0x91, "exif" }, + { 0x98, "scon0" }, + { 0x99, "sbuf0" }, + { 0xa9, "saddr0" }, + { 0xaa, "saddr1" }, + { 0xb9, "saden0" }, + { 0xba, "saden1" }, + { 0xc0, "scon1" }, + { 0xc1, "sbuf1" }, + { 0xc5, "status" }, + { 0xc7, "ta" }, + { 0xc9, "t2mod" }, + { 0xd8, "wdcon" }, + { 0xe8, "eie" }, + { 0xf8, "eip" }, + + { 0x198, "sm0_0" }, + { 0x199, "sm1_0" }, + { 0x19a, "sm2_0" }, + { 0x19b, "ren_0" }, + { 0x19c, "tb8_0" }, + { 0x19d, "rb8_0" }, + { 0x19e, "ti_0" }, + { 0x19f, "ri_0" }, + + { 0x1ac, "es0" }, + { 0x1ae, "es1" }, + + { 0x1bc, "ps0" }, + { 0x1be, "ps1" }, + + { 0x1c0, "sm0_1" }, + { 0x1c1, "sm1_1" }, + { 0x1c2, "sm2_1" }, + { 0x1c3, "ren_1" }, + { 0x1c4, "tb8_1" }, + { 0x1c5, "rb8_1" }, + { 0x1c6, "ti_1" }, + { 0x1c7, "ri_1" }, + + { 0x1d5, "f1" }, + + { 0x1d8, "rwt" }, + { 0x1d9, "ewt" }, + { 0x1da, "wtrf" }, + { 0x1db, "wdif" }, + { 0x1dc, "pf1" }, + { 0x1dd, "epf1" }, + { 0x1de, "por" }, + { 0x1df, "smod_1" }, + + { 0x1e8, "ex2" }, + { 0x1e9, "ex3" }, + { 0x1ea, "ex4" }, + { 0x1eb, "ex5" }, + { 0x1ec, "ewdi" }, + { 0x1ed, "eie.5" }, + { 0x1ee, "eie.6" }, + { 0x1ef, "eie.7" }, + + { 0x1f8, "px2" }, + { 0x1f9, "px3" }, + { 0x1fa, "px4" }, + { 0x1fb, "px5" }, + { 0x1fc, "pwdi" }, + { 0x1fd, "eip.5" }, + { 0x1fe, "eip.6" }, + { 0x1ff, "eip.7" }, + + { -1 } +}; + +const mcs51_disassembler::mem_info mcs51_disassembler::sab80515_names[] = { + { 0xa8, "ien0" }, + { 0xa9, "ip0" }, + { 0xb8, "ien1" }, + { 0xb9, "ip1" }, + { 0xc0, "ircon" }, + { 0xc1, "ccen" }, + { 0xc2, "ccl1" }, + { 0xc3, "cch1" }, + { 0xc4, "ccl2" }, + { 0xc5, "cch2" }, + { 0xc6, "ccl3" }, + { 0xc7, "cch3" }, + { 0xc8, "t2con" }, + { 0xca, "crcl" }, + { 0xcb, "crch" }, + { 0xcc, "tl2" }, + { 0xcd, "th2" }, + { 0xd8, "adcon" }, + { 0xd9, "addat" }, + { 0xda, "dapr" }, + { 0xe8, "p4" }, + { 0xf8, "p5" }, + + { 0x190, "cc0" }, + { 0x191, "cc1" }, + { 0x192, "cc2" }, + { 0x193, "cc3" }, + { 0x194, "int2" }, + { 0x195, "t2ex" }, + { 0x196, "clkout" }, + { 0x197, "t2" }, + + { 0x1ad, "et2" }, + { 0x1ae, "wdt" }, + + { 0x1b8, "eadc" }, + { 0x1b9, "ex2" }, + { 0x1ba, "ex3" }, + { 0x1bb, "ex4" }, + { 0x1bc, "ex5" }, + { 0x1bd, "ex6" }, + { 0x1be, "swdt" }, + { 0x1bf, "exen2" }, + + { 0x1c0, "iadc" }, + { 0x1c1, "iex2" }, + { 0x1c2, "iex3" }, + { 0x1c3, "iex4" }, + { 0x1c4, "iex5" }, + { 0x1c5, "iex6" }, + { 0x1c6, "tf2" }, + { 0x1c7, "exf2" }, + + { 0x1c8, "t2i0" }, + { 0x1c9, "t2i1" }, + { 0x1ca, "t2cm" }, + { 0x1cb, "t2r0" }, + { 0x1cc, "t2r1" }, + { 0x1cd, "i2fr" }, + { 0x1ce, "i3fr" }, + { 0x1cf, "t2ps" }, + + { 0x1d8, "mx0" }, + { 0x1d9, "mx1" }, + { 0x1da, "mx2" }, + { 0x1db, "adm" }, + { 0x1dc, "bsy" }, + { 0x1dd, "adex" }, + { 0x1de, "clk" }, + { 0x1df, "bd" }, + + { -1 } +}; + +const mcs51_disassembler::mem_info mcs51_disassembler::sab80c515_names[] = { + { 0xdb, "p6" }, + + { -1 } +}; + +const mcs51_disassembler::mem_info mcs51_disassembler::rupi44_names[] = { + { 0x00, "rb0r0" }, + { 0x01, "rb0r1" }, + { 0x02, "rb0r2" }, + { 0x03, "rb0r3" }, + { 0x04, "rb0r4" }, + { 0x05, "rb0r5" }, + { 0x06, "rb0r6" }, + { 0x07, "rb0r7" }, + { 0x08, "rb1r0" }, + { 0x09, "rb1r1" }, + { 0x0a, "rb1r2" }, + { 0x0b, "rb1r3" }, + { 0x0c, "rb1r4" }, + { 0x0d, "rb1r5" }, + { 0x0e, "rb1r6" }, + { 0x0f, "rb1r7" }, + { 0x10, "rb2r0" }, + { 0x11, "rb2r1" }, + { 0x12, "rb2r2" }, + { 0x13, "rb2r3" }, + { 0x14, "rb2r4" }, + { 0x15, "rb2r5" }, + { 0x16, "rb2r6" }, + { 0x17, "rb2r7" }, + { 0x18, "rb3r0" }, + { 0x19, "rb3r1" }, + { 0x1a, "rb3r2" }, + { 0x1b, "rb3r3" }, + { 0x1c, "rb3r4" }, + { 0x1d, "rb3r5" }, + { 0x1e, "rb3r6" }, + { 0x1f, "rb3r7" }, + + { 0x80, "p0" }, + { 0x81, "sp" }, + { 0x82, "dpl" }, + { 0x83, "dph" }, + { 0x87, "pcon" }, + { 0x88, "tcon" }, + { 0x89, "tmod" }, + { 0x8a, "tl0" }, + { 0x8b, "tl1" }, + { 0x8c, "th0" }, + { 0x8d, "th1" }, + { 0x90, "p1" }, + { 0xa0, "p2" }, + { 0xa8, "ie" }, + { 0xb0, "p3" }, + { 0xb8, "ip" }, + { 0xc8, "sts" }, + { 0xc9, "smd" }, + { 0xca, "rcb" }, + { 0xcb, "rbl" }, + { 0xcc, "rbs" }, + { 0xcd, "rfl" }, + { 0xce, "stad" }, + { 0xd0, "psw" }, + { 0xd8, "nsnr" }, + { 0xda, "tcb" }, + { 0xdb, "tbl" }, + { 0xdc, "tbc" }, + { 0xe0, "acc" }, + { 0xf0, "b" }, + + { 0x188, "it0" }, + { 0x189, "ie0" }, + { 0x18a, "it1" }, + { 0x18b, "ie1" }, + { 0x18c, "tr0" }, + { 0x18d, "tf0" }, + { 0x18e, "tr1" }, + { 0x18f, "tf1" }, + + { 0x1a8, "ex0" }, + { 0x1a9, "et0" }, + { 0x1aa, "ex1" }, + { 0x1ab, "et1" }, + { 0x1ac, "es" }, + { 0x1ad, "ie.5" }, + { 0x1ae, "ie.6" }, + { 0x1af, "ea" }, + + { 0x1b0, "io" }, + { 0x1b1, "data" }, + { 0x1b2, "int0" }, + { 0x1b3, "int1" }, + { 0x1b4, "t0" }, + { 0x1b5, "t1" }, + { 0x1b6, "wr" }, + { 0x1b7, "rd" }, + + { 0x1b8, "px0" }, + { 0x1b9, "pt0" }, + { 0x1ba, "px1" }, + { 0x1bb, "pt1" }, + { 0x1bc, "ps" }, + { 0x1bd, "ip.5" }, + { 0x1be, "ip.6" }, + { 0x1bf, "ip.7" }, + + { 0x1c8, "rbp" }, + { 0x1c9, "am" }, + { 0x1ca, "opb" }, + { 0x1cb, "bov" }, + { 0x1cc, "si" }, + { 0x1cd, "rts" }, + { 0x1ce, "rbe" }, + { 0x1cf, "tbf" }, + + { 0x1d0, "p" }, + { 0x1d1, "psw.1" }, + { 0x1d2, "ov" }, + { 0x1d3, "rs0" }, + { 0x1d4, "rs1" }, + { 0x1d5, "f0" }, + { 0x1d6, "ac" }, + { 0x1d7, "cy" }, + + { 0x1d8, "ser" }, + { 0x1d9, "nr0" }, + { 0x1da, "nr1" }, + { 0x1db, "nr2" }, + { 0x1dc, "ses" }, + { 0x1dd, "ns0" }, + { 0x1de, "ns1" }, + { 0x1df, "ns2" }, + + { -1 } +}; + +const mcs51_disassembler::mem_info mcs51_disassembler::p8xc562_names[] = { + { 0xa8, "ien0" }, + { 0xa9, "cml0" }, + { 0xaa, "cml1" }, + { 0xab, "cml2" }, + { 0xac, "ctl0" }, + { 0xad, "ctl1" }, + { 0xae, "ctl2" }, + { 0xaf, "ctl3" }, + { 0xb8, "ip0" }, + { 0xc0, "p4" }, + { 0xc4, "p5" }, + { 0xc5, "adcon" }, + { 0xc6, "adch" }, + { 0xc8, "tm2ir" }, + { 0xc9, "cmh0" }, + { 0xca, "cmh1" }, + { 0xcb, "cmh2" }, + { 0xcc, "cth0" }, + { 0xcd, "cth1" }, + { 0xce, "cth2" }, + { 0xcf, "cth3" }, + { 0xe8, "ien1" }, + { 0xea, "tm2con" }, + { 0xeb, "ctcon" }, + { 0xec, "tml2" }, + { 0xed, "tmh2" }, + { 0xee, "ste" }, + { 0xef, "rte" }, + { 0xf8, "ip1" }, + { 0xfc, "pwm0" }, + { 0xfd, "pwm1" }, + { 0xfe, "pwmp" }, + { 0xff, "t3" }, + + { 0x190, "ct0i" }, + { 0x191, "ct1i" }, + { 0x192, "ct2i" }, + { 0x193, "ct3i" }, + { 0x194, "t2" }, + { 0x195, "rt2" }, + + { 0x1ae, "ead" }, + + { 0x1be, "pad" }, + + { 0x1c0, "cmsr0" }, + { 0x1c1, "cmsr1" }, + { 0x1c2, "cmsr2" }, + { 0x1c3, "cmsr3" }, + { 0x1c4, "cmsr4" }, + { 0x1c5, "cmsr5" }, + { 0x1c6, "cmt0" }, + { 0x1c7, "cmt1" }, + + { 0x1c8, "cti0" }, + { 0x1c9, "cti1" }, + { 0x1ca, "cti2" }, + { 0x1cb, "cti3" }, + { 0x1cc, "cmi0" }, + { 0x1cd, "cmi1" }, + { 0x1ce, "cmi2" }, + { 0x1cf, "t2ov" }, + + { 0x1e8, "ect0" }, + { 0x1e9, "ect1" }, + { 0x1ea, "ect2" }, + { 0x1eb, "ect3" }, + { 0x1ec, "ecm0" }, + { 0x1ed, "ecm1" }, + { 0x1ee, "ecm2" }, + { 0x1ef, "et2" }, + + { 0x1f8, "pct0" }, + { 0x1f9, "pct1" }, + { 0x1fa, "pct2" }, + { 0x1fb, "pct3" }, + { 0x1fc, "pcm0" }, + { 0x1fd, "pcm1" }, + { 0x1fe, "pcm2" }, + { 0x1ff, "pt2" }, + + { -1 } +}; + +const mcs51_disassembler::mem_info mcs51_disassembler::p8xc552_names[] = { + { 0x98, "s0con" }, + { 0x99, "s0buf" }, + { 0xd8, "s1con" }, + { 0xd9, "s1sta" }, + { 0xda, "s1dat" }, + { 0xdb, "s1adr" }, + + { 0x196, "scl" }, + { 0x197, "sda" }, + + { 0x1ac, "es0" }, + { 0x1ad, "es1" }, + + { 0x1bc, "ps0" }, + { 0x1bd, "ps1" }, + + { 0x1d8, "cr0" }, + { 0x1d9, "cr1" }, + { 0x1da, "aa" }, + { 0x1db, "si" }, + { 0x1dc, "sto" }, + { 0x1dd, "sta" }, + { 0x1de, "ens1" }, + { 0x1df, "cr2" }, + + { -1 } +}; + mcs51_disassembler::mcs51_disassembler() { } @@ -495,6 +886,7 @@ offs_t mcs51_disassembler::disassemble_op(std::ostream &stream, unsigned PC, off sym = get_bit_address(params.r8(PC++)); rel = params.r8(PC++); util::stream_format(stream, "jbc %s,$%04X", sym, PC + rel); + flags = STEP_COND; break; //ACALL code addr /* 1: aaa1 0001 */ @@ -557,6 +949,7 @@ offs_t mcs51_disassembler::disassemble_op(std::ostream &stream, unsigned PC, off sym = get_bit_address(params.r8(PC++)); rel = params.r8(PC++); util::stream_format(stream, "jb %s,$%04X", sym, (PC + rel)); + flags = STEP_COND; break; //RET @@ -605,6 +998,7 @@ offs_t mcs51_disassembler::disassemble_op(std::ostream &stream, unsigned PC, off sym = get_bit_address(params.r8(PC++)); rel = params.r8(PC++); util::stream_format(stream, "jnb %s,$%04X", sym, (PC + rel)); + flags = STEP_COND; break; //RETI @@ -651,6 +1045,7 @@ offs_t mcs51_disassembler::disassemble_op(std::ostream &stream, unsigned PC, off case 0x40: /* 1: 0100 0000 */ rel = params.r8(PC++); util::stream_format(stream, "jc $%04X", PC + rel); + flags = STEP_COND; break; //ORL data addr, A @@ -699,6 +1094,7 @@ offs_t mcs51_disassembler::disassemble_op(std::ostream &stream, unsigned PC, off case 0x50: /* 1: 0101 0000 */ rel = params.r8(PC++); util::stream_format(stream, "jnc $%04X", PC + rel); + flags = STEP_COND; break; //Unable to test @@ -749,6 +1145,7 @@ offs_t mcs51_disassembler::disassemble_op(std::ostream &stream, unsigned PC, off case 0x60: /* 1: 0110 0000 */ rel = params.r8(PC++); util::stream_format(stream, "jz $%04X", PC + rel); + flags = STEP_COND; break; //Unable to test @@ -798,6 +1195,7 @@ offs_t mcs51_disassembler::disassemble_op(std::ostream &stream, unsigned PC, off case 0x70: /* 1: 0111 0000 */ rel = params.r8(PC++); util::stream_format(stream, "jnz $%04X", PC + rel); + flags = STEP_COND; break; //Unable to test @@ -1013,6 +1411,7 @@ offs_t mcs51_disassembler::disassemble_op(std::ostream &stream, unsigned PC, off data = params.r8(PC++); rel = params.r8(PC++); util::stream_format(stream, "cjne a,#$%02X,$%04X", data, PC + rel); + flags = STEP_COND; break; //CJNE A, data addr, code addr @@ -1020,6 +1419,7 @@ offs_t mcs51_disassembler::disassemble_op(std::ostream &stream, unsigned PC, off sym = get_data_address(params.r8(PC++)); rel = params.r8(PC++); util::stream_format(stream, "cjne a,%s,$%04X", sym, PC + rel); + flags = STEP_COND; break; //Unable to test @@ -1029,6 +1429,7 @@ offs_t mcs51_disassembler::disassemble_op(std::ostream &stream, unsigned PC, off data = params.r8(PC++); rel = params.r8(PC++); util::stream_format(stream, "cjne @r%d,#$%02X,$%04X", op&1, data, PC + rel); + flags = STEP_COND; break; //CJNE R0 to R7, #data, code addr/* 1: 1011 1rrr */ @@ -1043,6 +1444,7 @@ offs_t mcs51_disassembler::disassemble_op(std::ostream &stream, unsigned PC, off data = params.r8(PC++); rel = params.r8(PC++); util::stream_format(stream, "cjne r%d,#$%02X,$%04X", op&7, data, PC + rel); + flags = STEP_COND; break; //PUSH data addr @@ -1119,7 +1521,7 @@ offs_t mcs51_disassembler::disassemble_op(std::ostream &stream, unsigned PC, off sym = get_data_address(params.r8(PC++)); rel = params.r8(PC++); util::stream_format(stream, "djnz %s,$%04X", sym, PC + rel); - flags = STEP_OVER; + flags = STEP_COND; break; //XCHD A, @R0/@R1 /* 1: 1101 011i */ @@ -1139,7 +1541,7 @@ offs_t mcs51_disassembler::disassemble_op(std::ostream &stream, unsigned PC, off case 0xdf: rel = params.r8(PC++); util::stream_format(stream, "djnz r%d,$%04X", op&7, (PC + rel)); - flags = STEP_OVER; + flags = STEP_COND; break; //MOVX A,@DPTR @@ -1243,7 +1645,7 @@ i8051_disassembler::i8051_disassembler() : mcs51_disassembler(default_names) { } -i8052_disassembler::i8052_disassembler() : mcs51_disassembler(default_names, i8052_names) +i8052_disassembler::i8052_disassembler() : mcs51_disassembler(i8052_names, default_names) { } @@ -1251,18 +1653,42 @@ i80c51_disassembler::i80c51_disassembler() : mcs51_disassembler(default_names) { } -i80c52_disassembler::i80c52_disassembler() : mcs51_disassembler(default_names, i8052_names, i80c52_names) +i80c52_disassembler::i80c52_disassembler() : mcs51_disassembler(i8052_names, i80c52_names, default_names) +{ +} + +i8xc51fx_disassembler::i8xc51fx_disassembler() : mcs51_disassembler(i8052_names, i80c52_names, i8xc51fx_names, default_names) +{ +} + +i8xc51gb_disassembler::i8xc51gb_disassembler() : mcs51_disassembler(i8052_names, i80c52_names, i8xc51fx_names, i8xc51gb_names, default_names) +{ +} + +ds5002fp_disassembler::ds5002fp_disassembler() : mcs51_disassembler(i8052_names, i80c52_names, ds5002fp_names, i8xc751_names, default_names) +{ +} + +ds80c320_disassembler::ds80c320_disassembler() : mcs51_disassembler(i8052_names, ds80c320_names, default_names) +{ +} + +sab80515_disassembler::sab80515_disassembler() : mcs51_disassembler(sab80515_names, default_names) +{ +} + +sab80c515_disassembler::sab80c515_disassembler() : mcs51_disassembler(sab80515_names, sab80c515_names, default_names) { } -i8xc51fx_disassembler::i8xc51fx_disassembler() : mcs51_disassembler(default_names, i8052_names, i80c52_names, i8xc51fx_names) +rupi44_disassembler::rupi44_disassembler() : mcs51_disassembler(rupi44_names) { } -i8xc51gb_disassembler::i8xc51gb_disassembler() : mcs51_disassembler(default_names, i8052_names, i80c52_names, i8xc51fx_names, i8xc51gb_names) +p8xc552_disassembler::p8xc552_disassembler() : mcs51_disassembler(p8xc562_names, p8xc552_names, default_names) { } -ds5002fp_disassembler::ds5002fp_disassembler() : mcs51_disassembler(default_names, i8052_names, i80c52_names, ds5002fp_names, i8xc751_names) +p8xc562_disassembler::p8xc562_disassembler() : mcs51_disassembler(p8xc562_names, default_names) { } |