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-rw-r--r--src/devices/cpu/i386/athlon.cpp54
-rw-r--r--src/devices/cpu/i386/athlon.h6
-rw-r--r--src/devices/cpu/i386/i386.cpp4
-rw-r--r--src/devices/cpu/i386/i386.h16
4 files changed, 43 insertions, 37 deletions
diff --git a/src/devices/cpu/i386/athlon.cpp b/src/devices/cpu/i386/athlon.cpp
index e47f99a2af6..7da09ef271b 100644
--- a/src/devices/cpu/i386/athlon.cpp
+++ b/src/devices/cpu/i386/athlon.cpp
@@ -28,10 +28,11 @@ void athlonxp_device::device_start()
{
i386_common_init();
register_state_i386_x87_xmm();
- m_data = &space(AS_DATA);
- m_opcodes = &space(AS_OPCODES);
- mmacache32 = m_data->cache<2, 0, ENDIANNESS_LITTLE>();
- m_opcodes->install_read_handler(0, 0xffffffff, read32_delegate(*this, FUNC(athlonxp_device::debug_read_memory)));
+ space(AS_DATA).specific(m_data);
+ space(AS_OPCODES).specific(m_opcodes);
+ space(AS_DATA).cache(mmacache32);
+
+ space(AS_OPCODES).install_read_handler(0, 0xffffffff, read32_delegate(*this, FUNC(athlonxp_device::debug_read_memory)));
build_x87_opcode_table();
build_opcode_table(OP_I386 | OP_FPU | OP_I486 | OP_PENTIUM | OP_PPRO | OP_MMX | OP_SSE);
@@ -192,7 +193,6 @@ READ32_MEMBER(athlonxp_device::debug_read_memory)
offs_t address = offset << 2;
int mode = check_cacheable(address);
bool nocache = false;
- address_space *m = m_program;
u8 *data;
if ((mode & 7) == 0)
@@ -207,8 +207,8 @@ READ32_MEMBER(athlonxp_device::debug_read_memory)
return *(u32 *)(data + offset);
}
if (address_mode<1>(address))
- m = m_data;
- return m->read_dword(address);
+ return m_data.read_dword(address);
+ return m_program->read_dword(address);
}
template <class dt, offs_t xorle>
@@ -216,7 +216,6 @@ dt athlonxp_device::opcode_read_cache(offs_t address)
{
int mode = check_cacheable(address);
bool nocache = false;
- memory_access_cache<2, 0, ENDIANNESS_LITTLE> *m = macache32;
u8 *data;
if ((mode & 7) == 0)
@@ -238,28 +237,35 @@ dt athlonxp_device::opcode_read_cache(offs_t address)
offs_t old_address = cache.old();
for (int w = 0; w < 64; w += 4)
- m->write_dword(old_address + w, *(u32 *)(data + w));
+ macache32.write_dword(old_address + w, *(u32 *)(data + w));
}
for (int r = 0; r < 64; r += 4)
- *(u32 *)(data + r) = m->read_dword(address + r);
+ *(u32 *)(data + r) = macache32.read_dword(address + r);
return *(dt *)(data + offset);
}
}
if (address_mode<1>(address))
- m = mmacache32;
+ {
+ if (sizeof(dt) == 1)
+ return mmacache32.read_byte(address);
+ else if (sizeof(dt) == 2)
+ return mmacache32.read_word(address);
+ else
+ return mmacache32.read_dword(address);
+ }
if (sizeof(dt) == 1)
- return m->read_byte(address);
+ return macache32.read_byte(address);
else if (sizeof(dt) == 2)
- return m->read_word(address);
+ return macache32.read_word(address);
else
- return m->read_dword(address);
+ return macache32.read_dword(address);
+
}
uint32_t athlonxp_device::program_read_cache(offs_t address, uint32_t mask)
{
int mode = check_cacheable(address);
bool nocache = false;
- address_space *m = m_program;
u8 *data;
if ((mode & 7) == 0)
@@ -281,23 +287,22 @@ uint32_t athlonxp_device::program_read_cache(offs_t address, uint32_t mask)
offs_t old_address = cache.old();
for (int w = 0; w < 64; w += 4)
- m->write_dword(old_address + w, *(u32 *)(data + w));
+ m_program->write_dword(old_address + w, *(u32 *)(data + w));
}
for (int r = 0; r < 64; r += 4)
- *(u32 *)(data + r) = m->read_dword(address + r);
+ *(u32 *)(data + r) = m_program->read_dword(address + r);
return *(u32 *)(data + offset) & mask;
}
}
if (address_mode<1>(address))
- m = m_data;
- return m->read_dword(address, mask) & mask;
+ return m_data.read_dword(address, mask) & mask;
+ return m_program->read_dword(address, mask) & mask;
}
void athlonxp_device::program_write_cache(offs_t address, uint32_t data, uint32_t mask)
{
int mode = check_cacheable(address);
bool nocache = false;
- address_space *m = m_program;
u8 *dataw;
if ((mode & 7) == 0)
@@ -322,17 +327,18 @@ void athlonxp_device::program_write_cache(offs_t address, uint32_t data, uint32_
offs_t old_address = cache.old();
for (int w = 0; w < 64; w += 4)
- m->write_dword(old_address + w, *(u32 *)(dataw + w));
+ m_program->write_dword(old_address + w, *(u32 *)(dataw + w));
}
for (int r = 0; r < 64; r += 4)
- *(u32 *)(dataw + r) = m->read_dword(address + r);
+ *(u32 *)(dataw + r) = m_program->read_dword(address + r);
*(u32 *)(dataw + offset) = (*(u32 *)(dataw + offset) & ~mask) | (data & mask);
return;
}
}
if (address_mode<0>(address))
- m = m_data;
- m->write_dword(address, data, mask);
+ m_data.write_dword(address, data, mask);
+ else
+ m_program->write_dword(address, data, mask);
}
void athlonxp_device::cache_writeback()
diff --git a/src/devices/cpu/i386/athlon.h b/src/devices/cpu/i386/athlon.h
index a4559fcb682..f7ee68ce962 100644
--- a/src/devices/cpu/i386/athlon.h
+++ b/src/devices/cpu/i386/athlon.h
@@ -55,10 +55,10 @@ private:
DECLARE_READ32_MEMBER(debug_read_memory);
address_space_config m_data_config;
- address_space *m_data;
address_space_config m_opcodes_config;
- address_space *m_opcodes;
- memory_access_cache<2, 0, ENDIANNESS_LITTLE> *mmacache32;
+ memory_access<32, 2, 0, ENDIANNESS_LITTLE>::cache mmacache32;
+ memory_access<32, 2, 0, ENDIANNESS_LITTLE>::specific m_opcodes;
+ memory_access<32, 2, 0, ENDIANNESS_LITTLE>::specific m_data;
uint8_t m_processor_name_string[48];
offs_t m_msr_top_mem;
uint64_t m_msr_sys_cfg;
diff --git a/src/devices/cpu/i386/i386.cpp b/src/devices/cpu/i386/i386.cpp
index 0d42c78ac26..e8fdf6a12ea 100644
--- a/src/devices/cpu/i386/i386.cpp
+++ b/src/devices/cpu/i386/i386.cpp
@@ -1937,9 +1937,9 @@ void i386_device::i386_common_init()
m_program = &space(AS_PROGRAM);
if(m_program->data_width() == 16) {
// for the 386sx
- macache16 = m_program->cache<1, 0, ENDIANNESS_LITTLE>();
+ m_program->cache(macache16);
} else {
- macache32 = m_program->cache<2, 0, ENDIANNESS_LITTLE>();
+ m_program->cache(macache32);
}
m_io = &space(AS_IO);
diff --git a/src/devices/cpu/i386/i386.h b/src/devices/cpu/i386/i386.h
index a251cab955f..64730816b66 100644
--- a/src/devices/cpu/i386/i386.h
+++ b/src/devices/cpu/i386/i386.h
@@ -89,9 +89,9 @@ protected:
virtual void cache_clean() {}
// routine to access memory
- virtual u8 mem_pr8(offs_t address) { return macache32->read_byte(address); }
- virtual u16 mem_pr16(offs_t address) { return macache32->read_word(address); }
- virtual u32 mem_pr32(offs_t address) { return macache32->read_dword(address); }
+ virtual u8 mem_pr8(offs_t address) { return macache32.read_byte(address); }
+ virtual u16 mem_pr16(offs_t address) { return macache32.read_word(address); }
+ virtual u32 mem_pr32(offs_t address) { return macache32.read_dword(address); }
address_space_config m_program_config;
address_space_config m_io_config;
@@ -307,8 +307,8 @@ protected:
address_space *m_program;
address_space *m_io;
uint32_t m_a20_mask;
- memory_access_cache<1, 0, ENDIANNESS_LITTLE> *macache16;
- memory_access_cache<2, 0, ENDIANNESS_LITTLE> *macache32;
+ memory_access<32, 1, 0, ENDIANNESS_LITTLE>::cache macache16;
+ memory_access<32, 2, 0, ENDIANNESS_LITTLE>::cache macache32;
int m_cpuid_max_input_value_eax; // Highest CPUID standard function available
uint32_t m_cpuid_id0, m_cpuid_id1, m_cpuid_id2;
@@ -1528,9 +1528,9 @@ public:
i386sx_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
- virtual u8 mem_pr8(offs_t address) override { return macache16->read_byte(address); };
- virtual u16 mem_pr16(offs_t address) override { return macache16->read_word(address); };
- virtual u32 mem_pr32(offs_t address) override { return macache16->read_dword(address); };
+ virtual u8 mem_pr8(offs_t address) override { return macache16.read_byte(address); };
+ virtual u16 mem_pr16(offs_t address) override { return macache16.read_word(address); };
+ virtual u32 mem_pr32(offs_t address) override { return macache16.read_dword(address); };
virtual uint16_t READ16PL(uint32_t ea, uint8_t privilege) override;
virtual uint32_t READ32PL(uint32_t ea, uint8_t privilege) override;