diff options
Diffstat (limited to 'src/devices/cpu/dspp')
-rw-r--r-- | src/devices/cpu/dspp/dspp.cpp | 185 | ||||
-rw-r--r-- | src/devices/cpu/dspp/dspp.h | 64 | ||||
-rw-r--r-- | src/devices/cpu/dspp/dsppdasm.h | 6 | ||||
-rw-r--r-- | src/devices/cpu/dspp/dsppdrc.cpp | 22 | ||||
-rw-r--r-- | src/devices/cpu/dspp/dsppfe.cpp | 5 | ||||
-rw-r--r-- | src/devices/cpu/dspp/dsppfe.h | 9 |
6 files changed, 137 insertions, 154 deletions
diff --git a/src/devices/cpu/dspp/dspp.cpp b/src/devices/cpu/dspp/dspp.cpp index f93f841717f..0a82905bec1 100644 --- a/src/devices/cpu/dspp/dspp.cpp +++ b/src/devices/cpu/dspp/dspp.cpp @@ -14,8 +14,6 @@ #include "dsppfe.h" #include "dsppdasm.h" -#include "debugger.h" - //************************************************************************** // CONSTANTS @@ -87,46 +85,44 @@ DEFINE_DEVICE_TYPE(DSPP, dspp_device, "dspp", "3DO DSPP") // dspp_device - constructor //------------------------------------------------- -dspp_device::dspp_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) - : dspp_device(mconfig, DSPP, tag, owner, clock, address_map_constructor(FUNC(dspp_device::code_map), this), - address_map_constructor(FUNC(dspp_device::data_map), this)) -{ -} - -dspp_device::dspp_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, address_map_constructor code_map_ctor, address_map_constructor data_map_ctor) - : cpu_device(mconfig, type, tag, owner, clock), - m_int_handler(*this), - m_dma_read_handler(*this), - m_dma_write_handler(*this), - m_code_config("code", ENDIANNESS_BIG, 16, 10, -1, code_map_ctor), - m_data_config("data", ENDIANNESS_BIG, 16, 10, -1, data_map_ctor), - m_code(nullptr), - m_data(nullptr), - m_output_fifo_start(0), - m_output_fifo_count(0), - m_dspx_reset(0), - m_dspx_int_enable(0), - m_dspx_channel_enable(0), - m_dspx_channel_complete(0), - m_dspx_channel_direction(0), - m_dspx_channel_8bit(0), - m_dspx_channel_sqxd(0), - m_dspx_shadow_current_addr(0), - m_dspx_shadow_current_count(0), - m_dspx_shadow_next_addr(0), - m_dspx_shadow_next_count(0), - m_dspx_dmanext_int(0), - m_dspx_dmanext_enable(0), - m_dspx_consumed_int(0), - m_dspx_consumed_enable(0), - m_dspx_underover_int(0), - m_dspx_underover_enable(0), - m_dspx_audio_time(0), - m_dspx_audio_duration(0), - m_cache(CACHE_SIZE), - m_drcuml(nullptr), - m_drcfe(nullptr), - m_drcoptions(0) +dspp_device::dspp_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : + dspp_device(mconfig, DSPP, tag, owner, clock, address_map_constructor(FUNC(dspp_device::code_map), this), + address_map_constructor(FUNC(dspp_device::data_map), this)) +{ +} + +dspp_device::dspp_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, address_map_constructor code_map_ctor, address_map_constructor data_map_ctor) : + cpu_device(mconfig, type, tag, owner, clock), + m_int_handler(*this), + m_dma_read_handler(*this, 0), + m_dma_write_handler(*this), + m_code_config("code", ENDIANNESS_BIG, 16, 10, -1, code_map_ctor), + m_data_config("data", ENDIANNESS_BIG, 16, 10, -1, data_map_ctor), + m_output_fifo_start(0), + m_output_fifo_count(0), + m_dspx_reset(0), + m_dspx_int_enable(0), + m_dspx_channel_enable(0), + m_dspx_channel_complete(0), + m_dspx_channel_direction(0), + m_dspx_channel_8bit(0), + m_dspx_channel_sqxd(0), + m_dspx_shadow_current_addr(0), + m_dspx_shadow_current_count(0), + m_dspx_shadow_next_addr(0), + m_dspx_shadow_next_count(0), + m_dspx_dmanext_int(0), + m_dspx_dmanext_enable(0), + m_dspx_consumed_int(0), + m_dspx_consumed_enable(0), + m_dspx_underover_int(0), + m_dspx_underover_enable(0), + m_dspx_audio_time(0), + m_dspx_audio_duration(0), + m_cache(CACHE_SIZE), + m_drcuml(nullptr), + m_drcfe(nullptr), + m_drcoptions(0) { #if 0 memset(m_core->m_stack, 0, sizeof(m_core->m_stack)); @@ -154,18 +150,10 @@ void dspp_device::device_start() m_drcfe = std::make_unique<dspp_frontend>(this, COMPILE_BACKWARDS_BYTES, COMPILE_FORWARDS_BYTES, SINGLE_INSTRUCTION_MODE ? 1 : COMPILE_MAX_SEQUENCE); - // Resolve our callbacks - m_int_handler.resolve_safe(); - m_dma_read_handler.resolve_safe(0); - m_dma_write_handler.resolve_safe(); - // Get our address spaces - m_code = &space(AS_PROGRAM); - m_data = &space(AS_DATA); - auto code_cache = m_code->cache<1, -1, ENDIANNESS_BIG>(); - m_code_cache = code_cache; - m_code16 = [code_cache](offs_t address) -> uint16_t { return code_cache->read_word(address); }; - m_codeptr = [code_cache](offs_t address) -> const void * { return code_cache->read_ptr(address); }; + space(AS_PROGRAM).cache(m_code_cache); + space(AS_PROGRAM).specific(m_code); + space(AS_DATA).specific(m_data); // Register our state for the debugger state_add(DSPP_PC, "PC", m_core->m_pc); @@ -174,7 +162,6 @@ void dspp_device::device_start() #if 0 state_add(STATE_GENFLAGS, "GENFLAGS", m_core->m_flags).callimport().callexport().formatstr("%6s").noshow(); state_add(STATE_GENPCBASE, "GENPCBASE", m_ppc).noshow(); - state_add(STATE_GENSP, "GENSP", m_src2val[REGBASE + 31]).noshow(); state_add(DSPP_PS, "PS", m_core->m_flagsio).callimport().callexport(); for (int regnum = 0; regnum < 32; regnum++) @@ -201,22 +188,19 @@ void dspp_device::device_start() save_item(NAME(m_output_fifo_start)); save_item(NAME(m_output_fifo_count)); - for (uint32_t i = 0; i < NUM_DMA_CHANNELS; ++i) - { - save_item(NAME(m_fifo_dma[i].m_current_addr), i); - save_item(NAME(m_fifo_dma[i].m_current_count), i); - save_item(NAME(m_fifo_dma[i].m_next_addr), i); - save_item(NAME(m_fifo_dma[i].m_next_count), i); - save_item(NAME(m_fifo_dma[i].m_prev_value), i); - save_item(NAME(m_fifo_dma[i].m_prev_current), i); - save_item(NAME(m_fifo_dma[i].m_go_forever), i); - save_item(NAME(m_fifo_dma[i].m_next_valid), i); - save_item(NAME(m_fifo_dma[i].m_reserved), i); - save_item(NAME(m_fifo_dma[i].m_fifo), i); - save_item(NAME(m_fifo_dma[i].m_dma_ptr), i); - save_item(NAME(m_fifo_dma[i].m_dspi_ptr), i); - save_item(NAME(m_fifo_dma[i].m_depth), i); - } + save_item(STRUCT_MEMBER(m_fifo_dma, m_current_addr)); + save_item(STRUCT_MEMBER(m_fifo_dma, m_current_count)); + save_item(STRUCT_MEMBER(m_fifo_dma, m_next_addr)); + save_item(STRUCT_MEMBER(m_fifo_dma, m_next_count)); + save_item(STRUCT_MEMBER(m_fifo_dma, m_prev_value)); + save_item(STRUCT_MEMBER(m_fifo_dma, m_prev_current)); + save_item(STRUCT_MEMBER(m_fifo_dma, m_go_forever)); + save_item(STRUCT_MEMBER(m_fifo_dma, m_next_valid)); + save_item(STRUCT_MEMBER(m_fifo_dma, m_reserved)); + save_item(STRUCT_MEMBER(m_fifo_dma, m_fifo)); + save_item(STRUCT_MEMBER(m_fifo_dma, m_dma_ptr)); + save_item(STRUCT_MEMBER(m_fifo_dma, m_dspi_ptr)); + save_item(STRUCT_MEMBER(m_fifo_dma, m_depth)); save_item(NAME(m_last_frame_clock)); save_item(NAME(m_last_osc_count)); @@ -372,7 +356,7 @@ inline void dspp_device::update_ticks() uint16_t dspp_device::read_op(offs_t pc) { - return m_code_cache->read_word(pc); + return m_code_cache.read_word(pc); } @@ -382,7 +366,7 @@ uint16_t dspp_device::read_op(offs_t pc) inline uint16_t dspp_device::read_data(offs_t addr) { - return m_data->read_word(addr); + return m_data.read_word(addr); } @@ -392,7 +376,7 @@ inline uint16_t dspp_device::read_data(offs_t addr) inline void dspp_device::write_data(offs_t addr, uint16_t data) { - m_data->write_word(addr, data); + m_data.write_word(addr, data); } @@ -621,10 +605,11 @@ inline void dspp_device::set_rbase(uint32_t base, uint32_t addr) case 0: m_core->m_rbase[0] = addr; m_core->m_rbase[1] = addr + 4 - base; + [[fallthrough]]; // Intentional fall-through case 8: m_core->m_rbase[2] = addr + 8 - base; - + [[fallthrough]]; case 12: m_core->m_rbase[3] = addr + 12 - base; break; @@ -653,7 +638,7 @@ inline uint16_t dspp_device::translate_reg(uint16_t reg) // cycles it takes for one instruction to execute //------------------------------------------------- -uint32_t dspp_device::execute_min_cycles() const +uint32_t dspp_device::execute_min_cycles() const noexcept { return 1; } @@ -664,7 +649,7 @@ uint32_t dspp_device::execute_min_cycles() const // cycles it takes for one instruction to execute //------------------------------------------------- -uint32_t dspp_device::execute_max_cycles() const +uint32_t dspp_device::execute_max_cycles() const noexcept { return 5; // TODO ? } @@ -694,7 +679,7 @@ void dspp_device::execute_run() return; } - bool check_debugger = ((device_t::machine().debug_flags & DEBUG_FLAG_ENABLED) != 0); + const bool check_debugger = debugger_enabled(); do { @@ -1595,7 +1580,7 @@ void dspp_device::update_fifo_dma() while (mask != 0) { - uint32_t channel = 31 - count_leading_zeros(mask); + uint32_t channel = 31 - count_leading_zeros_32(mask); const fifo_dma & dma = m_fifo_dma[channel]; @@ -1646,7 +1631,7 @@ void dspp_device::reset_channel(int32_t channel) // input_r - Read digital input //------------------------------------------------- -READ16_MEMBER( dspp_device::input_r ) +uint16_t dspp_device::input_r() { // TODO return 0; @@ -1657,7 +1642,7 @@ READ16_MEMBER( dspp_device::input_r ) // output_w - Write to the 8 output registers //------------------------------------------------- -WRITE16_MEMBER( dspp_device::output_w ) +void dspp_device::output_w(offs_t offset, uint16_t data) { m_outputs[offset] = data; } @@ -1667,7 +1652,7 @@ WRITE16_MEMBER( dspp_device::output_w ) // fifo_osc_r - //------------------------------------------------- -READ16_MEMBER( dspp_device::fifo_osc_r ) +uint16_t dspp_device::fifo_osc_r(offs_t offset) { uint32_t data = 0; uint32_t channel = offset / 8; @@ -1737,7 +1722,7 @@ READ16_MEMBER( dspp_device::fifo_osc_r ) // fifo_osc_w - //------------------------------------------------- -WRITE16_MEMBER( dspp_device::fifo_osc_w ) +void dspp_device::fifo_osc_w(offs_t offset, uint16_t data) { uint32_t channel = offset / 8; @@ -1793,7 +1778,7 @@ WRITE16_MEMBER( dspp_device::fifo_osc_w ) // input_control_w - //------------------------------------------------- -WRITE16_MEMBER( dspp_device::input_control_w ) +void dspp_device::input_control_w(uint16_t data) { // TODO } @@ -1803,7 +1788,7 @@ WRITE16_MEMBER( dspp_device::input_control_w ) // output_control_w - //------------------------------------------------- -WRITE16_MEMBER( dspp_device::output_control_w ) +void dspp_device::output_control_w(uint16_t data) { // TODO if (data & 1) @@ -1840,7 +1825,7 @@ WRITE16_MEMBER( dspp_device::output_control_w ) // input_status_r - Read input state //------------------------------------------------- -READ16_MEMBER( dspp_device::input_status_r ) +uint16_t dspp_device::input_status_r() { // TODO: How should this work? return 1; @@ -1852,7 +1837,7 @@ READ16_MEMBER( dspp_device::input_status_r ) // entries in the output FIFO //------------------------------------------------- -READ16_MEMBER( dspp_device::output_status_r ) +uint16_t dspp_device::output_status_r() { return m_output_fifo_count; } @@ -1862,7 +1847,7 @@ READ16_MEMBER( dspp_device::output_status_r ) // cpu_int_w - Host CPU soft interrupt //------------------------------------------------- -WRITE16_MEMBER( dspp_device::cpu_int_w ) +void dspp_device::cpu_int_w(uint16_t data) { m_core->m_partial_int |= (data << DSPX_FLD_INT_SOFT_SHIFT) & DSPX_FLD_INT_SOFT_MASK; update_host_interrupt(); @@ -1873,7 +1858,7 @@ WRITE16_MEMBER( dspp_device::cpu_int_w ) // pc_r - Read program counter //------------------------------------------------- -READ16_MEMBER( dspp_device::pc_r ) +uint16_t dspp_device::pc_r() { return m_core->m_pc; } @@ -1883,7 +1868,7 @@ READ16_MEMBER( dspp_device::pc_r ) // pc_w - Write program counter //------------------------------------------------- -WRITE16_MEMBER(dspp_device:: pc_w ) +void dspp_device::pc_w(uint16_t data) { m_core->m_pc = data; } @@ -1893,7 +1878,7 @@ WRITE16_MEMBER(dspp_device:: pc_w ) // audlock_r - Read Audio Lock status //------------------------------------------------- -READ16_MEMBER( dspp_device::audlock_r ) +uint16_t dspp_device::audlock_r() { return m_core->m_flag_audlock; } @@ -1903,7 +1888,7 @@ READ16_MEMBER( dspp_device::audlock_r ) // audlock_w - Write Audio Lock status //------------------------------------------------- -WRITE16_MEMBER( dspp_device::audlock_w ) +void dspp_device::audlock_w(uint16_t data) { m_core->m_flag_audlock = data & 1; } @@ -1913,7 +1898,7 @@ WRITE16_MEMBER( dspp_device::audlock_w ) // clock_r - Read CPU tick counter //------------------------------------------------- -READ16_MEMBER( dspp_device::clock_r ) +uint16_t dspp_device::clock_r() { return m_core->m_tclock; } @@ -1923,7 +1908,7 @@ READ16_MEMBER( dspp_device::clock_r ) // clock_w - Write CPU tick counter //------------------------------------------------- -WRITE16_MEMBER( dspp_device::clock_w ) +void dspp_device::clock_w(uint16_t data) { m_core->m_tclock = data; } @@ -1933,7 +1918,7 @@ WRITE16_MEMBER( dspp_device::clock_w ) // noise_r - PRNG noise //------------------------------------------------- -READ16_MEMBER( dspp_device::noise_r ) +uint16_t dspp_device::noise_r() { // TODO: Obviously this isn't accurate return machine().rand(); @@ -2342,17 +2327,17 @@ void dspp_device::write_ext_control(offs_t offset, uint32_t data) // read - host CPU read from DSPP internals //------------------------------------------------- -READ32_MEMBER( dspp_device::read ) +uint32_t dspp_device::read(offs_t offset) { if (offset < 0x1000/4) { // 16-bit code memory - return m_code->read_word(offset); + return m_code.read_word(offset); } else if (offset >= 0x1000/4 && offset < 0x2000/4) { // 16-bit data memory and registers - return m_data->read_word((offset - 0x1000/4)); + return m_data.read_word((offset - 0x1000/4)); } else if(offset >= 0x5000/4 && offset < 0x6000/4) { @@ -2503,17 +2488,17 @@ void dspp_device::write_dma_stack(offs_t offset, uint32_t data) // write - host CPU write to DSPP internals //------------------------------------------------- -WRITE32_MEMBER( dspp_device::write ) +void dspp_device::write(offs_t offset, uint32_t data) { if (offset < 0x1000/4) { // 16-bit code memory - m_code->write_word(offset, data); + m_code.write_word(offset, data); } else if (offset >= 0x1000/4 && offset < 0x2000/4) { // 16-bit data memory and registers - m_data->write_word((offset - 0x1000/4), data); + m_data.write_word((offset - 0x1000/4), data); } else if(offset >= 0x5000/4 && offset < 0x6000/4) { diff --git a/src/devices/cpu/dspp/dspp.h b/src/devices/cpu/dspp/dspp.h index 302d141db13..13dc682b01f 100644 --- a/src/devices/cpu/dspp/dspp.h +++ b/src/devices/cpu/dspp/dspp.h @@ -8,10 +8,10 @@ ***************************************************************************/ -#pragma once +#ifndef MAME_CPU_DSPP_DSPP_H +#define MAME_CPU_DSPP_DSPP_H -#ifndef DEVICES_CPU_DSPP_DSPP_H -#define DEVICES_CPU_DSPP_DSPP_H +#pragma once #include "cpu/drcfe.h" #include "cpu/drcuml.h" @@ -41,30 +41,30 @@ public: auto dma_write_handler() { return m_dma_write_handler.bind(); } // Public interfaces - DECLARE_READ32_MEMBER( read ); - DECLARE_WRITE32_MEMBER( write ); + uint32_t read(offs_t offset); + void write(offs_t offset, uint32_t data); uint16_t read_output_fifo(); void dump_state(); // TODO: DEBUG REMOVE ME // Internal registers - DECLARE_READ16_MEMBER( input_r ); - DECLARE_WRITE16_MEMBER( output_w ); - DECLARE_READ16_MEMBER( fifo_osc_r ); - DECLARE_WRITE16_MEMBER( fifo_osc_w ); - DECLARE_WRITE16_MEMBER( input_control_w ); - DECLARE_WRITE16_MEMBER( output_control_w ); - DECLARE_READ16_MEMBER( input_status_r ); - DECLARE_READ16_MEMBER( output_status_r ); - DECLARE_WRITE16_MEMBER( cpu_int_w ); - DECLARE_READ16_MEMBER( pc_r ); - DECLARE_WRITE16_MEMBER( pc_w ); - DECLARE_READ16_MEMBER( audlock_r ); - DECLARE_WRITE16_MEMBER( audlock_w ); - DECLARE_READ16_MEMBER( clock_r ); - DECLARE_WRITE16_MEMBER( clock_w ); - DECLARE_READ16_MEMBER( noise_r ); + uint16_t input_r(); + void output_w(offs_t offset, uint16_t data); + uint16_t fifo_osc_r(offs_t offset); + void fifo_osc_w(offs_t offset, uint16_t data); + void input_control_w(uint16_t data); + void output_control_w(uint16_t data); + uint16_t input_status_r(); + uint16_t output_status_r(); + void cpu_int_w(uint16_t data); + uint16_t pc_r(); + void pc_w(uint16_t data); + uint16_t audlock_r(); + void audlock_w(uint16_t data); + uint16_t clock_r(); + void clock_w(uint16_t data); + uint16_t noise_r(); void update_fifo_dma(); void print_sums() { printf("%04x: %04x\n", (uint16_t)m_core->m_arg0, (uint16_t)m_core->m_arg1); } @@ -74,12 +74,12 @@ public: protected: // device-level overrides - virtual void device_start() override; - virtual void device_reset() override; + virtual void device_start() override ATTR_COLD; + virtual void device_reset() override ATTR_COLD; // device_execute_interface overrides - virtual uint32_t execute_min_cycles() const override; - virtual uint32_t execute_max_cycles() const override; + virtual uint32_t execute_min_cycles() const noexcept override; + virtual uint32_t execute_max_cycles() const noexcept override; virtual void execute_run() override; // device_memory_interface overrides @@ -93,8 +93,8 @@ protected: // device_disasm_interface overrides virtual std::unique_ptr<util::disasm_interface> create_disassembler() override; - void code_map(address_map &map); - void data_map(address_map &map); + void code_map(address_map &map) ATTR_COLD; + void data_map(address_map &map) ATTR_COLD; enum { @@ -199,11 +199,9 @@ private: // Address spaces const address_space_config m_code_config; const address_space_config m_data_config; - address_space * m_code; - address_space * m_data; - memory_access_cache<1, -1, ENDIANNESS_BIG> *m_code_cache; - std::function<uint16_t (offs_t)> m_code16; - std::function<const void * (offs_t)> m_codeptr; + memory_access<10, 1, -1, ENDIANNESS_BIG>::cache m_code_cache; + memory_access<10, 1, -1, ENDIANNESS_BIG>::specific m_code; + memory_access<10, 1, -1, ENDIANNESS_BIG>::specific m_data; struct dspp_internal_state { @@ -392,4 +390,4 @@ public: // TODO DECLARE_DEVICE_TYPE(DSPP, dspp_device); -#endif // DEVICES_CPU_DSPP_DSPP_H +#endif // MAME_CPU_DSPP_DSPP_H diff --git a/src/devices/cpu/dspp/dsppdasm.h b/src/devices/cpu/dspp/dsppdasm.h index 0ceae9b117b..538f0a96c0e 100644 --- a/src/devices/cpu/dspp/dsppdasm.h +++ b/src/devices/cpu/dspp/dsppdasm.h @@ -4,8 +4,8 @@ DSPP disassembler shim */ -#ifndef DEVICES_CPU_DSPP_DSPPDASM_H -#define DEVICES_CPU_DSPP_DSPPDASM_H +#ifndef MAME_CPU_DSPP_DSPPDASM_H +#define MAME_CPU_DSPP_DSPPDASM_H #pragma once @@ -19,4 +19,4 @@ public: virtual offs_t disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer ¶ms) override; }; -#endif // DEVICES_CPU_DSPP_DSPPDASM_H +#endif // MAME_CPU_DSPP_DSPPDASM_H diff --git a/src/devices/cpu/dspp/dsppdrc.cpp b/src/devices/cpu/dspp/dsppdrc.cpp index 68b0c3cb741..a010133cce9 100644 --- a/src/devices/cpu/dspp/dsppdrc.cpp +++ b/src/devices/cpu/dspp/dsppdrc.cpp @@ -8,7 +8,6 @@ ******************************************************************************/ #include "emu.h" -#include "debugger.h" #include "dspp.h" #include "dsppfe.h" #include "cpu/drcfe.h" @@ -94,7 +93,7 @@ registers inline void dspp_device::load_fast_iregs(drcuml_block &block) { #if 0 // TODO - for (uint32_t regnum = 0; regnum < ARRAY_LENGTH(m_regmap); regnum++) + for (uint32_t regnum = 0; regnum < std::size(m_regmap); regnum++) { if (m_regmap[regnum].is_int_register()) { @@ -115,7 +114,7 @@ void dspp_device::save_fast_iregs(drcuml_block &block) #if 0 // TODO int regnum; - for (regnum = 0; regnum < ARRAY_LENGTH(m_regmap); regnum++) + for (regnum = 0; regnum < std::size(m_regmap); regnum++) { if (m_regmap[regnum].is_int_register()) { @@ -188,7 +187,7 @@ void dspp_device::compile_block(offs_t pc) const opcode_desc *seqhead, *seqlast; int override = false; - g_profiler.start(PROFILER_DRC_COMPILE); + auto profile = g_profiler.start(PROFILER_DRC_COMPILE); /* get a description of this sequence */ const opcode_desc *desclist = m_drcfe->describe_code(pc); @@ -269,7 +268,6 @@ void dspp_device::compile_block(offs_t pc) /* end the sequence */ block.end(); - g_profiler.stop(); succeeded = true; } catch (drcuml_block::abort_compilation &) @@ -292,7 +290,7 @@ void dspp_device::generate_checksum_block(drcuml_block &block, compiler_state *c { uint32_t sum = seqhead->opptr.w[0]; uint32_t addr = seqhead->physpc; - const void *base = m_codeptr(addr); + const void *base = m_code_cache.read_ptr(addr); UML_MOV(block, I0, 0); UML_LOAD(block, I0, base, 0, SIZE_WORD, SCALE_x2); // load i0,base,0,word @@ -306,14 +304,14 @@ void dspp_device::generate_checksum_block(drcuml_block &block, compiler_state *c { uint32_t sum = 0; uint32_t addr = seqhead->physpc; - const void *base = m_codeptr(addr); + const void *base = m_code_cache.read_ptr(addr); UML_LOAD(block, I0, base, 0, SIZE_WORD, SCALE_x2); // load i0,base,0,dword sum += seqhead->opptr.w[0]; for (curdesc = seqhead->next(); curdesc != seqlast->next(); curdesc = curdesc->next()) if (!(curdesc->flags & OPFLAG_VIRTUAL_NOOP)) { addr = curdesc->physpc; - base = m_codeptr(addr); + base = m_code_cache.read_ptr(addr); assert(base != nullptr); UML_LOAD(block, I1, base, 0, SIZE_WORD, SCALE_x2); // load i1,base,dword UML_ADD(block, I0, I0, I1); // add i0,i0,i1 @@ -411,7 +409,7 @@ void dspp_device::generate_sequence_instruction(drcuml_block &block, compiler_st UML_MAPVAR(block, MAPVAR_CYCLES, compiler->cycles); // mapvar CYCLES,compiler->cycles /* if we are debugging, call the debugger */ - if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0) + if (debugger_enabled()) { UML_MOV(block, mem(&m_core->m_pc), desc->pc); // mov [pc],desc->pc //save_fast_iregs(block); // <save fastregs> @@ -501,10 +499,10 @@ void dspp_device::generate_set_rbase(drcuml_block &block, compiler_state *compil case 0: UML_MOV(block, mem(&m_core->m_rbase[0]), addr); UML_MOV(block, mem(&m_core->m_rbase[1]), addr + 4 - base); - // Intentional fall-through + [[fallthrough]]; case 8: UML_MOV(block, mem(&m_core->m_rbase[2]), addr + 8 - base); - // Intentional fall-through + [[fallthrough]]; case 12: UML_MOV(block, mem(&m_core->m_rbase[3]), addr + 12 - base); break; @@ -830,7 +828,7 @@ void dspp_device::generate_parse_operands(drcuml_block &block, compiler_state *c uint32_t opoffset = 1; while (opidx < numops) { - operand = m_code16(desc->pc + opoffset); + operand = m_code_cache.read_word(desc->pc + opoffset); opoffset++; if (operand & 0x8000) diff --git a/src/devices/cpu/dspp/dsppfe.cpp b/src/devices/cpu/dspp/dsppfe.cpp index 4f29ad08c0e..19b2cb1a3b8 100644 --- a/src/devices/cpu/dspp/dsppfe.cpp +++ b/src/devices/cpu/dspp/dsppfe.cpp @@ -86,13 +86,14 @@ bool dspp_frontend::describe(opcode_desc &desc, const opcode_desc *prev) { case 0: describe_special(op, desc); - + break; case 1: case 2: describe_branch(op, desc); - + break; case 3: describe_complex_branch(op, desc); + break; } } else diff --git a/src/devices/cpu/dspp/dsppfe.h b/src/devices/cpu/dspp/dsppfe.h index b3eb5cb0d4d..5c0023e313a 100644 --- a/src/devices/cpu/dspp/dsppfe.h +++ b/src/devices/cpu/dspp/dsppfe.h @@ -8,8 +8,10 @@ ***************************************************************************/ -#ifndef DEVICES_CPU_DSPP_DSPPFE_H -#define DEVICES_CPU_DSPP_DSPPFE_H +#ifndef MAME_CPU_DSPP_DSPPFE_H +#define MAME_CPU_DSPP_DSPPFE_H + +#pragma once #include "dspp.h" #include "cpu/drcfe.h" @@ -69,5 +71,4 @@ private: dspp_device *m_dspp; }; - -#endif /* DEVICES_CPU_DSPP_DSPPFE_H */ +#endif // MAME_CPU_DSPP_DSPPFE_H |