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Diffstat (limited to 'src/devices/cpu/dsp56156/dsp56pcu.h')
-rw-r--r--src/devices/cpu/dsp56156/dsp56pcu.h19
1 files changed, 11 insertions, 8 deletions
diff --git a/src/devices/cpu/dsp56156/dsp56pcu.h b/src/devices/cpu/dsp56156/dsp56pcu.h
index a04f7bf1f26..06d57689eb6 100644
--- a/src/devices/cpu/dsp56156/dsp56pcu.h
+++ b/src/devices/cpu/dsp56156/dsp56pcu.h
@@ -1,18 +1,21 @@
// license:BSD-3-Clause
// copyright-holders:Andrew Gardner
-#ifndef DSP56156_PCU_H
-#define DSP56156_PCU_H
+#ifndef MAME_CPU_DSP56156_DSP56PCU_H
+#define MAME_CPU_DSP56156_DSP56PCU_H
+
+#pragma once
#include "dsp56156.h"
-namespace DSP_56156
-{
+namespace DSP_56156 {
+
/***************************************************************************
PCU
***************************************************************************/
void pcu_reset(dsp56156_core* cpustate);
void pcu_init(dsp56156_core* cpustate, device_t *device);
#define PC (cpustate->PCU.pc)
+#define IPC (cpustate->PCU.ipc)
#define LA (cpustate->PCU.la)
#define LC (cpustate->PCU.lc)
#define SR (cpustate->PCU.sr)
@@ -103,7 +106,7 @@ void C_bit_set(dsp56156_core* cpustate, uint8_t value);
/* 1-28 OPERATING MODE REGISTER (OMR) BITS */
//uint8_t CD_bit(const dsp56156_core* cpustate);
//uint8_t SD_bit(const dsp56156_core* cpustate);
-//uint8_t R_bit(const dsp56156_core* cpustate);
+uint8_t R_bit(const dsp56156_core* cpustate);
//uint8_t SA_bit(const dsp56156_core* cpustate);
//uint8_t MC_bit(const dsp56156_core* cpustate);
uint8_t MB_bit(const dsp56156_core* cpustate);
@@ -121,8 +124,8 @@ void MA_bit_set(dsp56156_core* cpustate, uint8_t value);
uint8_t UF_bit(const dsp56156_core* cpustate);
uint8_t SE_bit(const dsp56156_core* cpustate);
-//void UF_bit_set(dsp56156_core* cpustate, uint8_t value) {};
-//void SE_bit_set(dsp56156_core* cpustate, uint8_t value) {};
+//void UF_bit_set(dsp56156_core* cpustate, uint8_t value) {}
+//void SE_bit_set(dsp56156_core* cpustate, uint8_t value) {}
// HACK - Bootstrap modes
@@ -147,4 +150,4 @@ int8_t dsp56156_get_irq_priority(dsp56156_core* cpustate, int index);
} // namespace DSP_56156
-#endif
+#endif // MAME_CPU_DSP56156_DSP56PCU_H