diff options
Diffstat (limited to 'src/devices/cpu/adsp2100/adsp2100.cpp')
-rw-r--r-- | src/devices/cpu/adsp2100/adsp2100.cpp | 390 |
1 files changed, 199 insertions, 191 deletions
diff --git a/src/devices/cpu/adsp2100/adsp2100.cpp b/src/devices/cpu/adsp2100/adsp2100.cpp index ff08e96b72b..817cd2c6bea 100644 --- a/src/devices/cpu/adsp2100/adsp2100.cpp +++ b/src/devices/cpu/adsp2100/adsp2100.cpp @@ -2,7 +2,7 @@ // copyright-holders:Aaron Giles /*************************************************************************** - ADSP2100.c + adsp2100.cpp ADSP-21xx series emulator. @@ -61,8 +61,8 @@ Program Space: Program Space: 0000-01ff = 512 Internal RAM (booted) 0000-37ff = 14k External access - 0400-07ff = 1k Reserved 3800-3bff = 1k Internal RAM - 0800-3fff = 14k External access 3c00-3fff = 1k Reserved + 0200-07ff = 1.5k Reserved 3800-39ff = 512 Internal RAM + 0800-3fff = 14k External access 3a00-3fff = 1.5k Reserved Data Space: Data Space: 0000-03ff = 1k External DWAIT0 0000-03ff = 1k External DWAIT0 @@ -71,7 +71,7 @@ 3000-33ff = 1k External DWAIT3 3000-33ff = 1k External DWAIT3 3400-37ff = 1k External DWAIT4 3400-37ff = 1k External DWAIT4 3800-38ff = 256 Internal RAM 3800-38ff = 256 Internal RAM - 3a00-3bff = 512 Reserved 3a00-3bff = 512 Reserved + 3900-3bff = 768 Reserved 3900-3bff = 768 Reserved 3c00-3fff = 1k Internal Control regs 3c00-3fff = 1k Internal Control regs @@ -80,12 +80,16 @@ MMAP = 0 MMAP = 1 + Auto boot loading via BDMA or IDMA No auto boot loading + Program Space: Program Space: 0000-1fff = 8k Internal RAM 0000-1fff = 8k External access - 2000-3fff = 8k Internal RAM or Overlay 2000-3fff = 8k Internal + 2000-3fff = 8k Internal RAM (PMOVLAY = 0) 2000-3fff = 8k Internal (PMOVLAY = 0) + 2000-3fff = 8k External (PMOVLAY = 1,2) Data Space: Data Space: - 0000-1fff = 8k Internal RAM or Overlay 0000-1fff = 8k Internal RAM or Overlay + 0000-1fff = 8k Internal RAM (DMOVLAY = 0) 0000-1fff = 8k Internal RAM (DMOVLAY = 0) + 0000-1fff = 8k External (DMOVLAY = 1,2) 0000-1fff = 8k External (DMOVLAY = 1,2) 2000-3fdf = 8k-32 Internal RAM 2000-3fdf = 8k-32 Internal RAM 3fe0-3fff = 32 Internal Control regs 3fe0-3fff = 32 Internal Control regs @@ -95,10 +99,13 @@ 0400-05ff = 512 External IOWAIT2 0400-05ff = 512 External IOWAIT2 0600-07ff = 512 External IOWAIT3 0600-07ff = 512 External IOWAIT3 + TODO: + - Move internal stuffs into CPU core file (on-chip RAM, control registers, etc) + - Support variable internal memory mappings + ***************************************************************************/ #include "emu.h" -#include "debugger.h" #include "adsp2100.h" #include "2100dasm.h" @@ -137,6 +144,8 @@ adsp21xx_device::adsp21xx_device(const machine_config &mconfig, device_type type m_astat_clear(0), m_idle(0), m_px(0), + m_pmovlay(0), + m_dmovlay(0), m_pc_sp(0), m_cntr_sp(0), m_stat_sp(0), @@ -156,7 +165,7 @@ adsp21xx_device::adsp21xx_device(const machine_config &mconfig, device_type type m_mstat_mask((m_chip_type >= CHIP_TYPE_ADSP2101) ? 0x7f : 0x0f), m_imask_mask((m_chip_type >= CHIP_TYPE_ADSP2181) ? 0x3ff : (m_chip_type >= CHIP_TYPE_ADSP2101) ? 0x3f : 0x0f), - m_sport_rx_cb(*this), + m_sport_rx_cb(*this, 0), m_sport_tx_cb(*this), m_timer_fired_cb(*this), m_dmovlay_cb(*this) @@ -275,7 +284,7 @@ adsp2115_device::adsp2115_device(const machine_config &mconfig, const char *tag, adsp2181_device::adsp2181_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : adsp21xx_device(mconfig, ADSP2181, tag, owner, clock, CHIP_TYPE_ADSP2181) - , m_io_config("I/O", ENDIANNESS_LITTLE, 16, 11, -1) + , m_io_config("io", ENDIANNESS_LITTLE, 16, 11, -1) { } @@ -411,16 +420,12 @@ uint16_t adsp2181_device::idma_data_r() void adsp21xx_device::device_start() { - m_sport_rx_cb.resolve(); - m_sport_tx_cb.resolve(); - m_timer_fired_cb.resolve(); - m_dmovlay_cb.resolve(); - // get our address spaces - m_program = &space(AS_PROGRAM); - m_cache = m_program->cache<2, -2, ENDIANNESS_LITTLE>(); - m_data = &space(AS_DATA); - m_io = has_space(AS_IO) ? &space(AS_IO) : nullptr; + space(AS_PROGRAM).cache(m_cache); + space(AS_PROGRAM).specific(m_program); + space(AS_DATA).specific(m_data); + if(has_space(AS_IO)) + space(AS_IO).specific(m_io); // "core" save_item(NAME(m_core.ax0.u)); @@ -466,6 +471,8 @@ void adsp21xx_device::device_start() save_item(NAME(m_lmask)); save_item(NAME(m_base)); save_item(NAME(m_px)); + save_item(NAME(m_pmovlay)); + save_item(NAME(m_dmovlay)); save_item(NAME(m_pc)); save_item(NAME(m_ppc)); @@ -569,7 +576,6 @@ void adsp21xx_device::device_start() state_add(ADSP2100_MSTAT, "MSTAT", m_mstat).mask((m_chip_type == CHIP_TYPE_ADSP2100) ? 0x0f : 0x7f).callimport(); state_add(ADSP2100_PCSP, "PCSP", m_pc_sp).mask(0xff); - state_add(STATE_GENSP, "CURSP", m_pc_sp).mask(0xff).noshow(); state_add(ADSP2100_CNTRSP, "CNTRSP", m_cntr_sp).mask(0xf); state_add(ADSP2100_STATSP, "STATSP", m_stat_sp).mask(0xf); state_add(ADSP2100_LOOPSP, "LOOPSP", m_loop_sp).mask(0xf); @@ -587,6 +593,12 @@ void adsp21xx_device::device_start() state_add(ADSP2100_FL1, "FL1", m_fl1).mask(1); state_add(ADSP2100_FL2, "FL2", m_fl2).mask(1); + if (m_chip_type == CHIP_TYPE_ADSP2181) + { + state_add(ADSP2100_PMOVLAY, "PMOVLAY", m_pmovlay); + state_add(ADSP2100_DMOVLAY, "DMOVLAY", m_dmovlay); + } + // set our instruction counter set_icountptr(m_icount); } @@ -611,6 +623,14 @@ void adsp21xx_device::device_reset() write_reg2(0x0a, m_l[6]); write_reg2(0x02, m_i[6]); write_reg2(0x0b, m_l[7]); write_reg2(0x03, m_i[7]); + // reset overlays + if (m_chip_type == CHIP_TYPE_ADSP2181) + { + m_pmovlay = m_dmovlay = 0; + // PMOVLAY + update_dmovlay(); + } + // reset PC and loops m_pc = (m_chip_type >= CHIP_TYPE_ADSP2101) ? 0 : 4; m_ppc = m_pc; @@ -645,6 +665,21 @@ void adsp21xx_device::device_reset() //------------------------------------------------- +// device_post_load - called after loading a saved state +//------------------------------------------------- + +void adsp21xx_device::device_post_load() +{ + // update overlays + if (m_chip_type == CHIP_TYPE_ADSP2181) + { + // PMOVLAY + update_dmovlay(); + } +} + + +//------------------------------------------------- // memory_space_config - return the configuration // of the specified address space, or nullptr if // the space doesn't exist @@ -728,6 +763,11 @@ void adsp21xx_device::state_import(const device_state_entry &entry) update_l(entry.index() - ADSP2100_L0); break; + // PMOVLAY + case ADSP2100_DMOVLAY: + update_dmovlay(); + break; + default: fatalerror("CPU_IMPORT_STATE(adsp21xx) called for unexpected value\n"); } @@ -776,37 +816,37 @@ std::unique_ptr<util::disasm_interface> adsp21xx_device::create_disassembler() inline uint16_t adsp21xx_device::data_read(uint32_t addr) { - return m_data->read_word(addr); + return m_data.read_word(addr); } inline void adsp21xx_device::data_write(uint32_t addr, uint16_t data) { - m_data->write_word(addr, data); + m_data.write_word(addr, data); } inline uint16_t adsp21xx_device::io_read(uint32_t addr) { - return m_io->read_word(addr); + return m_io.read_word(addr); } inline void adsp21xx_device::io_write(uint32_t addr, uint16_t data) { - m_io->write_word(addr, data); + m_io.write_word(addr, data); } inline uint32_t adsp21xx_device::program_read(uint32_t addr) { - return m_program->read_dword(addr); + return m_program.read_dword(addr); } inline void adsp21xx_device::program_write(uint32_t addr, uint32_t data) { - m_program->write_dword(addr, data & 0xffffff); + m_program.write_dword(addr, data & 0xffffff); } inline uint32_t adsp21xx_device::opcode_read() { - return m_cache->read_dword(m_pc); + return m_cache.read_dword(m_pc); } @@ -1048,7 +1088,7 @@ void adsp21xx_device::create_tables() // initialize the mask table for (int i = 0; i < 0x4000; i++) { - if (i > 0x2000) m_mask_table[i] = 0x0000; + if (i > 0x2000) m_mask_table[i] = 0x0000; else if (i > 0x1000) m_mask_table[i] = 0x2000; else if (i > 0x0800) m_mask_table[i] = 0x3000; else if (i > 0x0400) m_mask_table[i] = 0x3800; @@ -1104,7 +1144,7 @@ void adsp21xx_device::create_tables() // cycles it takes for one instruction to execute //------------------------------------------------- -uint32_t adsp21xx_device::execute_min_cycles() const +uint32_t adsp21xx_device::execute_min_cycles() const noexcept { return 1; } @@ -1115,33 +1155,12 @@ uint32_t adsp21xx_device::execute_min_cycles() const // cycles it takes for one instruction to execute //------------------------------------------------- -uint32_t adsp21xx_device::execute_max_cycles() const +uint32_t adsp21xx_device::execute_max_cycles() const noexcept { return 1; } -//------------------------------------------------- -// execute_input_lines - return the number of -// input/interrupt lines -//------------------------------------------------- - -uint32_t adsp2100_device::execute_input_lines() const -{ - return 4; -} - -uint32_t adsp2101_device::execute_input_lines() const -{ - return 5; -} - -uint32_t adsp2181_device::execute_input_lines() const -{ - return 9; -} - - void adsp21xx_device::execute_set_input(int inputnum, int state) { // update the latched state @@ -1156,12 +1175,13 @@ void adsp21xx_device::execute_set_input(int inputnum, int state) void adsp21xx_device::execute_run() { // Return if CPU is halted - if (current_input_state(INPUT_LINE_HALT)) { + if (input_line_state(INPUT_LINE_HALT)) { + debugger_wait_hook(); m_icount = 0; return; } - bool check_debugger = ((device_t::machine().debug_flags & DEBUG_FLAG_ENABLED) != 0); + const bool check_debugger = debugger_enabled(); check_irqs(); @@ -1201,7 +1221,7 @@ void adsp21xx_device::execute_run() // parse the instruction uint32_t temp; - switch ((op >> 16) & 0xff) + switch (BIT(op, 16, 8)) { case 0x00: // 00000000 00000000 00000000 NOP @@ -1212,68 +1232,56 @@ void adsp21xx_device::execute_run() // ADSP-218x only if (m_chip_type >= CHIP_TYPE_ADSP2181) { - if ((op & 0x008000) == 0x000000) - write_reg0(op & 15, io_read((op >> 4) & 0x7ff)); + if (!BIT(op, 15)) + write_reg0(BIT(op, 0, 4), io_read(BIT(op, 4, 11))); else - io_write((op >> 4) & 0x7ff, read_reg0(op & 15)); + io_write(BIT(op, 4, 11), read_reg0(BIT(op, 0, 4))); } break; case 0x02: // 00000010 0000xxxx xxxxxxxx modify flag out // 00000010 10000000 00000000 idle // 00000010 10000000 0000xxxx idle (n) - if (op & 0x008000) + if (BIT(op, 15)) { m_idle = 1; m_icount = 0; } else { - if (condition(op & 15)) + if (condition(BIT(op, 0, 4))) { - if (op & 0x020) m_flagout = 0; - if (op & 0x010) m_flagout ^= 1; + if (BIT(op, 5)) m_flagout = 0; + if (BIT(op, 4)) m_flagout ^= 1; if (m_chip_type >= CHIP_TYPE_ADSP2101) { - if (op & 0x080) m_fl0 = 0; - if (op & 0x040) m_fl0 ^= 1; - if (op & 0x200) m_fl1 = 0; - if (op & 0x100) m_fl1 ^= 1; - if (op & 0x800) m_fl2 = 0; - if (op & 0x400) m_fl2 ^= 1; + if (BIT(op, 7)) m_fl0 = 0; + if (BIT(op, 6)) m_fl0 ^= 1; + if (BIT(op, 9)) m_fl1 = 0; + if (BIT(op, 8)) m_fl1 ^= 1; + if (BIT(op, 11)) m_fl2 = 0; + if (BIT(op, 10)) m_fl2 ^= 1; } } } break; case 0x03: // 00000011 xxxxxxxx xxxxxxxx call or jump on flag in - if (op & 0x000002) + if (BIT(op, 1) ? m_flagin : !m_flagin) { - if (m_flagin) - { - if (op & 0x000001) - pc_stack_push(); - m_pc = ((op >> 4) & 0x0fff) | ((op << 10) & 0x3000); - } - } - else - { - if (!m_flagin) - { - if (op & 0x000001) - pc_stack_push(); - m_pc = ((op >> 4) & 0x0fff) | ((op << 10) & 0x3000); - } + if (BIT(op, 0)) + pc_stack_push(); + m_pc = BIT(op, 4, 12) | BIT(op, 2, 2) << 12; } break; case 0x04: // 00000100 00000000 000xxxxx stack control - if (op & 0x000010) pc_stack_pop_val(); - if (op & 0x000008) loop_stack_pop(); - if (op & 0x000004) cntr_stack_pop(); - if (op & 0x000002) + if (BIT(op, 4)) pc_stack_pop_val(); + if (BIT(op, 3)) loop_stack_pop(); + if (BIT(op, 2)) cntr_stack_pop(); + if (BIT(op, 1)) { - if (op & 0x000001) stat_stack_pop(); + if (BIT(op, 0)) stat_stack_pop(); else stat_stack_push(); } break; @@ -1290,8 +1298,8 @@ void adsp21xx_device::execute_run() case 0x06: // 00000110 000xxxxx 00000000 DIVS { - int xop = (op >> 8) & 7; - int yop = (op >> 11) & 3; + int xop = BIT(op, 8, 3); + int yop = BIT(op, 11, 2); xop = ALU_GETXREG_UNSIGNED(xop); yop = ALU_GETYREG_UNSIGNED(yop); @@ -1305,7 +1313,7 @@ void adsp21xx_device::execute_run() case 0x07: // 00000111 00010xxx 00000000 DIVQ { - int xop = (op >> 8) & 7; + int xop = BIT(op, 8, 3); int res; xop = ALU_GETXREG_UNSIGNED(xop); @@ -1326,68 +1334,68 @@ void adsp21xx_device::execute_run() break; case 0x09: // 00001001 00000000 000xxxxx modify address register - temp = (op >> 2) & 4; - modify_address(temp + ((op >> 2) & 3), temp + (op & 3)); + temp = BIT(op, 2, 3); + modify_address(temp, (temp & 4) | (op & 3)); break; case 0x0a: // 00001010 00000000 000xxxxx conditional return - if (condition(op & 15)) + if (condition(BIT(op, 0, 4))) { pc_stack_pop(); // RTI case - if (op & 0x000010) + if (BIT(op, 4)) stat_stack_pop(); } break; case 0x0b: // 00001011 00000000 xxxxxxxx conditional jump (indirect address) - if (condition(op & 15)) + if (condition(BIT(op, 0, 4))) { - if (op & 0x000010) + if (BIT(op, 4)) pc_stack_push(); - m_pc = m_i[4 + ((op >> 6) & 3)] & 0x3fff; + m_pc = m_i[4 + BIT(op, 6, 2)] & 0x3fff; } break; case 0x0c: // 00001100 xxxxxxxx xxxxxxxx mode control if (m_chip_type >= CHIP_TYPE_ADSP2101) { - if (op & 0x000008) m_mstat = (m_mstat & ~MSTAT_GOMODE) | ((op << 5) & MSTAT_GOMODE); - if (op & 0x002000) m_mstat = (m_mstat & ~MSTAT_INTEGER) | ((op >> 8) & MSTAT_INTEGER); - if (op & 0x008000) m_mstat = (m_mstat & ~MSTAT_TIMER) | ((op >> 9) & MSTAT_TIMER); + if (BIT(op, 3)) m_mstat = BIT(op, 2) ? (m_mstat | MSTAT_GOMODE) : (m_mstat & ~MSTAT_GOMODE); + if (BIT(op, 13)) m_mstat = BIT(op, 12) ? (m_mstat | MSTAT_INTEGER) : (m_mstat & ~MSTAT_INTEGER); + if (BIT(op, 15)) m_mstat = BIT(op, 14) ? (m_mstat | MSTAT_TIMER) : (m_mstat & ~MSTAT_TIMER); } - if (op & 0x000020) m_mstat = (m_mstat & ~MSTAT_BANK) | ((op >> 4) & MSTAT_BANK); - if (op & 0x000080) m_mstat = (m_mstat & ~MSTAT_REVERSE) | ((op >> 5) & MSTAT_REVERSE); - if (op & 0x000200) m_mstat = (m_mstat & ~MSTAT_STICKYV) | ((op >> 6) & MSTAT_STICKYV); - if (op & 0x000800) m_mstat = (m_mstat & ~MSTAT_SATURATE) | ((op >> 7) & MSTAT_SATURATE); + if (BIT(op, 5)) m_mstat = BIT(op, 4) ? (m_mstat | MSTAT_BANK) : (m_mstat & ~MSTAT_BANK); + if (BIT(op, 7)) m_mstat = BIT(op, 6) ? (m_mstat | MSTAT_REVERSE) : (m_mstat & ~MSTAT_REVERSE); + if (BIT(op, 9)) m_mstat = BIT(op, 8) ? (m_mstat | MSTAT_STICKYV) : (m_mstat & ~MSTAT_STICKYV); + if (BIT(op, 11)) m_mstat = BIT(op, 10) ? (m_mstat | MSTAT_SATURATE) : (m_mstat & ~MSTAT_SATURATE); update_mstat(); break; case 0x0d: // 00001101 0000xxxx xxxxxxxx internal data move - switch ((op >> 8) & 15) + switch (BIT(op, 8, 4)) { - case 0x00: write_reg0((op >> 4) & 15, read_reg0(op & 15)); break; - case 0x01: write_reg0((op >> 4) & 15, read_reg1(op & 15)); break; - case 0x02: write_reg0((op >> 4) & 15, read_reg2(op & 15)); break; - case 0x03: write_reg0((op >> 4) & 15, read_reg3(op & 15)); break; - case 0x04: write_reg1((op >> 4) & 15, read_reg0(op & 15)); break; - case 0x05: write_reg1((op >> 4) & 15, read_reg1(op & 15)); break; - case 0x06: write_reg1((op >> 4) & 15, read_reg2(op & 15)); break; - case 0x07: write_reg1((op >> 4) & 15, read_reg3(op & 15)); break; - case 0x08: write_reg2((op >> 4) & 15, read_reg0(op & 15)); break; - case 0x09: write_reg2((op >> 4) & 15, read_reg1(op & 15)); break; - case 0x0a: write_reg2((op >> 4) & 15, read_reg2(op & 15)); break; - case 0x0b: write_reg2((op >> 4) & 15, read_reg3(op & 15)); break; - case 0x0c: write_reg3((op >> 4) & 15, read_reg0(op & 15)); break; - case 0x0d: write_reg3((op >> 4) & 15, read_reg1(op & 15)); break; - case 0x0e: write_reg3((op >> 4) & 15, read_reg2(op & 15)); break; - case 0x0f: write_reg3((op >> 4) & 15, read_reg3(op & 15)); break; + case 0x00: write_reg0(BIT(op, 4, 4), read_reg0(BIT(op, 0, 4))); break; + case 0x01: write_reg0(BIT(op, 4, 4), read_reg1(BIT(op, 0, 4))); break; + case 0x02: write_reg0(BIT(op, 4, 4), read_reg2(BIT(op, 0, 4))); break; + case 0x03: write_reg0(BIT(op, 4, 4), read_reg3(BIT(op, 0, 4))); break; + case 0x04: write_reg1(BIT(op, 4, 4), read_reg0(BIT(op, 0, 4))); break; + case 0x05: write_reg1(BIT(op, 4, 4), read_reg1(BIT(op, 0, 4))); break; + case 0x06: write_reg1(BIT(op, 4, 4), read_reg2(BIT(op, 0, 4))); break; + case 0x07: write_reg1(BIT(op, 4, 4), read_reg3(BIT(op, 0, 4))); break; + case 0x08: write_reg2(BIT(op, 4, 4), read_reg0(BIT(op, 0, 4))); break; + case 0x09: write_reg2(BIT(op, 4, 4), read_reg1(BIT(op, 0, 4))); break; + case 0x0a: write_reg2(BIT(op, 4, 4), read_reg2(BIT(op, 0, 4))); break; + case 0x0b: write_reg2(BIT(op, 4, 4), read_reg3(BIT(op, 0, 4))); break; + case 0x0c: write_reg3(BIT(op, 4, 4), read_reg0(BIT(op, 0, 4))); break; + case 0x0d: write_reg3(BIT(op, 4, 4), read_reg1(BIT(op, 0, 4))); break; + case 0x0e: write_reg3(BIT(op, 4, 4), read_reg2(BIT(op, 0, 4))); break; + case 0x0f: write_reg3(BIT(op, 4, 4), read_reg3(BIT(op, 0, 4))); break; } break; case 0x0e: // 00001110 0xxxxxxx xxxxxxxx conditional shift - if (condition(op & 15)) shift_op(op); + if (condition(BIT(op, 0, 4))) shift_op(op); break; case 0x0f: // 00001111 0xxxxxxx xxxxxxxx shift immediate @@ -1396,46 +1404,46 @@ void adsp21xx_device::execute_run() case 0x10: // 00010000 0xxxxxxx xxxxxxxx shift with internal data register move shift_op(op); - temp = read_reg0(op & 15); - write_reg0((op >> 4) & 15, temp); + temp = read_reg0(BIT(op, 0, 4)); + write_reg0(BIT(op, 4, 4), temp); break; case 0x11: // 00010001 xxxxxxxx xxxxxxxx shift with pgm memory read/write - if (op & 0x8000) + if (BIT(op, 15)) { - pgm_write_dag2(op, read_reg0((op >> 4) & 15)); + pgm_write_dag2(op, read_reg0(BIT(op, 4, 4))); shift_op(op); } else { shift_op(op); - write_reg0((op >> 4) & 15, pgm_read_dag2(op)); + write_reg0(BIT(op, 4, 4), pgm_read_dag2(op)); } break; case 0x12: // 00010010 xxxxxxxx xxxxxxxx shift with data memory read/write DAG1 - if (op & 0x8000) + if (BIT(op, 15)) { - data_write_dag1(op, read_reg0((op >> 4) & 15)); + data_write_dag1(op, read_reg0(BIT(op, 4, 4))); shift_op(op); } else { shift_op(op); - write_reg0((op >> 4) & 15, data_read_dag1(op)); + write_reg0(BIT(op, 4, 4), data_read_dag1(op)); } break; case 0x13: // 00010011 xxxxxxxx xxxxxxxx shift with data memory read/write DAG2 - if (op & 0x8000) + if (BIT(op, 15)) { - data_write_dag2(op, read_reg0((op >> 4) & 15)); + data_write_dag2(op, read_reg0(BIT(op, 4, 4))); shift_op(op); } else { shift_op(op); - write_reg0((op >> 4) & 15, data_read_dag2(op)); + write_reg0(BIT(op, 4, 4), data_read_dag2(op)); } break; case 0x14: case 0x15: case 0x16: case 0x17: @@ -1445,9 +1453,9 @@ void adsp21xx_device::execute_run() break; case 0x18: case 0x19: case 0x1a: case 0x1b: // 000110xx xxxxxxxx xxxxxxxx conditional jump (immediate addr) - if (condition(op & 15)) + if (condition(BIT(op, 0, 4))) { - m_pc = (op >> 4) & 0x3fff; + m_pc = BIT(op, 4, 14); // check for a busy loop if (m_pc == m_ppc) m_icount = 0; @@ -1455,15 +1463,15 @@ void adsp21xx_device::execute_run() break; case 0x1c: case 0x1d: case 0x1e: case 0x1f: // 000111xx xxxxxxxx xxxxxxxx conditional call (immediate addr) - if (condition(op & 15)) + if (condition(BIT(op, 0, 4))) { pc_stack_push(); - m_pc = (op >> 4) & 0x3fff; + m_pc = BIT(op, 4, 14); } break; case 0x20: case 0x21: // 0010000x xxxxxxxx xxxxxxxx conditional MAC to MR - if (condition(op & 15)) + if (condition(BIT(op, 0, 4))) { if (m_chip_type >= CHIP_TYPE_ADSP2181 && (op & 0x0018f0) == 0x000010) mac_op_mr_xop(op); @@ -1473,9 +1481,9 @@ void adsp21xx_device::execute_run() break; case 0x22: case 0x23: // 0010001x xxxxxxxx xxxxxxxx conditional ALU to AR - if (condition(op & 15)) + if (condition(BIT(op, 0, 4))) { - if (m_chip_type >= CHIP_TYPE_ADSP2181 && (op & 0x000010) == 0x000010) + if (m_chip_type >= CHIP_TYPE_ADSP2181 && BIT(op, 4)) alu_op_ar_const(op); else alu_op_ar(op); @@ -1483,7 +1491,7 @@ void adsp21xx_device::execute_run() break; case 0x24: case 0x25: // 0010010x xxxxxxxx xxxxxxxx conditional MAC to MF - if (condition(op & 15)) + if (condition(BIT(op, 0, 4))) { if (m_chip_type >= CHIP_TYPE_ADSP2181 && (op & 0x0018f0) == 0x000010) mac_op_mf_xop(op); @@ -1493,9 +1501,9 @@ void adsp21xx_device::execute_run() break; case 0x26: case 0x27: // 0010011x xxxxxxxx xxxxxxxx conditional ALU to AF - if (condition(op & 15)) + if (condition(BIT(op, 0, 4))) { - if (m_chip_type >= CHIP_TYPE_ADSP2181 && (op & 0x000010) == 0x000010) + if (m_chip_type >= CHIP_TYPE_ADSP2181 && BIT(op, 4)) alu_op_af_const(op); else alu_op_af(op); @@ -1503,215 +1511,215 @@ void adsp21xx_device::execute_run() break; case 0x28: case 0x29: // 0010100x xxxxxxxx xxxxxxxx MAC to MR with internal data register move - temp = read_reg0(op & 15); + temp = read_reg0(BIT(op, 0, 4)); mac_op_mr(op); - write_reg0((op >> 4) & 15, temp); + write_reg0(BIT(op, 4, 4), temp); break; case 0x2a: case 0x2b: // 0010101x xxxxxxxx xxxxxxxx ALU to AR with internal data register move - if (m_chip_type >= CHIP_TYPE_ADSP2181 && (op & 0x0000ff) == 0x0000aa) + if (m_chip_type >= CHIP_TYPE_ADSP2181 && BIT(op, 0, 8) == 0xaa) alu_op_none(op); else { - temp = read_reg0(op & 15); + temp = read_reg0(BIT(op, 0, 4)); alu_op_ar(op); - write_reg0((op >> 4) & 15, temp); + write_reg0(BIT(op, 4, 4), temp); } break; case 0x2c: case 0x2d: // 0010110x xxxxxxxx xxxxxxxx MAC to MF with internal data register move - temp = read_reg0(op & 15); + temp = read_reg0(BIT(op, 0, 4)); mac_op_mf(op); - write_reg0((op >> 4) & 15, temp); + write_reg0(BIT(op, 4, 4), temp); break; case 0x2e: case 0x2f: // 0010111x xxxxxxxx xxxxxxxx ALU to AF with internal data register move - temp = read_reg0(op & 15); + temp = read_reg0(BIT(op, 0, 4)); alu_op_af(op); - write_reg0((op >> 4) & 15, temp); + write_reg0(BIT(op, 4, 4), temp); break; case 0x30: case 0x31: case 0x32: case 0x33: // 001100xx xxxxxxxx xxxxxxxx load non-data register immediate (group 0) - write_reg0(op & 15, (int32_t)(op << 14) >> 18); + write_reg0(BIT(op, 0, 4), util::sext(op >> 4, 14)); break; case 0x34: case 0x35: case 0x36: case 0x37: // 001101xx xxxxxxxx xxxxxxxx load non-data register immediate (group 1) - write_reg1(op & 15, (int32_t)(op << 14) >> 18); + write_reg1(BIT(op, 0, 4), util::sext(op >> 4, 14)); break; case 0x38: case 0x39: case 0x3a: case 0x3b: // 001110xx xxxxxxxx xxxxxxxx load non-data register immediate (group 2) - write_reg2(op & 15, (int32_t)(op << 14) >> 18); + write_reg2(BIT(op, 0, 4), util::sext(op >> 4, 14)); break; case 0x3c: case 0x3d: case 0x3e: case 0x3f: // 001111xx xxxxxxxx xxxxxxxx load non-data register immediate (group 3) - write_reg3(op & 15, (int32_t)(op << 14) >> 18); + write_reg3(BIT(op, 0, 4), util::sext(op >> 4, 14)); break; case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47: case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f: // 0100xxxx xxxxxxxx xxxxxxxx load data register immediate - write_reg0(op & 15, (op >> 4) & 0xffff); + write_reg0(BIT(op, 0, 4), BIT(op, 4, 16)); break; case 0x50: case 0x51: // 0101000x xxxxxxxx xxxxxxxx MAC to MR with pgm memory read mac_op_mr(op); - write_reg0((op >> 4) & 15, pgm_read_dag2(op)); + write_reg0(BIT(op, 4, 4), pgm_read_dag2(op)); break; case 0x52: case 0x53: // 0101001x xxxxxxxx xxxxxxxx ALU to AR with pgm memory read alu_op_ar(op); - write_reg0((op >> 4) & 15, pgm_read_dag2(op)); + write_reg0(BIT(op, 4, 4), pgm_read_dag2(op)); break; case 0x54: case 0x55: // 0101010x xxxxxxxx xxxxxxxx MAC to MF with pgm memory read mac_op_mf(op); - write_reg0((op >> 4) & 15, pgm_read_dag2(op)); + write_reg0(BIT(op, 4, 4), pgm_read_dag2(op)); break; case 0x56: case 0x57: // 0101011x xxxxxxxx xxxxxxxx ALU to AF with pgm memory read alu_op_af(op); - write_reg0((op >> 4) & 15, pgm_read_dag2(op)); + write_reg0(BIT(op, 4, 4), pgm_read_dag2(op)); break; case 0x58: case 0x59: // 0101100x xxxxxxxx xxxxxxxx MAC to MR with pgm memory write - pgm_write_dag2(op, read_reg0((op >> 4) & 15)); + pgm_write_dag2(op, read_reg0(BIT(op, 4, 4))); mac_op_mr(op); break; case 0x5a: case 0x5b: // 0101101x xxxxxxxx xxxxxxxx ALU to AR with pgm memory write - pgm_write_dag2(op, read_reg0((op >> 4) & 15)); + pgm_write_dag2(op, read_reg0(BIT(op, 4, 4))); alu_op_ar(op); break; case 0x5c: case 0x5d: // 0101110x xxxxxxxx xxxxxxxx ALU to MR with pgm memory write - pgm_write_dag2(op, read_reg0((op >> 4) & 15)); + pgm_write_dag2(op, read_reg0(BIT(op, 4, 4))); mac_op_mf(op); break; case 0x5e: case 0x5f: // 0101111x xxxxxxxx xxxxxxxx ALU to MF with pgm memory write - pgm_write_dag2(op, read_reg0((op >> 4) & 15)); + pgm_write_dag2(op, read_reg0(BIT(op, 4, 4))); alu_op_af(op); break; case 0x60: case 0x61: // 0110000x xxxxxxxx xxxxxxxx MAC to MR with data memory read DAG1 mac_op_mr(op); - write_reg0((op >> 4) & 15, data_read_dag1(op)); + write_reg0(BIT(op, 4, 4), data_read_dag1(op)); break; case 0x62: case 0x63: // 0110001x xxxxxxxx xxxxxxxx ALU to AR with data memory read DAG1 alu_op_ar(op); - write_reg0((op >> 4) & 15, data_read_dag1(op)); + write_reg0(BIT(op, 4, 4), data_read_dag1(op)); break; case 0x64: case 0x65: // 0110010x xxxxxxxx xxxxxxxx MAC to MF with data memory read DAG1 mac_op_mf(op); - write_reg0((op >> 4) & 15, data_read_dag1(op)); + write_reg0(BIT(op, 4, 4), data_read_dag1(op)); break; case 0x66: case 0x67: // 0110011x xxxxxxxx xxxxxxxx ALU to AF with data memory read DAG1 alu_op_af(op); - write_reg0((op >> 4) & 15, data_read_dag1(op)); + write_reg0(BIT(op, 4, 4), data_read_dag1(op)); break; case 0x68: case 0x69: // 0110100x xxxxxxxx xxxxxxxx MAC to MR with data memory write DAG1 - data_write_dag1(op, read_reg0((op >> 4) & 15)); + data_write_dag1(op, read_reg0(BIT(op, 4, 4))); mac_op_mr(op); break; case 0x6a: case 0x6b: // 0110101x xxxxxxxx xxxxxxxx ALU to AR with data memory write DAG1 - data_write_dag1(op, read_reg0((op >> 4) & 15)); + data_write_dag1(op, read_reg0(BIT(op, 4, 4))); alu_op_ar(op); break; case 0x6c: case 0x6d: // 0111110x xxxxxxxx xxxxxxxx MAC to MF with data memory write DAG1 - data_write_dag1(op, read_reg0((op >> 4) & 15)); + data_write_dag1(op, read_reg0(BIT(op, 4, 4))); mac_op_mf(op); break; case 0x6e: case 0x6f: // 0111111x xxxxxxxx xxxxxxxx ALU to AF with data memory write DAG1 - data_write_dag1(op, read_reg0((op >> 4) & 15)); + data_write_dag1(op, read_reg0(BIT(op, 4, 4))); alu_op_af(op); break; case 0x70: case 0x71: // 0111000x xxxxxxxx xxxxxxxx MAC to MR with data memory read DAG2 mac_op_mr(op); - write_reg0((op >> 4) & 15, data_read_dag2(op)); + write_reg0(BIT(op, 4, 4), data_read_dag2(op)); break; case 0x72: case 0x73: // 0111001x xxxxxxxx xxxxxxxx ALU to AR with data memory read DAG2 alu_op_ar(op); - write_reg0((op >> 4) & 15, data_read_dag2(op)); + write_reg0(BIT(op, 4, 4), data_read_dag2(op)); break; case 0x74: case 0x75: // 0111010x xxxxxxxx xxxxxxxx MAC to MF with data memory read DAG2 mac_op_mf(op); - write_reg0((op >> 4) & 15, data_read_dag2(op)); + write_reg0(BIT(op, 4, 4), data_read_dag2(op)); break; case 0x76: case 0x77: // 0111011x xxxxxxxx xxxxxxxx ALU to AF with data memory read DAG2 alu_op_af(op); - write_reg0((op >> 4) & 15, data_read_dag2(op)); + write_reg0(BIT(op, 4, 4), data_read_dag2(op)); break; case 0x78: case 0x79: // 0111100x xxxxxxxx xxxxxxxx MAC to MR with data memory write DAG2 - data_write_dag2(op, read_reg0((op >> 4) & 15)); + data_write_dag2(op, read_reg0(BIT(op, 4, 4))); mac_op_mr(op); break; case 0x7a: case 0x7b: // 0111101x xxxxxxxx xxxxxxxx ALU to AR with data memory write DAG2 - data_write_dag2(op, read_reg0((op >> 4) & 15)); + data_write_dag2(op, read_reg0(BIT(op, 4, 4))); alu_op_ar(op); break; case 0x7c: case 0x7d: // 0111110x xxxxxxxx xxxxxxxx MAC to MF with data memory write DAG2 - data_write_dag2(op, read_reg0((op >> 4) & 15)); + data_write_dag2(op, read_reg0(BIT(op, 4, 4))); mac_op_mf(op); break; case 0x7e: case 0x7f: // 0111111x xxxxxxxx xxxxxxxx ALU to AF with data memory write DAG2 - data_write_dag2(op, read_reg0((op >> 4) & 15)); + data_write_dag2(op, read_reg0(BIT(op, 4, 4))); alu_op_af(op); break; case 0x80: case 0x81: case 0x82: case 0x83: // 100000xx xxxxxxxx xxxxxxxx read data memory (immediate addr) to reg group 0 - write_reg0(op & 15, data_read((op >> 4) & 0x3fff)); + write_reg0(BIT(op, 0, 4), data_read(BIT(op, 4, 14))); break; case 0x84: case 0x85: case 0x86: case 0x87: // 100001xx xxxxxxxx xxxxxxxx read data memory (immediate addr) to reg group 1 - write_reg1(op & 15, data_read((op >> 4) & 0x3fff)); + write_reg1(BIT(op, 0, 4), data_read(BIT(op, 4, 14))); break; case 0x88: case 0x89: case 0x8a: case 0x8b: // 100010xx xxxxxxxx xxxxxxxx read data memory (immediate addr) to reg group 2 - write_reg2(op & 15, data_read((op >> 4) & 0x3fff)); + write_reg2(BIT(op, 0, 4), data_read(BIT(op, 4, 14))); break; case 0x8c: case 0x8d: case 0x8e: case 0x8f: // 100011xx xxxxxxxx xxxxxxxx read data memory (immediate addr) to reg group 3 - write_reg3(op & 15, data_read((op >> 4) & 0x3fff)); + write_reg3(BIT(op, 0, 4), data_read(BIT(op, 4, 14))); break; case 0x90: case 0x91: case 0x92: case 0x93: // 1001xxxx xxxxxxxx xxxxxxxx write data memory (immediate addr) from reg group 0 - data_write((op >> 4) & 0x3fff, read_reg0(op & 15)); + data_write(BIT(op, 4, 14), read_reg0(BIT(op, 0, 4))); break; case 0x94: case 0x95: case 0x96: case 0x97: // 1001xxxx xxxxxxxx xxxxxxxx write data memory (immediate addr) from reg group 1 - data_write((op >> 4) & 0x3fff, read_reg1(op & 15)); + data_write(BIT(op, 4, 14), read_reg1(BIT(op, 0, 4))); break; case 0x98: case 0x99: case 0x9a: case 0x9b: // 1001xxxx xxxxxxxx xxxxxxxx write data memory (immediate addr) from reg group 2 - data_write((op >> 4) & 0x3fff, read_reg2(op & 15)); + data_write(BIT(op, 4, 14), read_reg2(BIT(op, 0, 4))); break; case 0x9c: case 0x9d: case 0x9e: case 0x9f: // 1001xxxx xxxxxxxx xxxxxxxx write data memory (immediate addr) from reg group 3 - data_write((op >> 4) & 0x3fff, read_reg3(op & 15)); + data_write(BIT(op, 4, 14), read_reg3(BIT(op, 0, 4))); break; case 0xa0: case 0xa1: case 0xa2: case 0xa3: case 0xa4: case 0xa5: case 0xa6: case 0xa7: case 0xa8: case 0xa9: case 0xaa: case 0xab: case 0xac: case 0xad: case 0xae: case 0xaf: // 1010xxxx xxxxxxxx xxxxxxxx data memory write (immediate) DAG1 - data_write_dag1(op, (op >> 4) & 0xffff); + data_write_dag1(op, BIT(op, 4, 16)); break; case 0xb0: case 0xb1: case 0xb2: case 0xb3: case 0xb4: case 0xb5: case 0xb6: case 0xb7: case 0xb8: case 0xb9: case 0xba: case 0xbb: case 0xbc: case 0xbd: case 0xbe: case 0xbf: // 1011xxxx xxxxxxxx xxxxxxxx data memory write (immediate) DAG2 - data_write_dag2(op, (op >> 4) & 0xffff); + data_write_dag2(op, BIT(op, 4, 16)); break; case 0xc0: case 0xc1: // 1100000x xxxxxxxx xxxxxxxx MAC to MR with data read to AX0 & pgm read to AY0 |