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-rw-r--r--android-project/app/src/main/AndroidManifest.xml4
-rw-r--r--hash/ekara.xml73
-rw-r--r--hash/mac_hdflop.xml2
-rw-r--r--hash/x68k_flop.xml2
-rw-r--r--makefile4
-rw-r--r--scripts/src/cpu.lua6
-rw-r--r--scripts/src/machine.lua12
-rw-r--r--scripts/target/mame/mess.lua1
-rw-r--r--src/devices/bus/coco/coco_fdc.cpp4
-rw-r--r--src/devices/bus/coco/dragon_fdc.cpp6
-rw-r--r--src/devices/bus/cpc/cpc_rs232.cpp14
-rw-r--r--src/devices/bus/dmv/k220.cpp15
-rw-r--r--src/devices/bus/dmv/k230.cpp55
-rw-r--r--src/devices/bus/dmv/k230.h9
-rw-r--r--src/devices/bus/isa/ibm_mfc.cpp14
-rw-r--r--src/devices/bus/isa/myb3k_com.cpp15
-rw-r--r--src/devices/bus/isa/p1_sound.cpp46
-rw-r--r--src/devices/bus/s100/wunderbus.cpp17
-rw-r--r--src/devices/cpu/i386/i386.cpp209
-rw-r--r--src/devices/cpu/i386/i386.h28
-rw-r--r--src/devices/cpu/i386/i386priv.h223
-rw-r--r--src/devices/cpu/i386/i486ops.hxx3
-rw-r--r--src/devices/cpu/i386/pentops.hxx22
-rw-r--r--src/devices/cpu/i8008/i8008.cpp2
-rw-r--r--src/devices/cpu/m6502/oxavix2000.lst16
-rw-r--r--src/devices/cpu/m6502/xavix2000.cpp4
-rw-r--r--src/devices/cpu/m68000/m68000.h1
-rw-r--r--src/devices/cpu/m68000/m68kcpu.cpp32
-rw-r--r--src/devices/cpu/m68000/m68kdasm.cpp2
-rw-r--r--src/devices/cpu/m68000/m68kmmu.h727
-rw-r--r--src/devices/cpu/mips/r3000.cpp315
-rw-r--r--src/devices/cpu/mips/r3000.h112
-rw-r--r--src/devices/cpu/nec/v25.cpp24
-rw-r--r--src/devices/cpu/nec/v25.h71
-rw-r--r--src/devices/cpu/nec/v25instr.hxx8
-rw-r--r--src/devices/cpu/nec/v25priv.h6
-rw-r--r--src/devices/cpu/nec/v25sfr.cpp726
-rw-r--r--src/devices/cpu/nec/v53.cpp599
-rw-r--r--src/devices/cpu/nec/v53.h277
-rw-r--r--src/devices/cpu/nec/v5x.cpp428
-rw-r--r--src/devices/cpu/nec/v5x.h172
-rw-r--r--src/devices/machine/aic6250.cpp1038
-rw-r--r--src/devices/machine/aic6250.h282
-rw-r--r--src/devices/machine/am9517a.cpp93
-rw-r--r--src/devices/machine/am9517a.h34
-rw-r--r--src/devices/machine/cs4031.h9
-rw-r--r--src/devices/machine/i80130.cpp25
-rw-r--r--src/devices/machine/i8251.cpp47
-rw-r--r--src/devices/machine/i8251.h25
-rw-r--r--src/devices/machine/mb87030.cpp83
-rw-r--r--src/devices/machine/pdc.h5
-rw-r--r--src/devices/machine/phi.h53
-rw-r--r--src/devices/machine/pic8259.cpp24
-rw-r--r--src/devices/machine/pic8259.h34
-rw-r--r--src/devices/machine/pit8253.h24
-rw-r--r--src/devices/machine/smioc.cpp2
-rw-r--r--src/devices/sound/dac.cpp3
-rw-r--r--src/devices/video/cgapal.cpp1
-rw-r--r--src/emu/attotime.cpp4
-rw-r--r--src/emu/debug/textbuf.cpp2
-rw-r--r--src/emu/emualloc.cpp2
-rw-r--r--src/emu/video/rgbgen.cpp4
-rw-r--r--src/emu/video/rgbsse.cpp3
-rw-r--r--src/emu/video/rgbvmx.cpp3
-rw-r--r--src/frontend/mame/luaengine.cpp21
-rw-r--r--src/lib/formats/dsk_dsk.cpp6
-rw-r--r--src/mame/audio/hng64.cpp32
-rw-r--r--src/mame/audio/leland.cpp100
-rw-r--r--src/mame/audio/leland.h4
-rw-r--r--src/mame/drivers/a7150.cpp6
-rw-r--r--src/mame/drivers/akaiax80.cpp27
-rw-r--r--src/mame/drivers/alg.cpp2
-rw-r--r--src/mame/drivers/alphatpx.cpp35
-rw-r--r--src/mame/drivers/altos486.cpp39
-rw-r--r--src/mame/drivers/altos8600.cpp72
-rw-r--r--src/mame/drivers/amusco.cpp30
-rw-r--r--src/mame/drivers/apogee.cpp14
-rw-r--r--src/mame/drivers/apricot.cpp6
-rw-r--r--src/mame/drivers/apricotp.cpp2
-rw-r--r--src/mame/drivers/atvtrack.cpp7
-rw-r--r--src/mame/drivers/b2m.cpp18
-rw-r--r--src/mame/drivers/balsente.cpp14
-rw-r--r--src/mame/drivers/bw12.cpp14
-rw-r--r--src/mame/drivers/cbm2.cpp14
-rw-r--r--src/mame/drivers/compc.cpp14
-rw-r--r--src/mame/drivers/compis.cpp14
-rw-r--r--src/mame/drivers/crystal.cpp9
-rw-r--r--src/mame/drivers/dai.cpp18
-rw-r--r--src/mame/drivers/dmv.cpp10
-rw-r--r--src/mame/drivers/dvk_ksm.cpp8
-rw-r--r--src/mame/drivers/excali64.cpp12
-rw-r--r--src/mame/drivers/fantland.cpp254
-rw-r--r--src/mame/drivers/fanucspmg.cpp91
-rw-r--r--src/mame/drivers/fastinvaders.cpp8
-rw-r--r--src/mame/drivers/fk1.cpp16
-rw-r--r--src/mame/drivers/fmtowns.cpp46
-rw-r--r--src/mame/drivers/hp64k.cpp46
-rw-r--r--src/mame/drivers/hp9k_3xx.cpp3
-rw-r--r--src/mame/drivers/i7000.cpp17
-rw-r--r--src/mame/drivers/ibm6580.cpp14
-rw-r--r--src/mame/drivers/ibmpcjr.cpp26
-rw-r--r--src/mame/drivers/if800.cpp2
-rw-r--r--src/mame/drivers/iq151.cpp64
-rw-r--r--src/mame/drivers/irisha.cpp6
-rw-r--r--src/mame/drivers/isbc.cpp50
-rw-r--r--src/mame/drivers/jtc.cpp2
-rw-r--r--src/mame/drivers/konmedal.cpp5
-rw-r--r--src/mame/drivers/laserbas.cpp112
-rw-r--r--src/mame/drivers/m107.cpp6
-rw-r--r--src/mame/drivers/m20.cpp20
-rw-r--r--src/mame/drivers/m52.cpp374
-rw-r--r--src/mame/drivers/m72.cpp20
-rw-r--r--src/mame/drivers/m92.cpp6
-rw-r--r--src/mame/drivers/mbc55x.cpp32
-rw-r--r--src/mame/drivers/mc1502.cpp44
-rw-r--r--src/mame/drivers/mikie.cpp33
-rw-r--r--src/mame/drivers/mikrosha.cpp10
-rw-r--r--src/mame/drivers/miniframe.cpp17
-rw-r--r--src/mame/drivers/mips.cpp411
-rw-r--r--src/mame/drivers/mod8.cpp1
-rw-r--r--src/mame/drivers/model3.cpp218
-rw-r--r--src/mame/drivers/mpc3000.cpp26
-rw-r--r--src/mame/drivers/mrflea.cpp6
-rw-r--r--src/mame/drivers/ms0515.cpp17
-rw-r--r--src/mame/drivers/ms6102.cpp12
-rw-r--r--src/mame/drivers/multi16.cpp12
-rw-r--r--src/mame/drivers/multi8.cpp6
-rw-r--r--src/mame/drivers/myb3k.cpp34
-rw-r--r--src/mame/drivers/mz2000.cpp8
-rw-r--r--src/mame/drivers/mz2500.cpp12
-rw-r--r--src/mame/drivers/mz700.cpp17
-rw-r--r--src/mame/drivers/mz80.cpp14
-rw-r--r--src/mame/drivers/namcos22.cpp283
-rw-r--r--src/mame/drivers/ngen.cpp48
-rw-r--r--src/mame/drivers/notetaker.cpp33
-rw-r--r--src/mame/drivers/octopus.cpp14
-rw-r--r--src/mame/drivers/okean240.cpp6
-rw-r--r--src/mame/drivers/olyboss.cpp4
-rw-r--r--src/mame/drivers/pbaction.cpp263
-rw-r--r--src/mame/drivers/pc100.cpp20
-rw-r--r--src/mame/drivers/pc1512.cpp60
-rw-r--r--src/mame/drivers/pc88va.cpp10
-rw-r--r--src/mame/drivers/pc9801.cpp7
-rw-r--r--src/mame/drivers/pcd.cpp10
-rw-r--r--src/mame/drivers/peoplepc.cpp46
-rw-r--r--src/mame/drivers/pg685.cpp55
-rw-r--r--src/mame/drivers/pk8020.cpp22
-rw-r--r--src/mame/drivers/poisk1.cpp36
-rw-r--r--src/mame/drivers/pp01.cpp14
-rw-r--r--src/mame/drivers/prehisle.cpp2
-rw-r--r--src/mame/drivers/prophet600.cpp12
-rw-r--r--src/mame/drivers/pwrview.cpp10
-rw-r--r--src/mame/drivers/ql.cpp39
-rw-r--r--src/mame/drivers/rc759.cpp8
-rw-r--r--src/mame/drivers/sacstate.cpp1
-rw-r--r--src/mame/drivers/sage2.cpp40
-rw-r--r--src/mame/drivers/segacoin.cpp42
-rw-r--r--src/mame/drivers/segas16b.cpp94
-rw-r--r--src/mame/drivers/segasp.cpp55
-rw-r--r--src/mame/drivers/segaufo.cpp14
-rw-r--r--src/mame/drivers/seta.cpp24
-rw-r--r--src/mame/drivers/sm7238.cpp30
-rw-r--r--src/mame/drivers/snk.cpp5
-rw-r--r--src/mame/drivers/special.cpp14
-rw-r--r--src/mame/drivers/supbtime.cpp32
-rw-r--r--src/mame/drivers/tandy2k.cpp26
-rw-r--r--src/mame/drivers/tdv2324.cpp6
-rw-r--r--src/mame/drivers/tiamc1.cpp8
-rw-r--r--src/mame/drivers/tsispch.cpp12
-rw-r--r--src/mame/drivers/unistar.cpp3
-rw-r--r--src/mame/drivers/vector06.cpp14
-rw-r--r--src/mame/drivers/vertigo.cpp14
-rw-r--r--src/mame/drivers/wacky_gator.cpp50
-rw-r--r--src/mame/drivers/williams.cpp40
-rw-r--r--src/mame/drivers/wswan.cpp4
-rw-r--r--src/mame/drivers/xavix.cpp156
-rw-r--r--src/mame/drivers/z100.cpp24
-rw-r--r--src/mame/includes/combatsc.h10
-rw-r--r--src/mame/includes/fantland.h120
-rw-r--r--src/mame/includes/hng64.h2
-rw-r--r--src/mame/includes/m52.h67
-rw-r--r--src/mame/includes/mips.h57
-rw-r--r--src/mame/includes/model3.h1
-rw-r--r--src/mame/includes/pbaction.h51
-rw-r--r--src/mame/includes/supbtime.h2
-rw-r--r--src/mame/includes/xavix.h28
-rw-r--r--src/mame/layout/pbactiont.lay194
-rw-r--r--src/mame/machine/at.cpp14
-rw-r--r--src/mame/machine/m24_z8000.cpp18
-rw-r--r--src/mame/machine/xavix.cpp129
-rw-r--r--src/mame/machine/xbox.cpp30
-rw-r--r--src/mame/machine/zx8302.h78
-rw-r--r--src/mame/mame.lst23
-rw-r--r--src/mame/video/deco16ic.cpp2
-rw-r--r--src/mame/video/fantland.cpp13
-rw-r--r--src/mame/video/fmtowns.cpp12
-rw-r--r--src/mame/video/m107.cpp4
-rw-r--r--src/mame/video/m52.cpp244
-rw-r--r--src/mame/video/namco_c355spr.cpp4
-rw-r--r--src/mame/video/namco_c355spr.h3
-rw-r--r--src/mame/video/namcos22.cpp61
-rw-r--r--src/mame/video/supbtime.cpp44
-rw-r--r--src/mame/video/xavix.cpp20
-rw-r--r--src/mame/video/zx8301.h13
204 files changed, 7219 insertions, 4507 deletions
diff --git a/android-project/app/src/main/AndroidManifest.xml b/android-project/app/src/main/AndroidManifest.xml
index 413f1d5e478..02b31b3af14 100644
--- a/android-project/app/src/main/AndroidManifest.xml
+++ b/android-project/app/src/main/AndroidManifest.xml
@@ -4,8 +4,8 @@
-->
<manifest xmlns:android="http://schemas.android.com/apk/res/android"
package="org.mamedev.mame"
- android:versionCode="202"
- android:versionName="0.202"
+ android:versionCode="203"
+ android:versionName="0.203"
android:installLocation="auto">
<!-- Android 5.0 -->
diff --git a/hash/ekara.xml b/hash/ekara.xml
new file mode 100644
index 00000000000..d84d7c809e1
--- /dev/null
+++ b/hash/ekara.xml
@@ -0,0 +1,73 @@
+<?xml version="1.0"?>
+<!DOCTYPE softwarelist SYSTEM "softwarelist.dtd">
+<softwarelist name="ekara" description="Takara e-kara cartridges">
+ <!-- cartridges contain the ROM only, the XaviX CPU and BIOS are in the base unit -->
+
+ <!-- Each region has it's own set of cartridges (at least US, UK/EU and Japan)
+ The Japanese ones appear to have a number of different genres each with their own numbering -->
+
+ <!--
+ 1. "Stronger" Britney Spears
+ 2. "Bye Bye Bye" *N Sync
+ 3. "Independent Woman Part 1" Destiny's Child
+ 4. "I Want It That Way" Backstreet Boys
+ 5. "Yellow Submarine" The Beatles
+ -->
+ <software name="us_strt">
+ <description>e-kara US 5-Songs Starter (US-M001)</description>
+ <year>2000</year>
+ <publisher>Takara</publisher>
+ <part name="cart" interface="ekara_cart">
+ <dataarea name="rom" size="0x080000">
+ <rom name="ekara_starter.bin" size="0x080000" crc="8c12c0c2" sha1="8cc1b098894af25a4bfccada884125b66f5fe8b2" offset="0" />
+ </dataarea>
+ </part>
+ </software>
+
+ <!--
+ 1. "Oops!...I Did It Again" Britney Spears
+ 2. "...Baby One More Time" Britney Spears
+ 3. "Bye Bye Bye" *N Sync
+ 4. "It's Gonna Be Me" *N Sync
+ 5. "Take On Me" a1
+ 6. "Aaron's Party (Come Get It)" Aaron Carter
+ 7. "If Only" Hanson
+ 8. "He Loves U Not" Dream
+ 9. "The First Night" Monica
+ 10. "I Need You" LeAnn Rimes
+ -->
+ <software name="us_vol1">
+ <description>e-kara US Volume 1 (US-E001)</description>
+ <year>2000</year>
+ <publisher>Takara</publisher>
+ <part name="cart" interface="ekara_cart">
+ <dataarea name="rom" size="0x100000">
+ <rom name="ekaravol1.bin" size="0x100000" crc="29df4aea" sha1="b95835aaf8630b61b47e5da0968cd4a1dd3bc517" offset="0" />
+ </dataarea>
+ </part>
+ </software>
+
+ <!--
+ 1. "Larger Than Life" Backstreet Boys
+ 2. "I'll Be There For You" Backstreet Boys
+ 3. "My Everything" 98 Degrees
+ 4. "Dizzy" 98 Degrees
+ 5. "Independent Woman Part 1" Destiny's Child
+ 6. "Waiting For Tonight" Jennifer Lopez
+ 7. "Let Me Let Go" Faith Hill
+ 8. "There's Your Trouble" Dixie Chicks
+ 9. "5678" Steps
+ 10. "Stomp" Steps
+ -->
+ <software name="us_vol2">
+ <description>e-kara US Volume 2 (US-E002)</description>
+ <year>2000</year>
+ <publisher>Takara</publisher>
+ <part name="cart" interface="ekara_cart">
+ <dataarea name="rom" size="0x100000">
+ <rom name="ekaravol2.bin" size="0x100000" crc="6c66772e" sha1="e1e719df1e51caaafd9b3af187059334f7abbba3" offset="0" />
+ </dataarea>
+ </part>
+ </software>
+
+</softwarelist>
diff --git a/hash/mac_hdflop.xml b/hash/mac_hdflop.xml
index dc729e4dc12..8c3e5241f60 100644
--- a/hash/mac_hdflop.xml
+++ b/hash/mac_hdflop.xml
@@ -3,7 +3,7 @@
<softwarelist name="mac_hdflop" description="Macintosh High Density Disk images">
<!-- S/N: Z93350-001A -->
- <software name="clarisw">
+ <software name="clarisw" supported="no">
<description>ClarisWorks (Swedish)</description>
<year>1993</year>
<publisher>Claris</publisher>
diff --git a/hash/x68k_flop.xml b/hash/x68k_flop.xml
index 1dd2246ffd5..54330d89eba 100644
--- a/hash/x68k_flop.xml
+++ b/hash/x68k_flop.xml
@@ -3043,7 +3043,7 @@ Most info on release dates and Jpn titles come from the following (wonderful) re
<!-- Offset front layer, but playable -->
<software name="cuberunr">
- <description>Cueb Runner</description>
+ <description>Cube Runner</description>
<year>1990</year>
<publisher>SPS</publisher>
<info name="alt_title" value="キューブランナー" />
diff --git a/makefile b/makefile
index 14e89347611..a1244b74efb 100644
--- a/makefile
+++ b/makefile
@@ -1584,14 +1584,14 @@ endif
ifeq (posix,$(SHELLTYPE))
$(GENDIR)/version.cpp: $(GENDIR)/git_desc | $(GEN_FOLDERS)
- @echo '#define BARE_BUILD_VERSION "0.202"' > $@
+ @echo '#define BARE_BUILD_VERSION "0.203"' > $@
@echo 'extern const char bare_build_version[];' >> $@
@echo 'extern const char build_version[];' >> $@
@echo 'const char bare_build_version[] = BARE_BUILD_VERSION;' >> $@
@echo 'const char build_version[] = BARE_BUILD_VERSION " ($(NEW_GIT_VERSION))";' >> $@
else
$(GENDIR)/version.cpp: $(GENDIR)/git_desc
- @echo #define BARE_BUILD_VERSION "0.202" > $@
+ @echo #define BARE_BUILD_VERSION "0.203" > $@
@echo extern const char bare_build_version[]; >> $@
@echo extern const char build_version[]; >> $@
@echo const char bare_build_version[] = BARE_BUILD_VERSION; >> $@
diff --git a/scripts/src/cpu.lua b/scripts/src/cpu.lua
index 846e1bad71c..b4b06d5330f 100644
--- a/scripts/src/cpu.lua
+++ b/scripts/src/cpu.lua
@@ -1746,7 +1746,7 @@ end
-- NEC V-series Intel-compatible
--@src/devices/cpu/nec/nec.h,CPUS["NEC"] = true
--@src/devices/cpu/nec/v25.h,CPUS["NEC"] = true
---@src/devices/cpu/nec/v53.h,CPUS["NEC"] = true
+--@src/devices/cpu/nec/v5x.h,CPUS["NEC"] = true
--@src/devices/cpu/v30mz/v30mz.h,CPUS["V30MZ"] = true
--------------------------------------------------
@@ -1766,8 +1766,8 @@ if (CPUS["NEC"]~=null) then
MAME_DIR .. "src/devices/cpu/nec/v25.cpp",
MAME_DIR .. "src/devices/cpu/nec/v25.h",
MAME_DIR .. "src/devices/cpu/nec/v25sfr.cpp",
- MAME_DIR .. "src/devices/cpu/nec/v53.cpp",
- MAME_DIR .. "src/devices/cpu/nec/v53.h",
+ MAME_DIR .. "src/devices/cpu/nec/v5x.cpp",
+ MAME_DIR .. "src/devices/cpu/nec/v5x.h",
}
end
diff --git a/scripts/src/machine.lua b/scripts/src/machine.lua
index b88139367ad..836d3e2d5b9 100644
--- a/scripts/src/machine.lua
+++ b/scripts/src/machine.lua
@@ -3808,7 +3808,6 @@ if (MACHINES["Z8038"]~=null) then
}
end
-
---------------------------------------------------
--
--@src/devices/machine/scc2698b.h,MACHINES["SCC2698B"] = true
@@ -3821,3 +3820,14 @@ if (MACHINES["SCC2698B"]~=null) then
}
end
+---------------------------------------------------
+--
+--@src/devices/machine/aic6250.h,MACHINES["AIC6250"] = true
+---------------------------------------------------
+
+if (MACHINES["AIC6250"]~=null) then
+ files {
+ MAME_DIR .. "src/devices/machine/aic6250.cpp",
+ MAME_DIR .. "src/devices/machine/aic6250.h",
+ }
+end
diff --git a/scripts/target/mame/mess.lua b/scripts/target/mame/mess.lua
index 9edec06e61d..abc05e55868 100644
--- a/scripts/target/mame/mess.lua
+++ b/scripts/target/mame/mess.lua
@@ -673,6 +673,7 @@ MACHINES["IOPINTC"] = true
MACHINES["IOPSIO2"] = true
MACHINES["IOPTIMER"] = true
MACHINES["Z8038"] = true
+MACHINES["AIC6250"] = true
--------------------------------------------------
-- specify available bus cores
diff --git a/src/devices/bus/coco/coco_fdc.cpp b/src/devices/bus/coco/coco_fdc.cpp
index c8a6535c83a..06526073ca4 100644
--- a/src/devices/bus/coco/coco_fdc.cpp
+++ b/src/devices/bus/coco/coco_fdc.cpp
@@ -399,7 +399,7 @@ WRITE8_MEMBER(coco_fdc_device_base::scs_write)
ROM_START(coco_fdc)
ROM_REGION(0x4000, "eprom", ROMREGION_ERASE00)
- ROM_LOAD_OPTIONAL("disk10.rom", 0x0000, 0x2000, CRC(b4f9968e) SHA1(04115be3f97952b9d9310b52f806d04f80b40d03))
+ ROM_LOAD("disk10.rom", 0x0000, 0x2000, CRC(b4f9968e) SHA1(04115be3f97952b9d9310b52f806d04f80b40d03))
ROM_END
namespace
@@ -433,7 +433,7 @@ DEFINE_DEVICE_TYPE_PRIVATE(COCO_FDC, coco_family_fdc_device_base, coco_fdc_devic
ROM_START(coco_fdc_v11)
ROM_REGION(0x8000, "eprom", ROMREGION_ERASE00)
- ROM_LOAD_OPTIONAL("disk11.rom", 0x0000, 0x2000, CRC(0b9c5415) SHA1(10bdc5aa2d7d7f205f67b47b19003a4bd89defd1))
+ ROM_LOAD("disk11.rom", 0x0000, 0x2000, CRC(0b9c5415) SHA1(10bdc5aa2d7d7f205f67b47b19003a4bd89defd1))
ROM_RELOAD(0x2000, 0x2000)
ROM_RELOAD(0x4000, 0x2000)
ROM_RELOAD(0x6000, 0x2000)
diff --git a/src/devices/bus/coco/dragon_fdc.cpp b/src/devices/bus/coco/dragon_fdc.cpp
index 484802c6e1e..80fa31b0c98 100644
--- a/src/devices/bus/coco/dragon_fdc.cpp
+++ b/src/devices/bus/coco/dragon_fdc.cpp
@@ -367,7 +367,7 @@ WRITE8_MEMBER(premier_fdc_device_base::scs_write)
ROM_START(dragon_fdc)
ROM_REGION(0x4000, "eprom", ROMREGION_ERASE00)
- ROM_LOAD_OPTIONAL("ddos10.rom", 0x0000, 0x2000, CRC(b44536f6) SHA1(a8918c71d319237c1e3155bb38620acb114a80bc))
+ ROM_LOAD("ddos10.rom", 0x0000, 0x2000, CRC(b44536f6) SHA1(a8918c71d319237c1e3155bb38620acb114a80bc))
ROM_END
namespace
@@ -399,7 +399,7 @@ DEFINE_DEVICE_TYPE_PRIVATE(DRAGON_FDC, device_cococart_interface, dragon_fdc_dev
ROM_START(premier_fdc)
ROM_REGION(0x4000, "eprom", ROMREGION_ERASE00)
- ROM_LOAD_OPTIONAL("deltados.rom", 0x0000, 0x2000, CRC(149eb4dd) SHA1(eb686ce6afe63e4d4011b333a882ca812c69307f))
+ ROM_LOAD("deltados.rom", 0x0000, 0x2000, CRC(149eb4dd) SHA1(eb686ce6afe63e4d4011b333a882ca812c69307f))
ROM_END
namespace
@@ -431,7 +431,7 @@ DEFINE_DEVICE_TYPE_PRIVATE(PREMIER_FDC, device_cococart_interface, premier_fdc_d
ROM_START(sdtandy_fdc)
ROM_REGION(0x4000, "eprom", ROMREGION_ERASE00)
- ROM_LOAD_OPTIONAL("sdtandy.rom", 0x0000, 0x2000, CRC(5d7779b7) SHA1(ca03942118f2deab2f6c8a89b8a4f41f2d0b94f1))
+ ROM_LOAD("sdtandy.rom", 0x0000, 0x2000, CRC(5d7779b7) SHA1(ca03942118f2deab2f6c8a89b8a4f41f2d0b94f1))
ROM_END
namespace
diff --git a/src/devices/bus/cpc/cpc_rs232.cpp b/src/devices/bus/cpc/cpc_rs232.cpp
index 603e5e64625..cedbc6bfaf3 100644
--- a/src/devices/bus/cpc/cpc_rs232.cpp
+++ b/src/devices/bus/cpc/cpc_rs232.cpp
@@ -34,13 +34,13 @@ ROM_END
// device machine config
MACHINE_CONFIG_START(cpc_rs232_device::device_add_mconfig)
- MCFG_DEVICE_ADD(m_pit, PIT8253, 0)
- MCFG_PIT8253_CLK0(2000000)
- MCFG_PIT8253_CLK1(2000000)
- MCFG_PIT8253_CLK2(2000000)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, cpc_rs232_device, pit_out0_w))
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(*this, cpc_rs232_device, pit_out1_w))
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, cpc_rs232_device, pit_out2_w))
+ PIT8253(config, m_pit, 0);
+ m_pit->set_clk<0>(2000000);
+ m_pit->set_clk<1>(2000000);
+ m_pit->set_clk<2>(2000000);
+ m_pit->out_handler<0>().set(FUNC(cpc_rs232_device::pit_out0_w));
+ m_pit->out_handler<1>().set(FUNC(cpc_rs232_device::pit_out1_w));
+ m_pit->out_handler<2>().set(FUNC(cpc_rs232_device::pit_out2_w));
Z80DART(config, m_dart, XTAL(4'000'000));
m_dart->out_txda_callback().set(m_rs232, FUNC(rs232_port_device::write_txd));
diff --git a/src/devices/bus/dmv/k220.cpp b/src/devices/bus/dmv/k220.cpp
index 8776ae629d5..4fff4f5b2bf 100644
--- a/src/devices/bus/dmv/k220.cpp
+++ b/src/devices/bus/dmv/k220.cpp
@@ -158,18 +158,19 @@ void dmv_k220_device::device_reset()
// device_add_mconfig - add device configuration
//-------------------------------------------------
-MACHINE_CONFIG_START(dmv_k220_device::device_add_mconfig)
+void dmv_k220_device::device_add_mconfig(machine_config &config)
+{
I8255(config, m_ppi);
m_ppi->out_pa_callback().set(FUNC(dmv_k220_device::porta_w));
m_ppi->in_pb_callback().set_ioport("SWITCH");
m_ppi->out_pc_callback().set(FUNC(dmv_k220_device::portc_w));
- MCFG_DEVICE_ADD("pit8253", PIT8253, 0)
- MCFG_PIT8253_CLK0(XTAL(1'000'000)) // CLK1
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, dmv_k220_device, write_out0))
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(*this, dmv_k220_device, write_out1))
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, dmv_k220_device, write_out2))
-MACHINE_CONFIG_END
+ PIT8253(config, m_pit, 0);
+ m_pit->set_clk<0>(XTAL(1'000'000)); // CLK1
+ m_pit->out_handler<0>().set(FUNC(dmv_k220_device::write_out0));
+ m_pit->out_handler<1>().set(FUNC(dmv_k220_device::write_out1));
+ m_pit->out_handler<2>().set(FUNC(dmv_k220_device::write_out2));
+}
//-------------------------------------------------
// input_ports - device-specific input ports
diff --git a/src/devices/bus/dmv/k230.cpp b/src/devices/bus/dmv/k230.cpp
index 82c2e548012..9104abe2f7b 100644
--- a/src/devices/bus/dmv/k230.cpp
+++ b/src/devices/bus/dmv/k230.cpp
@@ -46,19 +46,19 @@ void dmv_k230_device::k230_io(address_map &map)
map(0x00, 0xff).rw(FUNC(dmv_k230_device::io_r), FUNC(dmv_k230_device::io_w));
}
-void dmv_k230_device::k234_mem(address_map &map)
+void dmv_k234_device::k234_mem(address_map &map)
{
map.unmap_value_high();
- map(0x00000, 0x7ffff).rw(FUNC(dmv_k230_device::program_r), FUNC(dmv_k230_device::program_w));
- map(0xfff00, 0xfffff).rw(FUNC(dmv_k230_device::io_r), FUNC(dmv_k230_device::io_w));
+ map(0x00000, 0x7ffff).rw(FUNC(dmv_k234_device::program_r), FUNC(dmv_k234_device::program_w));
+ map(0xfff00, 0xfffff).rw(FUNC(dmv_k234_device::io_r), FUNC(dmv_k234_device::io_w));
}
-void dmv_k230_device::k235_io(address_map &map)
+void dmv_k235_device::k235_io(address_map &map)
{
map.unmap_value_high();
map.global_mask(0xff);
- map(0x00, 0xff).rw(FUNC(dmv_k230_device::io_r), FUNC(dmv_k230_device::io_w));
- map(0x90, 0x91).rw("pic8259", FUNC(pic8259_device::read), FUNC(pic8259_device::write));
+ map(0x00, 0xff).rw(FUNC(dmv_k235_device::io_r), FUNC(dmv_k235_device::io_w));
+ map(0x90, 0x91).rw(m_pic, FUNC(pic8259_device::read), FUNC(pic8259_device::write));
}
static INPUT_PORTS_START( dmv_k235 )
@@ -166,26 +166,29 @@ void dmv_k234_device::device_reset()
// device_add_mconfig - add device configuration
//-------------------------------------------------
-MACHINE_CONFIG_START(dmv_k230_device::device_add_mconfig)
- MCFG_DEVICE_ADD("maincpu", I8088, XTAL(15'000'000) / 3)
- MCFG_DEVICE_PROGRAM_MAP(k230_mem)
- MCFG_DEVICE_IO_MAP(k230_io)
-MACHINE_CONFIG_END
-
-MACHINE_CONFIG_START(dmv_k234_device::device_add_mconfig)
- MCFG_DEVICE_ADD("maincpu", M68008, XTAL(16'000'000) / 2)
- MCFG_DEVICE_PROGRAM_MAP(k234_mem)
-MACHINE_CONFIG_END
-
-MACHINE_CONFIG_START(dmv_k235_device::device_add_mconfig)
- MCFG_DEVICE_ADD("maincpu", V20, XTAL(15'000'000) / 3)
- MCFG_DEVICE_PROGRAM_MAP(k230_mem)
- MCFG_DEVICE_IO_MAP(k235_io)
- MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE("pic8259", pic8259_device, inta_cb)
-
- MCFG_DEVICE_ADD("pic8259", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE("maincpu", 0))
-MACHINE_CONFIG_END
+void dmv_k230_device::device_add_mconfig(machine_config &config)
+{
+ I8088(config, m_maincpu, XTAL(15'000'000) / 3);
+ m_maincpu->set_addrmap(AS_PROGRAM, &dmv_k230_device::k230_mem);
+ m_maincpu->set_addrmap(AS_IO, &dmv_k230_device::k230_io);
+}
+
+void dmv_k234_device::device_add_mconfig(machine_config &config)
+{
+ M68008(config, m_maincpu, XTAL(16'000'000) / 2);
+ m_maincpu->set_addrmap(AS_PROGRAM, &dmv_k234_device::k234_mem);
+}
+
+void dmv_k235_device::device_add_mconfig(machine_config &config)
+{
+ V20(config, m_maincpu, XTAL(15'000'000) / 3);
+ m_maincpu->set_addrmap(AS_PROGRAM, &dmv_k235_device::k230_mem);
+ m_maincpu->set_addrmap(AS_IO, &dmv_k235_device::k235_io);
+ m_maincpu->set_irq_acknowledge_callback("pic8259", FUNC(pic8259_device::inta_cb));
+
+ PIC8259(config, m_pic, 0);
+ m_pic->out_int_callback().set_inputline(m_maincpu, 0);
+}
//-------------------------------------------------
// device_rom_region
diff --git a/src/devices/bus/dmv/k230.h b/src/devices/bus/dmv/k230.h
index 0e7bd6b19f5..7021a4a8987 100644
--- a/src/devices/bus/dmv/k230.h
+++ b/src/devices/bus/dmv/k230.h
@@ -48,8 +48,6 @@ protected:
void k230_io(address_map &map);
void k230_mem(address_map &map);
- void k234_mem(address_map &map);
- void k235_io(address_map &map);
required_device<cpu_device> m_maincpu;
optional_memory_region m_rom;
@@ -58,11 +56,12 @@ protected:
int m_switch16;
int m_hold;
-private:
DECLARE_READ8_MEMBER(io_r);
DECLARE_READ8_MEMBER(program_r);
DECLARE_WRITE8_MEMBER(io_w);
DECLARE_WRITE8_MEMBER(program_w);
+
+private:
DECLARE_READ8_MEMBER(rom_r);
};
@@ -108,6 +107,8 @@ private:
DECLARE_READ8_MEMBER(snr_r);
DECLARE_WRITE8_MEMBER(snr_w);
+
+ void k234_mem(address_map &map);
};
@@ -140,6 +141,8 @@ protected:
private:
required_device<pic8259_device> m_pic;
required_ioport m_dsw;
+
+ void k235_io(address_map &map);
};
// device type definition
diff --git a/src/devices/bus/isa/ibm_mfc.cpp b/src/devices/bus/isa/ibm_mfc.cpp
index 6ffed8dd904..d6c5c4a98ce 100644
--- a/src/devices/bus/isa/ibm_mfc.cpp
+++ b/src/devices/bus/isa/ibm_mfc.cpp
@@ -395,13 +395,13 @@ MACHINE_CONFIG_START(isa8_ibm_mfc_device::device_add_mconfig)
MCFG_DEVICE_ADD("usart_clock", CLOCK, XTAL(4'000'000) / 8) // 500KHz
MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(*this, isa8_ibm_mfc_device, write_usart_clock))
- MCFG_DEVICE_ADD("d8253", PIT8253, 0)
- MCFG_PIT8253_CLK0(XTAL(4'000'000) / 8)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, isa8_ibm_mfc_device, d8253_out0))
- MCFG_PIT8253_CLK1(0)
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(*this, isa8_ibm_mfc_device, d8253_out1))
- MCFG_PIT8253_CLK2(XTAL(4'000'000) / 2)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE("d8253", pit8253_device, write_clk1))
+ PIT8253(config, m_d8253, 0);
+ m_d8253->set_clk<0>(XTAL(4'000'000) / 8);
+ m_d8253->out_handler<0>().set(FUNC(isa8_ibm_mfc_device::d8253_out0));
+ m_d8253->set_clk<1>(0);
+ m_d8253->out_handler<1>().set(FUNC(isa8_ibm_mfc_device::d8253_out1));
+ m_d8253->set_clk<2>(XTAL(4'000'000) / 2);
+ m_d8253->out_handler<2>().set(m_d8253, FUNC(pit8253_device::write_clk1));
SPEAKER(config, "ymleft").front_left();
SPEAKER(config, "ymright").front_right();
diff --git a/src/devices/bus/isa/myb3k_com.cpp b/src/devices/bus/isa/myb3k_com.cpp
index a3f2fd79879..88987e87e41 100644
--- a/src/devices/bus/isa/myb3k_com.cpp
+++ b/src/devices/bus/isa/myb3k_com.cpp
@@ -31,7 +31,8 @@ DEFINE_DEVICE_TYPE(ISA8_MYB3K_COM, isa8_myb3k_com_device, "isa8_myb3k_com", "ADP
//-------------------------------------------------
// device_add_mconfig - add device configuration
//-------------------------------------------------
-MACHINE_CONFIG_START(isa8_myb3k_com_device::device_add_mconfig)
+void isa8_myb3k_com_device::device_add_mconfig(machine_config &config)
+{
I8251( config, m_usart, XTAL(15'974'400) / 8 );
m_usart->txd_handler().set("com1", FUNC(rs232_port_device::write_txd));
m_usart->dtr_handler().set("com1", FUNC(rs232_port_device::write_dtr));
@@ -48,13 +49,13 @@ MACHINE_CONFIG_START(isa8_myb3k_com_device::device_add_mconfig)
// TODO: configure RxC and TxC from RS232 connector when these are defined is rs232.h
/* Timer chip */
- MCFG_DEVICE_ADD("pit", PIT8253, 0)
- MCFG_PIT8253_CLK0(XTAL(15'974'400) / 8 ) /* TxC */
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, isa8_myb3k_com_device, pit_txc))
- MCFG_PIT8253_CLK1(XTAL(15'974'400) / 8 ) /* RxC */
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(*this, isa8_myb3k_com_device, pit_rxc))
+ pit8253_device &pit(PIT8253(config, "pit", 0));
+ pit.set_clk<0>(XTAL(15'974'400) / 8); /* TxC */
+ pit.out_handler<0>().set(FUNC(isa8_myb3k_com_device::pit_txc));
+ pit.set_clk<1>(XTAL(15'974'400) / 8); /* RxC */
+ pit.out_handler<1>().set(FUNC(isa8_myb3k_com_device::pit_rxc));
// Timer 2 is not used/connected to anything on the schematics
-MACHINE_CONFIG_END
+}
// PORT definitions moved to the end of this file as it became very long
diff --git a/src/devices/bus/isa/p1_sound.cpp b/src/devices/bus/isa/p1_sound.cpp
index 4d24328395f..485dca5205e 100644
--- a/src/devices/bus/isa/p1_sound.cpp
+++ b/src/devices/bus/isa/p1_sound.cpp
@@ -39,30 +39,30 @@ MACHINE_CONFIG_START(p1_sound_device::device_add_mconfig)
MCFG_MIDI_PORT_ADD("mdout", midiout_slot, "midiout")
- MCFG_DEVICE_ADD("d14", PIT8253, 0)
- MCFG_PIT8253_CLK0(XTAL(12'500'000)/10)
+ PIT8253(config, m_d14, 0);
+ m_d14->set_clk<0>(XTAL(12'500'000)/10);
// sampler at 10 KHz
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, p1_sound_device, sampler_sync))
- MCFG_PIT8253_CLK1(XTAL(12'500'000)/10)
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE("midi", i8251_device, write_txc))
- MCFG_PIT8253_CLK2(XTAL(12'500'000)/10)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE("midi", i8251_device, write_rxc))
-
- MCFG_DEVICE_ADD("d16", PIT8253, 0)
- MCFG_PIT8253_CLK0(XTAL(12'500'000)/10)
-// MCFG_PIT8253_OUT0_HANDLER(XXX)
- MCFG_PIT8253_CLK1(XTAL(12'500'000)/10)
-// MCFG_PIT8253_OUT1_HANDLER(XXX)
- MCFG_PIT8253_CLK2(XTAL(12'500'000)/10)
-// MCFG_PIT8253_OUT2_HANDLER(XXX)
-
- MCFG_DEVICE_ADD("d17", PIT8253, 0)
- MCFG_PIT8253_CLK0(XTAL(12'500'000)/10)
-// MCFG_PIT8253_OUT0_HANDLER(XXX)
- MCFG_PIT8253_CLK1(XTAL(12'500'000)/10)
-// MCFG_PIT8253_OUT1_HANDLER(XXX)
- MCFG_PIT8253_CLK2(XTAL(12'500'000)/10)
-// MCFG_PIT8253_OUT2_HANDLER(XXX)
+ m_d14->out_handler<0>().set(FUNC(p1_sound_device::sampler_sync));
+ m_d14->set_clk<1>(XTAL(12'500'000)/10);
+ m_d14->out_handler<1>().set(m_midi, FUNC(i8251_device::write_txc));
+ m_d14->set_clk<2>(XTAL(12'500'000)/10);
+ m_d14->out_handler<2>().set(m_midi, FUNC(i8251_device::write_rxc));
+
+ PIT8253(config, m_d16, 0);
+ m_d16->set_clk<0>(XTAL(12'500'000)/10);
+// m_d16->out_handler<0>().set(FUNC(XXX));
+ m_d16->set_clk<1>(XTAL(12'500'000)/10);
+// m_d16->out_handler<1>().set(FUNC(XXX));
+ m_d16->set_clk<2>(XTAL(12'500'000)/10);
+// m_d16->out_handler<2>().set(FUNC(XXX));
+
+ PIT8253(config, m_d17, 0);
+ m_d17->set_clk<0>(XTAL(12'500'000)/10);
+// m_d17->out_handler<0>().set(FUNC(XXX));
+ m_d17->set_clk<1>(XTAL(12'500'000)/10);
+// m_d17->out_handler<1>().set(FUNC(XXX));
+ m_d17->set_clk<2>(XTAL(12'500'000)/10);
+// m_d17->out_handler<2>().set(FUNC(XXX));
SPEAKER(config, "speaker").front_center();
MCFG_DEVICE_ADD("filter", FILTER_RC)
diff --git a/src/devices/bus/s100/wunderbus.cpp b/src/devices/bus/s100/wunderbus.cpp
index 7606ea447e5..43b7be095a3 100644
--- a/src/devices/bus/s100/wunderbus.cpp
+++ b/src/devices/bus/s100/wunderbus.cpp
@@ -87,28 +87,29 @@ WRITE_LINE_MEMBER( s100_wunderbus_device::rtc_tp_w )
//-------------------------------------------------
-MACHINE_CONFIG_START(s100_wunderbus_device::device_add_mconfig)
- MCFG_DEVICE_ADD(I8259A_TAG, PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(WRITELINE(*this, s100_wunderbus_device, pic_int_w))
- MCFG_PIC8259_IN_SP_CB(CONSTANT(1))
+void s100_wunderbus_device::device_add_mconfig(machine_config &config)
+{
+ PIC8259(config, m_pic, 0);
+ m_pic->out_int_callback().set(FUNC(s100_wunderbus_device::pic_int_w));
+ m_pic->in_sp_callback().set_constant(1);
INS8250(config, m_ace1, XTAL(18'432'000)/10);
m_ace1->out_tx_callback().set(RS232_A_TAG, FUNC(rs232_port_device::write_txd));
m_ace1->out_dtr_callback().set(RS232_A_TAG, FUNC(rs232_port_device::write_dtr));
m_ace1->out_rts_callback().set(RS232_A_TAG, FUNC(rs232_port_device::write_rts));
- m_ace1->out_int_callback().set(I8259A_TAG, FUNC(pic8259_device::ir3_w));
+ m_ace1->out_int_callback().set(m_pic, FUNC(pic8259_device::ir3_w));
INS8250(config, m_ace2, XTAL(18'432'000)/10);
m_ace2->out_tx_callback().set(RS232_B_TAG, FUNC(rs232_port_device::write_txd));
m_ace2->out_dtr_callback().set(RS232_B_TAG, FUNC(rs232_port_device::write_dtr));
m_ace2->out_rts_callback().set(RS232_B_TAG, FUNC(rs232_port_device::write_rts));
- m_ace2->out_int_callback().set(I8259A_TAG, FUNC(pic8259_device::ir4_w));
+ m_ace2->out_int_callback().set(m_pic, FUNC(pic8259_device::ir4_w));
INS8250(config, m_ace3, XTAL(18'432'000)/10);
m_ace3->out_tx_callback().set(RS232_C_TAG, FUNC(rs232_port_device::write_txd));
m_ace3->out_dtr_callback().set(RS232_C_TAG, FUNC(rs232_port_device::write_dtr));
m_ace3->out_rts_callback().set(RS232_C_TAG, FUNC(rs232_port_device::write_rts));
- m_ace3->out_int_callback().set(I8259A_TAG, FUNC(pic8259_device::ir5_w));
+ m_ace3->out_int_callback().set(m_pic, FUNC(pic8259_device::ir5_w));
rs232_port_device &rs232a(RS232_PORT(config, RS232_A_TAG, default_rs232_devices, "terminal"));
rs232a.rxd_handler().set(m_ace1, FUNC(ins8250_uart_device::rx_w));
@@ -134,7 +135,7 @@ MACHINE_CONFIG_START(s100_wunderbus_device::device_add_mconfig)
UPD1990A(config, m_rtc);
m_rtc->tp_callback().set(FUNC(s100_wunderbus_device::rtc_tp_w));
-MACHINE_CONFIG_END
+}
//-------------------------------------------------
diff --git a/src/devices/cpu/i386/i386.cpp b/src/devices/cpu/i386/i386.cpp
index 06fbfca3fb5..9952755dc22 100644
--- a/src/devices/cpu/i386/i386.cpp
+++ b/src/devices/cpu/i386/i386.cpp
@@ -99,26 +99,31 @@ mediagx_device::mediagx_device(const machine_config &mconfig, const char *tag, d
}
pentium_pro_device::pentium_pro_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : pentium_device(mconfig, PENTIUM_PRO, tag, owner, clock)
+ : pentium_pro_device(mconfig, PENTIUM_PRO, tag, owner, clock)
+{
+}
+
+pentium_pro_device::pentium_pro_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
+ : pentium_device(mconfig, type, tag, owner, clock)
{
}
pentium_mmx_device::pentium_mmx_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : pentium_device(mconfig, PENTIUM_MMX, tag, owner, clock)
+ : pentium_pro_device(mconfig, PENTIUM_MMX, tag, owner, clock)
{
// 64 dtlb small, 8 dtlb large, 32 itlb small, 2 itlb large
set_vtlb_dynamic_entries(96);
}
pentium2_device::pentium2_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : pentium_device(mconfig, PENTIUM2, tag, owner, clock)
+ : pentium_pro_device(mconfig, PENTIUM2, tag, owner, clock)
{
// 64 dtlb small, 8 dtlb large, 32 itlb small, 2 itlb large
set_vtlb_dynamic_entries(96);
}
pentium3_device::pentium3_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : pentium_device(mconfig, PENTIUM3, tag, owner, clock)
+ : pentium_pro_device(mconfig, PENTIUM3, tag, owner, clock)
{
// 64 dtlb small, 8 dtlb large, 32 itlb small, 2 itlb large
set_vtlb_dynamic_entries(96);
@@ -4039,6 +4044,24 @@ std::unique_ptr<util::disasm_interface> i386_device::create_disassembler()
return std::make_unique<i386_disassembler>(this);
}
+void i386_device::opcode_cpuid()
+{
+ logerror("CPUID called with unsupported EAX=%08x at %08x!\n", REG32(EAX), m_eip);
+}
+
+uint64_t i386_device::opcode_rdmsr(bool &valid_msr)
+{
+ valid_msr = false;
+ logerror("RDMSR called with unsupported ECX=%08x at %08x!\n", REG32(ECX), m_eip);
+ return -1;
+}
+
+void i386_device::opcode_wrmsr(uint64_t data, bool &valid_msr)
+{
+ valid_msr = false;
+ logerror("WRMSR called with unsupported ECX=%08x (%08x%08x) at %08x!\n", REG32(ECX), (uint32_t)(data >> 32), (uint32_t)data, m_eip);
+}
+
/*****************************************************************************/
/* Intel 486 */
@@ -4177,6 +4200,98 @@ void pentium_device::device_reset()
CHANGE_PC(m_eip);
}
+uint64_t pentium_device::opcode_rdmsr(bool &valid_msr)
+{
+ uint32_t offset = REG32(ECX);
+
+ switch (offset)
+ {
+ // Machine Check Exception (TODO)
+ case 0x00:
+ valid_msr = true;
+ popmessage("RDMSR: Reading P5_MC_ADDR");
+ return 0;
+ case 0x01:
+ valid_msr = true;
+ popmessage("RDMSR: Reading P5_MC_TYPE");
+ return 0;
+ // Time Stamp Counter
+ case 0x10:
+ valid_msr = true;
+ popmessage("RDMSR: Reading TSC");
+ return m_tsc;
+ // Event Counters (TODO)
+ case 0x11: // CESR
+ valid_msr = true;
+ popmessage("RDMSR: Reading CESR");
+ return 0;
+ case 0x12: // CTR0
+ valid_msr = true;
+ return m_perfctr[0];
+ case 0x13: // CTR1
+ valid_msr = true;
+ return m_perfctr[1];
+ default:
+ if (!(offset & ~0xf)) // 2-f are test registers
+ {
+ valid_msr = true;
+ logerror("RDMSR: Reading test MSR %x", offset);
+ return 0;
+ }
+ logerror("RDMSR: invalid P5 MSR read %08x at %08x\n", offset, m_pc - 2);
+ valid_msr = false;
+ return 0;
+ }
+ return -1;
+}
+
+void pentium_device::opcode_wrmsr(uint64_t data, bool &valid_msr)
+{
+ uint32_t offset = REG32(ECX);
+
+ switch (offset)
+ {
+ // Machine Check Exception (TODO)
+ case 0x00:
+ popmessage("WRMSR: Writing P5_MC_ADDR");
+ valid_msr = true;
+ break;
+ case 0x01:
+ popmessage("WRMSR: Writing P5_MC_TYPE");
+ valid_msr = true;
+ break;
+ // Time Stamp Counter
+ case 0x10:
+ m_tsc = data;
+ popmessage("WRMSR: Writing to TSC");
+ valid_msr = true;
+ break;
+ // Event Counters (TODO)
+ case 0x11: // CESR
+ popmessage("WRMSR: Writing to CESR");
+ valid_msr = true;
+ break;
+ case 0x12: // CTR0
+ m_perfctr[0] = data;
+ valid_msr = true;
+ break;
+ case 0x13: // CTR1
+ m_perfctr[1] = data;
+ valid_msr = true;
+ break;
+ default:
+ if (!(offset & ~0xf)) // 2-f are test registers
+ {
+ valid_msr = true;
+ logerror("WRMSR: Writing test MSR %x", offset);
+ break;
+ }
+ logerror("WRMSR: invalid MSR write %08x (%08x%08x) at %08x\n", offset, (uint32_t)(data >> 32), (uint32_t)data, m_pc - 2);
+ valid_msr = false;
+ break;
+ }
+}
+
/*****************************************************************************/
/* Cyrix MediaGX */
@@ -4314,6 +4429,69 @@ void pentium_pro_device::device_reset()
CHANGE_PC(m_eip);
}
+uint64_t pentium_pro_device::opcode_rdmsr(bool &valid_msr)
+{
+ uint32_t offset = REG32(ECX);
+
+ switch (offset)
+ {
+ // Machine Check Exception (TODO)
+ case 0x00:
+ valid_msr = true;
+ popmessage("RDMSR: Reading P5_MC_ADDR");
+ return 0;
+ case 0x01:
+ valid_msr = true;
+ popmessage("RDMSR: Reading P5_MC_TYPE");
+ return 0;
+ // Time Stamp Counter
+ case 0x10:
+ valid_msr = true;
+ popmessage("RDMSR: Reading TSC");
+ return m_tsc;
+ // Performance Counters (TODO)
+ case 0xc1: // PerfCtr0
+ valid_msr = true;
+ return m_perfctr[0];
+ case 0xc2: // PerfCtr1
+ valid_msr = true;
+ return m_perfctr[1];
+ default:
+ logerror("RDMSR: unimplemented register called %08x at %08x\n", offset, m_pc - 2);
+ valid_msr = true;
+ return 0;
+ }
+ return -1;
+}
+
+void pentium_pro_device::opcode_wrmsr(uint64_t data, bool &valid_msr)
+{
+ uint32_t offset = REG32(ECX);
+
+ switch (offset)
+ {
+ // Time Stamp Counter
+ case 0x10:
+ m_tsc = data;
+ popmessage("WRMSR: Writing to TSC");
+ valid_msr = true;
+ break;
+ // Performance Counters (TODO)
+ case 0xc1: // PerfCtr0
+ m_perfctr[0] = data;
+ valid_msr = true;
+ break;
+ case 0xc2: // PerfCtr1
+ m_perfctr[1] = data;
+ valid_msr = true;
+ break;
+ default:
+ logerror("WRMSR: unimplemented register called %08x (%08x%08x) at %08x\n", offset, (uint32_t)(data >> 32), (uint32_t)data, m_pc - 2);
+ valid_msr = true;
+ break;
+ }
+}
+
/*****************************************************************************/
/* Intel Pentium MMX */
@@ -4655,3 +4833,26 @@ void pentium4_device::device_reset()
CHANGE_PC(m_eip);
}
+
+uint64_t pentium4_device::opcode_rdmsr(bool &valid_msr)
+{
+ switch (REG32(ECX))
+ {
+ default:
+ logerror("RDMSR: unimplemented register called %08x at %08x\n", REG32(ECX), m_pc - 2);
+ valid_msr = true;
+ return 0;
+ }
+ return -1;
+}
+
+void pentium4_device::opcode_wrmsr(uint64_t data, bool &valid_msr)
+{
+ switch (REG32(ECX))
+ {
+ default:
+ logerror("WRMSR: unimplemented register called %08x (%08x%08x) at %08x\n", REG32(ECX), (uint32_t)(data >> 32), (uint32_t)data, m_pc - 2);
+ valid_msr = true;
+ break;
+ }
+}
diff --git a/src/devices/cpu/i386/i386.h b/src/devices/cpu/i386/i386.h
index 70db1238b8f..340e7a0c256 100644
--- a/src/devices/cpu/i386/i386.h
+++ b/src/devices/cpu/i386/i386.h
@@ -77,6 +77,12 @@ protected:
virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
virtual int get_mode() const override;
+ // routines for opcodes whose operation can vary between cpu models
+ // default implementations just log an error message
+ virtual void opcode_cpuid();
+ virtual uint64_t opcode_rdmsr(bool &valid_msr);
+ virtual void opcode_wrmsr(uint64_t data, bool &valid_msr);
+
address_space_config m_program_config;
address_space_config m_io_config;
@@ -425,14 +431,6 @@ protected:
inline void WRITEPORT16(offs_t port, uint16_t value);
inline uint32_t READPORT32(offs_t port);
inline void WRITEPORT32(offs_t port, uint32_t value);
- uint64_t pentium_msr_read(uint32_t offset,uint8_t *valid_msr);
- void pentium_msr_write(uint32_t offset, uint64_t data, uint8_t *valid_msr);
- uint64_t p6_msr_read(uint32_t offset,uint8_t *valid_msr);
- void p6_msr_write(uint32_t offset, uint64_t data, uint8_t *valid_msr);
- uint64_t piv_msr_read(uint32_t offset,uint8_t *valid_msr);
- void piv_msr_write(uint32_t offset, uint64_t data, uint8_t *valid_msr);
- inline uint64_t MSR_READ(uint32_t offset,uint8_t *valid_msr);
- inline void MSR_WRITE(uint32_t offset, uint64_t data, uint8_t *valid_msr);
uint32_t i386_load_protected_mode_segment(I386_SREG *seg, uint64_t *desc );
void i386_load_call_gate(I386_CALL_GATE *gate);
void i386_set_descriptor_accessed(uint16_t selector);
@@ -1542,6 +1540,8 @@ protected:
virtual bool execute_input_edge_triggered(int inputnum) const override { return inputnum == INPUT_LINE_NMI || inputnum == INPUT_LINE_SMI; }
virtual void execute_set_input(int inputnum, int state) override;
+ virtual uint64_t opcode_rdmsr(bool &valid_msr) override;
+ virtual void opcode_wrmsr(uint64_t data, bool &valid_msr) override;
virtual void device_start() override;
virtual void device_reset() override;
};
@@ -1566,12 +1566,16 @@ public:
pentium_pro_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
+ pentium_pro_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
+
+ virtual uint64_t opcode_rdmsr(bool &valid_msr) override;
+ virtual void opcode_wrmsr(uint64_t data, bool &valid_msr) override;
virtual void device_start() override;
virtual void device_reset() override;
};
-class pentium_mmx_device : public pentium_device
+class pentium_mmx_device : public pentium_pro_device
{
public:
// construction/destruction
@@ -1583,7 +1587,7 @@ protected:
};
-class pentium2_device : public pentium_device
+class pentium2_device : public pentium_pro_device
{
public:
// construction/destruction
@@ -1595,7 +1599,7 @@ protected:
};
-class pentium3_device : public pentium_device
+class pentium3_device : public pentium_pro_device
{
public:
// construction/destruction
@@ -1626,6 +1630,8 @@ public:
pentium4_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
+ virtual uint64_t opcode_rdmsr(bool &valid_msr) override;
+ virtual void opcode_wrmsr(uint64_t data, bool &valid_msr) override;
virtual void device_start() override;
virtual void device_reset() override;
};
diff --git a/src/devices/cpu/i386/i386priv.h b/src/devices/cpu/i386/i386priv.h
index f341edf2551..1e5439f205f 100644
--- a/src/devices/cpu/i386/i386priv.h
+++ b/src/devices/cpu/i386/i386priv.h
@@ -1200,227 +1200,4 @@ void i386_device::WRITEPORT32(offs_t port, uint32_t value)
}
}
-/***********************************************************************************
- MSR ACCESS
-***********************************************************************************/
-
-// Pentium MSR handling
-uint64_t i386_device::pentium_msr_read(uint32_t offset,uint8_t *valid_msr)
-{
- switch(offset)
- {
- // Machine Check Exception (TODO)
- case 0x00:
- *valid_msr = 1;
- popmessage("RDMSR: Reading P5_MC_ADDR");
- return 0;
- case 0x01:
- *valid_msr = 1;
- popmessage("RDMSR: Reading P5_MC_TYPE");
- return 0;
- // Time Stamp Counter
- case 0x10:
- *valid_msr = 1;
- popmessage("RDMSR: Reading TSC");
- return m_tsc;
- // Event Counters (TODO)
- case 0x11: // CESR
- *valid_msr = 1;
- popmessage("RDMSR: Reading CESR");
- return 0;
- case 0x12: // CTR0
- *valid_msr = 1;
- return m_perfctr[0];
- case 0x13: // CTR1
- *valid_msr = 1;
- return m_perfctr[1];
- default:
- if(!(offset & ~0xf)) // 2-f are test registers
- {
- *valid_msr = 1;
- logerror("RDMSR: Reading test MSR %x", offset);
- return 0;
- }
- logerror("RDMSR: invalid P5 MSR read %08x at %08x\n",offset,m_pc-2);
- *valid_msr = 0;
- return 0;
- }
- return -1;
-}
-
-void i386_device::pentium_msr_write(uint32_t offset, uint64_t data, uint8_t *valid_msr)
-{
- switch(offset)
- {
- // Machine Check Exception (TODO)
- case 0x00:
- popmessage("WRMSR: Writing P5_MC_ADDR");
- *valid_msr = 1;
- break;
- case 0x01:
- popmessage("WRMSR: Writing P5_MC_TYPE");
- *valid_msr = 1;
- break;
- // Time Stamp Counter
- case 0x10:
- m_tsc = data;
- popmessage("WRMSR: Writing to TSC");
- *valid_msr = 1;
- break;
- // Event Counters (TODO)
- case 0x11: // CESR
- popmessage("WRMSR: Writing to CESR");
- *valid_msr = 1;
- break;
- case 0x12: // CTR0
- m_perfctr[0] = data;
- *valid_msr = 1;
- break;
- case 0x13: // CTR1
- m_perfctr[1] = data;
- *valid_msr = 1;
- break;
- default:
- if(!(offset & ~0xf)) // 2-f are test registers
- {
- *valid_msr = 1;
- logerror("WRMSR: Writing test MSR %x", offset);
- break;
- }
- logerror("WRMSR: invalid MSR write %08x (%08x%08x) at %08x\n",offset,(uint32_t)(data >> 32),(uint32_t)data,m_pc-2);
- *valid_msr = 0;
- break;
- }
-}
-
-// P6 (Pentium Pro, Pentium II, Pentium III) MSR handling
-uint64_t i386_device::p6_msr_read(uint32_t offset,uint8_t *valid_msr)
-{
- switch(offset)
- {
- // Machine Check Exception (TODO)
- case 0x00:
- *valid_msr = 1;
- popmessage("RDMSR: Reading P5_MC_ADDR");
- return 0;
- case 0x01:
- *valid_msr = 1;
- popmessage("RDMSR: Reading P5_MC_TYPE");
- return 0;
- // Time Stamp Counter
- case 0x10:
- *valid_msr = 1;
- popmessage("RDMSR: Reading TSC");
- return m_tsc;
- // Performance Counters (TODO)
- case 0xc1: // PerfCtr0
- *valid_msr = 1;
- return m_perfctr[0];
- case 0xc2: // PerfCtr1
- *valid_msr = 1;
- return m_perfctr[1];
- default:
- logerror("RDMSR: unimplemented register called %08x at %08x\n",offset,m_pc-2);
- *valid_msr = 1;
- return 0;
- }
- return -1;
-}
-
-void i386_device::p6_msr_write(uint32_t offset, uint64_t data, uint8_t *valid_msr)
-{
- switch(offset)
- {
- // Time Stamp Counter
- case 0x10:
- m_tsc = data;
- popmessage("WRMSR: Writing to TSC");
- *valid_msr = 1;
- break;
- // Performance Counters (TODO)
- case 0xc1: // PerfCtr0
- m_perfctr[0] = data;
- *valid_msr = 1;
- break;
- case 0xc2: // PerfCtr1
- m_perfctr[1] = data;
- *valid_msr = 1;
- break;
- default:
- logerror("WRMSR: unimplemented register called %08x (%08x%08x) at %08x\n",offset,(uint32_t)(data >> 32),(uint32_t)data,m_pc-2);
- *valid_msr = 1;
- break;
- }
-}
-
-
-// PIV (Pentium 4+)
-uint64_t i386_device::piv_msr_read(uint32_t offset,uint8_t *valid_msr)
-{
- switch(offset)
- {
- default:
- logerror("RDMSR: unimplemented register called %08x at %08x\n",offset,m_pc-2);
- *valid_msr = 1;
- return 0;
- }
- return -1;
-}
-
-void i386_device::piv_msr_write(uint32_t offset, uint64_t data, uint8_t *valid_msr)
-{
- switch(offset)
- {
- default:
- logerror("WRMSR: unimplemented register called %08x (%08x%08x) at %08x\n",offset,(uint32_t)(data >> 32),(uint32_t)data,m_pc-2);
- *valid_msr = 1;
- break;
- }
-}
-
-uint64_t i386_device::MSR_READ(uint32_t offset,uint8_t *valid_msr)
-{
- uint64_t res;
- uint8_t cpu_type = (m_cpu_version >> 8) & 0x0f;
-
- *valid_msr = 0;
-
- switch(cpu_type)
- {
- case 5: // Pentium
- res = pentium_msr_read(offset,valid_msr);
- break;
- case 6: // Pentium Pro, Pentium II, Pentium III
- res = p6_msr_read(offset,valid_msr);
- break;
- case 15: // Pentium 4+
- res = piv_msr_read(offset,valid_msr);
- break;
- default:
- res = 0;
- break;
- }
-
- return res;
-}
-
-void i386_device::MSR_WRITE(uint32_t offset, uint64_t data, uint8_t *valid_msr)
-{
- *valid_msr = 0;
- uint8_t cpu_type = (m_cpu_version >> 8) & 0x0f;
-
- switch(cpu_type)
- {
- case 5: // Pentium
- pentium_msr_write(offset,data,valid_msr);
- break;
- case 6: // Pentium Pro, Pentium II, Pentium III
- p6_msr_write(offset,data,valid_msr);
- break;
- case 15: // Pentium 4+
- piv_msr_write(offset,data,valid_msr);
- break;
- }
-}
-
#endif /* __I386_H__ */
diff --git a/src/devices/cpu/i386/i486ops.hxx b/src/devices/cpu/i386/i486ops.hxx
index bb96ac5411b..37c8ee8d1c2 100644
--- a/src/devices/cpu/i386/i486ops.hxx
+++ b/src/devices/cpu/i386/i486ops.hxx
@@ -34,7 +34,8 @@ void i386_device::i486_cpuid() // Opcode 0x0F A2
default:
{
- logerror("CPUID called with unsupported EAX=%08x at %08x!\n", REG32(EAX), m_eip);
+ // call the model specific implementation
+ opcode_cpuid();
break;
}
}
diff --git a/src/devices/cpu/i386/pentops.hxx b/src/devices/cpu/i386/pentops.hxx
index ee67c5ca050..d5f6f6ca592 100644
--- a/src/devices/cpu/i386/pentops.hxx
+++ b/src/devices/cpu/i386/pentops.hxx
@@ -56,14 +56,17 @@ void i386_device::WRITEXMM_HI64(uint32_t ea,i386_device::XMM_REG &r)
void i386_device::pentium_rdmsr() // Opcode 0x0f 32
{
uint64_t data;
- uint8_t valid_msr = 0;
+ bool valid_msr = false;
- data = MSR_READ(REG32(ECX),&valid_msr);
- REG32(EDX) = data >> 32;
- REG32(EAX) = data & 0xffffffff;
-
- if(m_CPL != 0 || valid_msr == 0) // if current privilege level isn't 0 or the register isn't recognized ...
- FAULT(FAULT_GP,0) // ... throw a general exception fault
+ // call the model specific implementation
+ data = opcode_rdmsr(valid_msr);
+ if (m_CPL != 0 || valid_msr == false) // if current privilege level isn't 0 or the register isn't recognized ...
+ FAULT(FAULT_GP, 0) // ... throw a general exception fault
+ else
+ {
+ REG32(EDX) = data >> 32;
+ REG32(EAX) = data & 0xffffffff;
+ }
CYCLES(CYCLES_RDMSR);
}
@@ -71,12 +74,13 @@ void i386_device::pentium_rdmsr() // Opcode 0x0f 32
void i386_device::pentium_wrmsr() // Opcode 0x0f 30
{
uint64_t data;
- uint8_t valid_msr = 0;
+ bool valid_msr = false;
data = (uint64_t)REG32(EAX);
data |= (uint64_t)(REG32(EDX)) << 32;
- MSR_WRITE(REG32(ECX),data,&valid_msr);
+ // call the model specific implementation
+ opcode_wrmsr(data, valid_msr);
if(m_CPL != 0 || valid_msr == 0) // if current privilege level isn't 0 or the register isn't recognized
FAULT(FAULT_GP,0) // ... throw a general exception fault
diff --git a/src/devices/cpu/i8008/i8008.cpp b/src/devices/cpu/i8008/i8008.cpp
index 351edefb024..c0414390f4d 100644
--- a/src/devices/cpu/i8008/i8008.cpp
+++ b/src/devices/cpu/i8008/i8008.cpp
@@ -37,7 +37,7 @@ DEFINE_DEVICE_TYPE(I8008, i8008_device, "i8008", "Intel 8008")
i8008_device::i8008_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: cpu_device(mconfig, I8008, tag, owner, clock)
, m_program_config("program", ENDIANNESS_LITTLE, 8, 14)
- , m_io_config("io", ENDIANNESS_LITTLE, 8, 8)
+ , m_io_config("io", ENDIANNESS_LITTLE, 8, 5)
, m_program(nullptr)
, m_cache(nullptr)
{
diff --git a/src/devices/cpu/m6502/oxavix2000.lst b/src/devices/cpu/m6502/oxavix2000.lst
index 12be0a7868c..0832f2adef4 100644
--- a/src/devices/cpu/m6502/oxavix2000.lst
+++ b/src/devices/cpu/m6502/oxavix2000.lst
@@ -322,15 +322,15 @@ eorpa_imp
prefetch();
adcpa_imp
- do_adc(read_full_data_sp(m_pa+Y));
+ do_adc(read_full_data_sp(m_pa));
prefetch();
stapa_imp
- write_full_data_sp(m_pa+Y, A);
+ write_full_data_sp(m_pa, A);
prefetch();
ldapa_imp
- A = read_full_data_sp(m_pa+Y);
+ A = read_full_data_sp(m_pa);
prefetch();
cmppa_imp
@@ -339,7 +339,7 @@ cmppa_imp
prefetch();
sbcpa_imp
- do_sbc(read_full_data_sp(m_pa+Y));
+ do_sbc(read_full_data_sp(m_pa));
prefetch();
orapb_imp
@@ -358,15 +358,15 @@ eorpb_imp
prefetch();
adcpb_imp
- do_adc(read_full_data_sp(m_pb+Y));
+ do_adc(read_full_data_sp(m_pb));
prefetch();
stapb_imp
- write_full_data_sp(m_pb+Y, A);
+ write_full_data_sp(m_pb, A);
prefetch();
ldapb_imp
- A = read_full_data_sp(m_pb+Y);
+ A = read_full_data_sp(m_pb);
prefetch();
cmppb_imp
@@ -375,7 +375,7 @@ cmppb_imp
prefetch();
sbcpb_imp
- do_sbc(read_full_data_sp(m_pb+Y));
+ do_sbc(read_full_data_sp(m_pb));
prefetch();
stx_aby
diff --git a/src/devices/cpu/m6502/xavix2000.cpp b/src/devices/cpu/m6502/xavix2000.cpp
index fe173150de0..6431bf0d336 100644
--- a/src/devices/cpu/m6502/xavix2000.cpp
+++ b/src/devices/cpu/m6502/xavix2000.cpp
@@ -41,11 +41,11 @@
-- loop point 1
01BC3E: A3 ldal0 a // read byte 0 of 32-bit 'long' register into accumulator
- 01BC3F: 73 adcpa // adc ($Address PA), y
+ 01BC3F: 73 adcpa // adc ($Address PA)
01BC40: 83 stal0 a // store accumulator back in byte 0 of 32-bit 'long' register (even byte checksum?)
01BC41: FB incpa // increase 'address' register PA
01BC42: A7 ldal1 a // read byte 1 of 32-bit 'long' register into accumulator
- 01BC43: 73 adcpa // adc ($Address PA), y
+ 01BC43: 73 adcpa // adc ($Address PA)
01BC44: 87 stal1 a // store accumulator back in byte 0 of 32-bit 'long' register (odd byte checksum?)
01BC45: FB incpa // increase 'address' register PA
01BC46: D0 F6 bne $1bc3e // (branch based on PA increase, so PA must set flags?, probably overflows after 0xffff if upper byte is 'bank'? or at 0xff if this really is a mirror of the function below
diff --git a/src/devices/cpu/m68000/m68000.h b/src/devices/cpu/m68000/m68000.h
index 5d67e2a713f..fcceb9b5ac7 100644
--- a/src/devices/cpu/m68000/m68000.h
+++ b/src/devices/cpu/m68000/m68000.h
@@ -290,6 +290,7 @@ protected:
uint16_t m_mmu_tmp_buserror_rw; /* temporary hack: (first) bus error rw */
uint16_t m_mmu_tmp_buserror_sz; /* temporary hack: (first) bus error size` */
+ bool m_mmu_tablewalk; /* set when MMU walks page tables */
uint32_t m_ic_address[M68K_IC_SIZE]; /* instruction cache address data */
uint32_t m_ic_data[M68K_IC_SIZE]; /* instruction cache content data */
bool m_ic_valid[M68K_IC_SIZE]; /* instruction cache valid flags */
diff --git a/src/devices/cpu/m68000/m68kcpu.cpp b/src/devices/cpu/m68000/m68kcpu.cpp
index b0c26d00181..d57afa7acd7 100644
--- a/src/devices/cpu/m68000/m68kcpu.cpp
+++ b/src/devices/cpu/m68000/m68kcpu.cpp
@@ -725,7 +725,7 @@ bool m68000_base_device::memory_translate(int space, int intention, offs_t &addr
}
else
{
- address = pmmu_translate_addr_with_fc(address, mode, 1);
+ address = pmmu_translate_addr_with_fc<false, false>(address, mode, (intention & TRANSLATE_TYPE_MASK) == TRANSLATE_READ);
}
if ((m_mmu_tmp_sr & M68K_MMU_SR_INVALID) != 0) {
@@ -1280,7 +1280,7 @@ void m68000_base_device::init32mmu(address_space &space, address_space &ospace)
m_readimm16 = [this, ocache](offs_t address) -> u16 {
if (m_pmmu_enabled) {
- address = pmmu_translate_addr(address);
+ address = pmmu_translate_addr(address, 1);
if (m_mmu_tmp_buserror_occurred)
return ~0;
}
@@ -1290,7 +1290,7 @@ void m68000_base_device::init32mmu(address_space &space, address_space &ospace)
m_read8 = [this](offs_t address) -> u8 {
if (m_pmmu_enabled) {
- address = pmmu_translate_addr(address);
+ address = pmmu_translate_addr(address, 1);
if (m_mmu_tmp_buserror_occurred)
return ~0;
}
@@ -1299,12 +1299,12 @@ void m68000_base_device::init32mmu(address_space &space, address_space &ospace)
m_read16 = [this](offs_t address) -> u16 {
if (m_pmmu_enabled) {
- u32 address0 = pmmu_translate_addr(address);
+ u32 address0 = pmmu_translate_addr(address, 1);
if (m_mmu_tmp_buserror_occurred)
return ~0;
if (WORD_ALIGNED(address))
return m_space->read_word(address0);
- u32 address1 = pmmu_translate_addr(address + 1);
+ u32 address1 = pmmu_translate_addr(address + 1, 1);
if (m_mmu_tmp_buserror_occurred)
return ~0;
u16 result = m_space->read_byte(address0) << 8;
@@ -1319,7 +1319,7 @@ void m68000_base_device::init32mmu(address_space &space, address_space &ospace)
m_read32 = [this](offs_t address) -> u32 {
if (m_pmmu_enabled) {
- u32 address0 = pmmu_translate_addr(address);
+ u32 address0 = pmmu_translate_addr(address, 1);
if (m_mmu_tmp_buserror_occurred)
return ~0;
if ((address +3) & 0xfc)
@@ -1328,15 +1328,15 @@ void m68000_base_device::init32mmu(address_space &space, address_space &ospace)
else if (DWORD_ALIGNED(address)) // 0
return m_space->read_dword(address0);
else {
- u32 address2 = pmmu_translate_addr(address+2);
+ u32 address2 = pmmu_translate_addr(address+2, 1);
if (m_mmu_tmp_buserror_occurred)
return ~0;
if (WORD_ALIGNED(address)) { // 2
u32 result = m_space->read_word(address0) << 16;
return result | m_space->read_word(address2);
}
- u32 address1 = pmmu_translate_addr(address+1);
- u32 address3 = pmmu_translate_addr(address+3);
+ u32 address1 = pmmu_translate_addr(address+1, 1);
+ u32 address3 = pmmu_translate_addr(address+3, 1);
if (m_mmu_tmp_buserror_occurred)
return ~0;
u32 result = m_space->read_byte(address0) << 24;
@@ -1357,7 +1357,7 @@ void m68000_base_device::init32mmu(address_space &space, address_space &ospace)
m_write8 = [this](offs_t address, u8 data) {
if (m_pmmu_enabled) {
- address = pmmu_translate_addr(address);
+ address = pmmu_translate_addr(address, 0);
if (m_mmu_tmp_buserror_occurred)
return;
}
@@ -1366,14 +1366,14 @@ void m68000_base_device::init32mmu(address_space &space, address_space &ospace)
m_write16 = [this](offs_t address, u16 data) {
if (m_pmmu_enabled) {
- u32 address0 = pmmu_translate_addr(address);
+ u32 address0 = pmmu_translate_addr(address, 0);
if (m_mmu_tmp_buserror_occurred)
return;
if (WORD_ALIGNED(address)) {
m_space->write_word(address0, data);
return;
}
- u32 address1 = pmmu_translate_addr(address + 1);
+ u32 address1 = pmmu_translate_addr(address + 1, 0);
if (m_mmu_tmp_buserror_occurred)
return;
m_space->write_byte(address0, data >> 8);
@@ -1391,7 +1391,7 @@ void m68000_base_device::init32mmu(address_space &space, address_space &ospace)
m_write32 = [this](offs_t address, u32 data) {
if (m_pmmu_enabled) {
- u32 address0 = pmmu_translate_addr(address);
+ u32 address0 = pmmu_translate_addr(address, 0);
if (m_mmu_tmp_buserror_occurred)
return;
if ((address +3) & 0xfc) {
@@ -1401,7 +1401,7 @@ void m68000_base_device::init32mmu(address_space &space, address_space &ospace)
m_space->write_dword(address0, data);
return;
} else {
- u32 address2 = pmmu_translate_addr(address+2);
+ u32 address2 = pmmu_translate_addr(address+2, 0);
if (m_mmu_tmp_buserror_occurred)
return;
if (WORD_ALIGNED(address)) { // 2
@@ -1409,8 +1409,8 @@ void m68000_base_device::init32mmu(address_space &space, address_space &ospace)
m_space->write_word(address2, data);
return;
}
- u32 address1 = pmmu_translate_addr(address+1);
- u32 address3 = pmmu_translate_addr(address+3);
+ u32 address1 = pmmu_translate_addr(address+1, 0);
+ u32 address3 = pmmu_translate_addr(address+3, 0);
if (m_mmu_tmp_buserror_occurred)
return;
m_space->write_byte(address0, data >> 24);
diff --git a/src/devices/cpu/m68000/m68kdasm.cpp b/src/devices/cpu/m68000/m68kdasm.cpp
index a61acff8631..72794ad52b7 100644
--- a/src/devices/cpu/m68000/m68kdasm.cpp
+++ b/src/devices/cpu/m68000/m68kdasm.cpp
@@ -3005,7 +3005,7 @@ std::string m68k_disassembler::d68851_p000()
fc_to_string(modes),
str,
(modes >> 10) & 7,
- (modes >> 4) & 7);
+ (modes >> 5) & 7);
}
else
{
diff --git a/src/devices/cpu/m68000/m68kmmu.h b/src/devices/cpu/m68000/m68kmmu.h
index 60fda569f85..b519f63379f 100644
--- a/src/devices/cpu/m68000/m68kmmu.h
+++ b/src/devices/cpu/m68000/m68kmmu.h
@@ -1,14 +1,13 @@
// license:BSD-3-Clause
-// copyright-holders:R. Belmont, Hans Ostermeyer
-/*
- m68kmmu.h - PMMU implementation for 68851/68030/68040
- HMMU implementation for 68020 (II and LC variants)
+// copyright-holders:R. Belmont, Hans Ostermeyer, Sven Schnelle
- By R. Belmont and Hans Ostermeyer
-*/
+// m68kmmu.h - PMMU implementation for 68851/68030/68040
+// HMMU implementation for 68020 (II and LC variants)
-// MMU status register bit definitions
+// By R. Belmont and Hans Ostermeyer
+//
+// MMU status register bit definitions
#if 0
#define MMULOG logerror
@@ -16,42 +15,43 @@
#define MMULOG(...)
#endif
-static constexpr int M68K_MMU_SR_BUS_ERROR = 0x8000;
-static constexpr int M68K_MMU_SR_SUPERVISOR_ONLY = 0x2000;
-static constexpr int M68K_MMU_SR_WRITE_PROTECT = 0x0800;
-static constexpr int M68K_MMU_SR_INVALID = 0x0400;
-static constexpr int M68K_MMU_SR_MODIFIED = 0x0200;
-static constexpr int M68K_MMU_SR_LEVEL_0 = 0x0000;
-static constexpr int M68K_MMU_SR_LEVEL_1 = 0x0001;
-static constexpr int M68K_MMU_SR_LEVEL_2 = 0x0002;
-static constexpr int M68K_MMU_SR_LEVEL_3 = 0x0003;
+// MMU SR register fields
+static constexpr uint16_t M68K_MMU_SR_BUS_ERROR = 0x8000;
+static constexpr uint16_t M68K_MMU_SR_SUPERVISOR_ONLY = 0x2000;
+static constexpr uint16_t M68K_MMU_SR_WRITE_PROTECT = 0x0800;
+static constexpr uint16_t M68K_MMU_SR_INVALID = 0x0400;
+static constexpr uint16_t M68K_MMU_SR_MODIFIED = 0x0200;
+static constexpr uint16_t M68K_MMU_SR_TRANSPARENT = 0x0040;
// MMU translation table descriptor field definitions
-
-static constexpr int M68K_MMU_DF_DT = 0x0003;
-static constexpr int M68K_MMU_DF_DT0 = 0x0000;
-static constexpr int M68K_MMU_DF_DT1 = 0x0001;
-static constexpr int M68K_MMU_DF_DT2 = 0x0002;
-static constexpr int M68K_MMU_DF_DT3 = 0x0003;
-static constexpr int M68K_MMU_DF_WP = 0x0004;
-static constexpr int M68K_MMU_DF_USED = 0x0008;
-static constexpr int M68K_MMU_DF_MODIFIED = 0x0010;
-static constexpr int M68K_MMU_DF_CI = 0x0040;
-static constexpr int M68K_MMU_DF_SUPERVISOR = 0x0100;
+static constexpr uint32_t M68K_MMU_DF_DT = 0x00000003;
+static constexpr uint32_t M68K_MMU_DF_DT_INVALID = 0x00000000;
+static constexpr uint32_t M68K_MMU_DF_DT_PAGE = 0x00000001;
+static constexpr uint32_t M68K_MMU_DF_DT_TABLE_4BYTE = 0x00000002;
+static constexpr uint32_t M68K_MMU_DF_DT_TABLE_8BYTE = 0x00000003;
+static constexpr uint32_t M68K_MMU_DF_WP = 0x00000004;
+static constexpr uint32_t M68K_MMU_DF_USED = 0x00000008;
+static constexpr uint32_t M68K_MMU_DF_MODIFIED = 0x00000010;
+static constexpr uint32_t M68K_MMU_DF_CI = 0x00000040;
+static constexpr uint32_t M68K_MMU_DF_SUPERVISOR = 0000000100;
+static constexpr uint32_t M68K_MMU_DF_ADDR_MASK = 0xfffffff0;
+static constexpr uint32_t M68K_MMU_DF_IND_ADDR_MASK = 0xfffffffc;
// MMU ATC Fields
-
-static constexpr int M68K_MMU_ATC_BUSERROR = 0x08000000;
-static constexpr int M68K_MMU_ATC_CACHE_IN = 0x04000000;
-static constexpr int M68K_MMU_ATC_WRITE_PR = 0x02000000;
-static constexpr int M68K_MMU_ATC_MODIFIED = 0x01000000;
-static constexpr int M68K_MMU_ATC_MASK = 0x00ffffff;
-static constexpr int M68K_MMU_ATC_SHIFT = 8;
-static constexpr int M68K_MMU_ATC_VALID = 0x08000000;
+static constexpr uint32_t M68K_MMU_ATC_BUSERROR = 0x08000000;
+static constexpr uint32_t M68K_MMU_ATC_CACHE_IN = 0x04000000;
+static constexpr uint32_t M68K_MMU_ATC_WRITE_PR = 0x02000000;
+static constexpr uint32_t M68K_MMU_ATC_MODIFIED = 0x01000000;
+static constexpr uint32_t M68K_MMU_ATC_MASK = 0x00ffffff;
+static constexpr uint32_t M68K_MMU_ATC_SHIFT = 8;
+static constexpr uint32_t M68K_MMU_ATC_VALID = 0x08000000;
// MMU Translation Control register
-static constexpr int M68K_MMU_TC_SRE = 0x02000000;
+static constexpr uint32_t M68K_MMU_TC_SRE = 0x02000000;
+static constexpr uint32_t M68K_MMU_TC_FCL = 0x01000000;
+// TT register
+static constexpr uint16_t M68K_MMU_TT_ENABLE = 0x8000;
/* decodes the effective address */
uint32_t DECODE_EA_32(int ea)
{
@@ -120,15 +120,32 @@ void pmmu_set_buserror(uint32_t addr_in)
}
}
-/*
- pmmu_atc_add: adds this address to the ATC
-*/
-void pmmu_atc_add(uint32_t logical, uint32_t physical, int fc)
+
+// pmmu_atc_add: adds this address to the ATC
+void pmmu_atc_add(uint32_t logical, uint32_t physical, int fc, const int rw)
{
// get page size (i.e. # of bits to ignore); is 10 for Apollo
int ps = (m_mmu_tc >> 20) & 0xf;
// Note: exact emulation would use (logical >> ps) << (ps-8)
- uint32_t atc_tag = M68K_MMU_ATC_VALID | ((fc & 7) << 24)| logical >> ps;
+
+ uint32_t atc_tag = M68K_MMU_ATC_VALID | ((fc & 7) << 24) | logical >> ps;
+ uint32_t atc_data = (physical >> ps) << (ps - 8);
+
+
+ if (m_mmu_tmp_sr & (M68K_MMU_SR_BUS_ERROR|M68K_MMU_SR_INVALID|M68K_MMU_SR_SUPERVISOR_ONLY))
+ {
+ atc_data |= M68K_MMU_ATC_BUSERROR;
+ }
+
+ if (m_mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT)
+ {
+ atc_data |= M68K_MMU_ATC_WRITE_PR;
+ }
+
+ if (!rw && !(m_mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT))
+ {
+ atc_data |= M68K_MMU_ATC_MODIFIED;
+ }
// first see if this is already in the cache
for (int i = 0; i < MMU_ATC_ENTRIES; i++)
@@ -136,6 +153,8 @@ void pmmu_atc_add(uint32_t logical, uint32_t physical, int fc)
// if tag bits and function code match, don't add
if (m_mmu_atc_tag[i] == atc_tag)
{
+ MMULOG("%s: hit, old %08x new %08x\n", __func__, m_mmu_atc_data[i], atc_data);
+ m_mmu_atc_data[i] = atc_data;
return;
}
}
@@ -163,256 +182,383 @@ void pmmu_atc_add(uint32_t logical, uint32_t physical, int fc)
}
// add the entry
- MMULOG("ATC[%2d] add: log %08x -> phys %08x (fc=%d)\n", found, (logical >> ps) << ps, (physical >> ps) << ps, fc);
+ MMULOG("ATC[%2d] add: log %08x -> phys %08x (fc=%d) data=%08x\n",
+ found, (logical >> ps) << ps, (physical >> ps) << ps, fc, atc_data);
m_mmu_atc_tag[found] = atc_tag;
- m_mmu_atc_data[found] = (physical >> ps) << (ps - 8);
-
- if (m_mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT)
- {
- m_mmu_atc_data[found] |= M68K_MMU_ATC_WRITE_PR;
- }
+ m_mmu_atc_data[found] = atc_data;
}
-/*
- pmmu_atc_flush: flush entire ATC
- 7fff0003 001ffd10 80f05750 is what should load
-*/
+// pmmu_atc_flush: flush entire ATC
+// 7fff0003 001ffd10 80f05750 is what should load
void pmmu_atc_flush()
{
MMULOG("ATC flush: pc=%08x\n", m_ppc);
+ std::fill(std::begin(m_mmu_atc_tag), std::end(m_mmu_atc_tag), 0);
+ m_mmu_atc_rr = 0;
+}
+
+template<bool ptest>
+bool pmmu_atc_lookup(const uint32_t addr_in, const int fc, const bool rw,
+ uint32_t& addr_out)
+{
+ MMULOG("%s: LOOKUP addr_in=%08x, fc=%d, ptest=%d\n", __func__, addr_in, fc, ptest);
+ const int ps = (m_mmu_tc >> 20) & 0xf;
+ const uint32_t atc_tag = M68K_MMU_ATC_VALID | ((fc & 7) << 24) | (addr_in >> ps);
for (int i = 0; i < MMU_ATC_ENTRIES; i++)
{
- m_mmu_atc_tag[i] = 0;
- }
- m_mmu_atc_rr = 0;
-}
+ if (m_mmu_atc_tag[i] != atc_tag)
+ {
+ continue;
+ }
+ const uint32_t atc_data = m_mmu_atc_data[i];
-inline uint32_t get_dt2_table_entry(uint32_t tptr, uint8_t ptest, bool indirect)
-{
- uint32_t tbl_entry = m_program->read_dword(tptr);
- uint32_t dt = tbl_entry & M68K_MMU_DF_DT;
+ if (!ptest && !rw)
+ {
+ // According to MC86030UM:
+ // "If the M bit is clear and a write access to this logical
+ // address is attempted, the MC68030 aborts the access and initiates a table
+ // search, setting the M bit in the page descriptor, invalidating the old ATC
+ // entry, and creating a new entry with the M bit set.
+ if (!(atc_data & M68K_MMU_ATC_MODIFIED))
+ {
+ m_mmu_atc_tag[i] = 0;
+ continue;
+ }
+ }
- if (!indirect)
- m_mmu_tmp_sr |= tbl_entry & 0x0004 ? M68K_MMU_SR_WRITE_PROTECT : 0;
+ m_mmu_tmp_sr = 0;
+ if (atc_data & M68K_MMU_ATC_MODIFIED)
+ {
+ m_mmu_tmp_sr |= M68K_MMU_SR_MODIFIED;
+ }
- if (!ptest && !indirect && dt != M68K_MMU_DF_DT0)
- {
- if (dt == M68K_MMU_DF_DT1 && !m_mmu_tmp_rw && !(m_mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT))
+ if (atc_data & M68K_MMU_ATC_WRITE_PR)
{
- // set used and modified
- m_program->write_dword( tptr, tbl_entry | M68K_MMU_DF_USED | M68K_MMU_DF_MODIFIED);
+ m_mmu_tmp_sr |= M68K_MMU_SR_WRITE_PROTECT;
}
- else if (!(tbl_entry & M68K_MMU_DF_USED))
+
+ if (atc_data & M68K_MMU_ATC_BUSERROR)
{
- m_program->write_dword( tptr, tbl_entry | M68K_MMU_DF_USED);
+ m_mmu_tmp_sr |= M68K_MMU_SR_BUS_ERROR|M68K_MMU_SR_INVALID;
}
+ addr_out = (atc_data << 8) | (addr_in & ~(~0 << ps));
+ MMULOG("%s: addr_in=%08x, addr_out=%08x, MMU SR %04x\n",
+ __func__, addr_in, addr_out, m_mmu_tmp_sr);
+ return true;
+ }
+ MMULOG("%s: lookup failed\n", __func__);
+ if (ptest)
+ {
+ m_mmu_tmp_sr = M68K_MMU_SR_INVALID;
}
- return tbl_entry;
+ return false;
}
-inline uint32_t get_dt3_table_entry(uint32_t tptr, uint8_t fc, uint8_t ptest)
+bool pmmu_match_tt(const uint32_t addr_in, const int fc, const uint32_t tt, const bool rw)
{
- uint32_t tbl_entry2 = m_program->read_dword(tptr);
- uint32_t tbl_entry = m_program->read_dword(tptr + 4);
- uint32_t dt = tbl_entry2 & M68K_MMU_DF_DT;
+ if (!(tt & M68K_MMU_TT_ENABLE))
+ {
+ return false;
+ }
- m_mmu_tmp_sr |= ((tbl_entry2 & 0x0100) && !(fc & 4)) ? M68K_MMU_SR_SUPERVISOR_ONLY : 0;
- m_mmu_tmp_sr |= tbl_entry2 & 0x0004 ? M68K_MMU_SR_WRITE_PROTECT : 0;
+ // transparent translation enabled
+ const uint32_t address_base = tt & 0xff000000;
+ const uint32_t address_mask = ((tt << 8) & 0xff000000) ^ 0xff000000;
+ const uint32_t fcmask = (~tt) & 7;
+ const uint32_t fcbits = (tt >> 4) & 7;
+ const bool rwmask = (~tt & 0x100);
+ const bool rwbit = (tt & 0x200);
+
+ if ((addr_in & address_mask) != (address_base & address_mask))
+ {
+ return false;
+ }
- if (!ptest && dt != M68K_MMU_DF_DT0)
+ if ((fc & fcmask) != (fcbits & fcmask))
{
- if (dt == M68K_MMU_DF_DT1 && !m_mmu_tmp_rw && !(m_mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT))
- {
- // set modified
- m_program->write_dword( tptr, tbl_entry2 | M68K_MMU_DF_USED | M68K_MMU_DF_MODIFIED);
- }
- else if (!(tbl_entry2 & M68K_MMU_DF_USED))
- {
- m_program->write_dword( tptr, tbl_entry2 | M68K_MMU_DF_USED);
- }
+ return false;
}
- return (tbl_entry & ~M68K_MMU_DF_DT) | dt;
+ if ((rw & rwmask) != (rwbit & rwmask))
+ {
+ return false;
+ }
+
+ m_mmu_tmp_sr |= M68K_MMU_SR_TRANSPARENT;
+ return true;
}
-bool pmmu_atc_lookup(const uint32_t addr_in, const int fc, const int ptest, uint32_t& addr_out)
+void update_descriptor(const uint32_t tptr, const int type, const uint32_t entry, const bool rw)
{
- const int ps = (m_mmu_tc >> 20) & 0xf;
- const uint32_t atc_tag = M68K_MMU_ATC_VALID | ((fc & 7) << 24) | (addr_in >> ps);
-
- for (int i = 0; i < MMU_ATC_ENTRIES; i++)
+ if (type == M68K_MMU_DF_DT_PAGE && !rw &&
+ !(entry & M68K_MMU_DF_MODIFIED) &&
+ !(entry & M68K_MMU_DF_WP))
{
- if (m_mmu_atc_tag[i] != atc_tag)
- continue;
+ MMULOG("%s: set M+U at %08x\n", __func__, tptr);
+ m_program->write_dword(tptr, entry | M68K_MMU_DF_USED | M68K_MMU_DF_MODIFIED);
+ }
+ else if (type != M68K_MMU_DF_DT_INVALID && !(entry & M68K_MMU_DF_USED))
+ {
+ MMULOG("%s: set U at %08x\n", __func__, tptr);
+ m_program->write_dword(tptr, entry | M68K_MMU_DF_USED);
+ }
+}
- if (!m_mmu_tmp_rw && (m_mmu_atc_data[i] & M68K_MMU_ATC_WRITE_PR))
- continue;
- if (!m_mmu_tmp_rw && !(m_mmu_atc_data[i] & M68K_MMU_ATC_MODIFIED))
- continue;
+template<bool _long>
+void update_sr(const int type, const uint32_t tbl_entry)
+{
+ switch(type)
+ {
+ case M68K_MMU_DF_DT_INVALID:
+ // Invalid has no flags
+ break;
- // read access or write access and not write protected
- if (!ptest)
+ case M68K_MMU_DF_DT_PAGE:
+ if (tbl_entry & M68K_MMU_DF_MODIFIED)
{
- // FIXME: must set modified in PMMU tables as well
- m_mmu_atc_data[i] |= (!m_mmu_tmp_rw ? M68K_MMU_ATC_MODIFIED : 0);
+ m_mmu_tmp_sr |= M68K_MMU_SR_MODIFIED;
}
- else
- {
- uint16_t sr = 0;
+ // fall through
- if (m_mmu_atc_data[i] & M68K_MMU_ATC_MODIFIED)
- sr = M68K_MMU_SR_MODIFIED;
+ case M68K_MMU_DF_DT_TABLE_4BYTE:
+ // fall through
- if (m_mmu_atc_data[i] & M68K_MMU_ATC_WRITE_PR)
- sr |= M68K_MMU_SR_WRITE_PROTECT;
+ case M68K_MMU_DF_DT_TABLE_8BYTE:
- if (m_mmu_atc_data[i] & M68K_MMU_ATC_BUSERROR)
- sr |= M68K_MMU_SR_BUS_ERROR|M68K_MMU_SR_INVALID;
- m_mmu_tmp_sr = sr;
+ if (tbl_entry & M68K_MMU_DF_WP)
+ {
+ m_mmu_tmp_sr |= M68K_MMU_SR_WRITE_PROTECT;
}
- addr_out = (m_mmu_atc_data[i] << 8) | (addr_in & ~(~0 << ps));
- return true;
+
+ if (_long && (tbl_entry & M68K_MMU_DF_SUPERVISOR))
+ {
+ m_mmu_tmp_sr |= M68K_MMU_SR_SUPERVISOR_ONLY;
+ }
+ break;
+ default:
+ break;
}
- if (ptest)
- m_mmu_tmp_sr = M68K_MMU_SR_INVALID;
- return false;
}
-bool pmmu_match_tt(uint32_t addr_in, int fc, uint32_t tt)
+template<bool ptest>
+bool pmmu_walk_tables(uint32_t addr_in, int type, uint32_t table, const int fc,
+ const int limit, const bool rw, uint32_t &addr_out)
{
- if (!(tt & 0x8000))
- return false;
+ int level = 0;
+ const uint32_t bits = m_mmu_tc & 0xffff;
+ const int pagesize = (m_mmu_tc >> 20) & 0xf;
+ const int is = (m_mmu_tc >> 16) & 0xf;
+ int bitpos = 12;
+ int resolved = 0;
+ int pageshift = is;
- // transparent translation enabled
- uint32_t address_base = tt & 0xff000000;
- uint32_t address_mask = ((tt << 8) & 0xff000000) ^ 0xff000000;
- return (addr_in & address_mask) == address_base && (fc & ~tt) == ((tt >> 4) & 7);
-}
+ addr_in <<= is;
-bool pmmu_walk_table(uint32_t& tbl_entry, uint32_t addr_in, int shift, int bits, int nextbits, bool ptest, int fc, int level, uint32_t &addr_out)
-{
- // get table offset
- uint32_t tofs;
- uint32_t tptr = tbl_entry & 0xfffffff0;
- int ps = (m_mmu_tc >> 20) & 0xf;
- // get initial shift (# of top bits to ignore)
- int is = (m_mmu_tc >> 16) & 0xf;
-
- shift += is;
- tofs = (addr_in << shift) >> (32 - bits);
+ m_mmu_tablewalk = true;
- MMULOG("walk_table: addr_in %08x, tbl_entry %08x, tofs %08x shift %d, bits %d, nextbits %d\n", addr_in, tbl_entry, tofs, shift, bits, nextbits);
+ if (m_mmu_tc & M68K_MMU_TC_FCL)
+ {
+ bitpos = 16;
+ }
- switch (tbl_entry & M68K_MMU_DF_DT)
+ do
{
- case M68K_MMU_DF_DT0: // invalid, will cause MMU exception
- m_mmu_tmp_sr &= 0xfffffff0;
- m_mmu_tmp_sr |= M68K_MMU_SR_INVALID | level;
- addr_out = tbl_entry;
- MMULOG("PMMU: DT0 PC=%x (addr_in %08x -> %08x)\n", m_ppc, addr_in, addr_out);
- return true;
-
- case M68K_MMU_DF_DT1: // page descriptor, will cause direct mapping
- tbl_entry &= (~0 << ps);
- addr_out = ((addr_in << shift) >> shift) + tbl_entry;
- MMULOG("PMMU: DT1 PC=%x (addr_in %08x -> %08x)\n", m_ppc, addr_in, addr_out);
- return true;
-
- case M68K_MMU_DF_DT2: // valid 4 byte descriptors
- tofs *= 4;
-
- if (bits)
+ const int indexbits = (bits >> bitpos) & 0xf;
+ const int table_index = (bitpos == 16) ? fc : (addr_in >> (32 - indexbits));
+ bitpos -= 4;
+ const bool indirect = (!bitpos || !(bits >> bitpos)) && indexbits;
+ uint32_t tbl_entry, tbl_entry2;
+
+ MMULOG("%s: type %d, table %08x, addr_in %08x, indexbits %d, pageshift %d, indirect %d table_index %08x, rw=%d fc=%d\n",
+ __func__, type, table, addr_in, indexbits, pageshift, indirect, table_index, rw, fc);
+
+ switch(type)
+ {
+ case M68K_MMU_DF_DT_INVALID: // invalid, will cause MMU exception
+ m_mmu_tmp_sr = M68K_MMU_SR_INVALID;
+ MMULOG("PMMU: DT0 PC=%x (addr_in %08x -> %08x)\n", m_ppc, addr_in, addr_out);
+ resolved = 1;
+ break;
+
+ case M68K_MMU_DF_DT_PAGE: // page descriptor, will cause direct mapping
+ if (!ptest)
+ {
+ table &= ~0 << pagesize;
+ addr_out = table + (addr_in >> pageshift);
+ }
+ resolved = 1;
+ break;
+
+ case M68K_MMU_DF_DT_TABLE_4BYTE: // valid 4 byte descriptors
+ level++;
+ addr_out = table + (table_index << 2);
+ tbl_entry = m_program->read_dword(addr_out);
+ type = tbl_entry & M68K_MMU_DF_DT;
+
+ if (indirect && (type == 2 || type == 3))
+ {
+ level++;
+ MMULOG("SHORT INDIRECT DESC: %08x\n", tbl_entry);
+ addr_out = tbl_entry & M68K_MMU_DF_IND_ADDR_MASK;
+ tbl_entry = m_program->read_dword(addr_out);
+ type = tbl_entry & M68K_MMU_DF_DT;
+ }
+
+ MMULOG("SHORT DESC: %08x\n", tbl_entry);
+ table = tbl_entry & M68K_MMU_DF_ADDR_MASK;
+ update_sr<0>(type, tbl_entry);
+ if (!ptest)
+ {
+ update_descriptor(addr_out, type, tbl_entry, rw);
+ }
+ break;
+
+ case M68K_MMU_DF_DT_TABLE_8BYTE: // valid 8 byte descriptors
+ level++;
+ addr_out = table + (table_index << 3);
+ tbl_entry = m_program->read_dword(addr_out);
+ tbl_entry2 = m_program->read_dword(addr_out + 4);
+ type = tbl_entry & M68K_MMU_DF_DT;
+
+ if (indirect && (type == 2 || type == 3))
+ {
+ level++;
+ MMULOG("LONG INDIRECT DESC: %08x%08x\n", tbl_entry, tbl_entry2);
+ addr_out = tbl_entry2 & M68K_MMU_DF_IND_ADDR_MASK;
+ tbl_entry = m_program->read_dword(addr_out);
+ tbl_entry2 = m_program->read_dword(addr_out);
+ type = tbl_entry & M68K_MMU_DF_DT;
+ }
+
+ MMULOG("LONG DESC: %08x %08x\n", tbl_entry, tbl_entry2);
+ table = tbl_entry2 & M68K_MMU_DF_ADDR_MASK;
+ update_sr<1>(type, tbl_entry);
+ if (!ptest)
+ {
+ update_descriptor(addr_out, type, tbl_entry, rw);
+ }
+ break;
+ }
+
+ if (m_mmu_tmp_sr & M68K_MMU_SR_BUS_ERROR)
+ {
+ // Bus erorr during page table walking is always fatal
+ resolved = 1;
+ break;
+ }
+
+ if (!ptest)
+ {
+ if (!rw && (m_mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT))
{
- tbl_entry = get_dt2_table_entry(tptr + tofs, ptest, !nextbits);
- return false;
- } else
+ resolved = 1;
+ break;
+ }
+
+ if (!(fc & 4) && (m_mmu_tmp_sr & M68K_MMU_SR_SUPERVISOR_ONLY))
{
- tptr = tbl_entry & 0xfffffffc;
- tbl_entry = get_dt2_table_entry(tptr, ptest, 0);
- return false;
+ resolved = 1;
+ break;
}
- MMULOG("PMMU: %sDT2 read table entry at %08x: %08x\n", bits ? "" : "indirect ", tofs + tptr, tbl_entry);
- return false;
-
- case M68K_MMU_DF_DT3: // valid 8 byte descriptors
- tofs *= 8;
- tbl_entry = get_dt3_table_entry(tofs + tptr, fc, ptest);
- MMULOG("PMMU: DT3 read table A entries at %08x\n", tofs + tptr, tbl_entry);
- return false;
- }
- return true;
+
+ }
+ addr_in <<= indexbits;
+ pageshift += indexbits;
+ } while(level < limit && !resolved);
+
+
+ m_mmu_tmp_sr &= 0xfff0;
+ m_mmu_tmp_sr |= level;
+ MMULOG("MMU SR after walk: %04X\n", m_mmu_tmp_sr);
+ m_mmu_tablewalk = false;
+ return resolved;
}
-/*
- pmmu_translate_addr_with_fc: perform 68851/68030-style PMMU address translation
-*/
-uint32_t pmmu_translate_addr_with_fc(uint32_t addr_in, uint8_t fc, uint8_t ptest)
+// pmmu_translate_addr_with_fc: perform 68851/68030-style PMMU address translation
+template<bool ptest, bool pload>
+uint32_t pmmu_translate_addr_with_fc(uint32_t addr_in, uint8_t fc, bool rw, const int limit = 7)
{
- uint32_t addr_out, tbl_entry;
- uint32_t abits, bbits, cbits, dbits;
+ uint32_t addr_out = 0;
+
+ MMULOG("%s: addr_in=%08x, fc=%d, ptest=%d, rw=%d, limit=%d\n",
+ __func__, addr_in, fc, ptest, rw, limit);
m_mmu_tmp_sr = 0;
- if (fc == 7 ||
- pmmu_match_tt(addr_in, fc, m_mmu_tt0) ||
- pmmu_match_tt(addr_in, fc, m_mmu_tt1))
+ if (pmmu_match_tt(addr_in, fc, m_mmu_tt0, rw) ||
+ pmmu_match_tt(addr_in, fc, m_mmu_tt1, rw) ||
+ fc == 7)
{
return addr_in;
}
- if (pmmu_atc_lookup(addr_in, fc, ptest, addr_out))
+ if (ptest && limit == 0)
+ {
+ pmmu_atc_lookup<true>(addr_in, fc, rw, addr_out);
+ return addr_out;
+ }
+
+ if (!ptest && pmmu_atc_lookup<false>(addr_in, fc, rw, addr_out))
{
+ if (pload)
+ {
+ return addr_out;
+ }
+
+ if ((m_mmu_tmp_sr & M68K_MMU_SR_BUS_ERROR) || (!rw && (m_mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT)))
+ {
+ MMULOG("set atc hit buserror: addr_in=%08x, addr_out=%x, rw=%x, fc=%d, sz=%d\n",
+ addr_in, addr_out, m_mmu_tmp_rw, m_mmu_tmp_fc, m_mmu_tmp_sz);
+ pmmu_set_buserror(addr_in);
+ }
return addr_out;
}
+ int type;
+ uint32_t tbl_addr;
// if SRP is enabled and we're in supervisor mode, use it
if ((m_mmu_tc & M68K_MMU_TC_SRE) && (fc & 4))
{
- tbl_entry = (m_mmu_srp_aptr & 0xfffffff0) | (m_mmu_srp_limit & M68K_MMU_DF_DT);
+ tbl_addr = m_mmu_srp_aptr & M68K_MMU_DF_ADDR_MASK;
+ type = m_mmu_srp_limit & M68K_MMU_DF_DT;
}
else // else use the CRP
{
- tbl_entry = (m_mmu_crp_aptr & 0xfffffff0) | (m_mmu_crp_limit & M68K_MMU_DF_DT);
+ tbl_addr = m_mmu_crp_aptr & M68K_MMU_DF_ADDR_MASK;
+ type = m_mmu_crp_limit & M68K_MMU_DF_DT;
}
- m_mmu_tmp_sr = 0;
- abits = (m_mmu_tc >> 12) & 0xf;
- bbits = (m_mmu_tc >> 8) & 0xf;
- cbits = (m_mmu_tc >> 4) & 0xf;
- dbits = m_mmu_tc & 0x0f;
-
-
- if (!pmmu_walk_table(tbl_entry, addr_in, 0 , abits, bbits, ptest, fc, 0, addr_out) &&
- !pmmu_walk_table(tbl_entry, addr_in, abits , bbits, cbits, ptest, fc, 2, addr_out) &&
- !pmmu_walk_table(tbl_entry, addr_in, abits + bbits , cbits, dbits, ptest, fc, 3, addr_out) &&
- !pmmu_walk_table(tbl_entry, addr_in, abits + bbits + cbits , dbits, 0, ptest, fc, 4, addr_out) &&
- !pmmu_walk_table(tbl_entry, addr_in, abits + bbits + cbits + dbits, 0, 0, ptest, fc, 5, addr_out))
+ if (!pmmu_walk_tables<ptest>(addr_in, type, tbl_addr, fc, limit, rw, addr_out))
{
fatalerror("Table walk did not resolve\n");
}
- if (!ptest)
+ if (ptest)
{
- if ((m_mmu_tmp_sr & (M68K_MMU_SR_INVALID|M68K_MMU_SR_SUPERVISOR_ONLY)) ||
- ((m_mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT) && !m_mmu_tmp_rw))
- {
- pmmu_set_buserror(addr_in);
+ return addr_out;
+ }
- }
+ if ((m_mmu_tmp_sr & (M68K_MMU_SR_INVALID|M68K_MMU_SR_SUPERVISOR_ONLY)) ||
+ ((m_mmu_tmp_sr & M68K_MMU_SR_WRITE_PROTECT) && !rw))
+ {
- if (!m_mmu_tmp_buserror_occurred)
+ if (!pload)
{
- // we add only valid entries
- pmmu_atc_add(addr_in, addr_out, fc);
+ MMULOG("%s: set buserror (SR %04X)\n", __func__, m_mmu_tmp_sr);
+ pmmu_set_buserror(addr_in);
}
}
- MMULOG("PMMU: [%08x] => [%08x]\n", addr_in, addr_out);
+ // it seems like at least the 68030 sets the M bit in the MMU SR
+ // if the root descriptor is of PAGE type, so do a logical and
+ // between RW and the root type
+ pmmu_atc_add(addr_in, addr_out, fc, rw && type != 1);
+ MMULOG("PMMU: [%08x] => [%08x] (SR %04x)\n", addr_in, addr_out, m_mmu_tmp_sr);
return addr_out;
}
@@ -444,7 +590,7 @@ uint32_t pmmu_translate_addr_with_fc_040(uint32_t addr_in, uint8_t fc, uint8_t p
fatalerror("68040: function code %d is neither data nor program!\n", fc & 7);
}
- if (tt0 & 0x8000)
+ if (tt0 & M68K_MMU_TT_ENABLE)
{
static constexpr int fcmask[4] = { 4, 4, 0, 0 };
static constexpr int fcmatch[4] = { 0, 4, 0, 0 };
@@ -464,7 +610,7 @@ uint32_t pmmu_translate_addr_with_fc_040(uint32_t addr_in, uint8_t fc, uint8_t p
}
}
- if (tt1 & 0x8000)
+ if (tt1 & M68K_MMU_TT_ENABLE)
{
static int fcmask[4] = { 4, 4, 0, 0 };
static int fcmatch[4] = { 0, 4, 0, 0 };
@@ -662,10 +808,8 @@ uint32_t pmmu_translate_addr_with_fc_040(uint32_t addr_in, uint8_t fc, uint8_t p
return addr_out;
}
-/*
- pmmu_translate_addr: perform 68851/68030-style PMMU address translation
-*/
-uint32_t pmmu_translate_addr(uint32_t addr_in)
+// pmmu_translate_addr: perform 68851/68030-style PMMU address translation
+uint32_t pmmu_translate_addr(uint32_t addr_in, const bool rw)
{
uint32_t addr_out;
@@ -675,62 +819,96 @@ uint32_t pmmu_translate_addr(uint32_t addr_in)
}
else
{
- addr_out = pmmu_translate_addr_with_fc(addr_in, m_mmu_tmp_fc, 0);
+ addr_out = pmmu_translate_addr_with_fc<false, false>(addr_in, m_mmu_tmp_fc, rw);
}
-
-// if (m_mmu_tmp_buserror_occurred > 0)
-// {
-// MMULOG("PMMU: pc=%08x sp=%08x va=%08x pa=%08x - invalid Table mode for level=%d (buserror %d)\n",
-// m_ppc, REG_A()[7], addr_in, addr_out, m_mmu_tmp_sr & M68K_MMU_SR_LEVEL_3,
-// m_mmu_tmp_buserror_occurred);
-// }
-
return addr_out;
}
-/*
- m68851_mmu_ops: COP 0 MMU opcode handling
-*/
+// m68851_mmu_ops: COP 0 MMU opcode handling
+
+int fc_from_modes(const uint16_t modes)
+{
+ if ((modes & 0x1f) == 0)
+ {
+ return m_sfc;
+ }
+
+ if ((modes & 0x1f) == 1)
+ {
+ return m_dfc;
+ }
+
+ if (m_cpu_type & CPU_TYPE_030)
+ {
+ // 68030 has 3 bits fc, but 68851 4 bits
+ if (((modes >> 3) & 3) == 1)
+ {
+ return REG_D()[modes & 7] & 0x7;
+ }
+
+ if (((modes >> 3) & 3) == 2)
+ {
+ return modes & 7;
+ }
+ }
+ else
+ {
+ if (((modes >> 3) & 3) == 1)
+ {
+ return REG_D()[modes & 7] & 0xf;
+ }
+
+ if (modes & 0x10)
+ {
+ return modes & 0xf;
+ }
+ }
+
+
+ fatalerror("%s: unknown fc mode: 0x%02xn", __func__, modes & 0x1f);
+ return 0;
+}
void m68851_pload(const uint32_t ea, const uint16_t modes)
{
uint32_t ltmp = DECODE_EA_32(ea);
- uint32_t ptmp;
+ const int fc = fc_from_modes(modes);
+ bool rw = (modes & 0x200);
- ptmp = ltmp;
- if (m_pmmu_enabled)
+ MMULOG("%s: PLOAD%c addr=%08x, fc=%d\n", __func__, rw ? 'R' : 'W', ltmp, fc);
+
+ // MC68851 traps if MMU is not enabled, 030 not
+ if (m_pmmu_enabled || (m_cpu_type & CPU_TYPE_030))
{
if (CPU_TYPE_IS_040_PLUS())
{
- ptmp = pmmu_translate_addr_with_fc_040(ltmp, modes & 0x07, 0);
+ pmmu_translate_addr_with_fc_040(ltmp, fc, 0);
}
else
{
- ptmp = pmmu_translate_addr_with_fc(ltmp, modes & 0x07, 0);
+ pmmu_translate_addr_with_fc<false,true>(ltmp, fc, rw);
}
}
-
- MMULOG("680x0: PLOADing ATC with logical %08x => phys %08x\n", ltmp, ptmp);
- // FIXME: rw bit?
- pmmu_atc_add(ltmp, ptmp, modes & 0x07);
+ else
+ {
+ MMULOG("PLOAD with MMU disabled on MC68851\n");
+ m68ki_exception_trap(57);
+ return;
+ }
}
void m68851_ptest(const uint32_t ea, const uint16_t modes)
{
uint32_t v_addr = DECODE_EA_32(ea);
uint32_t p_addr;
- uint32_t fc = modes & 0x1f;
- switch (fc >> 3) {
- case 0:
- fc = fc == 0 ? m_sfc : m_dfc;
- break;
- case 1:
- fc = REG_D()[fc &7] &7;
- break;
- case 2:
- fc &=7;
- break;
- }
+
+ const int level = (modes >> 10) & 7;
+ const bool rw = (modes & 0x200);
+ const int fc = fc_from_modes(modes);
+
+ MMULOG("PMMU: PTEST%c (%04X) pc=%08x sp=%08x va=%08x fc=%x level=%x a=%d, areg=%d\n",
+ rw ? 'R' : 'W', modes, m_ppc, REG_A()[7], v_addr, fc, level,
+ (modes & 0x100) ? 1 : 0, (modes >> 5) & 7);
if (CPU_TYPE_IS_040_PLUS())
{
@@ -738,13 +916,12 @@ void m68851_ptest(const uint32_t ea, const uint16_t modes)
}
else
{
- p_addr = pmmu_translate_addr_with_fc(v_addr, fc, 1);
+ p_addr = pmmu_translate_addr_with_fc<true, false>(v_addr, fc, rw, level);
}
- m_mmu_sr = m_mmu_tmp_sr;
- MMULOG("PMMU: pc=%08x sp=%08x va=%08x pa=%08x PTEST fc=%x level=%x mmu_sr=%04x\n",
- m_ppc, REG_A()[7], v_addr, p_addr, fc, (modes >> 10) & 0x07, m_mmu_sr);
+ m_mmu_sr = m_mmu_tmp_sr;
+ MMULOG("PMMU: PTEST result: %04x pa=%08x\n", m_mmu_sr, p_addr);
if (modes & 0x100)
{
int areg = (modes >> 5) & 7;
@@ -781,8 +958,14 @@ void m68851_pmove_get(uint32_t ea, uint16_t modes)
default:
logerror("680x0: PMOVE from unknown MMU register %x, PC %x\n", (modes>>10) & 7, m_pc);
- break;
+ return;
}
+
+ if (!(modes & 0x100)) // flush ATC on moves to TC, SRP, CRP, TT with FD bit clear
+ {
+ pmmu_atc_flush();
+ }
+
}
void m68851_pmove_put(uint32_t ea, uint16_t modes)
@@ -794,24 +977,29 @@ void m68851_pmove_put(uint32_t ea, uint16_t modes)
{
uint32_t temp = READ_EA_32(ea);
- if (((modes>>10) & 7) == 2)
+ if (((modes >> 10) & 7) == 2)
{
MMULOG("WRITE TT0 = 0x%08x\n", m_mmu_tt0);
m_mmu_tt0 = temp;
}
- else if (((modes>>10) & 7) == 3)
+ else if (((modes >> 10) & 7) == 3)
{
MMULOG("WRITE TT1 = 0x%08x\n", m_mmu_tt1);
m_mmu_tt1 = temp;
}
break;
+
+ if (!(modes & 0x100))
+ {
+ pmmu_atc_flush();
+ }
}
case 1:
logerror("680x0: unknown PMOVE case 1, PC %x\n", m_pc);
break;
case 2:
- switch ((modes>>10) & 7)
+ switch ((modes >> 10) & 7)
{
case 0: // translation control register
m_mmu_tc = READ_EA_32(ea);
@@ -820,11 +1008,13 @@ void m68851_pmove_put(uint32_t ea, uint16_t modes)
if (m_mmu_tc & 0x80000000)
{
int bits = 0;
- for(int shift = 20; shift >= 0; shift -= 4) {
+ for (int shift = 20; shift >= 0; shift -= 4)
+ {
bits += (m_mmu_tc >> shift) & 0x0f;
}
- if (bits != 32 || !((m_mmu_tc >> 23) & 1)) {
+ if (bits != 32 || !((m_mmu_tc >> 23) & 1))
+ {
logerror("MMU: TC invalid!\n");
m_mmu_tc &= ~0x80000000;
m68ki_exception_trap(EXCEPTION_MMU_CONFIGURATION);
@@ -847,11 +1037,12 @@ void m68851_pmove_put(uint32_t ea, uint16_t modes)
case 2: // supervisor root pointer
temp64 = READ_EA_64(ea);
- m_mmu_srp_limit = (temp64>>32) & 0xffffffff;
+ m_mmu_srp_limit = (temp64 >> 32) & 0xffffffff;
m_mmu_srp_aptr = temp64 & 0xffffffff;
MMULOG("PMMU: SRP limit = %08x aptr = %08x\n", m_mmu_srp_limit, m_mmu_srp_aptr);
// SRP type 0 is not allowed
- if ((m_mmu_srp_limit & 3) == 0) {
+ if ((m_mmu_srp_limit & 3) == 0)
+ {
m68ki_exception_trap(EXCEPTION_MMU_CONFIGURATION);
return;
}
@@ -864,16 +1055,16 @@ void m68851_pmove_put(uint32_t ea, uint16_t modes)
case 3: // CPU root pointer
temp64 = READ_EA_64(ea);
- m_mmu_crp_limit = (temp64>>32) & 0xffffffff;
+ m_mmu_crp_limit = (temp64 >> 32) & 0xffffffff;
m_mmu_crp_aptr = temp64 & 0xffffffff;
MMULOG("PMMU: CRP limit = %08x aptr = %08x\n", m_mmu_crp_limit, m_mmu_crp_aptr);
// CRP type 0 is not allowed
- if ((m_mmu_crp_limit & 3) == 0) {
+ if ((m_mmu_crp_limit & 3) == 0)
+ {
m68ki_exception_trap(EXCEPTION_MMU_CONFIGURATION);
return;
}
-
if (!(modes & 0x100))
{
pmmu_atc_flush();
@@ -926,11 +1117,13 @@ void m68851_pmove(uint32_t ea, uint16_t modes)
case 3: // MC68030 to/from status reg
if (modes & 0x200)
{
+ MMULOG("%s: read SR = %04x\n", __func__, m_mmu_sr);
WRITE_EA_16(ea, m_mmu_sr);
}
else
{
m_mmu_sr = READ_EA_16(ea);
+ MMULOG("%s: write SR = %04X\n", __func__, m_mmu_sr);
}
break;
@@ -977,6 +1170,10 @@ void m68851_mmu_ops()
}
else if ((modes & 0xe200) == 0x2000) // PFLUSH
{
+ if (((modes >> 10) & 7) != 1)
+ {
+ logerror("PFLUSH by fc/ea not supported\n");
+ }
pmmu_atc_flush();
return;
}
@@ -1050,3 +1247,15 @@ inline uint32_t hmmu_translate_addr(uint32_t addr_in)
return addr_out;
}
+
+public:
+int m68851_buserror()
+{
+ if (!m_mmu_tablewalk)
+ {
+ return false;
+ }
+ MMULOG("buserror during table walk\n");
+ m_mmu_tmp_sr |= M68K_MMU_SR_BUS_ERROR|M68K_MMU_SR_INVALID;
+ return true;
+}
diff --git a/src/devices/cpu/mips/r3000.cpp b/src/devices/cpu/mips/r3000.cpp
index 9ac90837ec2..efbfaf99704 100644
--- a/src/devices/cpu/mips/r3000.cpp
+++ b/src/devices/cpu/mips/r3000.cpp
@@ -116,6 +116,9 @@
//**************************************************************************
DEFINE_DEVICE_TYPE(R2000, r2000_device, "r2000", "MIPS R2000")
+DEFINE_DEVICE_TYPE(R2000A, r2000a_device, "r2000a", "MIPS R2000A")
+DEFINE_DEVICE_TYPE(R3000, r3000_device, "r3000", "MIPS R3000")
+DEFINE_DEVICE_TYPE(R3000A, r3000a_device, "r3000a", "MIPS R3000A")
DEFINE_DEVICE_TYPE(R3041, r3041_device, "r3041", "MIPS R3041")
DEFINE_DEVICE_TYPE(R3051, r3051_device, "r3051", "MIPS R3051")
DEFINE_DEVICE_TYPE(R3052, r3052_device, "r3052", "MIPS R3052")
@@ -125,16 +128,17 @@ DEFINE_DEVICE_TYPE(SONYPS2_IOP, iop_device, "sonyiop", "Sony Playstation 2
//-------------------------------------------------
-// r3000_device - constructor
+// r3000_device_base - constructor
//-------------------------------------------------
-r3000_device::r3000_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, chip_type chiptype)
+r3000_device_base::r3000_device_base(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint32_t cpurev, size_t icache_size, size_t dcache_size)
: cpu_device(mconfig, type, tag, owner, clock),
m_program_config_be("program", ENDIANNESS_BIG, 32, 29),
m_program_config_le("program", ENDIANNESS_LITTLE, 32, 29),
m_program(nullptr),
- m_chip_type(chiptype),
+ m_cpurev(cpurev),
m_hasfpu(false),
+ m_fpurev(0),
m_endianness(ENDIANNESS_BIG),
m_pc(0),
m_nextpc(0),
@@ -144,6 +148,8 @@ r3000_device::r3000_device(const machine_config &mconfig, device_type type, cons
m_op(0),
m_icount(0),
m_interrupt_cycles(0),
+ m_icache_size(icache_size),
+ m_dcache_size(dcache_size),
m_in_brcond0(*this),
m_in_brcond1(*this),
m_in_brcond2(*this),
@@ -160,10 +166,10 @@ r3000_device::r3000_device(const machine_config &mconfig, device_type type, cons
//-------------------------------------------------
-// ~r3000_device - destructor
+// ~r3000_device_base - destructor
//-------------------------------------------------
-r3000_device::~r3000_device()
+r3000_device_base::~r3000_device_base()
{
}
@@ -171,8 +177,30 @@ r3000_device::~r3000_device()
// r2000_device - constructor
//-------------------------------------------------
-r2000_device::r2000_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : r3000_device(mconfig, R2000, tag, owner, clock, CHIP_TYPE_R2000) { }
+r2000_device::r2000_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, size_t icache_size, size_t dcache_size)
+ : r3000_device_base(mconfig, R2000, tag, owner, clock, 0x0100, icache_size, dcache_size) { }
+
+//-------------------------------------------------
+// r2000a_device - constructor
+//-------------------------------------------------
+
+r2000a_device::r2000a_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, size_t icache_size, size_t dcache_size)
+ : r3000_device_base(mconfig, R2000A, tag, owner, clock, 0x0216, icache_size, dcache_size) { }
+
+
+//-------------------------------------------------
+// r3000_device - constructor
+//-------------------------------------------------
+
+r3000_device::r3000_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, size_t icache_size, size_t dcache_size)
+ : r3000_device_base(mconfig, R3000, tag, owner, clock, 0x0220, icache_size, dcache_size) { }
+
+//-------------------------------------------------
+// r3000a_device - constructor
+//-------------------------------------------------
+
+r3000a_device::r3000a_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, size_t icache_size, size_t dcache_size)
+ : r3000_device_base(mconfig, R3000A, tag, owner, clock, 0x0230, icache_size, dcache_size) { }
//-------------------------------------------------
@@ -180,7 +208,7 @@ r2000_device::r2000_device(const machine_config &mconfig, const char *tag, devic
//-------------------------------------------------
r3041_device::r3041_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : r3000_device(mconfig, R3041, tag, owner, clock, CHIP_TYPE_R3041) { }
+ : r3000_device_base(mconfig, R3041, tag, owner, clock, 0x0700, 2048, 512) { }
//-------------------------------------------------
@@ -188,7 +216,7 @@ r3041_device::r3041_device(const machine_config &mconfig, const char *tag, devic
//-------------------------------------------------
r3051_device::r3051_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : r3000_device(mconfig, R3051, tag, owner, clock, CHIP_TYPE_R3051) { }
+ : r3000_device_base(mconfig, R3051, tag, owner, clock, 0x0200, 4096, 2048) { }
//-------------------------------------------------
@@ -196,23 +224,26 @@ r3051_device::r3051_device(const machine_config &mconfig, const char *tag, devic
//-------------------------------------------------
r3052_device::r3052_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : r3000_device(mconfig, R3052, tag, owner, clock, CHIP_TYPE_R3052) { }
+ : r3000_device_base(mconfig, R3052, tag, owner, clock, 0x0200, 8192, 2048) { }
//-------------------------------------------------
// r3071_device - constructor
//-------------------------------------------------
-r3071_device::r3071_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : r3000_device(mconfig, R3071, tag, owner, clock, CHIP_TYPE_R3071) { }
+r3071_device::r3071_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, size_t icache_size, size_t dcache_size)
+ : r3000_device_base(mconfig, R3071, tag, owner, clock, 0x0200, icache_size, dcache_size) { }
//-------------------------------------------------
// r3081_device - constructor
//-------------------------------------------------
-r3081_device::r3081_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : r3000_device(mconfig, R3081, tag, owner, clock, CHIP_TYPE_R3081) { }
+r3081_device::r3081_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, size_t icache_size, size_t dcache_size)
+ : r3000_device_base(mconfig, R3081, tag, owner, clock, 0x0200, icache_size, dcache_size)
+{
+ set_fpurev(0x0300);
+}
//-------------------------------------------------
@@ -220,7 +251,7 @@ r3081_device::r3081_device(const machine_config &mconfig, const char *tag, devic
//-------------------------------------------------
iop_device::iop_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : r3000_device(mconfig, SONYPS2_IOP, tag, owner, clock, CHIP_TYPE_IOP)
+ : r3000_device_base(mconfig, SONYPS2_IOP, tag, owner, clock, 0x001f, 4096, 1024)
{
m_endianness = ENDIANNESS_LITTLE;
}
@@ -230,7 +261,7 @@ iop_device::iop_device(const machine_config &mconfig, const char *tag, device_t
// device_start - start up the device
//-------------------------------------------------
-void r3000_device::device_start()
+void r3000_device_base::device_start()
{
// get our address spaces
m_program = &space(AS_PROGRAM);
@@ -247,56 +278,6 @@ void r3000_device::device_start()
m_prptr = [cache](offs_t address) -> const void * { return cache->read_ptr(address); };
}
- // determine the cache sizes
- switch (m_chip_type)
- {
- case CHIP_TYPE_R2000:
- {
- m_icache_size = 32768; // external
- m_dcache_size = 32768; // external
- break;
- }
- case CHIP_TYPE_R3041:
- {
- m_icache_size = 2048;
- m_dcache_size = 512;
- break;
- }
- case CHIP_TYPE_R3051:
- {
- m_icache_size = 4096;
- m_dcache_size = 2048;
- break;
- }
- case CHIP_TYPE_R3052:
- {
- m_icache_size = 8192;
- m_dcache_size = 2048;
- break;
- }
-
- // TODO: R3071 and R3081 have configurable cache sizes
- case CHIP_TYPE_R3071:
- {
- m_icache_size = 16384; // or 8kB
- m_dcache_size = 4096; // or 8kB
- break;
- }
- case CHIP_TYPE_R3081:
- {
- m_icache_size = 16384; // or 8kB
- m_dcache_size = 4096; // or 8kB
- m_hasfpu = true;
- break;
- }
- case CHIP_TYPE_IOP:
- {
- m_icache_size = 4096;
- m_dcache_size = 1024;
- break;
- }
- }
-
// allocate cache memory
m_icache.resize(m_icache_size/4);
m_dcache.resize(m_dcache_size/4);
@@ -305,40 +286,40 @@ void r3000_device::device_start()
m_cache_size = m_dcache_size;
// set up memory handlers
- m_memory_hand.m_read_byte = &r3000_device::readmem;
- m_memory_hand.m_read_word = &r3000_device::readmem_word;
- m_memory_hand.m_read_dword = &r3000_device::readmem_dword;
- m_memory_hand.m_write_byte = &r3000_device::writemem;
- m_memory_hand.m_write_word = &r3000_device::writemem_word;
- m_memory_hand.m_write_dword = &r3000_device::writemem_dword;
+ m_memory_hand.m_read_byte = &r3000_device_base::readmem;
+ m_memory_hand.m_read_word = &r3000_device_base::readmem_word;
+ m_memory_hand.m_read_dword = &r3000_device_base::readmem_dword;
+ m_memory_hand.m_write_byte = &r3000_device_base::writemem;
+ m_memory_hand.m_write_word = &r3000_device_base::writemem_word;
+ m_memory_hand.m_write_dword = &r3000_device_base::writemem_dword;
if (m_endianness == ENDIANNESS_BIG)
{
- m_lwl = &r3000_device::lwl_be;
- m_lwr = &r3000_device::lwr_be;
- m_swl = &r3000_device::swl_be;
- m_swr = &r3000_device::swr_be;
-
- m_cache_hand.m_read_byte = &r3000_device::readcache_be;
- m_cache_hand.m_read_word = &r3000_device::readcache_be_word;
- m_cache_hand.m_read_dword = &r3000_device::readcache_be_dword;
- m_cache_hand.m_write_byte = &r3000_device::writecache_be;
- m_cache_hand.m_write_word = &r3000_device::writecache_be_word;
- m_cache_hand.m_write_dword = &r3000_device::writecache_be_dword;
+ m_lwl = &r3000_device_base::lwl_be;
+ m_lwr = &r3000_device_base::lwr_be;
+ m_swl = &r3000_device_base::swl_be;
+ m_swr = &r3000_device_base::swr_be;
+
+ m_cache_hand.m_read_byte = &r3000_device_base::readcache_be;
+ m_cache_hand.m_read_word = &r3000_device_base::readcache_be_word;
+ m_cache_hand.m_read_dword = &r3000_device_base::readcache_be_dword;
+ m_cache_hand.m_write_byte = &r3000_device_base::writecache_be;
+ m_cache_hand.m_write_word = &r3000_device_base::writecache_be_word;
+ m_cache_hand.m_write_dword = &r3000_device_base::writecache_be_dword;
}
else
{
- m_lwl = &r3000_device::lwl_le;
- m_lwr = &r3000_device::lwr_le;
- m_swl = &r3000_device::swl_le;
- m_swr = &r3000_device::swr_le;
-
- m_cache_hand.m_read_byte = &r3000_device::readcache_le;
- m_cache_hand.m_read_word = &r3000_device::readcache_le_word;
- m_cache_hand.m_read_dword = &r3000_device::readcache_le_dword;
- m_cache_hand.m_write_byte = &r3000_device::writecache_le;
- m_cache_hand.m_write_word = &r3000_device::writecache_le_word;
- m_cache_hand.m_write_dword = &r3000_device::writecache_le_dword;
+ m_lwl = &r3000_device_base::lwl_le;
+ m_lwr = &r3000_device_base::lwr_le;
+ m_swl = &r3000_device_base::swl_le;
+ m_swr = &r3000_device_base::swr_le;
+
+ m_cache_hand.m_read_byte = &r3000_device_base::readcache_le;
+ m_cache_hand.m_read_word = &r3000_device_base::readcache_le_word;
+ m_cache_hand.m_read_dword = &r3000_device_base::readcache_le_dword;
+ m_cache_hand.m_write_byte = &r3000_device_base::writecache_le;
+ m_cache_hand.m_write_word = &r3000_device_base::writecache_le_word;
+ m_cache_hand.m_write_dword = &r3000_device_base::writecache_le_dword;
}
// resolve conditional branch input handlers
@@ -400,12 +381,16 @@ void r3000_device::device_start()
save_item(NAME(m_interrupt_cycles));
save_item(NAME(m_icache));
save_item(NAME(m_dcache));
+
+ // initialise cpu and fpu id registers
+ m_cpr[0][COP0_PRId] = m_cpurev;
+ m_ccr[1][0] = m_fpurev;
}
//-------------------------------------------------
// device_post_load -
//-------------------------------------------------
-void r3000_device::device_post_load()
+void r3000_device_base::device_post_load()
{
if (m_cpr[0][COP0_Status] & SR_IsC)
m_cur = &m_cache_hand;
@@ -418,7 +403,7 @@ void r3000_device::device_post_load()
// device_reset - reset the device
//-------------------------------------------------
-void r3000_device::device_reset()
+void r3000_device_base::device_reset()
{
// initialize the rest of the config
m_cur = &m_memory_hand;
@@ -426,16 +411,9 @@ void r3000_device::device_reset()
// initialize the state
m_pc = 0xbfc00000;
m_nextpc = ~0;
- m_cpr[0][COP0_PRId] = 0x0200;
m_cpr[0][COP0_Status] = 0x0000;
}
-void iop_device::device_reset()
-{
- r3000_device::device_reset();
- m_cpr[0][COP0_PRId] = 0x1f;
-}
-
//-------------------------------------------------
// memory_space_config - return the configuration
@@ -443,7 +421,7 @@ void iop_device::device_reset()
// the space doesn't exist
//-------------------------------------------------
-device_memory_interface::space_config_vector r3000_device::memory_space_config() const
+device_memory_interface::space_config_vector r3000_device_base::memory_space_config() const
{
return space_config_vector {
std::make_pair(AS_PROGRAM, (m_endianness == ENDIANNESS_BIG) ? &m_program_config_be : &m_program_config_le)
@@ -456,7 +434,7 @@ device_memory_interface::space_config_vector r3000_device::memory_space_config()
// after it has been set
//-------------------------------------------------
-void r3000_device::state_import(const device_state_entry &entry)
+void r3000_device_base::state_import(const device_state_entry &entry)
{
switch (entry.index())
{
@@ -464,7 +442,7 @@ void r3000_device::state_import(const device_state_entry &entry)
break;
default:
- fatalerror("r3000_device::state_import called for unexpected value\n");
+ fatalerror("r3000_device_base::state_import called for unexpected value\n");
}
}
@@ -473,7 +451,7 @@ void r3000_device::state_import(const device_state_entry &entry)
// state_export - export state out of the device
//-------------------------------------------------
-void r3000_device::state_export(const device_state_entry &entry)
+void r3000_device_base::state_export(const device_state_entry &entry)
{
switch (entry.index())
{
@@ -481,7 +459,7 @@ void r3000_device::state_export(const device_state_entry &entry)
break;
default:
- fatalerror("r3000_device::state_export called for unexpected value\n");
+ fatalerror("r3000_device_base::state_export called for unexpected value\n");
}
}
@@ -491,7 +469,7 @@ void r3000_device::state_export(const device_state_entry &entry)
// for the debugger
//-------------------------------------------------
-void r3000_device::state_string_export(const device_state_entry &entry, std::string &str) const
+void r3000_device_base::state_string_export(const device_state_entry &entry, std::string &str) const
{
switch (entry.index())
{
@@ -506,7 +484,7 @@ void r3000_device::state_string_export(const device_state_entry &entry, std::str
// helper function
//-------------------------------------------------
-std::unique_ptr<util::disasm_interface> r3000_device::create_disassembler()
+std::unique_ptr<util::disasm_interface> r3000_device_base::create_disassembler()
{
return std::make_unique<r3000_disassembler>();
}
@@ -516,47 +494,47 @@ std::unique_ptr<util::disasm_interface> r3000_device::create_disassembler()
MEMORY ACCESSORS
***************************************************************************/
-inline uint32_t r3000_device::readop(offs_t pc)
+inline uint32_t r3000_device_base::readop(offs_t pc)
{
return m_pr32(pc);
}
-uint8_t r3000_device::readmem(offs_t offset)
+uint8_t r3000_device_base::readmem(offs_t offset)
{
if (SR & SR_IsC)
return 0;
return m_program->read_byte(offset);
}
-uint16_t r3000_device::readmem_word(offs_t offset)
+uint16_t r3000_device_base::readmem_word(offs_t offset)
{
if (SR & SR_IsC)
return 0;
return m_program->read_word(offset);
}
-uint32_t r3000_device::readmem_dword(offs_t offset)
+uint32_t r3000_device_base::readmem_dword(offs_t offset)
{
if (SR & SR_IsC)
return 0;
return m_program->read_dword(offset);
}
-void r3000_device::writemem(offs_t offset, uint8_t data)
+void r3000_device_base::writemem(offs_t offset, uint8_t data)
{
if (SR & SR_IsC)
return;
m_program->write_byte(offset, data);
}
-void r3000_device::writemem_word(offs_t offset, uint16_t data)
+void r3000_device_base::writemem_word(offs_t offset, uint16_t data)
{
if (SR & SR_IsC)
return;
m_program->write_word(offset, data);
}
-void r3000_device::writemem_dword(offs_t offset, uint32_t data)
+void r3000_device_base::writemem_dword(offs_t offset, uint32_t data)
{
if (SR & SR_IsC)
return;
@@ -568,43 +546,43 @@ void r3000_device::writemem_dword(offs_t offset, uint32_t data)
BIG ENDIAN CACHE I/O
***************************************************************************/
-uint8_t r3000_device::readcache_be(offs_t offset)
+uint8_t r3000_device_base::readcache_be(offs_t offset)
{
offset &= 0x1fffffff;
return (offset * 4 < m_cache_size) ? m_cache[BYTE4_XOR_BE(offset)] : 0xff;
}
-uint16_t r3000_device::readcache_be_word(offs_t offset)
+uint16_t r3000_device_base::readcache_be_word(offs_t offset)
{
offset &= 0x1fffffff;
return (offset * 4 < m_cache_size) ? *(uint16_t *)&m_cache[WORD_XOR_BE(offset)] : 0xffff;
}
-uint32_t r3000_device::readcache_be_dword(offs_t offset)
+uint32_t r3000_device_base::readcache_be_dword(offs_t offset)
{
offset &= 0x1fffffff;
return (offset * 4 < m_cache_size) ? *(uint32_t *)&m_cache[offset] : 0xffffffff;
}
-void r3000_device::writecache_be(offs_t offset, uint8_t data)
+void r3000_device_base::writecache_be(offs_t offset, uint8_t data)
{
offset &= 0x1fffffff;
if (offset * 4 < m_cache_size) m_cache[BYTE4_XOR_BE(offset)] = data;
}
-void r3000_device::writecache_be_word(offs_t offset, uint16_t data)
+void r3000_device_base::writecache_be_word(offs_t offset, uint16_t data)
{
offset &= 0x1fffffff;
if (offset * 4 < m_cache_size) *(uint16_t *)&m_cache[WORD_XOR_BE(offset)] = data;
}
-void r3000_device::writecache_be_dword(offs_t offset, uint32_t data)
+void r3000_device_base::writecache_be_dword(offs_t offset, uint32_t data)
{
offset &= 0x1fffffff;
if (offset * 4 < m_cache_size) *(uint32_t *)&m_cache[offset] = data;
}
-uint8_t r3000_device::readcache_le(offs_t offset)
+uint8_t r3000_device_base::readcache_le(offs_t offset)
{
offset &= 0x1fffffff;
return (offset * 4 < m_cache_size) ? m_cache[BYTE4_XOR_LE(offset)] : 0xff;
@@ -615,31 +593,31 @@ uint8_t r3000_device::readcache_le(offs_t offset)
LITTLE ENDIAN CACHE I/O
***************************************************************************/
-uint16_t r3000_device::readcache_le_word(offs_t offset)
+uint16_t r3000_device_base::readcache_le_word(offs_t offset)
{
offset &= 0x1fffffff;
return (offset * 4 < m_cache_size) ? *(uint16_t *)&m_cache[WORD_XOR_LE(offset)] : 0xffff;
}
-uint32_t r3000_device::readcache_le_dword(offs_t offset)
+uint32_t r3000_device_base::readcache_le_dword(offs_t offset)
{
offset &= 0x1fffffff;
return (offset * 4 < m_cache_size) ? *(uint32_t *)&m_cache[offset] : 0xffffffff;
}
-void r3000_device::writecache_le(offs_t offset, uint8_t data)
+void r3000_device_base::writecache_le(offs_t offset, uint8_t data)
{
offset &= 0x1fffffff;
if (offset * 4 < m_cache_size) m_cache[BYTE4_XOR_LE(offset)] = data;
}
-void r3000_device::writecache_le_word(offs_t offset, uint16_t data)
+void r3000_device_base::writecache_le_word(offs_t offset, uint16_t data)
{
offset &= 0x1fffffff;
if (offset * 4 < m_cache_size) *(uint16_t *)&m_cache[WORD_XOR_LE(offset)] = data;
}
-void r3000_device::writecache_le_dword(offs_t offset, uint32_t data)
+void r3000_device_base::writecache_le_dword(offs_t offset, uint32_t data)
{
offset &= 0x1fffffff;
if (offset * 4 < m_cache_size) *(uint32_t *)&m_cache[offset] = data;
@@ -650,7 +628,7 @@ void r3000_device::writecache_le_dword(offs_t offset, uint32_t data)
EXECEPTION HANDLING
***************************************************************************/
-inline void r3000_device::generate_exception(int exception, bool backup)
+inline void r3000_device_base::generate_exception(int exception, bool backup)
{
// set the exception PC
m_cpr[0][COP0_EPC] = backup ? m_ppc : m_pc;
@@ -681,7 +659,7 @@ inline void r3000_device::generate_exception(int exception, bool backup)
}
-inline void r3000_device::invalid_instruction()
+inline void r3000_device_base::invalid_instruction()
{
generate_exception(EXCEPTION_INVALIDOP, true);
}
@@ -691,14 +669,14 @@ inline void r3000_device::invalid_instruction()
IRQ HANDLING
***************************************************************************/
-void r3000_device::check_irqs()
+void r3000_device_base::check_irqs()
{
if ((CAUSE & SR & 0xff00) && (SR & SR_IEc))
generate_exception(EXCEPTION_INTERRUPT, false);
}
-void r3000_device::set_irq_line(int irqline, int state)
+void r3000_device_base::set_irq_line(int irqline, int state)
{
if (state != CLEAR_LINE)
CAUSE |= 0x400 << irqline;
@@ -713,12 +691,12 @@ void r3000_device::set_irq_line(int irqline, int state)
COP0 (SYSTEM) EXECUTION HANDLING
***************************************************************************/
-inline uint32_t r3000_device::get_cop0_reg(int idx)
+inline uint32_t r3000_device_base::get_cop0_reg(int idx)
{
return m_cpr[0][idx];
}
-inline void r3000_device::set_cop0_reg(int idx, uint32_t val)
+inline void r3000_device_base::set_cop0_reg(int idx, uint32_t val)
{
if (idx == COP0_Cause)
{
@@ -754,21 +732,21 @@ inline void r3000_device::set_cop0_reg(int idx, uint32_t val)
// update interrupts
check_irqs();
}
- else
+ else if (idx != COP0_PRId)
m_cpr[0][idx] = val;
}
-inline uint32_t r3000_device::get_cop0_creg(int idx)
+inline uint32_t r3000_device_base::get_cop0_creg(int idx)
{
return m_ccr[0][idx];
}
-inline void r3000_device::set_cop0_creg(int idx, uint32_t val)
+inline void r3000_device_base::set_cop0_creg(int idx, uint32_t val)
{
m_ccr[0][idx] = val;
}
-inline void r3000_device::handle_cop0()
+inline void r3000_device_base::handle_cop0()
{
if (!(SR & SR_COP0) && (SR & SR_KUc))
generate_exception(EXCEPTION_BADCOP, true);
@@ -825,27 +803,28 @@ inline void r3000_device::handle_cop0()
COP1 (FPU) EXECUTION HANDLING
***************************************************************************/
-inline uint32_t r3000_device::get_cop1_reg(int idx)
+inline uint32_t r3000_device_base::get_cop1_reg(int idx)
{
return m_cpr[1][idx];
}
-inline void r3000_device::set_cop1_reg(int idx, uint32_t val)
+inline void r3000_device_base::set_cop1_reg(int idx, uint32_t val)
{
m_cpr[1][idx] = val;
}
-inline uint32_t r3000_device::get_cop1_creg(int idx)
+inline uint32_t r3000_device_base::get_cop1_creg(int idx)
{
return m_ccr[1][idx];
}
-inline void r3000_device::set_cop1_creg(int idx, uint32_t val)
+inline void r3000_device_base::set_cop1_creg(int idx, uint32_t val)
{
- m_ccr[1][idx] = val;
+ if (idx)
+ m_ccr[1][idx] = val;
}
-inline void r3000_device::handle_cop1()
+inline void r3000_device_base::handle_cop1()
{
if (!(SR & SR_COP1))
generate_exception(EXCEPTION_BADCOP, true);
@@ -893,27 +872,27 @@ inline void r3000_device::handle_cop1()
COP2 (CUSTOM) EXECUTION HANDLING
***************************************************************************/
-inline uint32_t r3000_device::get_cop2_reg(int idx)
+inline uint32_t r3000_device_base::get_cop2_reg(int idx)
{
return m_cpr[2][idx];
}
-inline void r3000_device::set_cop2_reg(int idx, uint32_t val)
+inline void r3000_device_base::set_cop2_reg(int idx, uint32_t val)
{
m_cpr[2][idx] = val;
}
-inline uint32_t r3000_device::get_cop2_creg(int idx)
+inline uint32_t r3000_device_base::get_cop2_creg(int idx)
{
return m_ccr[2][idx];
}
-inline void r3000_device::set_cop2_creg(int idx, uint32_t val)
+inline void r3000_device_base::set_cop2_creg(int idx, uint32_t val)
{
m_ccr[2][idx] = val;
}
-inline void r3000_device::handle_cop2()
+inline void r3000_device_base::handle_cop2()
{
if (!(SR & SR_COP2))
generate_exception(EXCEPTION_BADCOP, true);
@@ -959,27 +938,27 @@ inline void r3000_device::handle_cop2()
COP3 (CUSTOM) EXECUTION HANDLING
***************************************************************************/
-inline uint32_t r3000_device::get_cop3_reg(int idx)
+inline uint32_t r3000_device_base::get_cop3_reg(int idx)
{
return m_cpr[3][idx];
}
-inline void r3000_device::set_cop3_reg(int idx, uint32_t val)
+inline void r3000_device_base::set_cop3_reg(int idx, uint32_t val)
{
m_cpr[3][idx] = val;
}
-inline uint32_t r3000_device::get_cop3_creg(int idx)
+inline uint32_t r3000_device_base::get_cop3_creg(int idx)
{
return m_ccr[3][idx];
}
-inline void r3000_device::set_cop3_creg(int idx, uint32_t val)
+inline void r3000_device_base::set_cop3_creg(int idx, uint32_t val)
{
m_ccr[3][idx] = val;
}
-inline void r3000_device::handle_cop3()
+inline void r3000_device_base::handle_cop3()
{
if (!(SR & SR_COP3))
generate_exception(EXCEPTION_BADCOP, true);
@@ -1030,7 +1009,7 @@ inline void r3000_device::handle_cop3()
// cycles it takes for one instruction to execute
//-------------------------------------------------
-uint32_t r3000_device::execute_min_cycles() const
+uint32_t r3000_device_base::execute_min_cycles() const
{
return 1;
}
@@ -1041,7 +1020,7 @@ uint32_t r3000_device::execute_min_cycles() const
// cycles it takes for one instruction to execute
//-------------------------------------------------
-uint32_t r3000_device::execute_max_cycles() const
+uint32_t r3000_device_base::execute_max_cycles() const
{
return 40;
}
@@ -1052,7 +1031,7 @@ uint32_t r3000_device::execute_max_cycles() const
// input/interrupt lines
//-------------------------------------------------
-uint32_t r3000_device::execute_input_lines() const
+uint32_t r3000_device_base::execute_input_lines() const
{
return 6;
}
@@ -1062,7 +1041,7 @@ uint32_t r3000_device::execute_input_lines() const
// execute_set_input
//-------------------------------------------------
-void r3000_device::execute_set_input(int inputnum, int state)
+void r3000_device_base::execute_set_input(int inputnum, int state)
{
set_irq_line(inputnum, state);
}
@@ -1072,7 +1051,7 @@ void r3000_device::execute_set_input(int inputnum, int state)
// execute_run
//-------------------------------------------------
-void r3000_device::execute_run()
+void r3000_device_base::execute_run()
{
// count cycles and interrupt cycles
m_icount -= m_interrupt_cycles;
@@ -1285,7 +1264,7 @@ void r3000_device::execute_run()
COMPLEX OPCODE IMPLEMENTATIONS
***************************************************************************/
-void r3000_device::lwl_be()
+void r3000_device_base::lwl_be()
{
offs_t offs = SIMMVAL + RSVAL;
uint32_t temp = RLONG(offs & ~3);
@@ -1300,7 +1279,7 @@ void r3000_device::lwl_be()
}
}
-void r3000_device::lwr_be()
+void r3000_device_base::lwr_be()
{
offs_t offs = SIMMVAL + RSVAL;
uint32_t temp = RLONG(offs & ~3);
@@ -1315,7 +1294,7 @@ void r3000_device::lwr_be()
}
}
-void r3000_device::swl_be()
+void r3000_device_base::swl_be()
{
offs_t offs = SIMMVAL + RSVAL;
if (!(offs & 3)) WLONG(offs, RTVAL);
@@ -1328,7 +1307,7 @@ void r3000_device::swl_be()
}
-void r3000_device::swr_be()
+void r3000_device_base::swr_be()
{
offs_t offs = SIMMVAL + RSVAL;
if ((offs & 3) == 3) WLONG(offs & ~3, RTVAL);
@@ -1342,7 +1321,7 @@ void r3000_device::swr_be()
-void r3000_device::lwl_le()
+void r3000_device_base::lwl_le()
{
offs_t offs = SIMMVAL + RSVAL;
uint32_t temp = RLONG(offs & ~3);
@@ -1357,7 +1336,7 @@ void r3000_device::lwl_le()
}
}
-void r3000_device::lwr_le()
+void r3000_device_base::lwr_le()
{
offs_t offs = SIMMVAL + RSVAL;
uint32_t temp = RLONG(offs & ~3);
@@ -1372,7 +1351,7 @@ void r3000_device::lwr_le()
}
}
-void r3000_device::swl_le()
+void r3000_device_base::swl_le()
{
offs_t offs = SIMMVAL + RSVAL;
if (!(offs & 3)) WLONG(offs, RTVAL);
@@ -1384,7 +1363,7 @@ void r3000_device::swl_le()
}
}
-void r3000_device::swr_le()
+void r3000_device_base::swr_le()
{
offs_t offs = SIMMVAL + RSVAL;
if ((offs & 3) == 3) WLONG(offs & ~3, RTVAL);
diff --git a/src/devices/cpu/mips/r3000.h b/src/devices/cpu/mips/r3000.h
index cf495d188df..1ba98c11eea 100644
--- a/src/devices/cpu/mips/r3000.h
+++ b/src/devices/cpu/mips/r3000.h
@@ -19,19 +19,19 @@
***************************************************************************/
#define MCFG_R3000_ENDIANNESS(_endianness) \
- downcast<r3000_device &>(*device).set_endianness(_endianness);
+ downcast<r3000_device_base &>(*device).set_endianness(_endianness);
#define MCFG_R3000_BRCOND0_INPUT(_devcb) \
- downcast<r3000_device &>(*device).set_brcond0_input(DEVCB_##_devcb);
+ downcast<r3000_device_base &>(*device).set_brcond0_input(DEVCB_##_devcb);
#define MCFG_R3000_BRCOND1_INPUT(_devcb) \
- downcast<r3000_device &>(*device).set_brcond1_input(DEVCB_##_devcb);
+ downcast<r3000_device_base &>(*device).set_brcond1_input(DEVCB_##_devcb);
#define MCFG_R3000_BRCOND2_INPUT(_devcb) \
- downcast<r3000_device &>(*device).set_brcond2_input(DEVCB_##_devcb);
+ downcast<r3000_device_base &>(*device).set_brcond2_input(DEVCB_##_devcb);
#define MCFG_R3000_BRCOND3_INPUT(_devcb) \
- downcast<r3000_device &>(*device).set_brcond3_input(DEVCB_##_devcb);
+ downcast<r3000_device_base &>(*device).set_brcond3_input(DEVCB_##_devcb);
/***************************************************************************
@@ -64,16 +64,17 @@ enum
// TYPE DEFINITIONS
//**************************************************************************
-// ======================> r3000_device
+// ======================> r3000_device_base
-class r3000_device : public cpu_device
+class r3000_device_base : public cpu_device
{
public:
// construction/destruction
- virtual ~r3000_device();
+ virtual ~r3000_device_base();
// inline configuration helpers
void set_endianness(endianness_t endianness) { m_endianness = endianness; }
+ void set_fpurev(uint32_t revision) { m_hasfpu = true; m_fpurev = revision; }
template <class Object> devcb_base &set_brcond0_input(Object &&cb) { return m_in_brcond0.set_callback(std::forward<Object>(cb)); }
template <class Object> devcb_base &set_brcond1_input(Object &&cb) { return m_in_brcond1.set_callback(std::forward<Object>(cb)); }
@@ -85,18 +86,7 @@ public:
auto in_brcond3() { return m_in_brcond3.bind(); }
protected:
- enum chip_type
- {
- CHIP_TYPE_R2000,
- CHIP_TYPE_R3041,
- CHIP_TYPE_R3051,
- CHIP_TYPE_R3052,
- CHIP_TYPE_R3071,
- CHIP_TYPE_R3081,
- CHIP_TYPE_IOP
- };
-
- r3000_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, chip_type chiptype);
+ r3000_device_base(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, uint32_t cpurev, size_t icache_size, size_t dcache_size);
// device-level overrides
virtual void device_start() override;
@@ -124,12 +114,12 @@ protected:
// memory accessors
struct r3000_data_accessors
{
- uint8_t (r3000_device::*m_read_byte)(offs_t byteaddress);
- uint16_t (r3000_device::*m_read_word)(offs_t byteaddress);
- uint32_t (r3000_device::*m_read_dword)(offs_t byteaddress);
- void (r3000_device::*m_write_byte)(offs_t byteaddress, uint8_t data);
- void (r3000_device::*m_write_word)(offs_t byteaddress, uint16_t data);
- void (r3000_device::*m_write_dword)(offs_t byteaddress, uint32_t data);
+ uint8_t (r3000_device_base::*m_read_byte)(offs_t byteaddress);
+ uint16_t (r3000_device_base::*m_read_word)(offs_t byteaddress);
+ uint32_t (r3000_device_base::*m_read_dword)(offs_t byteaddress);
+ void (r3000_device_base::*m_write_byte)(offs_t byteaddress, uint8_t data);
+ void (r3000_device_base::*m_write_word)(offs_t byteaddress, uint16_t data);
+ void (r3000_device_base::*m_write_dword)(offs_t byteaddress, uint32_t data);
};
uint32_t readop(offs_t pc);
@@ -204,8 +194,9 @@ protected:
std::function<const void * (offs_t)> m_prptr;
// configuration
- chip_type m_chip_type;
+ uint32_t m_cpurev;
bool m_hasfpu;
+ uint32_t m_fpurev;
endianness_t m_endianness;
// core registers
@@ -226,10 +217,10 @@ protected:
int m_interrupt_cycles;
// endian-dependent load/store
- void (r3000_device::*m_lwl)();
- void (r3000_device::*m_lwr)();
- void (r3000_device::*m_swl)();
- void (r3000_device::*m_swr)();
+ void (r3000_device_base::*m_lwl)();
+ void (r3000_device_base::*m_lwr)();
+ void (r3000_device_base::*m_swl)();
+ void (r3000_device_base::*m_swr)();
// memory accesses
r3000_data_accessors *m_cur;
@@ -241,8 +232,8 @@ protected:
std::vector<uint32_t> m_icache;
std::vector<uint32_t> m_dcache;
size_t m_cache_size;
- size_t m_icache_size;
- size_t m_dcache_size;
+ size_t const m_icache_size;
+ size_t const m_dcache_size;
// I/O
devcb_read_line m_in_brcond0;
@@ -251,18 +242,45 @@ protected:
devcb_read_line m_in_brcond3;
};
-// ======================> r3041_device
+// ======================> r2000_device
+
+class r2000_device : public r3000_device_base
+{
+public:
+ r2000_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, size_t icache_size = 0, size_t dcache_size = 0);
+};
+
+
+// ======================> r2000a_device
-class r2000_device : public r3000_device
+class r2000a_device : public r3000_device_base
{
public:
- r2000_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+ r2000a_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, size_t icache_size = 0, size_t dcache_size = 0);
+};
+
+
+// ======================> r3000_device
+
+class r3000_device : public r3000_device_base
+{
+public:
+ r3000_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, size_t icache_size = 0, size_t dcache_size = 0);
+};
+
+
+// ======================> r3000a_device
+
+class r3000a_device : public r3000_device_base
+{
+public:
+ r3000a_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, size_t icache_size = 0, size_t dcache_size = 0);
};
// ======================> r3041_device
-class r3041_device : public r3000_device
+class r3041_device : public r3000_device_base
{
public:
r3041_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
@@ -271,7 +289,7 @@ public:
// ======================> r3051_device
-class r3051_device : public r3000_device
+class r3051_device : public r3000_device_base
{
public:
r3051_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
@@ -280,7 +298,7 @@ public:
// ======================> r3052_device
-class r3052_device : public r3000_device
+class r3052_device : public r3000_device_base
{
public:
r3052_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
@@ -289,37 +307,37 @@ public:
// ======================> r3071_device
-class r3071_device : public r3000_device
+class r3071_device : public r3000_device_base
{
public:
- r3071_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+ r3071_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, size_t icache_size = 16384, size_t dcache_size = 4096);
};
// ======================> r3081_device
-class r3081_device : public r3000_device
+class r3081_device : public r3000_device_base
{
public:
- r3081_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+ r3081_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, size_t icache_size = 16384, size_t dcache_size = 4096);
};
// ======================> iop_device
-class iop_device : public r3000_device
+class iop_device : public r3000_device_base
{
public:
iop_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
-
-protected:
- virtual void device_reset() override;
};
// device type definition
DECLARE_DEVICE_TYPE(R2000, r2000_device)
+DECLARE_DEVICE_TYPE(R2000A, r2000a_device)
+DECLARE_DEVICE_TYPE(R3000, r3000_device)
+DECLARE_DEVICE_TYPE(R3000A, r3000a_device)
DECLARE_DEVICE_TYPE(R3041, r3041_device)
DECLARE_DEVICE_TYPE(R3051, r3051_device)
DECLARE_DEVICE_TYPE(R3052, r3052_device)
diff --git a/src/devices/cpu/nec/v25.cpp b/src/devices/cpu/nec/v25.cpp
index 7a076f2c6c3..9800540a04c 100644
--- a/src/devices/cpu/nec/v25.cpp
+++ b/src/devices/cpu/nec/v25.cpp
@@ -50,11 +50,12 @@ DEFINE_DEVICE_TYPE(V25, v25_device, "v25", "NEC V25")
DEFINE_DEVICE_TYPE(V35, v35_device, "v35", "NEC V35")
-v25_common_device::v25_common_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, bool is_16bit, offs_t fetch_xor, uint8_t prefetch_size, uint8_t prefetch_cycles, uint32_t chip_type)
+v25_common_device::v25_common_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, bool is_16bit, uint8_t prefetch_size, uint8_t prefetch_cycles, uint32_t chip_type)
: cpu_device(mconfig, type, tag, owner, clock)
, m_program_config("program", ENDIANNESS_LITTLE, is_16bit ? 16 : 8, 20, 0)
+ , m_data_config("data", ENDIANNESS_LITTLE, 16, 9, 0, address_map_constructor(FUNC(v25_common_device::ida_sfr_map), this))
, m_io_config("io", ENDIANNESS_LITTLE, is_16bit ? 16 : 8, 16, 0)
- , m_fetch_xor(fetch_xor)
+ , m_internal_ram(*this, "internal_ram")
, m_PCK(8)
, m_pt_in(*this)
, m_p0_in(*this)
@@ -72,13 +73,13 @@ v25_common_device::v25_common_device(const machine_config &mconfig, device_type
v25_device::v25_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : v25_common_device(mconfig, V25, tag, owner, clock, false, 0, 4, 4, V20_TYPE)
+ : v25_common_device(mconfig, V25, tag, owner, clock, false, 4, 4, V20_TYPE)
{
}
v35_device::v35_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : v25_common_device(mconfig, V35, tag, owner, clock, true, BYTE_XOR_LE(0), 6, 2, V30_TYPE)
+ : v25_common_device(mconfig, V35, tag, owner, clock, true, 6, 2, V30_TYPE)
{
}
@@ -86,6 +87,7 @@ device_memory_interface::space_config_vector v25_common_device::memory_space_con
{
return space_config_vector {
std::make_pair(AS_PROGRAM, &m_program_config),
+ std::make_pair(AS_DATA, &m_data_config),
std::make_pair(AS_IO, &m_io_config)
};
}
@@ -177,8 +179,6 @@ uint8_t v25_common_device::fetchop()
void v25_common_device::device_reset()
{
- attotime time;
-
m_ip = 0;
m_IBRK = 1;
m_F0 = 0;
@@ -216,10 +216,12 @@ void v25_common_device::device_reset()
m_RAMEN = 1;
m_TB = 20;
m_PCK = 8;
- m_IDB = 0xFFE00;
+ m_RFM = 0xfc;
+ m_WTC = 0xffff;
+ m_IDB = 0xffe00;
- int tmp = m_PCK << m_TB;
- time = attotime::from_hz(unscaled_clock()) * tmp;
+ unsigned tmp = m_PCK << m_TB;
+ attotime time = clocks_to_attotime(tmp);
m_timers[3]->adjust(time, INTTB, time);
m_timers[0]->adjust(attotime::never);
@@ -462,7 +464,6 @@ void v25_common_device::device_start()
for (i = 0; i < 4; i++)
m_timers[i] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(v25_common_device::v25_timer_callback),this));
- save_item(NAME(m_ram.w));
save_item(NAME(m_intp_state));
save_item(NAME(m_ip));
@@ -506,6 +507,8 @@ void v25_common_device::device_start()
save_item(NAME(m_RAMEN));
save_item(NAME(m_TB));
save_item(NAME(m_PCK));
+ save_item(NAME(m_RFM));
+ save_item(NAME(m_WTC));
save_item(NAME(m_IDB));
save_item(NAME(m_prefetch_count));
save_item(NAME(m_prefetch_reset));
@@ -518,6 +521,7 @@ void v25_common_device::device_start()
auto cache = m_program->cache<1, 0, ENDIANNESS_LITTLE>();
m_dr8 = [cache](offs_t address) -> u8 { return cache->read_byte(address); };
}
+ m_data = &space(AS_DATA);
m_io = &space(AS_IO);
m_pt_in.resolve_safe(0xff);
diff --git a/src/devices/cpu/nec/v25.h b/src/devices/cpu/nec/v25.h
index af7d5eb4d93..3f651337667 100644
--- a/src/devices/cpu/nec/v25.h
+++ b/src/devices/cpu/nec/v25.h
@@ -74,7 +74,7 @@ public:
protected:
// construction/destruction
- v25_common_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, bool is_16bit, offs_t fetch_xor, uint8_t prefetch_size, uint8_t prefetch_cycles, uint32_t chip_type);
+ v25_common_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, bool is_16bit, uint8_t prefetch_size, uint8_t prefetch_cycles, uint32_t chip_type);
// device-level overrides
virtual void device_start() override;
@@ -105,17 +105,11 @@ protected:
private:
address_space_config m_program_config;
+ address_space_config m_data_config;
address_space_config m_io_config;
/* internal RAM and register banks */
- union internalram
- {
- uint16_t w[128];
- uint8_t b[256];
- };
-
- internalram m_ram;
- offs_t m_fetch_xor;
+ required_shared_ptr<uint16_t> m_internal_ram;
uint16_t m_ip;
@@ -146,10 +140,13 @@ private:
/* system control */
uint8_t m_RAMEN, m_TB, m_PCK; /* PRC register */
+ uint8_t m_RFM;
+ uint16_t m_WTC;
uint32_t m_IDB;
address_space *m_program;
std::function<u8 (offs_t address)> m_dr8;
+ address_space *m_data;
address_space *m_io;
int m_icount;
@@ -194,12 +191,60 @@ private:
void nec_bankswitch(unsigned bank_num);
void nec_trap();
void external_int();
+
+ void ida_sfr_map(address_map &map);
uint8_t read_irqcontrol(int /*INTSOURCES*/ source, uint8_t priority);
- uint8_t read_sfr(unsigned o);
- uint16_t read_sfr_word(unsigned o);
void write_irqcontrol(int /*INTSOURCES*/ source, uint8_t d);
- void write_sfr(unsigned o, uint8_t d);
- void write_sfr_word(unsigned o, uint16_t d);
+ uint8_t p0_r();
+ void p0_w(uint8_t d);
+ void pm0_w(uint8_t d);
+ void pmc0_w(uint8_t d);
+ uint8_t p1_r();
+ void p1_w(uint8_t d);
+ void pm1_w(uint8_t d);
+ void pmc1_w(uint8_t d);
+ uint8_t p2_r();
+ void p2_w(uint8_t d);
+ void pm2_w(uint8_t d);
+ void pmc2_w(uint8_t d);
+ uint8_t pt_r();
+ void pmt_w(uint8_t d);
+ uint8_t exic0_r();
+ void exic0_w(uint8_t d);
+ uint8_t exic1_r();
+ void exic1_w(uint8_t d);
+ uint8_t exic2_r();
+ void exic2_w(uint8_t d);
+ uint16_t tm0_r();
+ void tm0_w(uint16_t d);
+ uint16_t md0_r();
+ void md0_w(uint16_t d);
+ uint16_t tm1_r();
+ void tm1_w(uint16_t d);
+ uint16_t md1_r();
+ void md1_w(uint16_t d);
+ void tmc0_w(uint8_t d);
+ void tmc1_w(uint8_t d);
+ uint8_t tmic0_r();
+ void tmic0_w(uint8_t d);
+ uint8_t tmic1_r();
+ void tmic1_w(uint8_t d);
+ uint8_t tmic2_r();
+ void tmic2_w(uint8_t d);
+ uint8_t rfm_r();
+ void rfm_w(uint8_t d);
+ uint16_t wtc_r();
+ void wtc_w(offs_t a, uint16_t d, uint16_t m);
+ uint8_t flag_r();
+ void flag_w(uint8_t d);
+ uint8_t prc_r();
+ void prc_w(uint8_t d);
+ uint8_t tbic_r();
+ void tbic_w(uint8_t d);
+ uint8_t irqs_r();
+ uint8_t ispr_r();
+ uint8_t idb_r();
+ void idb_w(uint8_t d);
uint8_t v25_read_byte(unsigned a);
uint16_t v25_read_word(unsigned a);
void v25_write_byte(unsigned a, uint8_t d);
diff --git a/src/devices/cpu/nec/v25instr.hxx b/src/devices/cpu/nec/v25instr.hxx
index e394e9ab213..9d1fcccfdee 100644
--- a/src/devices/cpu/nec/v25instr.hxx
+++ b/src/devices/cpu/nec/v25instr.hxx
@@ -26,13 +26,13 @@
#define MOVSPA \
tmp = (Wreg(PSW_SAVE) & 0x7000) >> 8; \
- Sreg(SS) = m_ram.w[tmp+SS]; \
- Wreg(SP) = m_ram.w[tmp+SP]
+ Sreg(SS) = m_internal_ram[tmp+SS]; \
+ Wreg(SP) = m_internal_ram[tmp+SP]
#define MOVSPB \
tmp <<= 4; \
- m_ram.w[tmp+SS] = Sreg(SS); \
- m_ram.w[tmp+SP] = Wreg(SP)
+ m_internal_ram[tmp+SS] = Sreg(SS); \
+ m_internal_ram[tmp+SP] = Wreg(SP)
#define FINT \
for(tmp = 1; tmp < 0x100; tmp <<= 1) { \
diff --git a/src/devices/cpu/nec/v25priv.h b/src/devices/cpu/nec/v25priv.h
index a5e1b484808..018bd5c94d9 100644
--- a/src/devices/cpu/nec/v25priv.h
+++ b/src/devices/cpu/nec/v25priv.h
@@ -93,9 +93,9 @@ enum BREGS {
#define SetRB(x) do { m_RBW = (x) << 4; m_RBB = (x) << 5; } while (0)
-#define Sreg(x) m_ram.w[m_RBW + (x)]
-#define Wreg(x) m_ram.w[m_RBW + (x)]
-#define Breg(x) m_ram.b[m_RBB + (x)]
+#define Sreg(x) m_internal_ram[m_RBW + (x)]
+#define Wreg(x) m_internal_ram[m_RBW + (x)]
+#define Breg(x) reinterpret_cast<uint8_t *>(&m_internal_ram[0])[m_RBB + (x)]
#define PC() ((Sreg(PS)<<4)+m_ip)
diff --git a/src/devices/cpu/nec/v25sfr.cpp b/src/devices/cpu/nec/v25sfr.cpp
index 788ab419b29..acab173e363 100644
--- a/src/devices/cpu/nec/v25sfr.cpp
+++ b/src/devices/cpu/nec/v25sfr.cpp
@@ -2,7 +2,7 @@
// copyright-holders:Bryan McPhail, Alex W. Jackson
/****************************************************************************
- NEC V25/V35 special function registers and internal ram access
+ NEC V25/V35 special function registers and internal data area access
****************************************************************************/
@@ -10,6 +10,42 @@
#include "v25.h"
#include "v25priv.h"
+void v25_common_device::ida_sfr_map(address_map &map)
+{
+ map(0x000, 0x0ff).ram().share("internal_ram");
+ map(0x100, 0x100).rw(FUNC(v25_common_device::p0_r), FUNC(v25_common_device::p0_w));
+ map(0x101, 0x101).w(FUNC(v25_common_device::pm0_w));
+ map(0x102, 0x102).w(FUNC(v25_common_device::pmc0_w));
+ map(0x108, 0x108).rw(FUNC(v25_common_device::p1_r), FUNC(v25_common_device::p1_w));
+ map(0x109, 0x109).w(FUNC(v25_common_device::pm1_w));
+ map(0x10a, 0x10a).w(FUNC(v25_common_device::pmc1_w));
+ map(0x110, 0x110).rw(FUNC(v25_common_device::p2_r), FUNC(v25_common_device::p2_w));
+ map(0x111, 0x111).w(FUNC(v25_common_device::pm2_w));
+ map(0x112, 0x112).w(FUNC(v25_common_device::pmc2_w));
+ map(0x138, 0x138).r(FUNC(v25_common_device::pt_r));
+ map(0x13b, 0x13b).w(FUNC(v25_common_device::pmt_w));
+ map(0x14c, 0x14c).rw(FUNC(v25_common_device::exic0_r), FUNC(v25_common_device::exic0_w));
+ map(0x14d, 0x14d).rw(FUNC(v25_common_device::exic1_r), FUNC(v25_common_device::exic1_w));
+ map(0x14e, 0x14e).rw(FUNC(v25_common_device::exic2_r), FUNC(v25_common_device::exic2_w));
+ map(0x180, 0x181).rw(FUNC(v25_common_device::tm0_r), FUNC(v25_common_device::tm0_w));
+ map(0x182, 0x183).rw(FUNC(v25_common_device::md0_r), FUNC(v25_common_device::md0_w));
+ map(0x188, 0x189).rw(FUNC(v25_common_device::tm1_r), FUNC(v25_common_device::tm1_w));
+ map(0x18a, 0x18b).rw(FUNC(v25_common_device::md1_r), FUNC(v25_common_device::md1_w));
+ map(0x190, 0x190).w(FUNC(v25_common_device::tmc0_w));
+ map(0x191, 0x191).w(FUNC(v25_common_device::tmc1_w));
+ map(0x19c, 0x19c).rw(FUNC(v25_common_device::tmic0_r), FUNC(v25_common_device::tmic0_w));
+ map(0x19d, 0x19d).rw(FUNC(v25_common_device::tmic1_r), FUNC(v25_common_device::tmic1_w));
+ map(0x19e, 0x19e).rw(FUNC(v25_common_device::tmic2_r), FUNC(v25_common_device::tmic2_w));
+ map(0x1e1, 0x1e1).rw(FUNC(v25_common_device::rfm_r), FUNC(v25_common_device::rfm_w));
+ map(0x1e8, 0x1e9).rw(FUNC(v25_common_device::wtc_r), FUNC(v25_common_device::wtc_w));
+ map(0x1ea, 0x1ea).rw(FUNC(v25_common_device::flag_r), FUNC(v25_common_device::flag_w));
+ map(0x1eb, 0x1eb).rw(FUNC(v25_common_device::prc_r), FUNC(v25_common_device::prc_w));
+ map(0x1ec, 0x1ec).rw(FUNC(v25_common_device::tbic_r), FUNC(v25_common_device::tbic_w));
+ map(0x1ef, 0x1ef).r(FUNC(v25_common_device::irqs_r));
+ map(0x1fc, 0x1fc).r(FUNC(v25_common_device::ispr_r));
+ map(0x1ff, 0x1ff).rw(FUNC(v25_common_device::idb_r), FUNC(v25_common_device::idb_w));
+}
+
uint8_t v25_common_device::read_irqcontrol(int /*INTSOURCES*/ source, uint8_t priority)
{
return (((m_pending_irq & source) ? 0x80 : 0x00)
@@ -18,386 +54,436 @@ uint8_t v25_common_device::read_irqcontrol(int /*INTSOURCES*/ source, uint8_t pr
| priority);
}
-uint8_t v25_common_device::read_sfr(unsigned o)
-{
- uint8_t ret;
-
- switch(o)
- {
- case 0x00: /* P0 */
- ret = m_p0_in();
- break;
- case 0x08: /* P1 */
- /* P1 is combined with the interrupt lines */
- ret = ((m_p1_in() & 0xF0)
- | (m_nmi_state ? 0x00 : 0x01)
- | (m_intp_state[0] ? 0x00 : 0x02)
- | (m_intp_state[1] ? 0x00 : 0x04)
- | (m_intp_state[2] ? 0x00 : 0x08));
- break;
- case 0x10: /* P2 */
- ret = m_p2_in();
- break;
- case 0x38: /* PT */
- ret = m_pt_in();
- break;
- case 0x4C: /* EXIC0 */
- ret = read_irqcontrol(INTP0, m_priority_intp);
- break;
- case 0x4D: /* EXIC1 */
- ret = read_irqcontrol(INTP1, 7);
- break;
- case 0x4E: /* EXIC2 */
- ret = read_irqcontrol(INTP2, 7);
- break;
- case 0x9C: /* TMIC0 */
- ret = read_irqcontrol(INTTU0, m_priority_inttu);
- break;
- case 0x9D: /* TMIC1 */
- ret = read_irqcontrol(INTTU1, 7);
- break;
- case 0x9E: /* TMIC2 */
- ret = read_irqcontrol(INTTU2, 7);
- break;
- case 0xEA: /* FLAG */
- ret = ((m_F0 << 3) | (m_F1 << 5));
- break;
- case 0xEB: /* PRC */
- ret = (m_RAMEN ? 0x40 : 0);
- switch (m_TB)
- {
- case 10:
- break;
- case 13:
- ret |= 0x04;
- break;
- case 16:
- ret |= 0x08;
- break;
- case 20:
- ret |= 0x0C;
- break;
- }
- switch (m_PCK)
- {
- case 2:
- break;
- case 4:
- ret |= 0x01;
- break;
- case 8:
- ret |= 0x02;
- break;
- }
- break;
- case 0xEC: /* TBIC */
- ret = read_irqcontrol(INTTB, 7);
- break;
- case 0xEF: /* IRQS */
- ret = m_IRQS;
- break;
- case 0xFC: /* ISPR */
- ret = m_ISPR;
- break;
- case 0xFF: /* IDB */
- ret = (m_IDB >> 12);
- break;
- default:
- logerror("%06x: Read from special function register %02x\n",PC(),o);
- ret = 0;
- }
- return ret;
-}
-
-uint16_t v25_common_device::read_sfr_word(unsigned o)
-{
- uint16_t ret;
-
- switch(o)
- {
- case 0x80: /* TM0 */
- logerror("%06x: Warning: read back TM0\n",PC());
- ret = m_TM0;
- break;
- case 0x82: /* MD0 */
- logerror("%06x: Warning: read back MD0\n",PC());
- ret = m_MD0;
- break;
- case 0x88: /* TM1 */
- logerror("%06x: Warning: read back TM1\n",PC());
- ret = m_TM1;
- break;
- case 0x8A: /* MD1 */
- logerror("%06x: Warning: read back MD1\n",PC());
- ret = m_MD1;
- break;
- default:
- ret = (read_sfr(o) | (read_sfr(o+1) << 8));
- }
- return ret;
-}
-
void v25_common_device::write_irqcontrol(int /*INTSOURCES*/ source, uint8_t d)
{
- if(d & 0x80)
+ if (BIT(d, 7))
m_pending_irq |= source;
else
m_pending_irq &= ~source;
- if(d & 0x40)
+ if (BIT(d, 6))
m_unmasked_irq &= ~source;
else
m_unmasked_irq |= source;
- if(d & 0x20)
+ if (BIT(d, 5))
logerror("%06x: Warning: macro service function not implemented\n",PC());
- if(d & 0x10)
+ if (BIT(d, 4))
m_bankswitch_irq |= source;
else
m_bankswitch_irq &= ~source;
}
-void v25_common_device::write_sfr(unsigned o, uint8_t d)
+uint8_t v25_common_device::p0_r()
{
- int tmp;
- attotime time;
+ return m_p0_in();
+}
- static const int timebases[4] = { 10, 13, 16, 20 };
- static const int clocks[4] = { 2, 4, 8, 0 };
+void v25_common_device::p0_w(uint8_t d)
+{
+ m_p0_out(d);
+}
- switch(o)
- {
- case 0x00: /* P0 */
- m_p0_out(d);
- break;
- case 0x08: /* P1 */
- /* only the upper four bits of P1 can be used as output */
- m_p1_out(d & 0xF0);
- break;
- case 0x10: /* P2 */
- m_p2_out(d);
- break;
- case 0x4C: /* EXIC0 */
- write_irqcontrol(INTP0, d);
- m_priority_intp = d & 0x7;
- break;
- case 0x4D: /* EXIC1 */
- write_irqcontrol(INTP1, d);
- break;
- case 0x4E: /* EXIC2 */
- write_irqcontrol(INTP2, d);
- break;
- case 0x90: /* TMC0 */
- m_TMC0 = d;
- if(d & 1) /* oneshot mode */
- {
- if(d & 0x80)
- {
- tmp = m_PCK * m_TM0 * ((d & 0x40) ? 128 : 12 );
- time = attotime::from_hz(unscaled_clock()) * tmp;
- m_timers[0]->adjust(time, INTTU0);
- }
- else
- m_timers[0]->adjust(attotime::never);
-
- if(d & 0x20)
- {
- tmp = m_PCK * m_MD0 * ((d & 0x10) ? 128 : 12 );
- time = attotime::from_hz(unscaled_clock()) * tmp;
- m_timers[1]->adjust(time, INTTU1);
- }
- else
- m_timers[1]->adjust(attotime::never);
- }
- else /* interval mode */
- {
- if(d & 0x80)
- {
- tmp = m_PCK * m_MD0 * ((d & 0x40) ? 128 : 6 );
- time = attotime::from_hz(unscaled_clock()) * tmp;
- m_timers[0]->adjust(time, INTTU0, time);
- m_timers[1]->adjust(attotime::never);
- m_TM0 = m_MD0;
- }
- else
- {
- m_timers[0]->adjust(attotime::never);
- m_timers[1]->adjust(attotime::never);
- }
- }
- break;
- case 0x91: /* TMC1 */
- m_TMC1 = d & 0xC0;
- if(d & 0x80)
- {
- tmp = m_PCK * m_MD1 * ((d & 0x40) ? 128 : 6 );
- time = attotime::from_hz(unscaled_clock()) * tmp;
- m_timers[2]->adjust(time, INTTU2, time);
- m_TM1 = m_MD1;
- }
- else
- m_timers[2]->adjust(attotime::never);
- break;
- case 0x9C: /* TMIC0 */
- write_irqcontrol(INTTU0, d);
- m_priority_inttu = d & 0x7;
- break;
- case 0x9D: /* TMIC1 */
- write_irqcontrol(INTTU1, d);
- break;
- case 0x9E: /* TMIC2 */
- write_irqcontrol(INTTU2, d);
- break;
- case 0xEA: /* FLAG */
- m_F0 = ((d & 0x08) == 0x08);
- m_F1 = ((d & 0x20) == 0x20);
- break;
- case 0xEB: /* PRC */
- logerror("%06x: PRC set to %02x\n", PC(), d);
- m_RAMEN = ((d & 0x40) == 0x40);
- m_TB = timebases[(d & 0x0C) >> 2];
- m_PCK = clocks[d & 0x03];
- if (m_PCK == 0)
- {
- logerror(" Warning: invalid clock divider\n");
- m_PCK = 8;
- }
- tmp = m_PCK << m_TB;
- time = attotime::from_hz(unscaled_clock()) * tmp;
- m_timers[3]->adjust(time, INTTB, time);
- notify_clock_changed(); /* make device_execute_interface pick up the new clocks_to_cycles() */
- logerror(" Internal RAM %sabled\n", (m_RAMEN ? "en" : "dis"));
- logerror(" Time base set to 2^%d\n", m_TB);
- logerror(" Clock divider set to %d\n", m_PCK);
- break;
- case 0xEC: /* TBIC */
- /* time base interrupt doesn't support macro service, bank switching or priority control */
- write_irqcontrol(INTTB, d & 0xC0);
- break;
- case 0xFF: /* IDB */
- m_IDB = (d << 12) | 0xE00;
- logerror("%06x: IDB set to %02x\n",PC(),d);
- break;
- default:
- logerror("%06x: Wrote %02x to special function register %02x\n",PC(),d,o);
- }
+void v25_common_device::pm0_w(uint8_t d)
+{
+ logerror("%06x: PM0 set to %02x\n", PC(), d);
}
-void v25_common_device::write_sfr_word(unsigned o, uint16_t d)
+void v25_common_device::pmc0_w(uint8_t d)
{
- switch(o)
- {
- case 0x80: /* TM0 */
- m_TM0 = d;
- break;
- case 0x82: /* MD0 */
- m_MD0 = d;
- break;
- case 0x88: /* TM1 */
- m_TM1 = d;
- break;
- case 0x8A: /* MD1 */
- m_MD1 = d;
- break;
- default:
- write_sfr(o, d);
- write_sfr(o+1, d >> 8);
- }
+ logerror("%06x: PMC0 set to %02x\n", PC(), d);
}
-uint8_t v25_common_device::v25_read_byte(unsigned a)
+uint8_t v25_common_device::p1_r()
{
- if((a & 0xFFE00) == m_IDB || a == 0xFFFFF)
- {
- unsigned o = a & 0x1FF;
+ // P1 is combined with the interrupt lines
+ return ((m_p1_in() & 0xf0)
+ | (m_nmi_state ? 0x00 : 0x01)
+ | (m_intp_state[0] ? 0x00 : 0x02)
+ | (m_intp_state[1] ? 0x00 : 0x04)
+ | (m_intp_state[2] ? 0x00 : 0x08));
+}
- if(m_RAMEN && o < 0x100)
- return m_ram.b[BYTE_XOR_LE(o)];
+void v25_common_device::p1_w(uint8_t d)
+{
+ // only the upper four bits of P1 can be used as output
+ m_p1_out(d & 0xf0);
+}
- if(o >= 0x100)
- return read_sfr(o-0x100);
- }
+void v25_common_device::pm1_w(uint8_t d)
+{
+ logerror("%06x: PM1 set to %02x\n", PC(), d);
+}
- return m_program->read_byte(a);
+void v25_common_device::pmc1_w(uint8_t d)
+{
+ logerror("%06x: PMC1 set to %02x\n", PC(), d);
}
-uint16_t v25_common_device::v25_read_word(unsigned a)
+uint8_t v25_common_device::p2_r()
{
- if( a & 1 )
- return (v25_read_byte(a) | (v25_read_byte(a + 1) << 8));
+ return m_p2_in();
+}
- if((a & 0xFFE00) == m_IDB)
- {
- unsigned o = a & 0x1FF;
+void v25_common_device::p2_w(uint8_t d)
+{
+ m_p2_out(d);
+}
- if(m_RAMEN && o < 0x100)
- return m_ram.w[o/2];
+void v25_common_device::pm2_w(uint8_t d)
+{
+ logerror("%06x: PM2 set to %02x\n", PC(), d);
+}
- if(o >= 0x100)
- return read_sfr_word(o-0x100);
- }
+void v25_common_device::pmc2_w(uint8_t d)
+{
+ logerror("%06x: PMC2 set to %02x\n", PC(), d);
+}
- if(a == 0xFFFFE) /* not sure about this - manual says FFFFC-FFFFE are "reserved" */
- return (m_program->read_byte(a) | (read_sfr(0xFF) << 8));
+uint8_t v25_common_device::pt_r()
+{
+ return m_pt_in();
+}
- return m_program->read_word(a);
+void v25_common_device::pmt_w(uint8_t d)
+{
+ logerror("%06x: PMT set to %02x\n", PC(), d);
}
-void v25_common_device::v25_write_byte(unsigned a, uint8_t d)
+uint8_t v25_common_device::exic0_r()
{
- if((a & 0xFFE00) == m_IDB || a == 0xFFFFF)
- {
- unsigned o = a & 0x1FF;
+ return read_irqcontrol(INTP0, m_priority_intp);
+}
+
+void v25_common_device::exic0_w(uint8_t d)
+{
+ write_irqcontrol(INTP0, d);
+ m_priority_intp = d & 0x7;
+}
+
+uint8_t v25_common_device::exic1_r()
+{
+ return read_irqcontrol(INTP1, 7);
+}
+
+void v25_common_device::exic1_w(uint8_t d)
+{
+ write_irqcontrol(INTP1, d);
+}
+
+uint8_t v25_common_device::exic2_r()
+{
+ return read_irqcontrol(INTP2, 7);
+}
- if(m_RAMEN && o < 0x100)
+void v25_common_device::exic2_w(uint8_t d)
+{
+ write_irqcontrol(INTP2, d);
+}
+
+uint16_t v25_common_device::tm0_r()
+{
+ if (!machine().side_effects_disabled())
+ logerror("%06x: Warning: read back TM0\n",PC());
+ return m_TM0;
+}
+
+void v25_common_device::tm0_w(uint16_t d)
+{
+ m_TM0 = d;
+}
+
+uint16_t v25_common_device::md0_r()
+{
+ if (!machine().side_effects_disabled())
+ logerror("%06x: Warning: read back MD0\n",PC());
+ return m_MD0;
+}
+
+void v25_common_device::md0_w(uint16_t d)
+{
+ m_MD0 = d;
+}
+
+uint16_t v25_common_device::tm1_r()
+{
+ if (!machine().side_effects_disabled())
+ logerror("%06x: Warning: read back TM1\n",PC());
+ return m_TM1;
+}
+
+void v25_common_device::tm1_w(uint16_t d)
+{
+ m_TM1 = d;
+}
+
+uint16_t v25_common_device::md1_r()
+{
+ if (!machine().side_effects_disabled())
+ logerror("%06x: Warning: read back MD1\n",PC());
+ return m_MD1;
+}
+
+void v25_common_device::md1_w(uint16_t d)
+{
+ m_MD1 = d;
+}
+
+void v25_common_device::tmc0_w(uint8_t d)
+{
+ m_TMC0 = d;
+ if (BIT(d, 0)) // oneshot mode
+ {
+ if (BIT(d, 7))
{
- m_ram.b[BYTE_XOR_LE(o)] = d;
- return;
+ unsigned tmp = m_PCK * m_TM0 * (BIT(d, 6) ? 128 : 12);
+ attotime time = clocks_to_attotime(tmp);
+ m_timers[0]->adjust(time, INTTU0);
}
+ else
+ m_timers[0]->adjust(attotime::never);
- if(o >= 0x100)
+ if (BIT(d, 5))
+ {
+ unsigned tmp = m_PCK * m_MD0 * (BIT(d, 4) ? 128 : 12);
+ attotime time = clocks_to_attotime(tmp);
+ m_timers[1]->adjust(time, INTTU1);
+ }
+ else
+ m_timers[1]->adjust(attotime::never);
+ }
+ else // interval mode
+ {
+ if (BIT(d, 7))
+ {
+ unsigned tmp = m_PCK * m_MD0 * (BIT(d, 6) ? 128 : 6);
+ attotime time = clocks_to_attotime(tmp);
+ m_timers[0]->adjust(time, INTTU0, time);
+ m_timers[1]->adjust(attotime::never);
+ m_TM0 = m_MD0;
+ }
+ else
{
- write_sfr(o-0x100, d);
- return;
+ m_timers[0]->adjust(attotime::never);
+ m_timers[1]->adjust(attotime::never);
}
}
+}
+
+void v25_common_device::tmc1_w(uint8_t d)
+{
+ m_TMC1 = d & 0xC0;
+ if (BIT(d, 7))
+ {
+ unsigned tmp = m_PCK * m_MD1 * (BIT(d, 6) ? 128 : 6);
+ attotime time = clocks_to_attotime(tmp);
+ m_timers[2]->adjust(time, INTTU2, time);
+ m_TM1 = m_MD1;
+ }
+ else
+ m_timers[2]->adjust(attotime::never);
+}
- m_program->write_byte(a, d);
+uint8_t v25_common_device::tmic0_r()
+{
+ return read_irqcontrol(INTTU0, m_priority_inttu);
}
-void v25_common_device::v25_write_word(unsigned a, uint16_t d)
+void v25_common_device::tmic0_w(uint8_t d)
+{
+ write_irqcontrol(INTTU0, d);
+ m_priority_inttu = d & 0x7;
+}
+
+uint8_t v25_common_device::tmic1_r()
+{
+ return read_irqcontrol(INTTU1, 7);
+}
+
+void v25_common_device::tmic1_w(uint8_t d)
+{
+ write_irqcontrol(INTTU1, d);
+}
+
+uint8_t v25_common_device::tmic2_r()
+{
+ return read_irqcontrol(INTTU2, 7);
+}
+
+void v25_common_device::tmic2_w(uint8_t d)
+{
+ write_irqcontrol(INTTU2, d);
+}
+
+uint8_t v25_common_device::rfm_r()
+{
+ return m_RFM;
+}
+
+void v25_common_device::rfm_w(uint8_t d)
+{
+ m_RFM = d;
+}
+
+uint16_t v25_common_device::wtc_r()
+{
+ return m_WTC;
+}
+
+void v25_common_device::wtc_w(offs_t a, uint16_t d, uint16_t m)
+{
+ m_WTC = (m_WTC & ~m) | (d & m);
+}
+
+uint8_t v25_common_device::flag_r()
+{
+ return (m_F0 << 3) | (m_F1 << 5);
+}
+
+void v25_common_device::flag_w(uint8_t d)
+{
+ m_F0 = BIT(d, 3);
+ m_F1 = BIT(d, 5);
+}
+
+uint8_t v25_common_device::prc_r()
{
- if( a & 1 )
+ uint8_t ret = m_RAMEN ? 0x40 : 0;
+
+ switch (m_TB)
{
- v25_write_byte(a, d);
- v25_write_byte(a + 1, d >> 8);
- return;
+ case 10:
+ break;
+ case 13:
+ ret |= 0x04;
+ break;
+ case 16:
+ ret |= 0x08;
+ break;
+ case 20:
+ ret |= 0x0C;
+ break;
}
- if((a & 0xFFE00) == m_IDB)
+ switch (m_PCK)
{
- unsigned o = a & 0x1FF;
+ case 2:
+ break;
+ case 4:
+ ret |= 0x01;
+ break;
+ case 8:
+ ret |= 0x02;
+ break;
+ }
- if(m_RAMEN && o < 0x100)
- {
- m_ram.w[o/2] = d;
- return;
- }
+ return ret;
+}
- if(o >= 0x100)
- {
- write_sfr_word(o-0x100, d);
- return;
- }
- }
+void v25_common_device::prc_w(uint8_t d)
+{
+ static const int timebases[4] = { 10, 13, 16, 20 };
+ static const int clocks[4] = { 2, 4, 8, 0 };
- if(a == 0xFFFFE) /* not sure about this - manual says FFFFC-FFFFE are "reserved" */
+ logerror("%06x: PRC set to %02x\n", PC(), d);
+ m_RAMEN = ((d & 0x40) == 0x40);
+ m_TB = timebases[(d & 0x0C) >> 2];
+ m_PCK = clocks[d & 0x03];
+ if (m_PCK == 0)
{
+ logerror(" Warning: invalid clock divider\n");
+ m_PCK = 8;
+ }
+
+ unsigned tmp = m_PCK << m_TB;
+ attotime time = clocks_to_attotime(tmp);
+ m_timers[3]->adjust(time, INTTB, time);
+ notify_clock_changed(); // make device_execute_interface pick up the new clocks_to_cycles()
+
+ logerror(" Internal RAM %sabled\n", (m_RAMEN ? "en" : "dis"));
+ logerror(" Time base set to 2^%d\n", m_TB);
+ logerror(" Clock divider set to %d\n", m_PCK);
+}
+
+uint8_t v25_common_device::tbic_r()
+{
+ return read_irqcontrol(INTTB, 7);
+}
+
+void v25_common_device::tbic_w(uint8_t d)
+{
+ // time base interrupt doesn't support macro service, bank switching or priority control
+ write_irqcontrol(INTTB, d & 0xC0);
+}
+
+uint8_t v25_common_device::irqs_r()
+{
+ return m_IRQS;
+}
+
+uint8_t v25_common_device::ispr_r()
+{
+ return m_ISPR;
+}
+
+uint8_t v25_common_device::idb_r()
+{
+ return m_IDB >> 12;
+}
+
+void v25_common_device::idb_w(uint8_t d)
+{
+ m_IDB = (d << 12) | 0xe00;
+}
+
+uint8_t v25_common_device::v25_read_byte(unsigned a)
+{
+ if (((a & 0xffe00) == m_IDB && (m_RAMEN || BIT(a, 8))) || a == 0xfffff)
+ return m_data->read_byte(a & 0x1ff);
+ else
+ return m_program->read_byte(a);
+}
+
+uint16_t v25_common_device::v25_read_word(unsigned a)
+{
+ if (BIT(a, 0))
+ return (v25_read_byte(a) | (v25_read_byte(a + 1) << 8));
+
+ // not sure about this - manual says FFFFC-FFFFE are "reserved"
+ if (a == 0xffffe)
+ return (m_program->read_byte(a) | (m_data->read_byte(0x1ff) << 8));
+ else if ((a & 0xffe00) == m_IDB && (m_RAMEN || BIT(a, 8)))
+ return m_data->read_word(a & 0x1ff);
+ else
+ return m_program->read_word(a);
+}
+
+void v25_common_device::v25_write_byte(unsigned a, uint8_t d)
+{
+ if (((a & 0xffe00) == m_IDB && (m_RAMEN || BIT(a, 8))) || a == 0xfffff)
+ m_data->write_byte(a & 0x1ff, d);
+ else
m_program->write_byte(a, d);
- write_sfr(0xFF, d >> 8);
+}
+
+void v25_common_device::v25_write_word(unsigned a, uint16_t d)
+{
+ if (BIT(a, 0))
+ {
+ v25_write_byte(a, d);
+ v25_write_byte(a + 1, d >> 8);
return;
}
- m_program->write_word(a, d);
+ // not sure about this - manual says FFFFC-FFFFE are "reserved"
+ if (a == 0xffffe)
+ {
+ m_program->write_byte(a, d);
+ m_data->write_byte(0x1ff, d >> 8);
+ }
+ else if ((a & 0xffe00) == m_IDB && (m_RAMEN || BIT(a, 8)))
+ m_data->write_word(a & 0x1ff, d);
+ else
+ m_program->write_word(a, d);
}
diff --git a/src/devices/cpu/nec/v53.cpp b/src/devices/cpu/nec/v53.cpp
deleted file mode 100644
index 5b31c6bcb7e..00000000000
--- a/src/devices/cpu/nec/v53.cpp
+++ /dev/null
@@ -1,599 +0,0 @@
-// license:BSD-3-Clause
-// copyright-holders:Bryan McPhail
-/* V53 */
-
-// V33 / V33A cores with onboard peripherals
-
-// Interrupt Controller is uPD71059 equivalent (a PIC8259 clone?)
-// DMA Controller can operate in modes providing a subset of the uPD71071 or uPD71037 functionality (some modes unavailable / settings ignored) (uPD71071 mode is an extended 8237A, uPD71037 mode is plain 8237A)
-// Serial Controller is based on the uPD71051 but with some changes (i8251 clone?)
-// Timer Unit is functionally identical to uPD71054 (which in turn is said to be the same as a pit8253)
-
-#include "emu.h"
-#include "v53.h"
-
-#include "necpriv.h"
-
-
-
-DEFINE_DEVICE_TYPE(V53, v53_device, "v53", "NEC V53")
-DEFINE_DEVICE_TYPE(V53A, v53a_device, "v53a", "NEC V53A")
-
-WRITE8_MEMBER(v53_base_device::BSEL_w)
-{
- //printf("v53: BSEL_w %02x\n", data);
-}
-
-WRITE8_MEMBER(v53_base_device::BADR_w)
-{
- //printf("v53: BADR_w %02x\n", data);
-}
-
-WRITE8_MEMBER(v53_base_device::BRC_w)
-{
- //printf("v53: BRC_w %02x\n", data);
-}
-
-WRITE8_MEMBER(v53_base_device::WMB0_w)
-{
- //printf("v53: WMB0_w %02x\n", data);
-}
-
-WRITE8_MEMBER(v53_base_device::WCY1_w)
-{
- //printf("v53: WCY1_w %02x\n", data);
-}
-
-WRITE8_MEMBER(v53_base_device::WCY0_w)
-{
- //printf("v53: WCY0_w %02x\n", data);
-}
-
-WRITE8_MEMBER(v53_base_device::WAC_w)
-{
- //printf("v53: WAC_w %02x\n", data);
-}
-
-WRITE8_MEMBER(v53_base_device::TCKS_w)
-{
- //printf("v53: TCKS_w %02x\n", data);
-}
-
-WRITE8_MEMBER(v53_base_device::SBCR_w)
-{
- //printf("v53: SBCR_w %02x\n", data);
-}
-
-WRITE8_MEMBER(v53_base_device::REFC_w)
-{
- //printf("v53: REFC_w %02x\n", data);
-}
-
-WRITE8_MEMBER(v53_base_device::WMB1_w)
-{
- //printf("v53: WMB1_w %02x\n", data);
-}
-
-WRITE8_MEMBER(v53_base_device::WCY2_w)
-{
- //printf("v53: WCY2_w %02x\n", data);
-}
-
-WRITE8_MEMBER(v53_base_device::WCY3_w)
-{
- //printf("v53: WCY3_w %02x\n", data);
-}
-
-WRITE8_MEMBER(v53_base_device::WCY4_w)
-{
- //printf("v53: WCY4_w %02x\n", data);
-}
-
-WRITE8_MEMBER(v53_base_device::SULA_w)
-{
- //printf("v53: SULA_w %02x\n", data);
- m_SULA = data;
- install_peripheral_io();
-}
-
-WRITE8_MEMBER(v53_base_device::TULA_w)
-{
- //printf("v53: TULA_w %02x\n", data);
- m_TULA = data;
- install_peripheral_io();
-}
-
-WRITE8_MEMBER(v53_base_device::IULA_w)
-{
- //printf("v53: IULA_w %02x\n", data);
- m_IULA = data;
- install_peripheral_io();
-}
-
-WRITE8_MEMBER(v53_base_device::DULA_w)
-{
- //printf("v53: DULA_w %02x\n", data);
- m_DULA = data;
- install_peripheral_io();
-}
-
-WRITE8_MEMBER(v53_base_device::OPHA_w)
-{
- //printf("v53: OPHA_w %02x\n", data);
- m_OPHA = data;
- install_peripheral_io();
-}
-
-WRITE8_MEMBER(v53_base_device::OPSEL_w)
-{
- //printf("v53: OPSEL_w %02x\n", data);
- m_OPSEL = data;
- install_peripheral_io();
-}
-
-WRITE8_MEMBER(v53_base_device::SCTL_w)
-{
- // bit 7: unused
- // bit 6: unused
- // bit 5: unused
- // bit 4: SCU input clock source
- // bit 3: uPD71037 DMA mode - Carry A20
- // bit 2: uPD71037 DMA mode - Carry A16
- // bit 1: uPD71037 DMA mode enable (otherwise in uPD71071 mode)
- // bit 0: Onboard pripheral I/O maps to 8-bit boundaries? (otherwise 16-bit)
-
- //printf("v53: SCTL_w %02x\n", data);
- m_SCTL = data;
- install_peripheral_io();
-}
-/*
-m_WCY0 = 0x07;
-m_WCY1 = 0x77;
-m_WCY2 = 0x77;
-m_WCY3 = 0x77;
-m_WCY4 = 0x77;
-m_WMB0 = 0x77;
-m_WMB1 = 0x77;
-m_WAC = 0x00;
-m_TCKS = 0x00;
-m_RFC = 0x80;
-m_SBCR = 0x00;
-m_BRC = 0x00;
-// SCU
-m_SMD = 0x4b;
-m_SCM = 0x00;
-m_SIMK = 0x03;
-m_SST = 0x04;
-// DMA
-m_DCH = 0x01;
-m_DMD = 0x00;
-m_DCC = 0x0000;
-m_DST = 0x00;
-m_DMK = 0x0f;
-*/
-
-void v53_base_device::device_reset()
-{
- v33_base_device::device_reset();
-
- m_SCTL = 0x00;
- m_OPSEL= 0x00;
-
- // peripheral addresses
- m_SULA = 0x00;
- m_TULA = 0x00;
- m_IULA = 0x00;
- m_DULA = 0x00;
- m_OPHA = 0x00;
-
- m_simk = 0x03;
-}
-
-void v53_base_device::device_start()
-{
- v33_base_device::device_start();
-
- m_txd_handler.resolve_safe();
- m_rts_handler.resolve_safe();
- m_dtr_handler.resolve_safe();
- m_rxrdy_handler.resolve_safe();
- m_txrdy_handler.resolve_safe();
- m_txempty_handler.resolve_safe();
-
- m_out0_handler.resolve_safe();
- m_out1_handler.resolve_safe();
- m_out2_handler.resolve_safe();
-
- m_out_hreq_cb.resolve_safe();
- m_out_eop_cb.resolve_safe();
- m_in_memr_cb.resolve_safe(0);
- m_out_memw_cb.resolve_safe();
- m_in_ior_0_cb.resolve_safe(0);
- m_in_ior_1_cb.resolve_safe(0);
- m_in_ior_2_cb.resolve_safe(0);
- m_in_ior_3_cb.resolve_safe(0);
- m_out_iow_0_cb.resolve_safe();
- m_out_iow_1_cb.resolve_safe();
- m_out_iow_2_cb.resolve_safe();
- m_out_iow_3_cb.resolve_safe();
- m_out_dack_0_cb.resolve_safe();
- m_out_dack_1_cb.resolve_safe();
- m_out_dack_2_cb.resolve_safe();
- m_out_dack_3_cb.resolve_safe();
-
- set_irq_acknowledge_callback(device_irq_acknowledge_delegate(FUNC(pic8259_device::inta_cb), (pic8259_device*)m_v53icu));
-
- save_item(NAME(m_SCTL));
- save_item(NAME(m_OPSEL));
- save_item(NAME(m_SULA));
- save_item(NAME(m_TULA));
- save_item(NAME(m_IULA));
- save_item(NAME(m_DULA));
- save_item(NAME(m_OPHA));
-
- save_item(NAME(m_simk));
-}
-
-void v53_base_device::device_post_load()
-{
- install_peripheral_io();
-}
-
-void v53_base_device::install_peripheral_io()
-{
- // unmap everything in I/O space up to the fixed position registers (we avoid overwriting them, it isn't a valid config)
- space(AS_IO).unmap_readwrite(0x1000, 0xfeff); // todo, we need to have a way to NOT unmap things defined in the drivers, but instead have this act as an overlay mapping / unampping only!!
-
- // IOAG determines if the handlers used 8-bit or 16-bit access
- // the hng64.c games first set everything up in 8-bit mode, then
- // do the procedure again in 16-bit mode before using them?!
-
- int IOAG = m_SCTL & 1;
-
- if (m_OPSEL & 0x01) // DMA Unit available
- {
- uint16_t base = (m_OPHA << 8) | m_DULA;
- base &= 0xfffe;
-
- if (m_SCTL & 0x02) // uPD71037 mode
- {
- if (IOAG) // 8-bit
- {
- }
- else
- {
- }
- }
- else // uPD71071 mode
- {
- space(AS_IO).install_readwrite_handler(base+0x00, base+0x0f, read8_delegate(FUNC(upd71071_v53_device::read), (upd71071_v53_device*)m_v53dmau), write8_delegate(FUNC(upd71071_v53_device::write), (upd71071_v53_device*)m_v53dmau), 0xffff);
- }
- }
-
- if (m_OPSEL & 0x02) // Interrupt Control Unit available
- {
- uint16_t base = (m_OPHA << 8) | m_IULA;
- base &= 0xfffe;
-
- if (IOAG) // 8-bit
- {
- space(AS_IO).install_readwrite_handler(base+0x00, base+0x01, read8sm_delegate(FUNC(pic8259_device::read), (pic8259_device*)m_v53icu), write8sm_delegate(FUNC(pic8259_device::write), (pic8259_device*)m_v53icu), 0xffff);
- }
- else
- {
- space(AS_IO).install_readwrite_handler(base+0x00, base+0x03, read8sm_delegate(FUNC(pic8259_device::read), (pic8259_device*)m_v53icu), write8sm_delegate(FUNC(pic8259_device::write), (pic8259_device*)m_v53icu), 0x00ff);
- }
- }
-
- if (m_OPSEL & 0x04) // Timer Control Unit available
- {
- uint16_t base = (m_OPHA << 8) | m_TULA;
- //printf("installing TCU to %04x\n", base);
- base &= 0xfffe;
-
- if (IOAG) // 8-bit
- {
- space(AS_IO).install_readwrite_handler(base+0x00, base+0x01, read8_delegate(FUNC(v53_base_device::tmu_tst0_r), this), write8_delegate(FUNC(v53_base_device::tmu_tct0_w), this), 0x00ff);
- space(AS_IO).install_readwrite_handler(base+0x00, base+0x01, read8_delegate(FUNC(v53_base_device::tmu_tst1_r), this), write8_delegate(FUNC(v53_base_device::tmu_tct1_w), this), 0xff00);
- space(AS_IO).install_readwrite_handler(base+0x02, base+0x03, read8_delegate(FUNC(v53_base_device::tmu_tst2_r), this), write8_delegate(FUNC(v53_base_device::tmu_tct2_w), this), 0x00ff);
- space(AS_IO).install_write_handler(base+0x02, base+0x03, write8_delegate(FUNC(v53_base_device::tmu_tmd_w), this), 0xff00);
- }
- else
- {
- space(AS_IO).install_readwrite_handler(base+0x00, base+0x01, read8_delegate(FUNC(v53_base_device::tmu_tst0_r), this), write8_delegate(FUNC(v53_base_device::tmu_tct0_w), this), 0x00ff);
- space(AS_IO).install_readwrite_handler(base+0x02, base+0x03, read8_delegate(FUNC(v53_base_device::tmu_tst1_r), this), write8_delegate(FUNC(v53_base_device::tmu_tct1_w), this), 0x00ff);
- space(AS_IO).install_readwrite_handler(base+0x04, base+0x05, read8_delegate(FUNC(v53_base_device::tmu_tst2_r), this), write8_delegate(FUNC(v53_base_device::tmu_tct2_w), this), 0x00ff);
- space(AS_IO).install_write_handler(base+0x06, base+0x07, write8_delegate(FUNC(v53_base_device::tmu_tmd_w), this), 0x00ff);
- }
- }
-
- if (m_OPSEL & 0x08) // Serial Control Unit available
- {
- uint16_t base = (m_OPHA << 8) | m_SULA;
- base &= 0xfffe;
-
- if (IOAG) // 8-bit
- {
- space(AS_IO).install_readwrite_handler(base+0x00, base+0x01, read8smo_delegate(FUNC(v53_scu_device::data_r), m_v53scu.target()), write8smo_delegate(FUNC(v53_scu_device::data_w), m_v53scu.target()), 0x00ff);
- space(AS_IO).install_readwrite_handler(base+0x00, base+0x01, read8smo_delegate(FUNC(v53_scu_device::status_r), m_v53scu.target()), write8smo_delegate(FUNC(v53_scu_device::command_w), m_v53scu.target()), 0xff00);
- space(AS_IO).install_write_handler(base+0x02, base+0x03, write8smo_delegate(FUNC(v53_scu_device::mode_w), m_v53scu.target()), 0x00ff);
- space(AS_IO).install_readwrite_handler(base+0x02, base+0x03, read8_delegate(FUNC(v53_base_device::scu_simk_r), this), write8_delegate(FUNC(v53_base_device::scu_simk_w), this), 0xff00);
- }
- else
- {
- space(AS_IO).install_readwrite_handler(base+0x00, base+0x01, read8smo_delegate(FUNC(v53_scu_device::data_r), m_v53scu.target()), write8smo_delegate(FUNC(v53_scu_device::data_w), m_v53scu.target()), 0x00ff);
- space(AS_IO).install_readwrite_handler(base+0x02, base+0x03, read8smo_delegate(FUNC(v53_scu_device::status_r), m_v53scu.target()), write8smo_delegate(FUNC(v53_scu_device::command_w), m_v53scu.target()), 0x00ff);
- space(AS_IO).install_write_handler(base+0x04, base+0x05, write8smo_delegate(FUNC(v53_scu_device::mode_w), m_v53scu.target()), 0x00ff);
- space(AS_IO).install_readwrite_handler(base+0x06, base+0x07, read8_delegate(FUNC(v53_base_device::scu_simk_r), this), write8_delegate(FUNC(v53_base_device::scu_simk_w), this), 0x00ff);
-
- }
- }
-
-}
-
-
-
-/*** SCU ***/
-
-
-READ8_MEMBER(v53_base_device::scu_simk_r)
-{
- //printf("v53: scu_simk_r\n");
- return m_simk;
-}
-
-WRITE8_MEMBER(v53_base_device::scu_simk_w)
-{
- m_simk = data;
- //printf("v53: scu_simk_w %02x\n", data);
-}
-
-
-
-/*** TCU ***/
-
-WRITE8_MEMBER(v53_base_device::tmu_tct0_w) { m_v53tcu->write(0, data); }
-WRITE8_MEMBER(v53_base_device::tmu_tct1_w) { m_v53tcu->write(1, data); }
-WRITE8_MEMBER(v53_base_device::tmu_tct2_w) { m_v53tcu->write(2, data); }
-WRITE8_MEMBER(v53_base_device::tmu_tmd_w) { m_v53tcu->write(3, data); }
-
-
-READ8_MEMBER(v53_base_device::tmu_tst0_r) { return m_v53tcu->read(0); }
-READ8_MEMBER(v53_base_device::tmu_tst1_r) { return m_v53tcu->read(1); }
-READ8_MEMBER(v53_base_device::tmu_tst2_r) { return m_v53tcu->read(2); }
-
-
-
-
-
-/*** DMA ***/
-
-// could be wrong / nonexistent
-WRITE_LINE_MEMBER(v53_base_device::dreq0_w)
-{
- if (!(m_SCTL & 0x02))
- {
- m_v53dmau->dreq0_w(state);
- }
- else
- {
- //printf("v53: dreq0 not in 71071mode\n");
- }
-}
-
-WRITE_LINE_MEMBER(v53_base_device::dreq1_w)
-{
- if (!(m_SCTL & 0x02))
- {
- m_v53dmau->dreq1_w(state);
- }
- else
- {
- //printf("v53: dreq1 not in 71071mode\n");
- }
-}
-
-WRITE_LINE_MEMBER(v53_base_device::dreq2_w)
-{
- if (!(m_SCTL & 0x02))
- {
- m_v53dmau->dreq2_w(state);
- }
- else
- {
- //printf("v53: dreq2 not in 71071mode\n");
- }
-}
-
-WRITE_LINE_MEMBER(v53_base_device::dreq3_w)
-{
- if (!(m_SCTL & 0x02))
- {
- m_v53dmau->dreq3_w(state);
- }
- else
- {
- //printf("v53: dreq3 not in 71071mode\n");
- }
-}
-
-WRITE_LINE_MEMBER(v53_base_device::hack_w)
-{
- if (!(m_SCTL & 0x02))
- {
- m_v53dmau->hack_w(state);
- }
- else
- {
- //printf("v53: hack_w not in 71071mode\n");
- }
-}
-
-/* General stuff */
-
-void v53_base_device::v53_internal_port_map(address_map &map)
-{
- v33_internal_port_map(map);
- map(0xffe0, 0xffe0).w(FUNC(v53_base_device::BSEL_w)); // 0xffe0 // uPD71037 DMA mode bank selection register
- map(0xffe1, 0xffe1).w(FUNC(v53_base_device::BADR_w)); // 0xffe1 // uPD71037 DMA mode bank register peripheral mapping (also uses OPHA)
-// AM_RANGE(0xffe2, 0xffe3) // (reserved , 0x00ff) // 0xffe2
-// AM_RANGE(0xffe2, 0xffe3) // (reserved , 0xff00) // 0xffe3
-// AM_RANGE(0xffe4, 0xffe5) // (reserved , 0x00ff) // 0xffe4
-// AM_RANGE(0xffe4, 0xffe5) // (reserved , 0xff00) // 0xffe5
-// AM_RANGE(0xffe6, 0xffe7) // (reserved , 0x00ff) // 0xffe6
-// AM_RANGE(0xffe6, 0xffe7) // (reserved , 0xff00) // 0xffe7
-// AM_RANGE(0xffe8, 0xffe9) // (reserved , 0x00ff) // 0xffe8
- map(0xffe9, 0xffe9).w(FUNC(v53_base_device::BRC_w)); // 0xffe9 // baud rate counter (used for serial peripheral)
- map(0xffea, 0xffea).w(FUNC(v53_base_device::WMB0_w)); // 0xffea // waitstate control
- map(0xffeb, 0xffeb).w(FUNC(v53_base_device::WCY1_w)); // 0xffeb // waitstate control
- map(0xffec, 0xffec).w(FUNC(v53_base_device::WCY0_w)); // 0xffec // waitstate control
- map(0xffed, 0xffed).w(FUNC(v53_base_device::WAC_w)); // 0xffed // waitstate control
-// AM_RANGE(0xffee, 0xffef) // (reserved , 0x00ff) // 0xffee
-// AM_RANGE(0xffee, 0xffef) // (reserved , 0xff00) // 0xffef
- map(0xfff0, 0xfff0).w(FUNC(v53_base_device::TCKS_w)); // 0xfff0 // timer clocks
- map(0xfff1, 0xfff1).w(FUNC(v53_base_device::SBCR_w)); // 0xfff1 // internal clock divider, halt behavior etc.
- map(0xfff2, 0xfff2).w(FUNC(v53_base_device::REFC_w)); // 0xfff2 // ram refresh control
- map(0xfff3, 0xfff3).w(FUNC(v53_base_device::WMB1_w)); // 0xfff3 // waitstate control
- map(0xfff4, 0xfff4).w(FUNC(v53_base_device::WCY2_w)); // 0xfff4 // waitstate control
- map(0xfff5, 0xfff5).w(FUNC(v53_base_device::WCY3_w)); // 0xfff5 // waitstate control
- map(0xfff6, 0xfff6).w(FUNC(v53_base_device::WCY4_w)); // 0xfff6 // waitstate control
-// AM_RANGE(0xfff6, 0xfff7) // (reserved , 0xff00) // 0xfff7
- map(0xfff8, 0xfff8).w(FUNC(v53_base_device::SULA_w)); // 0xfff8 // peripheral mapping
- map(0xfff9, 0xfff9).w(FUNC(v53_base_device::TULA_w)); // 0xfff9 // peripheral mapping
- map(0xfffa, 0xfffa).w(FUNC(v53_base_device::IULA_w)); // 0xfffa // peripheral mapping
- map(0xfffb, 0xfffb).w(FUNC(v53_base_device::DULA_w)); // 0xfffb // peripheral mapping
- map(0xfffc, 0xfffc).w(FUNC(v53_base_device::OPHA_w)); // 0xfffc // peripheral mapping (upper bits, common)
- map(0xfffd, 0xfffd).w(FUNC(v53_base_device::OPSEL_w)); // 0xfffd // peripheral enabling
- map(0xfffe, 0xfffe).w(FUNC(v53_base_device::SCTL_w)); // 0xfffe // peripheral configuration (& byte / word mapping)
-// AM_RANGE(0xfffe, 0xffff) // (reserved , 0xff00) // 0xffff
-}
-
-
-
-
-READ8_MEMBER(v53_base_device::get_pic_ack)
-{
- return 0;
-}
-
-
-
-// the external interface provides no external access to the usual IRQ line of the V33, everything goes through the interrupt controller
-void v53_base_device::execute_set_input(int irqline, int state)
-{
- switch (irqline)
- {
- case INPUT_LINE_IRQ0: m_v53icu->ir0_w(state); break;
- case INPUT_LINE_IRQ1: m_v53icu->ir1_w(state); break;
- case INPUT_LINE_IRQ2: m_v53icu->ir2_w(state); break;
- case INPUT_LINE_IRQ3: m_v53icu->ir3_w(state); break;
- case INPUT_LINE_IRQ4: m_v53icu->ir4_w(state); break;
- case INPUT_LINE_IRQ5: m_v53icu->ir5_w(state); break;
- case INPUT_LINE_IRQ6: m_v53icu->ir6_w(state); break;
- case INPUT_LINE_IRQ7: m_v53icu->ir7_w(state); break;
-
- case INPUT_LINE_NMI: nec_common_device::execute_set_input(irqline, state); break;
- case NEC_INPUT_LINE_POLL: nec_common_device::execute_set_input(irqline, state); break;
- }
-}
-
-// for hooking the interrupt controller output up to the core
-WRITE_LINE_MEMBER(v53_base_device::internal_irq_w)
-{
- nec_common_device::execute_set_input(0, state);
-}
-
-
-void v53_base_device::device_add_mconfig(machine_config &config)
-{
- PIT8254(config, m_v53tcu, 0); // functionality identical to uPD71054
- m_v53tcu->set_clk<0>(16000000); // manual implicitly claims that these runs at same speed as the CPU
- m_v53tcu->set_clk<1>(16000000);
- m_v53tcu->set_clk<2>(16000000);
- m_v53tcu->out_handler<0>().set([this] (int state) { m_out0_handler(state); });
- m_v53tcu->out_handler<1>().set([this] (int state) { m_out1_handler(state); });
- m_v53tcu->out_handler<2>().set([this] (int state) { m_out2_handler(state); });
-
- V53_DMAU(config, m_v53dmau, 4000000);
- m_v53dmau->out_hreq_callback().set([this] (int state) { m_out_hreq_cb(state); });
- m_v53dmau->out_eop_callback().set([this] (int state) { m_out_eop_cb(state); });
- m_v53dmau->in_memr_callback().set([this] (address_space &space, offs_t offset) { return m_in_memr_cb(space, offset); });
- m_v53dmau->out_memw_callback().set([this] (address_space &space, offs_t offset, uint8_t data) { m_out_memw_cb(space, offset, data); });
- m_v53dmau->in_ior_callback<0>().set([this] (address_space &space, offs_t offset) { return m_in_ior_0_cb(space, offset); });
- m_v53dmau->in_ior_callback<1>().set([this] (address_space &space, offs_t offset) { return m_in_ior_1_cb(space, offset); });
- m_v53dmau->in_ior_callback<2>().set([this] (address_space &space, offs_t offset) { return m_in_ior_2_cb(space, offset); });
- m_v53dmau->in_ior_callback<3>().set([this] (address_space &space, offs_t offset) { return m_in_ior_3_cb(space, offset); });
- m_v53dmau->out_iow_callback<0>().set([this] (address_space &space, offs_t offset, uint8_t data) { m_out_iow_0_cb(space, offset, data); });
- m_v53dmau->out_iow_callback<1>().set([this] (address_space &space, offs_t offset, uint8_t data) { m_out_iow_1_cb(space, offset, data); });
- m_v53dmau->out_iow_callback<2>().set([this] (address_space &space, offs_t offset, uint8_t data) { m_out_iow_2_cb(space, offset, data); });
- m_v53dmau->out_iow_callback<3>().set([this] (address_space &space, offs_t offset, uint8_t data) { m_out_iow_3_cb(space, offset, data); });
- m_v53dmau->out_dack_callback<0>().set([this] (int state) { m_out_dack_0_cb(state); });
- m_v53dmau->out_dack_callback<1>().set([this] (int state) { m_out_dack_1_cb(state); });
- m_v53dmau->out_dack_callback<2>().set([this] (int state) { m_out_dack_2_cb(state); });
- m_v53dmau->out_dack_callback<3>().set([this] (int state) { m_out_dack_3_cb(state); });
-
- PIC8259(config, m_v53icu, 0);
- m_v53icu->out_int_callback().set(FUNC(v53_base_device::internal_irq_w));
- m_v53icu->in_sp_callback().set_constant(1);
- m_v53icu->read_slave_ack_callback().set(FUNC(v53_base_device::get_pic_ack));
-
- V53_SCU(config, m_v53scu, 0);
- m_v53scu->txd_handler().set(FUNC(v53_base_device::scu_txd_trampoline_cb));
- m_v53scu->dtr_handler().set(FUNC(v53_base_device::scu_dtr_trampoline_cb));
- m_v53scu->rts_handler().set(FUNC(v53_base_device::scu_rts_trampoline_cb));
- m_v53scu->rxrdy_handler().set(FUNC(v53_base_device::scu_rxrdy_trampoline_cb));
- m_v53scu->txrdy_handler().set(FUNC(v53_base_device::scu_txrdy_trampoline_cb));
- m_v53scu->txempty_handler().set(FUNC(v53_base_device::scu_txempty_trampoline_cb));
- m_v53scu->syndet_handler().set(FUNC(v53_base_device::scu_syndet_trampoline_cb));
-}
-
-
-v53_base_device::v53_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock) :
- v33_base_device(mconfig, type, tag, owner, clock, address_map_constructor(FUNC(v53_base_device::v53_internal_port_map), this)),
- m_v53tcu(*this, "pit"),
- m_v53dmau(*this, "upd71071dma"),
- m_v53icu(*this, "upd71059pic"),
- m_v53scu(*this, "v53scu"),
- // SCU
- m_txd_handler(*this),
- m_dtr_handler(*this),
- m_rts_handler(*this),
- m_rxrdy_handler(*this),
- m_txrdy_handler(*this),
- m_txempty_handler(*this),
- m_syndet_handler(*this),
- // TCU
- m_out0_handler(*this),
- m_out1_handler(*this),
- m_out2_handler(*this),
- // DMAU
- m_out_hreq_cb(*this),
- m_out_eop_cb(*this),
- m_in_memr_cb(*this),
- m_out_memw_cb(*this),
- m_in_ior_0_cb(*this),
- m_in_ior_1_cb(*this),
- m_in_ior_2_cb(*this),
- m_in_ior_3_cb(*this),
- m_out_iow_0_cb(*this),
- m_out_iow_1_cb(*this),
- m_out_iow_2_cb(*this),
- m_out_iow_3_cb(*this),
- m_out_dack_0_cb(*this),
- m_out_dack_1_cb(*this),
- m_out_dack_2_cb(*this),
- m_out_dack_3_cb(*this)
-{
-}
-
-
-v53_device::v53_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : v53_base_device(mconfig, V53, tag, owner, clock)
-{
-}
-
-
-v53a_device::v53a_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : v53_base_device(mconfig, V53A, tag, owner, clock)
-{
-}
diff --git a/src/devices/cpu/nec/v53.h b/src/devices/cpu/nec/v53.h
deleted file mode 100644
index 70909a619bd..00000000000
--- a/src/devices/cpu/nec/v53.h
+++ /dev/null
@@ -1,277 +0,0 @@
-// license:BSD-3-Clause
-// copyright-holders:Bryan McPhail
-/* V53 */
-#ifndef MAME_CPU_NEC_V53_H
-#define MAME_CPU_NEC_V53_H
-
-#pragma once
-
-#include "nec.h"
-
-#include "machine/am9517a.h"
-#include "machine/i8251.h"
-#include "machine/pic8259.h"
-#include "machine/pit8253.h"
-
-// SCU
-
-#define MCFG_V53_SCU_TXD_HANDLER(_devcb) \
- downcast<v53_base_device &>(*device).set_txd_handler(DEVCB_##_devcb);
-
-#define MCFG_V53_SCU_DTR_HANDLER(_devcb) \
- downcast<v53_base_device &>(*device).set_dtr_handler(DEVCB_##_devcb);
-
-#define MCFG_V53_SCU_RTS_HANDLER(_devcb) \
- downcast<v53_base_device &>(*device).set_rts_handler(DEVCB_##_devcb);
-
-#define MCFG_V53_SCU_RXRDY_HANDLER(_devcb) \
- downcast<v53_base_device &>(*device).set_rxrdy_handler(DEVCB_##_devcb);
-
-#define MCFG_V53_SCU_TXRDY_HANDLER(_devcb) \
- downcast<v53_base_device &>(*device).set_txrdy_handler(DEVCB_##_devcb);
-
-#define MCFG_V53_SCU_TXEMPTY_HANDLER(_devcb) \
- downcast<v53_base_device &>(*device).set_txempty_handler(DEVCB_##_devcb);
-
-#define MCFG_V53_SCU_SYNDET_HANDLER(_devcb) \
- downcast<v53_base_device &>(*device).set_syndet_handler(DEVCB_##_devcb);
-
-// TCU
-#define MCFG_V53_TCU_CLK0(_clk) \
- downcast<v53_base_device &>(*device).set_clk0(_clk);
-
-#define MCFG_V53_TCU_CLK1(_clk) \
- downcast<v53_base_device &>(*device).set_clk1(_clk);
-
-#define MCFG_V53_TCU_CLK2(_clk) \
- downcast<v53_base_device &>(*device).set_clk2(_clk);
-
-#define MCFG_V53_TCU_OUT0_HANDLER(_devcb) \
- downcast<v53_base_device &>(*device).set_out0_handler(DEVCB_##_devcb);
-
-#define MCFG_V53_TCU_OUT1_HANDLER(_devcb) \
- downcast<v53_base_device &>(*device).set_out1_handler(DEVCB_##_devcb);
-
-#define MCFG_V53_TCU_OUT2_HANDLER(_devcb) \
- downcast<v53_base_device &>(*device).set_out2_handler(DEVCB_##_devcb);
-
-// DMAU
-
-#define MCFG_V53_DMAU_OUT_HREQ_CB(_devcb) \
- downcast<v53_base_device &>(*device).set_out_hreq_callback(DEVCB_##_devcb);
-
-#define MCFG_V53_DMAU_OUT_EOP_CB(_devcb) \
- downcast<v53_base_device &>(*device).set_out_eop_callback(DEVCB_##_devcb);
-
-#define MCFG_V53_DMAU_IN_MEMR_CB(_devcb) \
- downcast<v53_base_device &>(*device).set_in_memr_callback(DEVCB_##_devcb);
-
-#define MCFG_V53_DMAU_OUT_MEMW_CB(_devcb) \
- downcast<v53_base_device &>(*device).set_out_memw_callback(DEVCB_##_devcb);
-
-#define MCFG_V53_DMAU_IN_IOR_0_CB(_devcb) \
- downcast<v53_base_device &>(*device).set_in_ior_0_callback(DEVCB_##_devcb);
-
-#define MCFG_V53_DMAU_IN_IOR_1_CB(_devcb) \
- downcast<v53_base_device &>(*device).set_in_ior_1_callback(DEVCB_##_devcb);
-
-#define MCFG_V53_DMAU_IN_IOR_2_CB(_devcb) \
- downcast<v53_base_device &>(*device).set_in_ior_2_callback(DEVCB_##_devcb);
-
-#define MCFG_V53_DMAU_IN_IOR_3_CB(_devcb) \
- downcast<v53_base_device &>(*device).set_in_ior_3_callback(DEVCB_##_devcb);
-
-#define MCFG_V53_DMAU_OUT_IOW_0_CB(_devcb) \
- downcast<v53_base_device &>(*device).set_out_iow_0_callback(DEVCB_##_devcb);
-
-#define MCFG_V53_DMAU_OUT_IOW_1_CB(_devcb) \
- downcast<v53_base_device &>(*device).set_out_iow_1_callback(DEVCB_##_devcb);
-
-#define MCFG_V53_DMAU_OUT_IOW_2_CB(_devcb) \
- downcast<v53_base_device &>(*device).set_out_iow_2_callback(DEVCB_##_devcb);
-
-#define MCFG_V53_DMAU_OUT_IOW_3_CB(_devcb) \
- downcast<v53_base_device &>(*device).set_out_iow_3_callback(DEVCB_##_devcb);
-
-#define MCFG_V53_DMAU_OUT_DACK_0_CB(_devcb) \
- downcast<v53_base_device &>(*device).set_out_dack_0_callback(DEVCB_##_devcb);
-
-#define MCFG_V53_DMAU_OUT_DACK_1_CB(_devcb) \
- downcast<v53_base_device &>(*device).set_out_dack_1_callback(DEVCB_##_devcb);
-
-#define MCFG_V53_DMAU_OUT_DACK_2_CB(_devcb) \
- downcast<v53_base_device &>(*device).set_out_dack_2_callback(DEVCB_##_devcb);
-
-#define MCFG_V53_DMAU_OUT_DACK_3_CB(_devcb) \
- downcast<v53_base_device &>(*device).set_out_dack_3_callback(DEVCB_##_devcb);
-
-
-
-class v53_base_device : public v33_base_device
-{
-public:
- DECLARE_WRITE8_MEMBER(BSEL_w);
- DECLARE_WRITE8_MEMBER(BADR_w);
- DECLARE_WRITE8_MEMBER(BRC_w);
- DECLARE_WRITE8_MEMBER(WMB0_w);
- DECLARE_WRITE8_MEMBER(WCY1_w);
- DECLARE_WRITE8_MEMBER(WCY0_w);
- DECLARE_WRITE8_MEMBER(WAC_w);
- DECLARE_WRITE8_MEMBER(TCKS_w);
- DECLARE_WRITE8_MEMBER(SBCR_w);
- DECLARE_WRITE8_MEMBER(REFC_w);
- DECLARE_WRITE8_MEMBER(WMB1_w);
- DECLARE_WRITE8_MEMBER(WCY2_w);
- DECLARE_WRITE8_MEMBER(WCY3_w);
- DECLARE_WRITE8_MEMBER(WCY4_w);
- DECLARE_WRITE8_MEMBER(SULA_w);
- DECLARE_WRITE8_MEMBER(TULA_w);
- DECLARE_WRITE8_MEMBER(IULA_w);
- DECLARE_WRITE8_MEMBER(DULA_w);
- DECLARE_WRITE8_MEMBER(OPHA_w);
- DECLARE_WRITE8_MEMBER(OPSEL_w);
- DECLARE_WRITE8_MEMBER(SCTL_w);
-
- // SCU
- DECLARE_READ8_MEMBER(scu_simk_r);
- DECLARE_WRITE8_MEMBER(scu_simk_w);
- template <class Object> devcb_base &set_txd_handler(Object &&cb) { return m_txd_handler.set_callback(std::forward<Object>(cb)); }
- template <class Object> devcb_base &set_dtr_handler(Object &&cb) { return m_dtr_handler.set_callback(std::forward<Object>(cb)); }
- template <class Object> devcb_base &set_rts_handler(Object &&cb) { return m_rts_handler.set_callback(std::forward<Object>(cb)); }
- template <class Object> devcb_base &set_rxrdy_handler(Object &&cb) { return m_rxrdy_handler.set_callback(std::forward<Object>(cb)); }
- template <class Object> devcb_base &set_txrdy_handler(Object &&cb) { return m_txrdy_handler.set_callback(std::forward<Object>(cb)); }
- template <class Object> devcb_base &set_txempty_handler(Object &&cb) { return m_txempty_handler.set_callback(std::forward<Object>(cb)); }
- template <class Object> devcb_base &set_syndet_handler(Object &&cb) { return m_syndet_handler.set_callback(std::forward<Object>(cb)); }
- DECLARE_WRITE_LINE_MEMBER(scu_txd_trampoline_cb) { m_txd_handler(state); }
- DECLARE_WRITE_LINE_MEMBER(scu_dtr_trampoline_cb) { m_dtr_handler(state); }
- DECLARE_WRITE_LINE_MEMBER(scu_rts_trampoline_cb) { m_rts_handler(state); }
- DECLARE_WRITE_LINE_MEMBER(scu_rxrdy_trampoline_cb) { m_rxrdy_handler(state); } /* should we mask this here based on m_simk? it can mask the interrupt */
- DECLARE_WRITE_LINE_MEMBER(scu_txrdy_trampoline_cb) { m_txrdy_handler(state); } /* should we mask this here based on m_simk? it can mask the interrupt */
- DECLARE_WRITE_LINE_MEMBER(scu_txempty_trampoline_cb) { m_txempty_handler(state); }
- DECLARE_WRITE_LINE_MEMBER(scu_syndet_trampoline_cb) { m_syndet_handler(state); }
-
- // TCU
- DECLARE_READ8_MEMBER(tmu_tst0_r);
- DECLARE_WRITE8_MEMBER(tmu_tct0_w);
- DECLARE_READ8_MEMBER(tmu_tst1_r);
- DECLARE_WRITE8_MEMBER(tmu_tct1_w);
- DECLARE_READ8_MEMBER(tmu_tst2_r);
- DECLARE_WRITE8_MEMBER(tmu_tct2_w);
- DECLARE_WRITE8_MEMBER(tmu_tmd_w);
-// void set_clk0(double clk0) { m_clk0 = clk0; }
-// void set_clk1(double clk1) { m_clk1 = clk1; }
-// void set_clk2(double clk2) { m_clk2 = clk2; }
- template <class Object> devcb_base &set_out0_handler(Object &&cb) { return m_out0_handler.set_callback(std::forward<Object>(cb)); }
- template <class Object> devcb_base &set_out1_handler(Object &&cb) { return m_out1_handler.set_callback(std::forward<Object>(cb)); }
- template <class Object> devcb_base &set_out2_handler(Object &&cb) { return m_out2_handler.set_callback(std::forward<Object>(cb)); }
-
- // DMAU
- template<class Object> devcb_base &set_out_hreq_callback(Object &&cb) { return m_out_hreq_cb.set_callback(std::forward<Object>(cb)); }
- template<class Object> devcb_base &set_out_eop_callback(Object &&cb) { return m_out_eop_cb.set_callback(std::forward<Object>(cb)); }
- template<class Object> devcb_base &set_in_memr_callback(Object &&cb) { return m_in_memr_cb.set_callback(std::forward<Object>(cb)); }
- template<class Object> devcb_base &set_out_memw_callback(Object &&cb) { return m_out_memw_cb.set_callback(std::forward<Object>(cb)); }
- template<class Object> devcb_base &set_in_ior_0_callback(Object &&cb) { return m_in_ior_0_cb.set_callback(std::forward<Object>(cb)); }
- template<class Object> devcb_base &set_in_ior_1_callback(Object &&cb) { return m_in_ior_1_cb.set_callback(std::forward<Object>(cb)); }
- template<class Object> devcb_base &set_in_ior_2_callback(Object &&cb) { return m_in_ior_2_cb.set_callback(std::forward<Object>(cb)); }
- template<class Object> devcb_base &set_in_ior_3_callback(Object &&cb) { return m_in_ior_3_cb.set_callback(std::forward<Object>(cb)); }
- template<class Object> devcb_base &set_out_iow_0_callback(Object &&cb) { return m_out_iow_0_cb.set_callback(std::forward<Object>(cb)); }
- template<class Object> devcb_base &set_out_iow_1_callback(Object &&cb) { return m_out_iow_1_cb.set_callback(std::forward<Object>(cb)); }
- template<class Object> devcb_base &set_out_iow_2_callback(Object &&cb) { return m_out_iow_2_cb.set_callback(std::forward<Object>(cb)); }
- template<class Object> devcb_base &set_out_iow_3_callback(Object &&cb) { return m_out_iow_3_cb.set_callback(std::forward<Object>(cb)); }
- template<class Object> devcb_base &set_out_dack_0_callback(Object &&cb) { return m_out_dack_0_cb.set_callback(std::forward<Object>(cb)); }
- template<class Object> devcb_base &set_out_dack_1_callback(Object &&cb) { return m_out_dack_1_cb.set_callback(std::forward<Object>(cb)); }
- template<class Object> devcb_base &set_out_dack_2_callback(Object &&cb) { return m_out_dack_2_cb.set_callback(std::forward<Object>(cb)); }
- template<class Object> devcb_base &set_out_dack_3_callback(Object &&cb) { return m_out_dack_3_cb.set_callback(std::forward<Object>(cb)); }
-
- DECLARE_WRITE_LINE_MEMBER(dreq0_w);
- DECLARE_WRITE_LINE_MEMBER(dreq1_w);
- DECLARE_WRITE_LINE_MEMBER(dreq2_w);
- DECLARE_WRITE_LINE_MEMBER(dreq3_w);
- DECLARE_WRITE_LINE_MEMBER(hack_w);
-
- void v53_internal_port_map(address_map &map);
-protected:
- v53_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
-
- // device-level overrides
- virtual void device_add_mconfig(machine_config &config) override;
- virtual void device_start() override;
- virtual void device_reset() override;
- virtual void device_post_load() override;
- virtual void execute_set_input(int inputnum, int state) override;
-
- void install_peripheral_io();
-
- uint8_t m_SCTL;
- uint8_t m_OPSEL;
-
- uint8_t m_SULA;
- uint8_t m_TULA;
- uint8_t m_IULA;
- uint8_t m_DULA;
- uint8_t m_OPHA;
-
- uint8_t m_simk;
-
- required_device<pit8253_device> m_v53tcu;
- required_device<upd71071_v53_device> m_v53dmau;
- required_device<pic8259_device> m_v53icu;
- required_device<v53_scu_device> m_v53scu;
-
- // SCU
- devcb_write_line m_txd_handler;
- devcb_write_line m_dtr_handler;
- devcb_write_line m_rts_handler;
- devcb_write_line m_rxrdy_handler;
- devcb_write_line m_txrdy_handler;
- devcb_write_line m_txempty_handler;
- devcb_write_line m_syndet_handler;
-
- // TCU
-// double m_clk0;
-// double m_clk1;
-// double m_clk2;
- devcb_write_line m_out0_handler;
- devcb_write_line m_out1_handler;
- devcb_write_line m_out2_handler;
-
-
- // DMAU
- devcb_write_line m_out_hreq_cb;
- devcb_write_line m_out_eop_cb;
- devcb_read8 m_in_memr_cb;
- devcb_write8 m_out_memw_cb;
- devcb_read8 m_in_ior_0_cb;
- devcb_read8 m_in_ior_1_cb;
- devcb_read8 m_in_ior_2_cb;
- devcb_read8 m_in_ior_3_cb;
- devcb_write8 m_out_iow_0_cb;
- devcb_write8 m_out_iow_1_cb;
- devcb_write8 m_out_iow_2_cb;
- devcb_write8 m_out_iow_3_cb;
- devcb_write_line m_out_dack_0_cb;
- devcb_write_line m_out_dack_1_cb;
- devcb_write_line m_out_dack_2_cb;
- devcb_write_line m_out_dack_3_cb;
-
- DECLARE_READ8_MEMBER(get_pic_ack);
- DECLARE_WRITE_LINE_MEMBER(internal_irq_w);
-};
-
-
-class v53_device : public v53_base_device
-{
-public:
- v53_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
-};
-
-class v53a_device : public v53_base_device
-{
-public:
- v53a_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
-};
-
-DECLARE_DEVICE_TYPE(V53, v53_device)
-DECLARE_DEVICE_TYPE(V53A, v53a_device)
-
-#endif // MAME_CPU_NEC_V53_H
diff --git a/src/devices/cpu/nec/v5x.cpp b/src/devices/cpu/nec/v5x.cpp
new file mode 100644
index 00000000000..533a112a7a4
--- /dev/null
+++ b/src/devices/cpu/nec/v5x.cpp
@@ -0,0 +1,428 @@
+// license:BSD-3-Clause
+// copyright-holders:Patrick Mackinlay
+
+/*
+ * NEC V5x devices consist of a V3x CPU core plus integrated peripherals. The
+ * CPU cores within each device are as follows:
+ *
+ * Device CPU
+ * V50 (µPD70216) V30 (µPD70116)
+ * V53 (µPD70236) V33 (µPD70136)
+ * V53A (µPD70236A) V33A (µPD70136A)
+ *
+ * The peripherals are nearly identical between all three devices:
+ *
+ * Name Description Device
+ * TCU Timer/Counter Unit µPD71054/i8254 subset
+ * DMAU DMA Control Unit µPD71071 equivalent
+ * ICU Interrupt control Unit µPD71059/i8259 equivalent
+ * SCU Serial Control Unit µPD71051/i8251 subset (async only)
+ *
+ * The V53/V53A DMAU also supports a configurable µPD71037/i8237A mode.
+ *
+ * Sources:
+ *
+ * http://www.chipfind.net/datasheet/pdf/nec/upd70236.pdf
+ * https://datasheet.datasheetarchive.com/originals/scans/Scans-107/DSASCANS15-59637.pdf
+ *
+ */
+#include "emu.h"
+#include "v5x.h"
+
+#include "necpriv.h"
+
+#define VERBOSE 0
+#include "logmacro.h"
+
+DEFINE_DEVICE_TYPE(V50, v50_device, "v50", "NEC V50")
+DEFINE_DEVICE_TYPE(V53, v53_device, "v53", "NEC V53")
+DEFINE_DEVICE_TYPE(V53A, v53a_device, "v53a", "NEC V53A")
+
+WRITE8_MEMBER(v5x_base_device::SULA_w)
+{
+ LOG("SULA_w %02x\n", data);
+ m_SULA = data;
+ install_peripheral_io();
+}
+
+WRITE8_MEMBER(v5x_base_device::TULA_w)
+{
+ LOG("TULA_w %02x\n", data);
+ m_TULA = data;
+ install_peripheral_io();
+}
+
+WRITE8_MEMBER(v5x_base_device::IULA_w)
+{
+ LOG("IULA_w %02x\n", data);
+ m_IULA = data;
+ install_peripheral_io();
+}
+
+WRITE8_MEMBER(v5x_base_device::DULA_w)
+{
+ LOG("DULA_w %02x\n", data);
+ m_DULA = data;
+ install_peripheral_io();
+}
+
+WRITE8_MEMBER(v5x_base_device::OPHA_w)
+{
+ LOG("OPHA_w %02x\n", data);
+ m_OPHA = data;
+ install_peripheral_io();
+}
+
+WRITE8_MEMBER(v5x_base_device::OPSEL_w)
+{
+ LOG("OPSEL_w %02x\n", data);
+ m_OPSEL = data;
+ install_peripheral_io();
+}
+
+WRITE8_MEMBER(v53_device::SCTL_w)
+{
+ // bit 7: unused
+ // bit 6: unused
+ // bit 5: unused
+ // bit 4: SCU input clock source
+ // bit 3: uPD71037 DMA mode - Carry A20
+ // bit 2: uPD71037 DMA mode - Carry A16
+ // bit 1: uPD71037 DMA mode enable (otherwise in uPD71071 mode)
+ // bit 0: Onboard pripheral I/O maps to 8-bit boundaries? (otherwise 16-bit)
+
+ LOG("SCTL_w %02x\n", data);
+ m_SCTL = data;
+ install_peripheral_io();
+}
+
+WRITE8_MEMBER(v50_device::OPCN_w)
+{
+ // bit 7: unused
+ // bit 6: unused
+ // bit 5: unused
+ // bit 4: unused
+ // bit 3: IRSW
+ // bit 2: IRSW
+ // bit 1: PF
+ // bit 0: PF
+
+ LOG("OPCN_w %02x\n", data);
+ m_OPCN = data;
+ install_peripheral_io();
+}
+
+void v5x_base_device::device_reset()
+{
+ v33_base_device::device_reset();
+
+ m_OPSEL= 0x00;
+
+ // peripheral addresses
+ m_SULA = 0x00;
+ m_TULA = 0x00;
+ m_IULA = 0x00;
+ m_DULA = 0x00;
+ m_OPHA = 0x00;
+}
+
+void v50_device::device_reset()
+{
+ v5x_base_device::device_reset();
+
+ m_OPCN = 0;
+}
+
+void v53_device::device_reset()
+{
+ v5x_base_device::device_reset();
+
+ m_SCTL = 0x00;
+}
+
+void v5x_base_device::device_start()
+{
+ v33_base_device::device_start();
+
+ set_irq_acknowledge_callback(device_irq_acknowledge_delegate(FUNC(v5x_icu_device::inta_cb), m_icu.target()));
+
+ save_item(NAME(m_OPSEL));
+ save_item(NAME(m_SULA));
+ save_item(NAME(m_TULA));
+ save_item(NAME(m_IULA));
+ save_item(NAME(m_DULA));
+ save_item(NAME(m_OPHA));
+}
+
+void v50_device::device_start()
+{
+ v5x_base_device::device_start();
+
+ save_item(NAME(m_OPCN));
+}
+
+void v53_device::device_start()
+{
+ v5x_base_device::device_start();
+
+ save_item(NAME(m_SCTL));
+}
+
+void v5x_base_device::device_post_load()
+{
+ install_peripheral_io();
+}
+
+void v53_device::install_peripheral_io()
+{
+ // unmap everything in I/O space up to the fixed position registers (we avoid overwriting them, it isn't a valid config)
+ space(AS_IO).unmap_readwrite(0x1000, 0xfeff);
+
+ // IOAG determines if the handlers used 8-bit or 16-bit access
+ // the hng64.c games first set everything up in 8-bit mode, then
+ // do the procedure again in 16-bit mode before using them?!
+
+ int const IOAG = m_SCTL & 1;
+
+ if (m_OPSEL & OPSEL_DS)
+ {
+ u16 const base = ((m_OPHA << 8) | m_DULA) & 0xfffe;
+
+ if (m_SCTL & 0x02) // uPD71037 mode
+ {
+ if (IOAG) // 8-bit
+ {
+ }
+ else
+ {
+ }
+ }
+ else // uPD71071 mode
+ space(AS_IO).install_readwrite_handler(base + 0x00, base + 0x0f,
+ read8_delegate(FUNC(v5x_dmau_device::read), m_dmau.target()),
+ write8_delegate(FUNC(v5x_dmau_device::write), m_dmau.target()), 0xffff);
+ }
+
+ if (m_OPSEL & OPSEL_IS)
+ {
+ u16 const base = ((m_OPHA << 8) | m_IULA) & 0xfffe;
+
+ if (IOAG) // 8-bit
+ space(AS_IO).install_readwrite_handler(base + 0x00, base + 0x01,
+ read8sm_delegate(FUNC(v5x_icu_device::read), m_icu.target()),
+ write8sm_delegate(FUNC(v5x_icu_device::write), m_icu.target()), 0xffff);
+ else
+ space(AS_IO).install_readwrite_handler(base + 0x00, base + 0x03,
+ read8sm_delegate(FUNC(v5x_icu_device::read), m_icu.target()),
+ write8sm_delegate(FUNC(v5x_icu_device::write), m_icu.target()), 0x00ff);
+ }
+
+ if (m_OPSEL & OPSEL_TS)
+ {
+ u16 const base = ((m_OPHA << 8) | m_TULA) & 0xfffe;
+
+ if (IOAG) // 8-bit
+ space(AS_IO).install_readwrite_handler(base + 0x00, base + 0x03,
+ read8sm_delegate(FUNC(pit8253_device::read), m_tcu.target()),
+ write8sm_delegate(FUNC(pit8253_device::write), m_tcu.target()), 0xffff);
+ else
+ space(AS_IO).install_readwrite_handler(base + 0x00, base + 0x07,
+ read8sm_delegate(FUNC(pit8253_device::read), m_tcu.target()),
+ write8sm_delegate(FUNC(pit8253_device::write), m_tcu.target()), 0x00ff);
+ }
+
+ if (m_OPSEL & OPSEL_SS)
+ {
+ u16 const base = ((m_OPHA << 8) | m_SULA) & 0xfffe;
+
+ if (IOAG) // 8-bit
+ space(AS_IO).install_readwrite_handler(base + 0x00, base + 0x03,
+ read8sm_delegate(FUNC(v5x_scu_device::read), m_scu.target()),
+ write8sm_delegate(FUNC(v5x_scu_device::write), m_scu.target()), 0xffff);
+ else
+ space(AS_IO).install_readwrite_handler(base + 0x00, base + 0x07,
+ read8sm_delegate(FUNC(v5x_scu_device::read), m_scu.target()),
+ write8sm_delegate(FUNC(v5x_scu_device::write), m_scu.target()), 0x00ff);
+ }
+}
+
+WRITE_LINE_MEMBER(v53_device::hack_w)
+{
+ if (!(m_SCTL & 0x02))
+ m_dmau->hack_w(state);
+ else
+ LOG("hack_w not in 71071mode\n");
+}
+
+void v50_device::install_peripheral_io()
+{
+ // unmap everything in I/O space up to the fixed position registers (we avoid overwriting them, it isn't a valid config)
+ space(AS_IO).unmap_readwrite(0x1000, 0xfeff);
+
+ if (m_OPSEL & OPSEL_DS)
+ {
+ u16 const base = ((m_OPHA << 8) | m_DULA) & 0xfffe;
+
+ space(AS_IO).install_readwrite_handler(base + 0x00, base + 0x0f,
+ read8_delegate(FUNC(v5x_dmau_device::read), m_dmau.target()),
+ write8_delegate(FUNC(v5x_dmau_device::write), m_dmau.target()), 0xffff);
+ }
+
+ if (m_OPSEL & OPSEL_IS)
+ {
+ u16 const base = ((m_OPHA << 8) | m_IULA) & 0xfffe;
+
+ space(AS_IO).install_readwrite_handler(base + 0x00, base + 0x03,
+ read8sm_delegate(FUNC(v5x_icu_device::read), m_icu.target()),
+ write8sm_delegate(FUNC(v5x_icu_device::write), m_icu.target()), 0x00ff);
+ }
+
+ if (m_OPSEL & OPSEL_TS)
+ {
+ u16 const base = ((m_OPHA << 8) | m_TULA) & 0xfffe;
+
+ space(AS_IO).install_readwrite_handler(base + 0x00, base + 0x07,
+ read8sm_delegate(FUNC(pit8253_device::read), m_tcu.target()),
+ write8sm_delegate(FUNC(pit8253_device::write), m_tcu.target()), 0x00ff);
+ }
+
+ if (m_OPSEL & OPSEL_SS)
+ {
+ u16 const base = ((m_OPHA << 8) | m_SULA) & 0xfffe;
+
+ space(AS_IO).install_readwrite_handler(base + 0x00, base + 0x07,
+ read8sm_delegate(FUNC(v5x_scu_device::read), m_scu.target()),
+ write8sm_delegate(FUNC(v5x_scu_device::write), m_scu.target()), 0x00ff);
+ }
+}
+
+void v50_device::internal_port_map(address_map &map)
+{
+ v33_internal_port_map(map);
+
+ map(0xfff0, 0xfff0).w(FUNC(v50_device::TCKS_w));
+
+ map(0xfff2, 0xfff2).w(FUNC(v50_device::RFC_w));
+
+ map(0xfff4, 0xfff4).w(FUNC(v50_device::WMB0_w)); // actually WMB on V50
+ map(0xfff5, 0xfff5).w(FUNC(v50_device::WCY1_w));
+ map(0xfff6, 0xfff6).w(FUNC(v50_device::WCY2_w));
+
+ map(0xfff8, 0xfff8).w(FUNC(v50_device::SULA_w));
+ map(0xfff9, 0xfff9).w(FUNC(v50_device::TULA_w));
+ map(0xfffa, 0xfffa).w(FUNC(v50_device::IULA_w));
+ map(0xfffb, 0xfffb).w(FUNC(v50_device::DULA_w));
+ map(0xfffc, 0xfffc).w(FUNC(v50_device::OPHA_w));
+ map(0xfffd, 0xfffd).w(FUNC(v50_device::OPSEL_w));
+ map(0xfffe, 0xfffe).w(FUNC(v50_device::OPCN_w));
+}
+
+void v53_device::internal_port_map(address_map &map)
+{
+ v33_internal_port_map(map);
+
+ map(0xffe0, 0xffe0).w(FUNC(v53_device::BSEL_w)); // uPD71037 DMA mode bank selection register
+ map(0xffe1, 0xffe1).w(FUNC(v53_device::BADR_w)); // uPD71037 DMA mode bank register peripheral mapping (also uses OPHA)
+ // 0xffe2-0xffe9 reserved
+ map(0xffe9, 0xffe9).w(FUNC(v53_device::BRC_w)); // baud rate counter (used for serial peripheral)
+ map(0xffea, 0xffea).w(FUNC(v53_device::WMB0_w)); // waitstate control
+ map(0xffeb, 0xffeb).w(FUNC(v53_device::WCY1_w)); // waitstate control
+ map(0xffec, 0xffec).w(FUNC(v53_device::WCY0_w)); // waitstate control
+ map(0xffed, 0xffed).w(FUNC(v53_device::WAC_w)); // waitstate control
+ // 0xffee-0xffef reserved
+ map(0xfff0, 0xfff0).w(FUNC(v53_device::TCKS_w)); // timer clocks
+ map(0xfff1, 0xfff1).w(FUNC(v53_device::SBCR_w)); // internal clock divider, halt behavior etc.
+ map(0xfff2, 0xfff2).w(FUNC(v53_device::RFC_w)); // ram refresh control
+ map(0xfff3, 0xfff3).w(FUNC(v53_device::WMB1_w)); // waitstate control
+ map(0xfff4, 0xfff4).w(FUNC(v53_device::WCY2_w)); // waitstate control
+ map(0xfff5, 0xfff5).w(FUNC(v53_device::WCY3_w)); // waitstate control
+ map(0xfff6, 0xfff6).w(FUNC(v53_device::WCY4_w)); // waitstate control
+ // 0xfff6 reserved
+ map(0xfff8, 0xfff8).w(FUNC(v53_device::SULA_w)); // scu mapping
+ map(0xfff9, 0xfff9).w(FUNC(v53_device::TULA_w)); // tcu mapping
+ map(0xfffa, 0xfffa).w(FUNC(v53_device::IULA_w)); // icu mapping
+ map(0xfffb, 0xfffb).w(FUNC(v53_device::DULA_w)); // dmau mapping
+ map(0xfffc, 0xfffc).w(FUNC(v53_device::OPHA_w)); // peripheral mapping (upper bits, common)
+ map(0xfffd, 0xfffd).w(FUNC(v53_device::OPSEL_w)); // peripheral enabling
+ map(0xfffe, 0xfffe).w(FUNC(v53_device::SCTL_w)); // peripheral configuration (& byte / word mapping)
+ // 0xffff reserved
+}
+
+// the external interface provides no external access to the usual IRQ line of the V33, everything goes through the interrupt controller
+void v5x_base_device::execute_set_input(int irqline, int state)
+{
+ switch (irqline)
+ {
+ case INPUT_LINE_IRQ0: m_icu->ir0_w(state); break;
+ case INPUT_LINE_IRQ1: m_icu->ir1_w(state); break;
+ case INPUT_LINE_IRQ2: m_icu->ir2_w(state); break;
+ case INPUT_LINE_IRQ3: m_icu->ir3_w(state); break;
+ case INPUT_LINE_IRQ4: m_icu->ir4_w(state); break;
+ case INPUT_LINE_IRQ5: m_icu->ir5_w(state); break;
+ case INPUT_LINE_IRQ6: m_icu->ir6_w(state); break;
+ case INPUT_LINE_IRQ7: m_icu->ir7_w(state); break;
+
+ case INPUT_LINE_NMI: nec_common_device::execute_set_input(irqline, state); break;
+ case NEC_INPUT_LINE_POLL: nec_common_device::execute_set_input(irqline, state); break;
+ }
+}
+
+// for hooking the interrupt controller output up to the core
+WRITE_LINE_MEMBER(v5x_base_device::internal_irq_w)
+{
+ nec_common_device::execute_set_input(0, state);
+}
+
+void v5x_base_device::device_add_mconfig(machine_config &config)
+{
+ PIT8254(config, m_tcu, 0);
+ m_tcu->set_clk<0>(clock());
+ m_tcu->set_clk<1>(clock());
+ m_tcu->set_clk<2>(clock());
+
+ V5X_DMAU(config, m_dmau, 4000000);
+
+ V5X_ICU(config, m_icu, 0);
+ m_icu->out_int_callback().set(FUNC(v5x_base_device::internal_irq_w));
+ m_icu->in_sp_callback().set_constant(1);
+ m_icu->read_slave_ack_callback().set(FUNC(v5x_base_device::get_pic_ack));
+
+ V5X_SCU(config, m_scu, 0);
+}
+
+void v50_device::device_add_mconfig(machine_config &config)
+{
+ v5x_base_device::device_add_mconfig(config);
+
+ // V50 timer 0 is internally connected to INT0
+ m_tcu->out_handler<0>().set(m_icu, FUNC(pic8259_device::ir0_w));
+}
+
+v5x_base_device::v5x_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, address_map_constructor port_map)
+ : v33_base_device(mconfig, type, tag, owner, clock, port_map)
+ , m_tcu(*this, "tcu")
+ , m_dmau(*this, "dmau")
+ , m_icu(*this, "icu")
+ , m_scu(*this, "scu")
+{
+}
+
+v50_device::v50_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
+ : v5x_base_device(mconfig, V50, tag, owner, clock, address_map_constructor(FUNC(v50_device::internal_port_map), this))
+{
+}
+
+v53_device::v53_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock)
+ : v5x_base_device(mconfig, type, tag, owner, clock, address_map_constructor(FUNC(v53_device::internal_port_map), this))
+{
+}
+
+v53_device::v53_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
+ : v53_device(mconfig, V53, tag, owner, clock)
+{
+}
+
+v53a_device::v53a_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
+ : v53_device(mconfig, V53A, tag, owner, clock)
+{
+}
diff --git a/src/devices/cpu/nec/v5x.h b/src/devices/cpu/nec/v5x.h
new file mode 100644
index 00000000000..6cff7c3bd91
--- /dev/null
+++ b/src/devices/cpu/nec/v5x.h
@@ -0,0 +1,172 @@
+// license:BSD-3-Clause
+// copyright-holders:Patrick Mackinlay
+
+#ifndef MAME_CPU_NEC_V5X_H
+#define MAME_CPU_NEC_V5X_H
+
+#pragma once
+
+#include "nec.h"
+
+#include "machine/am9517a.h"
+#include "machine/i8251.h"
+#include "machine/pic8259.h"
+#include "machine/pit8253.h"
+
+class v5x_base_device : public v33_base_device
+{
+public:
+ // TCU
+ template <unsigned Timer> void set_clk(double clk) { subdevice<pit8253_device>("tcu")->set_clk<Timer>(clk); }
+ template <unsigned Timer> void set_clk(const XTAL &xtal) { subdevice<pit8253_device>("tcu")->set_clk<Timer>(xtal.dvalue()); }
+ template <unsigned Timer> auto out_handler() { return subdevice<pit8253_device>("tcu")->out_handler<Timer>(); }
+
+ // DMAU
+ auto out_hreq_cb() { return subdevice<v5x_dmau_device>("dmau")->out_hreq_callback(); }
+ auto out_eop_cb() { return subdevice<v5x_dmau_device>("dmau")->out_eop_callback(); }
+ auto in_memr_cb() { return subdevice<v5x_dmau_device>("dmau")->in_memr_callback(); }
+ auto in_mem16r_cb() { return subdevice<v5x_dmau_device>("dmau")->in_mem16r_callback(); }
+ auto out_memw_cb() { return subdevice<v5x_dmau_device>("dmau")->out_memw_callback(); }
+ auto out_mem16w_cb() { return subdevice<v5x_dmau_device>("dmau")->out_mem16w_callback(); }
+ template <unsigned Channel> auto in_ior_cb() { return subdevice<v5x_dmau_device>("dmau")->in_ior_callback<Channel>(); }
+ template <unsigned Channel> auto in_io16r_cb() { return subdevice<v5x_dmau_device>("dmau")->in_io16r_callback<Channel>(); }
+ template <unsigned Channel> auto out_iow_cb() { return subdevice<v5x_dmau_device>("dmau")->out_iow_callback<Channel>(); }
+ template <unsigned Channel> auto out_io16w_cb() { return subdevice<v5x_dmau_device>("dmau")->out_io16w_callback<Channel>(); }
+ template <unsigned Channel> auto out_dack_cb() { return subdevice<v5x_dmau_device>("dmau")->out_dack_callback<Channel>(); }
+
+ // SCU
+ auto txd_handler_cb() { return subdevice<v5x_scu_device>("scu")->txd_handler(); }
+ auto dtr_handler_cb() { return subdevice<v5x_scu_device>("scu")->dtr_handler(); }
+ auto rts_handler_cb() { return subdevice<v5x_scu_device>("scu")->rts_handler(); }
+ auto rxrdy_handler_cb() { return subdevice<v5x_scu_device>("scu")->rxrdy_handler(); }
+ auto txrdy_handler_cb() { return subdevice<v5x_scu_device>("scu")->txrdy_handler(); }
+ auto txempty_handler_cb() { return subdevice<v5x_scu_device>("scu")->txempty_handler(); }
+ auto syndet_handler_cb() { return subdevice<v5x_scu_device>("scu")->syndet_handler(); }
+
+protected:
+ v5x_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, address_map_constructor port_map);
+
+ // device_interface overrides
+ virtual void device_add_mconfig(machine_config &config) override;
+ virtual void device_start() override;
+ virtual void device_reset() override;
+ virtual void device_post_load() override;
+
+ // device_execute_interface overrides
+ virtual void execute_set_input(int inputnum, int state) override;
+
+ virtual void install_peripheral_io() = 0;
+
+ DECLARE_WRITE8_MEMBER(BSEL_w) {}
+ DECLARE_WRITE8_MEMBER(BADR_w) {}
+ DECLARE_WRITE8_MEMBER(BRC_w) {}
+ DECLARE_WRITE8_MEMBER(WMB0_w) {}
+ DECLARE_WRITE8_MEMBER(WCY1_w) {}
+ DECLARE_WRITE8_MEMBER(WCY0_w) {}
+ DECLARE_WRITE8_MEMBER(WAC_w) {}
+ DECLARE_WRITE8_MEMBER(TCKS_w) {}
+ DECLARE_WRITE8_MEMBER(SBCR_w) {}
+ DECLARE_WRITE8_MEMBER(RFC_w) {}
+ DECLARE_WRITE8_MEMBER(WMB1_w) {}
+ DECLARE_WRITE8_MEMBER(WCY2_w) {}
+ DECLARE_WRITE8_MEMBER(WCY3_w) {}
+ DECLARE_WRITE8_MEMBER(WCY4_w) {}
+ DECLARE_WRITE8_MEMBER(SULA_w);
+ DECLARE_WRITE8_MEMBER(TULA_w);
+ DECLARE_WRITE8_MEMBER(IULA_w);
+ DECLARE_WRITE8_MEMBER(DULA_w);
+ DECLARE_WRITE8_MEMBER(OPHA_w);
+ DECLARE_WRITE8_MEMBER(OPSEL_w);
+ DECLARE_READ8_MEMBER(get_pic_ack) { return 0; }
+ DECLARE_WRITE_LINE_MEMBER(internal_irq_w);
+
+ required_device<pit8253_device> m_tcu;
+ required_device<v5x_dmau_device> m_dmau;
+ required_device<v5x_icu_device> m_icu;
+ required_device<v5x_scu_device> m_scu;
+
+ enum opsel_mask
+ {
+ OPSEL_DS = 0x01, // dmau enabled
+ OPSEL_IS = 0x02, // icu enabled
+ OPSEL_TS = 0x04, // tcu enabled
+ OPSEL_SS = 0x08, // scu enabled
+ };
+ u8 m_OPSEL;
+
+ u8 m_SULA;
+ u8 m_TULA;
+ u8 m_IULA;
+ u8 m_DULA;
+ u8 m_OPHA;
+};
+
+class v50_device : public v5x_base_device
+{
+public:
+ v50_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
+
+ template <unsigned Channel> DECLARE_WRITE_LINE_MEMBER(dreq_w) { m_dmau->dreq_w<Channel>(state); }
+ DECLARE_WRITE_LINE_MEMBER(hack_w) { m_dmau->hack_w(state); }
+
+protected:
+ // device_interface overrides
+ virtual void device_add_mconfig(machine_config &config) override;
+ virtual void device_start() override;
+ virtual void device_reset() override;
+
+ void internal_port_map(address_map &map);
+ virtual void install_peripheral_io() override;
+
+ DECLARE_WRITE8_MEMBER(OPCN_w);
+
+private:
+ u8 m_OPCN;
+};
+
+class v53_device : public v5x_base_device
+{
+public:
+ v53_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
+
+ template <unsigned Channel> DECLARE_WRITE_LINE_MEMBER(dreq_w)
+ {
+ // dreq0 could be wrong / nonexistent
+ if (!(m_SCTL & 0x02))
+ {
+ m_dmau->dreq_w<Channel>(state);
+ }
+ else
+ {
+ logerror("dreq%d not in 71071mode\n", Channel);
+ }
+ }
+ DECLARE_WRITE_LINE_MEMBER(hack_w);
+
+protected:
+ v53_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock);
+
+ // device_interface overrides
+ virtual void device_start() override;
+ virtual void device_reset() override;
+
+ void internal_port_map(address_map &map);
+ virtual void install_peripheral_io() override;
+
+ DECLARE_WRITE8_MEMBER(SCTL_w);
+
+private:
+ u8 m_SCTL;
+};
+
+class v53a_device : public v53_device
+{
+public:
+ v53a_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
+};
+
+DECLARE_DEVICE_TYPE(V50, v50_device)
+DECLARE_DEVICE_TYPE(V53, v53_device)
+DECLARE_DEVICE_TYPE(V53A, v53a_device)
+
+#endif // MAME_CPU_NEC_V5X_H
diff --git a/src/devices/machine/aic6250.cpp b/src/devices/machine/aic6250.cpp
new file mode 100644
index 00000000000..f9ab06d71a5
--- /dev/null
+++ b/src/devices/machine/aic6250.cpp
@@ -0,0 +1,1038 @@
+// license:BSD-3-Clause
+// copyright-holders:Patrick Mackinlay
+
+/*
+ * An emulation of the Adaptec AIC-6250 SCSI Protocol Chip.
+ *
+ * Used in:
+ *
+ * MIPS Rx2030
+ * Data General AViiON (AV100, 200, 300, 400 and 4300)
+ * Microbotics HardFrame (SCSI controller for Amiga 2000)
+ * Radio Shack 250-4161 (16 bit ISA hard/floppy controller card)
+ * pc532
+ *
+ * Sources:
+ *
+ * http://bitsavers.org/pdf/adaptec/asic/AIC-6250_1988.pdf
+ *
+ * Status: very WIP, enough to load RISC/os on MIPS Rx2030 driver, but many
+ * unimplemented and incorrect behaviours.
+ *
+ * TODO
+ * - fix problems with ATN
+ * - 16 bit DMA including odd address start
+ * - disconnect/reselect
+ * - phase checks
+ */
+
+#include "emu.h"
+#include "aic6250.h"
+
+#define LOG_GENERAL (1U << 0)
+#define LOG_REG (1U << 1)
+#define LOG_STATE (1U << 2)
+#define LOG_CONFIG (1U << 3)
+#define LOG_INT (1U << 4)
+#define LOG_SCSI (1U << 5)
+#define LOG_DMA (1U << 6)
+
+//#define VERBOSE (LOG_GENERAL|LOG_REG|LOG_STATE|LOG_CONFIG|LOG_INT|LOG_SCSI|LOG_DMA)
+
+#include "logmacro.h"
+
+DEFINE_DEVICE_TYPE(AIC6250, aic6250_device, "aic6250", "Adaptec High-Performance SCSI Protocol Chip")
+
+static char const *const nscsi_phase[] = { "DATA OUT", "DATA IN", "COMMAND", "STATUS", "*", "*", "MESSAGE OUT", "MESSAGE IN" };
+static char const *const aic6250_phase[] = { "DATA OUT", "*", "DATA IN", "*", "COMMAND", "MESSAGE OUT", "STATUS", "MESSAGE IN" };
+
+aic6250_device::aic6250_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+ : nscsi_device(mconfig, AIC6250, tag, owner, clock)
+ , m_int_cb(*this)
+ , m_breq_cb(*this)
+ , m_port_a_r_cb(*this)
+ , m_port_a_w_cb(*this)
+ , m_port_b_r_cb(*this)
+ , m_port_b_w_cb(*this)
+{
+}
+
+void aic6250_device::map(address_map &map)
+{
+ map(0x0, 0x0).rw(FUNC(aic6250_device::dma_count_l_r), FUNC(aic6250_device::dma_count_l_w));
+ map(0x1, 0x1).rw(FUNC(aic6250_device::dma_count_m_r), FUNC(aic6250_device::dma_count_m_w));
+ map(0x2, 0x2).rw(FUNC(aic6250_device::dma_count_h_r), FUNC(aic6250_device::dma_count_h_w));
+ map(0x3, 0x3).w(FUNC(aic6250_device::int_msk_reg_0_w));
+ map(0x4, 0x4).w(FUNC(aic6250_device::offset_cntrl_w));
+ map(0x5, 0x5).rw(FUNC(aic6250_device::fifo_status_r), FUNC(aic6250_device::dma_cntrl_w));
+ map(0x6, 0x6).rw(FUNC(aic6250_device::rev_cntrl_r), FUNC(aic6250_device::int_msk_reg_1_w));
+ map(0x7, 0x7).rw(FUNC(aic6250_device::status_reg_0_r), FUNC(aic6250_device::control_reg_0_w));
+ map(0x8, 0x8).rw(FUNC(aic6250_device::status_reg_1_r), FUNC(aic6250_device::control_reg_1_w));
+ map(0x9, 0x9).rw(FUNC(aic6250_device::scsi_signal_reg_r), FUNC(aic6250_device::scsi_signal_reg_w));
+ map(0xa, 0xa).rw(FUNC(aic6250_device::scsi_id_data_r), FUNC(aic6250_device::scsi_id_data_w));
+ map(0xb, 0xb).r(FUNC(aic6250_device::source_dest_id_r));
+ map(0xc, 0xc).rw(FUNC(aic6250_device::memory_data_r), FUNC(aic6250_device::memory_data_w));
+ map(0xd, 0xd).rw(FUNC(aic6250_device::port_a_r), FUNC(aic6250_device::port_a_w));
+ map(0xe, 0xe).rw(FUNC(aic6250_device::port_b_r), FUNC(aic6250_device::port_b_w));
+ map(0xf, 0xf).rw(FUNC(aic6250_device::scsi_latch_data_r), FUNC(aic6250_device::scsi_bsy_rst_w));
+}
+
+READ8_MEMBER(aic6250_device::read)
+{
+ u8 data = space.unmap();
+
+ if (offset)
+ {
+ switch (m_address_reg)
+ {
+ case 0x0: data = dma_count_l_r(); m_address_reg++; break;
+ case 0x1: data = dma_count_m_r(); m_address_reg++; break;
+ case 0x2: data = dma_count_h_r(); m_address_reg++; break;
+ case 0x3: m_address_reg++; break;
+ case 0x4: m_address_reg++; break;
+ case 0x5: data = fifo_status_r(); m_address_reg++; break;
+ case 0x6: data = rev_cntrl_r(); m_address_reg++; break;
+ case 0x7: data = status_reg_0_r(); m_address_reg++; break;
+
+ case 0x8: data = status_reg_1_r(); break;
+ case 0x9: data = scsi_signal_reg_r(); break;
+ case 0xa: data = scsi_id_data_r(); break;
+ case 0xb: data = source_dest_id_r(); break;
+ case 0xc: data = memory_data_r(); break;
+ case 0xd: data = port_a_r(); break;
+ case 0xe: data = port_b_r(); break;
+ case 0xf: data = scsi_latch_data_r(); break;
+ }
+ }
+ else
+ // FIXME: not sure if possible to read address register
+ data = m_address_reg;
+
+ return data;
+}
+
+WRITE8_MEMBER(aic6250_device::write)
+{
+ if (offset)
+ {
+ switch (m_address_reg)
+ {
+ case 0x0: dma_count_l_w(data); m_address_reg++; break;
+ case 0x1: dma_count_m_w(data); m_address_reg++; break;
+ case 0x2: dma_count_h_w(data); m_address_reg++; break;
+ case 0x3: int_msk_reg_0_w(data); m_address_reg++; break;
+ case 0x4: offset_cntrl_w(data); m_address_reg++; break;
+ case 0x5: dma_cntrl_w(data); m_address_reg++; break;
+ case 0x6: int_msk_reg_1_w(data); m_address_reg++; break;
+ case 0x7: control_reg_0_w(data); m_address_reg++; break;
+
+ case 0x8: control_reg_1_w(data); break;
+ case 0x9: scsi_signal_reg_w(data); break;
+ case 0xa: scsi_id_data_w(data); break;
+ case 0xb: break;
+ case 0xc: memory_data_w(data); break;
+ case 0xd: port_a_w(data); break;
+ case 0xe: port_b_w(data); break;
+ case 0xf: scsi_bsy_rst_w(data); break;
+ }
+ }
+ else
+ m_address_reg = data & 0xf;
+}
+
+void aic6250_device::device_start()
+{
+ m_int_cb.resolve_safe();
+ m_breq_cb.resolve_safe();
+
+ m_port_a_r_cb.resolve_safe(0xff);
+ m_port_a_w_cb.resolve_safe();
+ m_port_b_r_cb.resolve_safe(0xff);
+ m_port_b_w_cb.resolve_safe();
+
+ save_item(NAME(m_dma_count));
+ save_item(NAME(m_int_msk_reg_0));
+ save_item(NAME(m_offset_cntrl));
+ save_item(NAME(m_dma_cntrl));
+ save_item(NAME(m_rev_cntrl));
+ save_item(NAME(m_int_msk_reg_1));
+ save_item(NAME(m_status_reg_0));
+ save_item(NAME(m_control_reg_0));
+ save_item(NAME(m_status_reg_1));
+ save_item(NAME(m_control_reg_1));
+ save_item(NAME(m_scsi_signal_reg));
+ save_item(NAME(m_scsi_id_data));
+ save_item(NAME(m_source_dest_id));
+ save_item(NAME(m_memory_data));
+ save_item(NAME(m_port_a_latch));
+ save_item(NAME(m_port_b_latch));
+ save_item(NAME(m_scsi_latch_data));
+
+ m_rev_cntrl = 0x02;
+
+ m_state_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(aic6250_device::state_loop), this));
+ m_state = IDLE;
+
+ m_int_asserted = false;
+
+ // FIXME: for now, let's just look at everything
+ scsi_bus->ctrl_wait(scsi_refid, S_ALL, S_ALL);
+}
+
+/*
+ * Register Conditions On Reset
+ *
+ * The AIC-6250 essentially has two modes of reset; i.e., the Power On Reset
+ * (/POR) and the SCSI Reset (SCSI /RST) which could be asserted through
+ * software on the SCSI bus. Registers 00, 01, 02, 09, 0a, 0b, 0c and 0f are
+ * not affected by any reset condition and their content is unknown on power
+ * up. At other times it would depend on the activity which preceded the reset
+ * action. Also, these registers are relevant only when some activity has been
+ * initiated.
+ *
+ * Registers 04, 06, 0d and 0e are reset (to inactive zeroes) by the /POR only.
+ *
+ * Registers 05 and 09 are reset (to inactive zeros) by both the /POR or SCSI
+ * /RST. On reset, the state of register 05(R) would be XX110000. The other
+ * registers have multiple conditions as outlined below.
+ *
+ * Register 03 is reset to zero by the /POR; however, bit 6 (ARB/SEL Start)
+ * would be reset by SCSI /RST also.
+ *
+ * Register 07(R) bits 0,1 are unaffected, while bits 2-7 are reset by /POR.
+ * Bits 2,3,5 are also reset and bit 7 is set to 1 by the SCSI /RST condition.
+ * Bit 4 will be set to 1 if EN BUS FREE DETECT INT (Reg 06, bit 2) is set to 1.
+ *
+ * Register 07(W), all bits except bit 6 are reset by /POR, while bits 3-5
+ * would also be reset by SCSI /RST.
+ *
+ * Register 08(R), bits 0-5 are reset by /POR while bits 0-2 are reset by SCSI
+ * /RST also. The state of bits 3-5 on reset will be 0. Bit 6 will be 1, bit 7
+ * will normally be 1 as determined by /BACK * /BREQ.
+ *
+ * Register 08(W) bit 5 is a don't care. Bits 1-7 are reset by /POR. Bit 0 is
+ * set to 1 while bit 7 is also reset by SCSI /RST.
+ */
+void aic6250_device::device_reset()
+{
+ // registers 04, 06, 0d, 0e
+ m_offset_cntrl = 0;
+ m_dma_cntrl = 0;
+ m_port_a_latch = 0;
+ m_port_a_latch = 0;
+
+ // registers 05, 09
+ m_offset_count_zero = true;
+ m_fifo.clear();
+ m_scsi_signal_reg = 0;
+
+ // register 03
+ m_int_msk_reg_0 = 0;
+
+ // registers 07(R) and 07(W)
+ m_status_reg_0 &= (R07R_SCSI_PHASE_CHG_ATN | R07R_DMA_BYTE_CNT_ZERO);
+ m_control_reg_0 &= R07W_P_MEM_RW;
+
+ // registers 08(R) and 08(W)
+ m_status_reg_1 = R08R_RESERVED;
+}
+
+void aic6250_device::scsi_reset()
+{
+ // registers 04, 06, 0d, 0e
+ m_offset_count_zero = true;
+ m_fifo.clear();
+ m_scsi_signal_reg = 0;
+
+ // register 03
+ m_int_msk_reg_0 &= ~R03W_ARB_SEL_START;
+
+ // register 07(R)
+ m_status_reg_0 &= ~(R07R_SCSI_REQ_ON | R07R_SCSI_PARITY_ERR | R07R_PHASE_MISMATCH_ERR);
+ m_status_reg_0 |= R07R_SCSI_RST_OCCURRED;
+ if (m_int_msk_reg_1 & R06W_EN_BUS_FREE_DETECT_INT)
+ m_status_reg_0 |= R07R_BUS_FREE_DETECT;
+
+ // register 07(W)
+ m_control_reg_0 &= ~(R07W_SCSI_INTERFACE_MODE | R07W_EN_PORT_A_INP_OR_OUT | R07W_TARGET_MODE);
+
+ // registers 08(R) and 08(W)
+ m_status_reg_1 &= ~(R08R_SELECTED | R08R_RESELECTED | R08R_SEL_OUT);
+ m_control_reg_1 &= ~R08W_AUTO_SCSI_PIO_REQ;
+}
+
+void aic6250_device::int_msk_reg_0_w(u8 data)
+{
+ LOGMASKED(LOG_REG, "int_msk_reg_0_w 0x%02x\n", data);
+
+ /*
+ * Writing a zero to Bits 0 and 1 of this register will reset the selected
+ * or reselected interrupt status in Status Register 1 (Register 08),
+ * causing the interrupt status to be lost.
+ */
+ if (!(data & R03W_EN_SELECT_INT))
+ m_status_reg_1 &= ~R08R_SELECTED;
+
+ if (!(data & R03W_EN_RESEL_INT))
+ m_status_reg_1 &= ~R08R_RESELECTED;
+
+ /*
+ * This bit will be reset to 0 when the Enable Command Done interrupt bit (Reg 03, Bit 3) is set to zero.
+ */
+ if (!(data & R03W_EN_CMD_DONE_INT))
+ m_status_reg_1 &= ~R08R_CMD_DONE;
+
+ if ((m_int_msk_reg_0 ^ data) & R03W_ARB_SEL_START)
+ {
+ if (data & R03W_ARB_SEL_START)
+ {
+ if (m_state != IDLE)
+ fatalerror("attempted to start selection while not idle\n");
+
+ m_state = ARB_BUS_FREE;
+ m_state_timer->adjust(attotime::zero);
+ }
+ else
+ {
+ if (m_state == IDLE)
+ fatalerror("attempted to abort selection while idle\n");
+
+ m_state = IDLE;
+ }
+ }
+
+ m_int_msk_reg_0 = data;
+}
+
+void aic6250_device::offset_cntrl_w(u8 data)
+{
+ LOGMASKED(LOG_REG, "offset_cntrl_w 0x%02x\n", data);
+
+ if (VERBOSE & LOG_CONFIG)
+ {
+ if (data & R04W_OFFSET)
+ {
+ double divisor = 4.0 + ((data & R04W_SYNC_XFER_RATE) >> 4);
+
+ LOGMASKED(LOG_CONFIG, "synchronous offset %d speed %.3f\n",
+ data & R04W_OFFSET, clock() / divisor);
+ }
+ else
+ LOGMASKED(LOG_CONFIG, "asynchronous transfer mode\n");
+ }
+
+ m_offset_cntrl = data;
+}
+
+u8 aic6250_device::fifo_status_r()
+{
+ u8 const data =
+ (m_offset_count_zero ? R05R_OFFSET_COUNT_ZERO : 0) |
+ (m_fifo.empty() ? R05R_FIFO_EMPTY : 0) |
+ (m_fifo.full() ? R05R_FIFO_FULL : 0) |
+ (m_fifo.queue_length() & R05R_FIFO_COUNTER);
+
+ LOGMASKED(LOG_REG, "fifo_status_r 0x%02x\n", data);
+
+ return data;
+}
+
+void aic6250_device::dma_cntrl_w(u8 data)
+{
+ LOGMASKED(LOG_REG, "dma_cntrl_w 0x%02x\n", data);
+
+ if (!(m_dma_cntrl & R05W_DMA_XFER_EN) && (data & R05W_DMA_XFER_EN))
+ {
+ LOGMASKED(LOG_DMA, "dma transfer %s memory, count %d\n",
+ data & R05W_TRANSFER_DIR ? "from" : "to", m_dma_count);
+
+ if (m_state != IDLE)
+ fatalerror("attempt to start dma while not idle\n");
+
+ // FIXME: should we trigger the state machine directly, or from the dma_w?
+ if (data & R05W_TRANSFER_DIR)
+ {
+ m_state = DMA_OUT;
+ m_breq_cb(1);
+ }
+ else
+ {
+ m_state = DMA_IN;
+ m_state_timer->adjust(attotime::zero);
+ }
+ }
+
+ m_dma_cntrl = data;
+}
+
+void aic6250_device::int_msk_reg_1_w(u8 data)
+{
+ LOGMASKED(LOG_REG, "int_msk_reg_1_w 0x%02x\n", data);
+
+ if (!(data & R06W_EN_BUS_FREE_DETECT_INT))
+ m_status_reg_0 &= ~R07R_BUS_FREE_DETECT;
+
+ m_int_msk_reg_1 = data;
+}
+
+u8 aic6250_device::status_reg_0_r()
+{
+ u8 const dma_count_zero = !m_dma_count ? R07R_DMA_BYTE_CNT_ZERO : 0;
+
+ return (m_status_reg_0 & ~R07R_DMA_BYTE_CNT_ZERO) | dma_count_zero;
+}
+
+void aic6250_device::control_reg_0_w(u8 data)
+{
+ LOGMASKED(LOG_REG, "control_reg_0_w 0x%02x\n", data);
+
+ LOGMASKED(LOG_CONFIG, "scsi id %d, %s, port A %d, %s\n",
+ data & R07W_SCSI_ID,
+ data & R07W_SCSI_INTERFACE_MODE ? "differential" : "single-ended",
+ data & R07W_EN_PORT_A_INP_OR_OUT ? "output" : "input",
+ data & R07W_TARGET_MODE ? "target" : "initiator");
+
+ if (data & R07W_P_MEM_CYCLE_REQ)
+ logerror("processor memory %s request not supported\n", data & R07W_P_MEM_RW ? "write" : "read");
+
+ m_control_reg_0 = data;
+}
+
+u8 aic6250_device::status_reg_1_r()
+{
+ if (m_status_reg_0 & R07R_ERROR_MASK)
+ return m_status_reg_1 | R08R_ERROR;
+ else
+ return m_status_reg_1;
+}
+
+void aic6250_device::control_reg_1_w(u8 data)
+{
+ LOGMASKED(LOG_REG, "control_reg_1_w 0x%02x\n", data);
+
+ if (data & R08W_CHIP_SW_RESET)
+ {
+ LOG("chip software reset\n");
+
+ m_state = IDLE;
+
+ scsi_reset();
+ device_reset();
+
+ m_control_reg_1 = R08W_CHIP_SW_RESET;
+
+ set_int_state(false);
+ }
+ else
+ {
+ LOGMASKED(LOG_CONFIG, "%s frequency, port B input/output %s, %d-bit memory bus%s\n",
+ data & R08W_CLK_FREQ_MODE ? "high" : "low",
+ data & R08W_EN_PORT_B_INP_OR_OUT ? "enabled" : "disabled",
+ data & R08W_EN_16_BIT_MEM_BUS ? 16 : 8,
+ data & R08W_AUTO_SCSI_PIO_REQ ? ", automatic PIO" : "");
+
+ if (!(m_control_reg_1 & R08W_AUTO_SCSI_PIO_REQ) && (data & R08W_AUTO_SCSI_PIO_REQ))
+ {
+ if (m_state != IDLE)
+ fatalerror("attempted to start auto pio while not idle\n");
+
+ m_state = AUTO_PIO;
+ m_state_timer->adjust(attotime::zero);
+ }
+
+ m_control_reg_1 = data;
+ }
+}
+
+u8 aic6250_device::scsi_signal_reg_r()
+{
+ u32 const ctrl = scsi_bus->ctrl_r();
+
+ u8 const data =
+ ((ctrl & S_ACK) ? R09R_SCSI_ACK_IN : 0) |
+ ((ctrl & S_REQ) ? R09R_SCSI_REQ_IN : 0) |
+ ((ctrl & S_BSY) ? R09R_SCSI_BSY_IN : 0) |
+ ((ctrl & S_SEL) ? R09R_SCSI_SEL_IN : 0) |
+ ((ctrl & S_ATN) ? R09R_SCSI_ATN_IN : 0) |
+ ((ctrl & S_MSG) ? R09R_SCSI_MSG_IN : 0) |
+ ((ctrl & S_INP) ? R09R_SCSI_IO_IN : 0) |
+ ((ctrl & S_CTL) ? R09R_SCSI_CD_IN : 0);
+
+ LOGMASKED(LOG_REG, "scsi_signal_reg_r 0x%02x\n", data);
+
+ return data;
+}
+
+void aic6250_device::scsi_signal_reg_w(u8 data)
+{
+ LOGMASKED(LOG_REG, "scsi_signal_reg_w 0x%02x\n", data);
+
+ if (m_control_reg_0 & R07W_TARGET_MODE)
+ scsi_bus->ctrl_w(scsi_refid,
+ ((data & R09W_SCSI_REQ_OUT) ? S_REQ : 0) |
+ ((data & R09W_SCSI_BSY_OUT) ? S_BSY : 0) |
+ ((data & R09W_SCSI_SEL_OUT) ? S_SEL : 0) |
+ ((data & R09W_SCSI_MSG_OUT) ? S_MSG : 0) |
+ ((data & R09W_SCSI_IO_OUT) ? S_INP : 0) |
+ ((data & R09W_SCSI_CD_OUT) ? S_CTL : 0), S_REQ | S_BSY | S_SEL | S_MSG | S_INP | S_CTL);
+ else
+ scsi_bus->ctrl_w(scsi_refid,
+ ((data & R09W_SCSI_ACK_OUT) ? S_ACK : 0) |
+ ((data & R09W_SCSI_BSY_OUT) ? S_BSY : 0) |
+ ((data & R09W_SCSI_SEL_OUT) ? S_SEL : 0) |
+ ((data & R09W_SCSI_ATN_OUT) ? S_ATN : 0), S_ACK | S_BSY | S_SEL | S_ATN);
+
+ if ((data ^ m_scsi_signal_reg) & R09R_PHASE_MASK)
+ LOGMASKED(LOG_SCSI, "expecting phase %s\n", aic6250_phase[data >> 5]);
+
+ if (!(m_control_reg_0 & R07W_TARGET_MODE) && phase_match(data, scsi_bus->ctrl_r()))
+ m_status_reg_0 &= ~R07R_PHASE_MISMATCH_ERR;
+
+ m_scsi_signal_reg = data;
+
+ // HACK: trigger check for phase match
+ scsi_ctrl_changed();
+}
+
+u8 aic6250_device::scsi_id_data_r()
+{
+ // TODO: selection/reselection phase
+ u8 const data = scsi_bus->data_r();
+
+ LOGMASKED(LOG_REG, "scsi_id_data_r 0x%02x\n", data);
+
+ return data;
+}
+
+void aic6250_device::scsi_id_data_w(u8 data)
+{
+ LOGMASKED(LOG_REG, "scsi_id_data_w 0x%02x\n", data);
+
+ scsi_bus->data_w(scsi_refid, data);
+
+ m_scsi_id_data = data;
+}
+
+u8 aic6250_device::memory_data_r()
+{
+ LOGMASKED(LOG_REG, "memory_data_r 0x%02x\n", m_memory_data);
+
+ return m_memory_data;
+}
+
+void aic6250_device::memory_data_w(u8 data)
+{
+ LOGMASKED(LOG_REG, "memory_data_w 0x%02x\n", data);
+
+ m_memory_data = data;
+}
+
+u8 aic6250_device::port_a_r()
+{
+ // FIXME: not sure if port A can be read in differential mode
+ u8 const data = (m_control_reg_0 & R07W_SCSI_INTERFACE_MODE)
+ || (m_control_reg_0 & R07W_EN_PORT_A_INP_OR_OUT) ? m_port_a_latch : m_port_a_r_cb();
+
+ LOGMASKED(LOG_REG, "port_a_r 0x%02x\n", data);
+
+ return data;
+}
+
+void aic6250_device::port_a_w(u8 data)
+{
+ LOGMASKED(LOG_REG, "port_a_w 0x%02x\n", data);
+
+ if (!(m_control_reg_0 & R07W_SCSI_INTERFACE_MODE) && (m_control_reg_0 & R07W_EN_PORT_A_INP_OR_OUT))
+ m_port_a_w_cb(data);
+
+ m_port_a_latch = data;
+}
+
+u8 aic6250_device::port_b_r()
+{
+ u8 const data = ((m_control_reg_1 & R08W_EN_16_BIT_MEM_BUS)
+ || (m_control_reg_1 & R08W_EN_PORT_B_INP_OR_OUT)) ? m_port_b_latch : m_port_b_r_cb();
+
+ LOGMASKED(LOG_REG, "port_b_r 0x%02x\n", data);
+
+ return data;
+}
+
+void aic6250_device::port_b_w(u8 data)
+{
+ LOGMASKED(LOG_REG, "port_b_w 0x%02x\n", data);
+
+ if (!(m_control_reg_1 & R08W_EN_16_BIT_MEM_BUS) && (m_control_reg_1 & R08W_EN_PORT_B_INP_OR_OUT))
+ m_port_b_w_cb(data);
+
+ m_port_b_latch = data;
+}
+
+void aic6250_device::scsi_ctrl_changed()
+{
+ u32 const control = scsi_bus->ctrl_r();
+
+ if ((control & S_BSY) && !(control & S_SEL))
+ LOGMASKED(LOG_SCSI, "scsi_ctrl_changed 0x%08x phase %s%s%s\n", control, nscsi_phase[control & S_PHASE_MASK],
+ control & S_REQ ? " REQ" : "", control & S_ACK ? " ACK" : "");
+ else if (control & S_BSY)
+ LOGMASKED(LOG_SCSI, "scsi_ctrl_changed 0x%08x arbitration/selection\n", control);
+ else
+ LOGMASKED(LOG_SCSI, "scsi_ctrl_changed 0x%08x BUS FREE\n", control);
+
+ // phase change/atn
+ if (!(m_control_reg_0 & R07W_TARGET_MODE))
+ {
+ if ((control ^ m_scsi_ctrl_state) & S_PHASE_MASK)
+ {
+ if ((m_control_reg_1 & R08W_PHASE_CHANGE_MODE) || (control & S_REQ))
+ {
+ LOGMASKED(LOG_SCSI, "bus phase change\n");
+
+ m_status_reg_0 |= R07R_SCSI_PHASE_CHG_ATN;
+ }
+
+ if ((control & S_REQ) && !phase_match(m_scsi_signal_reg, control))
+ {
+ LOGMASKED(LOG_SCSI, "bus phase mismatch expect %s found %s\n", aic6250_phase[m_scsi_signal_reg >> 5], nscsi_phase[control & S_PHASE_MASK]);
+
+ m_status_reg_0 |= R07R_PHASE_MISMATCH_ERR;
+ }
+ }
+ }
+ else
+ if (!(m_scsi_ctrl_state & S_ATN) && (control & S_ATN))
+ {
+ LOGMASKED(LOG_SCSI, "bus atn asserted\n");
+
+ m_status_reg_0 |= R07R_SCSI_PHASE_CHG_ATN;
+ }
+
+ // scsi req on
+ if (!(m_control_reg_0 & R07W_TARGET_MODE) && !(m_scsi_ctrl_state & S_REQ) && (control & S_REQ))
+ {
+ LOGMASKED(LOG_SCSI, "bus req asserted\n");
+
+ m_status_reg_0 |= R07R_SCSI_REQ_ON;
+ }
+
+ // bus free
+ if ((m_scsi_ctrl_state & (S_SEL | S_BSY | S_RST)) && !(control & (S_SEL | S_BSY | S_RST)))
+ {
+ LOGMASKED(LOG_SCSI, "bus free\n");
+
+ m_status_reg_0 |= R07R_BUS_FREE_DETECT;
+ }
+
+ if (!(m_scsi_ctrl_state & S_RST) && (control & S_RST))
+ {
+ LOGMASKED(LOG_SCSI, "bus reset asserted\n");
+
+ m_status_reg_0 |= R07R_SCSI_RST_OCCURRED;
+
+ scsi_bus->data_w(scsi_refid, 0);
+ scsi_bus->ctrl_w(scsi_refid, 0, S_ALL);
+ }
+
+ // record new state
+ m_scsi_ctrl_state = control;
+
+ int_check();
+
+ // TODO: in future, probably schedule scsi engine, not just interrupt checks
+ //m_state_timer->adjust(attotime::zero);
+}
+
+
+TIMER_CALLBACK_MEMBER(aic6250_device::state_loop)
+{
+ // step state machine until delay, idle state or interrupt
+ int delay = state_step();
+
+ // check for interrupts
+ bool const interrupt = int_check();
+
+ if (delay < 0)
+ return;
+
+ /*
+ * All clock cycles are referred to assuming the high-frequency mode, set
+ * by the Clock Frequency mode bit in Control Register 1 (Bit 2, Register
+ * 08). If the low-frequency mode is being used, the number of clock cycles
+ * must be divided by two.
+ */
+ if (!(m_control_reg_1 & R08W_CLK_FREQ_MODE))
+ delay >>= 1;
+
+ if (m_state != IDLE && !interrupt)
+ m_state_timer->adjust(attotime::from_ticks(delay, clock()));
+}
+
+int aic6250_device::state_step()
+{
+ u8 const scsi_id = 1 << (m_control_reg_0 & R07W_SCSI_ID);
+ int delay = 0;
+
+ switch (m_state)
+ {
+ case IDLE:
+ break;
+
+ case ARB_BUS_FREE:
+ LOGMASKED(LOG_STATE, "arbitration: waiting for bus free\n");
+ if (!(scsi_bus->ctrl_r() & (S_SEL | S_BSY | S_RST)))
+ {
+ m_state = ARB_START;
+ delay = 16; // 800ns
+ }
+ break;
+
+ case ARB_START:
+ LOGMASKED(LOG_STATE, "arbitration: started\n");
+ m_state = ARB_EVALUATE;
+
+ // drive our SCSI ID and assert BSY
+ scsi_bus->data_w(scsi_refid, scsi_id);
+ scsi_bus->ctrl_w(scsi_refid, S_BSY, S_BSY);
+
+ delay = 56; // 2800ns
+ break;
+
+ case ARB_EVALUATE:
+ // check if SEL asserted, or if there's a higher ID on the bus
+ if ((scsi_bus->ctrl_r() & S_SEL) || (scsi_bus->data_r() & ~((scsi_id - 1) | scsi_id)))
+ {
+ LOGMASKED(LOG_STATE, "arbitration: lost\n");
+ m_state = ARB_BUS_FREE;
+ scsi_bus->ctrl_w(scsi_refid, 0, S_BSY);
+ break;
+ }
+
+ LOGMASKED(LOG_STATE, "arbitration: won\n");
+ m_state = SEL_START;
+ delay = 24; // 1200ns
+ break;
+
+ case SEL_START:
+ LOGMASKED(LOG_STATE, "selection: SEL asserted\n");
+
+ m_status_reg_1 |= R08R_SEL_OUT;
+
+ m_state = SEL_DELAY;
+ delay = 2; // 100ns
+
+ // drive both SCSI IDs and assert SEL
+ scsi_bus->data_w(scsi_refid, m_scsi_id_data);
+ scsi_bus->ctrl_w(scsi_refid, S_SEL, S_SEL);
+ break;
+
+ case SEL_DELAY:
+ LOGMASKED(LOG_STATE, "selection: BSY cleared\n");
+
+ m_state = SEL_WAIT_BSY;
+ delay = 12; // 600ns
+
+ // clear BSY, optionally assert ATN
+ if (m_int_msk_reg_0 & R03W_EN_AUTO_ATN)
+ scsi_bus->ctrl_w(scsi_refid, S_ATN, S_BSY | S_ATN);
+ else
+ scsi_bus->ctrl_w(scsi_refid, 0, S_BSY);
+ break;
+
+ case SEL_WAIT_BSY:
+ if (scsi_bus->ctrl_r() & S_BSY)
+ {
+ LOGMASKED(LOG_STATE, "selection: BSY asserted by target\n");
+
+ m_state = SEL_COMPLETE;
+ delay = 1; // 50ns
+ }
+ else
+ delay = -1;
+ break;
+
+ case SEL_COMPLETE:
+ LOGMASKED(LOG_STATE, "selection: complete\n");
+
+ m_int_msk_reg_0 &= ~R03W_ARB_SEL_START;
+ m_status_reg_1 &= ~R08R_SEL_OUT;
+ m_status_reg_1 |= R08R_CMD_DONE;
+ m_source_dest_id = m_scsi_id_data;
+
+ m_state = IDLE;
+
+ // clear data and SEL
+ // FIXME: should not clear ATN
+ scsi_bus->data_w(scsi_refid, 0);
+ scsi_bus->ctrl_w(scsi_refid, 0, S_SEL | S_ATN);
+ break;
+
+ case DMA_IN:
+ // FIXME: assert ack when: req asserted && phase match && count not zero && fifo not full
+ if (!m_fifo.full())
+ {
+ u8 const data = scsi_bus->data_r();
+ LOGMASKED(LOG_STATE, "dma in 0x%02x\n", data);
+
+ m_dma_count--;
+ m_fifo.enqueue(data);
+
+ m_state = DMA_IN_NEXT;
+
+ scsi_bus->ctrl_w(scsi_refid, S_ACK, S_ACK);
+ }
+ else
+ {
+ delay = -1;
+ m_breq_cb(1);
+ }
+ break;
+
+ case DMA_IN_NEXT:
+ if (!(scsi_bus->ctrl_r() & S_REQ))
+ {
+ LOGMASKED(LOG_STATE, "dma in next count %d\n", m_dma_count);
+ m_state = m_dma_count ? DMA_IN_REQ : DMA_IN_DRAIN;
+
+ scsi_bus->ctrl_w(scsi_refid, 0, S_ACK);
+ }
+ break;
+
+ case DMA_IN_REQ:
+ if (scsi_bus->ctrl_r() & S_REQ)
+ m_state = DMA_IN;
+ break;
+
+ case DMA_IN_DRAIN:
+ if (!m_fifo.empty())
+ {
+ m_breq_cb(1);
+ delay = -1;
+ }
+ else
+ m_state = DMA_IN_DONE;
+ break;
+
+ case DMA_IN_DONE:
+ LOGMASKED(LOG_STATE, "dma in done\n");
+ m_status_reg_1 |= R08R_CMD_DONE;
+ m_dma_cntrl &= ~R05W_DMA_XFER_EN;
+ m_state = IDLE;
+ break;
+
+ case DMA_OUT:
+ // FIXME: assert ack when: req asserted && phase match && count not zero && fifo not empty
+ if (!m_fifo.empty())
+ {
+ u8 const data = m_fifo.dequeue();
+ LOGMASKED(LOG_STATE, "dma out 0x%02x\n", data);
+
+ m_dma_count--;
+
+ m_state = DMA_OUT_NEXT;
+
+ // drive data, assert ACK
+ scsi_bus->data_w(scsi_refid, data);
+ scsi_bus->ctrl_w(scsi_refid, S_ACK, S_ACK);
+ }
+ else
+ {
+ delay = -1;
+ m_breq_cb(1);
+ }
+ break;
+
+ case DMA_OUT_NEXT:
+ if (!(scsi_bus->ctrl_r() & S_REQ))
+ {
+ LOGMASKED(LOG_STATE, "dma out next count %d\n", m_dma_count);
+ m_state = m_dma_count ? DMA_OUT_REQ : DMA_OUT_DONE;
+
+ scsi_bus->data_w(scsi_refid, 0);
+ scsi_bus->ctrl_w(scsi_refid, 0, S_ACK);
+ }
+ break;
+
+ case DMA_OUT_REQ:
+ if (scsi_bus->ctrl_r() & S_REQ)
+ m_state = DMA_OUT;
+ break;
+
+ case DMA_OUT_DONE:
+ LOGMASKED(LOG_STATE, "dma out done\n");
+ m_status_reg_1 |= R08R_CMD_DONE;
+ m_dma_cntrl &= ~R05W_DMA_XFER_EN;
+
+ m_state = IDLE;
+ break;
+
+ case AUTO_PIO:
+ // TODO: test expected phase
+ // out: wait for req, check phase match, ack
+ if (scsi_bus->ctrl_r() & S_REQ)
+ {
+ LOGMASKED(LOG_STATE, "auto pio\n");
+
+ m_state = (m_dma_cntrl & R05W_TRANSFER_DIR) ? AUTO_PIO_OUT : AUTO_PIO_IN;
+ }
+ break;
+
+ case AUTO_PIO_IN:
+ m_state = AUTO_PIO_DONE;
+ m_scsi_latch_data = scsi_bus->data_r();
+ LOGMASKED(LOG_STATE, "auto pio in 0x%02x\n", m_scsi_latch_data);
+ scsi_bus->ctrl_w(scsi_refid, S_ACK, S_ACK);
+ break;
+
+ case AUTO_PIO_OUT:
+ LOGMASKED(LOG_STATE, "auto pio out 0x%02x\n", m_scsi_id_data);
+ m_state = AUTO_PIO_DONE;
+
+ scsi_bus->data_w(scsi_refid, m_scsi_id_data);
+ scsi_bus->ctrl_w(scsi_refid, S_ACK, S_ACK);
+ break;
+
+ case AUTO_PIO_DONE:
+ if (!(scsi_bus->ctrl_r() & S_REQ))
+ {
+ LOGMASKED(LOG_STATE, "auto pio done\n");
+
+ m_status_reg_1 |= R08R_CMD_DONE;
+ m_control_reg_1 &= ~R08W_AUTO_SCSI_PIO_REQ;
+ m_state = IDLE;
+
+ scsi_bus->data_w(scsi_refid, 0);
+ scsi_bus->ctrl_w(scsi_refid, 0, S_ACK);
+ }
+ break;
+ }
+
+ return delay;
+}
+
+bool aic6250_device::int_check()
+{
+ bool int_asserted = false;
+
+ // status interrupts
+ if (m_int_msk_reg_0 & m_status_reg_1 & R03W_INT_MASK)
+ int_asserted = true;
+
+ // error interrupts
+ if ((m_int_msk_reg_0 & R03W_EN_ERROR_INT) && (m_int_msk_reg_1 & R06W_ERROR_INT_MASK))
+ {
+ // phase change/atn
+ if ((m_int_msk_reg_1 & R06W_EN_PHASE_CHANGE_INT_INIT) && (m_status_reg_0 & R07R_SCSI_PHASE_CHG_ATN))
+ int_asserted = true;
+
+ // scsi parity
+ if ((m_int_msk_reg_1 & R06W_EN_SCSI_PARITY_ERR_INT) && (m_status_reg_0 & R07R_SCSI_PARITY_ERR))
+ int_asserted = true;
+
+ // bus free
+ if ((m_int_msk_reg_1 & R06W_EN_BUS_FREE_DETECT_INT) && (m_status_reg_0 & R07R_BUS_FREE_DETECT))
+ int_asserted = true;
+
+ // phase mismatch (initiator only)
+ if ((m_int_msk_reg_1 & R06W_EN_PHASE_MISMATCH_INT) && (m_status_reg_0 & R07R_PHASE_MISMATCH_ERR))
+ int_asserted = true;
+
+ // memory parity
+ if ((m_int_msk_reg_1 & R06W_EN_MEM_PARITY_ERROR_INT) && (m_status_reg_0 & R07R_MEMORY_PARITY_ERR))
+ int_asserted = true;
+
+ // scsi reset
+ if ((m_int_msk_reg_1 & R06W_EN_SCSI_RST_INT) && (m_status_reg_0 & R07R_SCSI_RST_OCCURRED))
+ int_asserted = true;
+
+ // scsi req on (initiator only)
+ if ((m_int_msk_reg_1 & R06W_EN_SCSI_REQ_ON_INT) && (m_status_reg_0 & R07R_SCSI_REQ_ON))
+ int_asserted = true;
+ }
+
+ if (int_asserted)
+ LOGMASKED(LOG_INT, "sr0 0x%02x sr1 0x%02x\n", m_status_reg_0, m_status_reg_1);
+
+ // update int line state
+ set_int_state(int_asserted);
+
+ return int_asserted;
+}
+
+void aic6250_device::set_int_state(bool asserted)
+{
+ if (m_int_asserted != asserted)
+ {
+ LOGMASKED(LOG_INT, "set_int_state interrupt %s\n", asserted ? "asserted" : "cleared");
+
+ m_int_asserted = asserted;
+
+ // line is active low
+ m_int_cb(asserted ? 0 : 1);
+ }
+}
+
+/*
+ * This implementation has a simplistic DMA approach. DMA transfers to memory
+ * start with the SCSI interface filling up the FIFO. When it's full (or the
+ * count exhausted), BÌ…RÌ…EÌ…QÌ… is asserted and cleared in a loop until the FIFO is
+ * empty, after which the SCSI interface is scheduled again.
+ *
+ * Transfers from memory start with BÌ…RÌ…EÌ…QÌ… being asserted and cleared until the
+ * FIFO is full, after which the SCSI interface is scheduled. If the SCSI
+ * interface requires more data, BÌ…RÌ…EÌ…QÌ… is asserted and the cycle repeats. When
+ * the DMA transfer count falls below 8, data is transferred via individual
+ * cycles on demand rather than prefetched.
+ */
+WRITE_LINE_MEMBER(aic6250_device::back_w)
+{
+ LOGMASKED(LOG_DMA, "back_w %d\n", state);
+
+ m_breq_cb(0);
+
+ if (m_dma_cntrl & R05W_TRANSFER_DIR)
+ if (m_fifo.full() || m_dma_count < 8)
+ m_state_timer->adjust(attotime::zero);
+ else
+ m_breq_cb(1);
+ else
+ if (m_fifo.empty())
+ m_state_timer->adjust(attotime::zero);
+ else
+ m_breq_cb(1);
+}
+
+u8 aic6250_device::dma_r()
+{
+ u8 const data = m_fifo.dequeue();
+
+ LOGMASKED(LOG_DMA, "dma_r 0x%02x\n", data);
+
+ return data;
+}
+
+u16 aic6250_device::dma16_r()
+{
+ u16 data = m_fifo.dequeue();
+
+ data |= u16(m_fifo.dequeue()) << 8;
+
+ LOGMASKED(LOG_DMA, "dma16_r 0x%04x\n", data);
+
+ return data;
+}
+
+void aic6250_device::dma_w(u8 data)
+{
+ LOGMASKED(LOG_DMA, "dma_w 0x%02x\n", data);
+
+ m_fifo.enqueue(data);
+}
+
+void aic6250_device::dma16_w(u16 data)
+{
+ LOGMASKED(LOG_DMA, "dma16_w 0x%04x\n", data);
+
+ m_fifo.enqueue(data);
+ m_fifo.enqueue(data >> 8);
+}
diff --git a/src/devices/machine/aic6250.h b/src/devices/machine/aic6250.h
new file mode 100644
index 00000000000..029c7f72dca
--- /dev/null
+++ b/src/devices/machine/aic6250.h
@@ -0,0 +1,282 @@
+// license:BSD-3-Clause
+// copyright-holders:Patrick Mackinlay
+
+#ifndef MAME_MACHINE_AIC6250_H
+#define MAME_MACHINE_AIC6250_H
+
+#pragma once
+
+#include "machine/nscsi_bus.h"
+
+class aic6250_device : public nscsi_device
+{
+public:
+ aic6250_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+ void map(address_map &map);
+
+ auto int_cb() { return m_int_cb.bind(); }
+ auto breq_cb() { return m_breq_cb.bind(); }
+
+ auto port_a_r_cb() { return m_port_a_r_cb.bind(); }
+ auto port_a_w_cb() { return m_port_a_w_cb.bind(); }
+ auto port_b_r_cb() { return m_port_b_r_cb.bind(); }
+ auto port_b_w_cb() { return m_port_b_w_cb.bind(); }
+
+ DECLARE_WRITE_LINE_MEMBER(back_w);
+
+ DECLARE_READ8_MEMBER(read);
+ DECLARE_WRITE8_MEMBER(write);
+
+ u8 dma_r();
+ u16 dma16_r();
+ void dma_w(u8 data);
+ void dma16_w(u16 data);
+
+protected:
+ // standard device_interface overrides
+ virtual void device_start() override;
+ virtual void device_reset() override;
+
+ // ncsci_device overrides
+ virtual void scsi_ctrl_changed() override;
+
+ void scsi_reset();
+
+ u8 dma_count_l_r() { return m_dma_count >> 0; }
+ u8 dma_count_m_r() { return m_dma_count >> 8; }
+ u8 dma_count_h_r() { return m_dma_count >> 16; }
+ u8 fifo_status_r();
+ u8 rev_cntrl_r() { return m_rev_cntrl; }
+ u8 status_reg_0_r();
+ u8 status_reg_1_r();
+ u8 scsi_signal_reg_r();
+ u8 scsi_id_data_r();
+ u8 source_dest_id_r() { logerror("source_dest_id_r\n"); return m_source_dest_id; }
+ u8 memory_data_r();
+ u8 port_a_r();
+ u8 port_b_r();
+ u8 scsi_latch_data_r() { logerror("scsi_latch_data_r 0x%02x\n", m_scsi_latch_data); return m_scsi_latch_data; }
+
+ void dma_count_l_w(u8 data) { m_dma_count &= ~0x0000ff; m_dma_count |= (data << 0); }
+ void dma_count_m_w(u8 data) { m_dma_count &= ~0x00ff00; m_dma_count |= (data << 8); }
+ void dma_count_h_w(u8 data) { m_dma_count &= ~0xff0000; m_dma_count |= (data << 16); }
+ void int_msk_reg_0_w(u8 data);
+ void offset_cntrl_w(u8 data);
+ void dma_cntrl_w(u8 data);
+ void int_msk_reg_1_w(u8 data);
+ void control_reg_0_w(u8 data);
+ void control_reg_1_w(u8 data);
+ void scsi_signal_reg_w(u8 data);
+ void scsi_id_data_w(u8 data);
+ void memory_data_w(u8 data);
+ void port_a_w(u8 data);
+ void port_b_w(u8 data);
+ void scsi_bsy_rst_w(u8 data) { /* TODO: target mode, reset /BSY out and enter bus free */ }
+
+private:
+ TIMER_CALLBACK_MEMBER(state_loop);
+ int state_step();
+
+ bool int_check();
+ void set_int_state(bool asserted);
+
+ bool phase_match(u8 aic6250_phase, u32 nscsi_phase)
+ {
+ return (bool(aic6250_phase & R09W_SCSI_CD_OUT) == bool(nscsi_phase & S_CTL))
+ && (bool(aic6250_phase & R09W_SCSI_IO_OUT) == bool(nscsi_phase & S_INP))
+ && (bool(aic6250_phase & R09W_SCSI_MSG_OUT) == bool(nscsi_phase & S_MSG));
+ }
+
+ enum int_msk_reg_0_mask : u8
+ {
+ R03W_EN_SELECT_INT = 0x01,
+ R03W_EN_RESEL_INT = 0x02,
+ R03W_EN_SEL_OUT_INT = 0x04,
+ R03W_EN_CMD_DONE_INT = 0x08,
+ R03W_EN_ERROR_INT = 0x10,
+ R03W_EN_AUTO_ATN = 0x20,
+ R03W_ARB_SEL_START = 0x40,
+ R03W_RESERVED = 0x80,
+
+ R03W_INT_MASK = 0x0f
+ };
+ enum offset_cntrl_mask : u8
+ {
+ R04W_OFFSET = 0x0f,
+ R04W_SYNC_XFER_RATE = 0x70,
+ R04W_RESERVED = 0x80
+ };
+ enum fifo_status_mask : u8
+ {
+ R05R_FIFO_COUNTER = 0x07,
+ R05R_FIFO_FULL = 0x08,
+ R05R_FIFO_EMPTY = 0x10,
+ R05R_OFFSET_COUNT_ZERO = 0x20,
+ R05R_TEST_SIGNAL = 0xc0
+ };
+ enum dma_cntrl_mask : u8
+ {
+ R05W_DMA_XFER_EN = 0x01,
+ R05W_TRANSFER_DIR = 0x02,
+ R05W_ODD_XFER_START = 0x04,
+ R05W_RESERVED = 0xf8
+ };
+ enum rev_cntrl_mask : u8
+ {
+ R06R_REVISION = 0x03,
+ R06R_RESERVED = 0xfc
+ };
+ enum int_msk_reg_1_mask : u8
+ {
+ R06W_EN_ATN_ON_INT_TGT = 0x01,
+ R06W_EN_PHASE_CHANGE_INT_INIT = 0x01,
+ R06W_EN_SCSI_PARITY_ERR_INT = 0x02,
+ R06W_EN_BUS_FREE_DETECT_INT = 0x04,
+ R06W_EN_PHASE_MISMATCH_INT = 0x08,
+ R06W_EN_MEM_PARITY_ERROR_INT = 0x10,
+ R06W_EN_SCSI_RST_INT = 0x20,
+ R06W_EN_SCSI_REQ_ON_INT = 0x40,
+ R06W_RESERVED = 0x80,
+
+ R06W_ERROR_INT_MASK = 0x3f
+ };
+ enum status_reg_0_mask : u8
+ {
+ R07R_DMA_BYTE_CNT_ZERO = 0x01,
+ R07R_SCSI_PHASE_CHG_ATN = 0x02,
+ R07R_SCSI_REQ_ON = 0x04,
+ R07R_SCSI_PARITY_ERR = 0x08,
+ R07R_BUS_FREE_DETECT = 0x10,
+ R07R_PHASE_MISMATCH_ERR = 0x20,
+ R07R_MEMORY_PARITY_ERR = 0x40,
+ R07R_SCSI_RST_OCCURRED = 0x80,
+
+ R07R_ERROR_MASK = 0xfa
+ };
+ enum control_reg_0_mask : u8
+ {
+ R07W_SCSI_ID = 0x07,
+ R07W_SCSI_INTERFACE_MODE = 0x08,
+ R07W_EN_PORT_A_INP_OR_OUT = 0x10,
+ R07W_TARGET_MODE = 0x20,
+ R07W_P_MEM_RW = 0x40,
+ R07W_P_MEM_CYCLE_REQ = 0x80
+ };
+ enum status_reg_1_mask : u8
+ {
+ R08R_SELECTED = 0x01,
+ R08R_RESELECTED = 0x02,
+ R08R_SEL_OUT = 0x04,
+ R08R_CMD_DONE = 0x08,
+ R08R_ERROR = 0x10,
+ R08R_SCSI_RST_IN = 0x20,
+ R08R_RESERVED = 0x40,
+ R08R_MEM_CYCLE_CMPL = 0x80
+ };
+ enum control_reg_1_mask : u8
+ {
+ R08W_CHIP_SW_RESET = 0x01,
+ R08W_SCSI_RST_OUT = 0x02,
+ R08W_CLK_FREQ_MODE = 0x04,
+ R08W_PHASE_CHANGE_MODE = 0x08,
+ R08W_EN_PORT_B_INP_OR_OUT = 0x10,
+ R08W_RESERVED = 0x20,
+ R08W_EN_16_BIT_MEM_BUS = 0x40,
+ R08W_AUTO_SCSI_PIO_REQ = 0x80
+ };
+ enum scsi_signal_reg_mask : u8
+ {
+ R09R_SCSI_ACK_IN = 0x01,
+ R09R_SCSI_REQ_IN = 0x02,
+ R09R_SCSI_BSY_IN = 0x04,
+ R09R_SCSI_SEL_IN = 0x08,
+ R09R_SCSI_ATN_IN = 0x10,
+ R09R_SCSI_MSG_IN = 0x20,
+ R09R_SCSI_IO_IN = 0x40,
+ R09R_SCSI_CD_IN = 0x80,
+
+ R09W_RESERVED = 0x01,
+ R09W_SCSI_REQ_OUT = 0x02, // target mode
+ R09W_SCSI_ACK_OUT = 0x02, // initiator mode
+ R09W_SCSI_BSY_OUT = 0x04,
+ R09W_SCSI_SEL_OUT = 0x08,
+ R09W_SCSI_ATN_OUT = 0x10,
+ R09W_SCSI_MSG_OUT = 0x20,
+ R09W_SCSI_IO_OUT = 0x40,
+ R09W_SCSI_CD_OUT = 0x80,
+
+ R09R_PHASE_MASK = 0xe0
+ };
+
+ devcb_write_line m_int_cb;
+ devcb_write_line m_breq_cb;
+
+ devcb_read8 m_port_a_r_cb;
+ devcb_write8 m_port_a_w_cb;
+ devcb_read8 m_port_b_r_cb;
+ devcb_write8 m_port_b_w_cb;
+
+ enum state_t
+ {
+ IDLE,
+ ARB_BUS_FREE,
+ ARB_START,
+ ARB_EVALUATE,
+ SEL_START,
+ SEL_DELAY,
+ SEL_WAIT_BSY,
+ SEL_COMPLETE,
+
+ DMA_IN,
+ DMA_IN_NEXT,
+ DMA_IN_REQ,
+ DMA_IN_DRAIN,
+ DMA_IN_DONE,
+ DMA_OUT,
+ DMA_OUT_NEXT,
+ DMA_OUT_REQ,
+ DMA_OUT_DONE,
+
+ AUTO_PIO,
+ AUTO_PIO_IN,
+ AUTO_PIO_OUT,
+ AUTO_PIO_DONE,
+ };
+
+ // internal state
+ emu_timer *m_state_timer;
+ state_t m_state;
+ bool m_int_asserted;
+
+ u32 m_scsi_ctrl_state;
+
+ u8 m_address_reg;
+
+ // registers
+ u32 m_dma_count;
+ bool m_offset_count_zero;
+ u8 m_rev_cntrl;
+ u8 m_status_reg_0;
+ u8 m_status_reg_1;
+ u8 m_scsi_signal_reg;
+ u8 m_scsi_id_data;
+ u8 m_source_dest_id;
+ u8 m_memory_data;
+ u8 m_port_a_latch;
+ u8 m_port_b_latch;
+ u8 m_scsi_latch_data;
+
+ u8 m_int_msk_reg_0;
+ u8 m_offset_cntrl;
+ u8 m_dma_cntrl;
+ u8 m_int_msk_reg_1;
+ u8 m_control_reg_0;
+ u8 m_control_reg_1;
+
+ util::fifo <u8, 8> m_fifo;
+};
+
+DECLARE_DEVICE_TYPE(AIC6250, aic6250_device)
+
+#endif // MAME_MACHINE_AIC6250_H
diff --git a/src/devices/machine/am9517a.cpp b/src/devices/machine/am9517a.cpp
index cd6955b63ed..463f1c447ef 100644
--- a/src/devices/machine/am9517a.cpp
+++ b/src/devices/machine/am9517a.cpp
@@ -52,7 +52,7 @@
//**************************************************************************
DEFINE_DEVICE_TYPE(AM9517A, am9517a_device, "am9517a", "AM9517A")
-DEFINE_DEVICE_TYPE(V53_DMAU, upd71071_v53_device, "v53_dmau", "V53 DMAU")
+DEFINE_DEVICE_TYPE(V5X_DMAU, v5x_dmau_device, "v5x_dmau", "V5X DMAU")
DEFINE_DEVICE_TYPE(PCXPORT_DMAC, pcxport_dmac_device, "pcx_dmac", "PC Transporter DMAC")
@@ -132,7 +132,7 @@ enum
// dma_request -
//-------------------------------------------------
-inline void am9517a_device::dma_request(int channel, int state)
+void am9517a_device::dma_request(int channel, int state)
{
LOG("AM9517A Channel %u DMA Request: %u\n", channel, state);
@@ -215,7 +215,7 @@ inline void am9517a_device::set_eop(int state)
//-------------------------------------------------
-// dma_read -
+// get_state1 -
//-------------------------------------------------
inline int am9517a_device::get_state1(bool msb_changed)
@@ -235,7 +235,7 @@ inline int am9517a_device::get_state1(bool msb_changed)
// dma_read -
//-------------------------------------------------
-inline void am9517a_device::dma_read()
+void am9517a_device::dma_read()
{
offs_t offset = m_channel[m_current_channel].m_address;
@@ -257,7 +257,7 @@ inline void am9517a_device::dma_read()
// dma_write -
//-------------------------------------------------
-inline void am9517a_device::dma_write()
+void am9517a_device::dma_write()
{
offs_t offset = m_channel[m_current_channel].m_address;
@@ -296,7 +296,7 @@ inline void am9517a_device::dma_advance()
{
if (MODE_ADDRESS_DECREMENT)
{
- m_channel[m_current_channel].m_address--;
+ m_channel[m_current_channel].m_address -= transfer_size(m_current_channel);
m_channel[m_current_channel].m_address &= m_address_mask;
if ((m_channel[m_current_channel].m_address & 0xff) == 0xff)
@@ -306,7 +306,7 @@ inline void am9517a_device::dma_advance()
}
else
{
- m_channel[m_current_channel].m_address++;
+ m_channel[m_current_channel].m_address += transfer_size(m_current_channel);
m_channel[m_current_channel].m_address &= m_address_mask;
if ((m_channel[m_current_channel].m_address & 0xff) == 0x00)
@@ -430,8 +430,13 @@ am9517a_device::am9517a_device(const machine_config &mconfig, const char *tag, d
{
}
-upd71071_v53_device::upd71071_v53_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : am9517a_device(mconfig, V53_DMAU, tag, owner, clock)
+v5x_dmau_device::v5x_dmau_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+ : am9517a_device(mconfig, V5X_DMAU, tag, owner, clock)
+ , m_in_mem16r_cb(*this)
+ , m_out_mem16w_cb(*this)
+ , m_in_io16r_cb{ { *this },{ *this },{ *this },{ *this } }
+ , m_out_io16w_cb{ { *this },{ *this },{ *this },{ *this } }
+
{
}
@@ -686,12 +691,12 @@ void am9517a_device::execute_run()
m_channel[m_current_channel].m_count--;
if (MODE_ADDRESS_DECREMENT)
{
- m_channel[m_current_channel].m_address--;
+ m_channel[m_current_channel].m_address -= transfer_size(m_current_channel);
m_channel[m_current_channel].m_address &= m_address_mask;
}
else
{
- m_channel[m_current_channel].m_address++;
+ m_channel[m_current_channel].m_address += transfer_size(m_current_channel);
m_channel[m_current_channel].m_address &= m_address_mask;
}
@@ -980,11 +985,18 @@ WRITE_LINE_MEMBER( am9517a_device::dreq3_w )
// upd71071 register layouts
//-------------------------------------------------
-void upd71071_v53_device::device_start()
+void v5x_dmau_device::device_start()
{
am9517a_device::device_start();
m_address_mask = 0x00ffffff;
+ m_in_mem16r_cb.resolve_safe(0);
+ m_out_mem16w_cb.resolve_safe();
+ for (auto &cb : m_in_io16r_cb)
+ cb.resolve_safe(0);
+ for (auto &cb : m_out_io16w_cb)
+ cb.resolve_safe();
+
m_selected_channel = 0;
m_base = 0;
@@ -992,7 +1004,7 @@ void upd71071_v53_device::device_start()
save_item(NAME(m_base));
}
-void upd71071_v53_device::device_reset()
+void v5x_dmau_device::device_reset()
{
am9517a_device::device_reset();
@@ -1001,7 +1013,7 @@ void upd71071_v53_device::device_reset()
}
-READ8_MEMBER(upd71071_v53_device::read)
+READ8_MEMBER(v5x_dmau_device::read)
{
uint8_t ret = 0;
int channel = m_selected_channel;
@@ -1085,7 +1097,7 @@ READ8_MEMBER(upd71071_v53_device::read)
return ret;
}
-WRITE8_MEMBER(upd71071_v53_device::write)
+WRITE8_MEMBER(v5x_dmau_device::write)
{
int channel = m_selected_channel;
@@ -1182,6 +1194,57 @@ WRITE8_MEMBER(upd71071_v53_device::write)
}
+void v5x_dmau_device::dma_read()
+{
+ if (m_channel[m_current_channel].m_mode & 0x1)
+ {
+ offs_t const offset = m_channel[m_current_channel].m_address >> 1;
+
+ switch (MODE_TRANSFER_MASK)
+ {
+ case MODE_TRANSFER_VERIFY:
+ case MODE_TRANSFER_WRITE:
+ m_temp = m_in_io16r_cb[m_current_channel](offset);
+ break;
+
+ case MODE_TRANSFER_READ:
+ m_temp = m_in_mem16r_cb(offset);
+ break;
+ }
+ }
+ else
+ am9517a_device::dma_read();
+}
+
+void v5x_dmau_device::dma_write()
+{
+ if (m_channel[m_current_channel].m_mode & 0x1)
+ {
+ offs_t const offset = m_channel[m_current_channel].m_address >> 1;
+
+ switch (MODE_TRANSFER_MASK)
+ {
+ case MODE_TRANSFER_VERIFY:
+ {
+ u16 const v1 = m_in_mem16r_cb(offset);
+ if (0 && m_temp != v1)
+ logerror("verify error %04x vs. %04x\n", m_temp, v1);
+ }
+ break;
+
+ case MODE_TRANSFER_WRITE:
+ m_out_mem16w_cb(offset, m_temp);
+ break;
+
+ case MODE_TRANSFER_READ:
+ m_out_io16w_cb[m_current_channel](offset, m_temp);
+ break;
+ }
+ }
+ else
+ am9517a_device::dma_write();
+}
+
void pcxport_dmac_device::device_reset()
{
m_state = STATE_SI;
diff --git a/src/devices/machine/am9517a.h b/src/devices/machine/am9517a.h
index 365246f60c6..37390a930d3 100644
--- a/src/devices/machine/am9517a.h
+++ b/src/devices/machine/am9517a.h
@@ -68,6 +68,7 @@ public:
DECLARE_WRITE_LINE_MEMBER( ready_w );
DECLARE_WRITE_LINE_MEMBER( eop_w );
+ template <unsigned C> DECLARE_WRITE_LINE_MEMBER( dreq_w ) { dma_request(C, state); }
DECLARE_WRITE_LINE_MEMBER( dreq0_w );
DECLARE_WRITE_LINE_MEMBER( dreq1_w );
DECLARE_WRITE_LINE_MEMBER( dreq2_w );
@@ -83,6 +84,11 @@ protected:
virtual void end_of_process();
+ virtual void dma_read();
+ virtual void dma_write();
+
+ virtual int transfer_size(int const channel) const { return 1; }
+
int m_icount;
uint32_t m_address_mask;
@@ -110,15 +116,13 @@ protected:
uint8_t m_request;
private:
- inline void dma_request(int channel, int state);
+ void dma_request(int channel, int state);
inline bool is_request_active(int channel);
inline bool is_software_request_active(int channel);
inline void set_hreq(int state);
inline void set_dack();
inline void set_eop(int state);
inline int get_state1(bool msb_changed);
- inline void dma_read();
- inline void dma_write();
inline void dma_advance();
devcb_write_line m_out_hreq_cb;
@@ -133,11 +137,17 @@ private:
};
-class upd71071_v53_device : public am9517a_device
+class v5x_dmau_device : public am9517a_device
{
public:
// construction/destruction
- upd71071_v53_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+ v5x_dmau_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+ auto in_mem16r_callback() { return m_in_mem16r_cb.bind(); }
+ auto out_mem16w_callback() { return m_out_mem16w_cb.bind(); }
+
+ template <unsigned C> auto in_io16r_callback() { return m_in_io16r_cb[C].bind(); }
+ template <unsigned C> auto out_io16w_callback() { return m_out_io16w_cb[C].bind(); }
virtual DECLARE_READ8_MEMBER( read ) override;
virtual DECLARE_WRITE8_MEMBER( write ) override;
@@ -147,10 +157,20 @@ protected:
virtual void device_start() override;
virtual void device_reset() override;
+ virtual void dma_read() override;
+ virtual void dma_write() override;
+
+ virtual int transfer_size(int const channel) const override { return (m_channel[channel].m_mode & 0x1) ? 2 : 1; }
+
+ // 16 bit transfer callbacks
+ devcb_read16 m_in_mem16r_cb;
+ devcb_write16 m_out_mem16w_cb;
+ devcb_read16 m_in_io16r_cb[4];
+ devcb_write16 m_out_io16w_cb[4];
+
int m_selected_channel;
int m_base;
uint8_t m_command_high;
-
};
@@ -170,7 +190,7 @@ protected:
// device type definition
DECLARE_DEVICE_TYPE(AM9517A, am9517a_device)
-DECLARE_DEVICE_TYPE(V53_DMAU, upd71071_v53_device)
+DECLARE_DEVICE_TYPE(V5X_DMAU, v5x_dmau_device)
DECLARE_DEVICE_TYPE(PCXPORT_DMAC, pcxport_dmac_device)
#endif // MAME_MACHINE_AM9517_H
diff --git a/src/devices/machine/cs4031.h b/src/devices/machine/cs4031.h
index 4ea5829e3aa..e8b6e314f93 100644
--- a/src/devices/machine/cs4031.h
+++ b/src/devices/machine/cs4031.h
@@ -48,15 +48,6 @@ public:
cs4031_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
// callbacks
- template <class Obj> devcb_base &set_ior_callback(Obj &&ior) { return m_read_ior.set_callback(std::forward<Obj>(ior)); }
- template <class Obj> devcb_base &set_iow_callback(Obj &&iow) { return m_write_iow.set_callback(std::forward<Obj>(iow)); }
- template <class Obj> devcb_base &set_tc_callback(Obj &&tc) { return m_write_tc.set_callback(std::forward<Obj>(tc)); }
- template <class Obj> devcb_base &set_hold_callback(Obj &&hold) { return m_write_hold.set_callback(std::forward<Obj>(hold)); }
- template <class Obj> devcb_base &set_cpureset_callback(Obj &&cpureset) { return m_write_cpureset.set_callback(std::forward<Obj>(cpureset)); }
- template <class Obj> devcb_base &set_nmi_callback(Obj &&nmi) { return m_write_nmi.set_callback(std::forward<Obj>(nmi)); }
- template <class Obj> devcb_base &set_intr_callback(Obj &&intr) { return m_write_intr.set_callback(std::forward<Obj>(intr)); }
- template <class Obj> devcb_base &set_a20m_callback(Obj &&a20m) { return m_write_a20m.set_callback(std::forward<Obj>(a20m)); }
- template <class Obj> devcb_base &set_spkr_callback(Obj &&spkr) { return m_write_spkr.set_callback(std::forward<Obj>(spkr)); }
auto ior() { return m_read_ior.bind(); }
auto iow() { return m_write_iow.bind(); }
auto tc() { return m_write_tc.bind(); }
diff --git a/src/devices/machine/i80130.cpp b/src/devices/machine/i80130.cpp
index 5f974cb532f..7242e783592 100644
--- a/src/devices/machine/i80130.cpp
+++ b/src/devices/machine/i80130.cpp
@@ -100,18 +100,19 @@ const tiny_rom_entry *i80130_device::device_rom_region() const
// device_add_mconfig - add device configuration
//-------------------------------------------------
-MACHINE_CONFIG_START(i80130_device::device_add_mconfig)
- MCFG_DEVICE_ADD("pic", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(WRITELINE(*this, i80130_device, irq_w))
-
- MCFG_DEVICE_ADD("pit", PIT8254, 0)
- MCFG_PIT8253_CLK0(0)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, i80130_device, systick_w))
- MCFG_PIT8253_CLK1(0)
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(*this, i80130_device, delay_w))
- MCFG_PIT8253_CLK2(0)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, i80130_device, baud_w))
-MACHINE_CONFIG_END
+void i80130_device::device_add_mconfig(machine_config &config)
+{
+ PIC8259(config, m_pic, 0);
+ m_pic->out_int_callback().set(FUNC(i80130_device::irq_w));
+
+ PIT8254(config, m_pit, 0);
+ m_pit->set_clk<0>(0);
+ m_pit->out_handler<0>().set(FUNC(i80130_device::systick_w));
+ m_pit->set_clk<1>(0);
+ m_pit->out_handler<1>().set(FUNC(i80130_device::delay_w));
+ m_pit->set_clk<2>(0);
+ m_pit->out_handler<2>().set(FUNC(i80130_device::baud_w));
+}
diff --git a/src/devices/machine/i8251.cpp b/src/devices/machine/i8251.cpp
index da883cd7b06..69883c412af 100644
--- a/src/devices/machine/i8251.cpp
+++ b/src/devices/machine/i8251.cpp
@@ -26,7 +26,7 @@
//**************************************************************************
DEFINE_DEVICE_TYPE(I8251, i8251_device, "i8251", "Intel 8251 USART")
-DEFINE_DEVICE_TYPE(V53_SCU, v53_scu_device, "v63_scu", "NEC V53 SCU")
+DEFINE_DEVICE_TYPE(V5X_SCU, v5x_scu_device, "v5x_scu", "NEC V5X SCU")
//-------------------------------------------------
@@ -61,8 +61,8 @@ i8251_device::i8251_device(const machine_config &mconfig, const char *tag, devic
{
}
-v53_scu_device::v53_scu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : i8251_device(mconfig, V53_SCU, tag, owner, clock)
+v5x_scu_device::v5x_scu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+ : i8251_device(mconfig, V5X_SCU, tag, owner, clock)
{
}
@@ -740,3 +740,44 @@ READ_LINE_MEMBER(i8251_device::txrdy_r)
{
return is_tx_enabled() && (m_status & I8251_STATUS_TX_READY) != 0;
}
+
+void v5x_scu_device::device_start()
+{
+ i8251_device::device_start();
+
+ save_item(NAME(m_simk));
+}
+
+void v5x_scu_device::device_reset()
+{
+ // FIXME: blindly copied from v53.cpp - not verified
+ m_simk = 0x03;
+
+ i8251_device::device_reset();
+}
+
+u8 v5x_scu_device::read(offs_t offset)
+{
+ u8 data = 0;
+
+ switch (offset)
+ {
+ case 0: data = data_r(); break;
+ case 1: data = status_r(); break;
+ case 2: break;
+ case 3: data = simk_r(); break;
+ }
+
+ return data;
+}
+
+void v5x_scu_device::write(offs_t offset, uint8_t data)
+{
+ switch (offset)
+ {
+ case 0: data_w(data); break;
+ case 1: control_w(data); break;
+ case 2: mode_w(data); break;
+ case 3: simk_w(data); break;
+ }
+}
diff --git a/src/devices/machine/i8251.h b/src/devices/machine/i8251.h
index 4a9f7bb3eba..4e2773c3e40 100644
--- a/src/devices/machine/i8251.h
+++ b/src/devices/machine/i8251.h
@@ -43,8 +43,8 @@ public:
uint8_t status_r();
void control_w(uint8_t data);
- uint8_t read(offs_t offset);
- void write(offs_t offset, uint8_t data);
+ virtual uint8_t read(offs_t offset);
+ virtual void write(offs_t offset, uint8_t data);
DECLARE_WRITE_LINE_MEMBER( write_rxd );
DECLARE_WRITE_LINE_MEMBER( write_cts );
@@ -138,20 +138,31 @@ private:
uint8_t m_tx_data;
};
-class v53_scu_device : public i8251_device
+class v5x_scu_device : public i8251_device
{
public:
// construction/destruction
- v53_scu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+ v5x_scu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
- void command_w(uint8_t data) { i8251_device::command_w(data); }
- void mode_w(uint8_t data) { i8251_device::mode_w(data); }
+ virtual uint8_t read(offs_t offset) override;
+ virtual void write(offs_t offset, uint8_t data) override;
+
+protected:
+ virtual void device_start() override;
+ virtual void device_reset() override;
+
+ // TODO: currently unimplemented interrupt masking
+ u8 simk_r() { return m_simk; }
+ void simk_w(u8 data) { m_simk = data; }
+
+private:
+ u8 m_simk;
};
// device type definition
DECLARE_DEVICE_TYPE(I8251, i8251_device)
-DECLARE_DEVICE_TYPE(V53_SCU, v53_scu_device)
+DECLARE_DEVICE_TYPE(V5X_SCU, v5x_scu_device)
#endif // MAME_MACHINE_I8251_H
diff --git a/src/devices/machine/mb87030.cpp b/src/devices/machine/mb87030.cpp
index 966cb1e6699..9edbec0f429 100644
--- a/src/devices/machine/mb87030.cpp
+++ b/src/devices/machine/mb87030.cpp
@@ -2,22 +2,24 @@
// copyright-holders:Sven Schnelle
#include "emu.h"
-#define VERBOSE 0
-#include "logmacro.h"
#include "mb87030.h"
+//#define VERBOSE 1
+#include "logmacro.h"
+
+
DEFINE_DEVICE_TYPE(MB87030, mb87030_device, "mb87030", "Fujitsu MB87030 SCSI controller")
mb87030_device::mb87030_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
- mb87030_device(mconfig, MB87030, tag, owner, clock)
+ mb87030_device(mconfig, MB87030, tag, owner, clock)
{
}
mb87030_device::mb87030_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock) :
- nscsi_device(mconfig, type, tag, owner, clock),
- m_irq_handler(*this),
- m_dreq_handler(*this)
+ nscsi_device(mconfig, type, tag, owner, clock),
+ m_irq_handler(*this),
+ m_dreq_handler(*this)
{
}
@@ -71,7 +73,7 @@ void mb87030_device::device_reset()
auto mb87030_device::get_state_name(State state) const
{
- switch(state) {
+ switch (state) {
case State::Idle:
return "Idle";
case State::ArbitrationWaitBusFree:
@@ -166,10 +168,6 @@ void mb87030_device::scsi_disconnect()
LOG("%s: m_tc %d\n", __FUNCTION__, m_tc);
m_ssts &= ~(SSTS_INIT_CONNECTED|SSTS_TARG_CONNECTED|SSTS_SPC_BUSY|SSTS_XFER_IN_PROGRESS);
m_ints = INTS_DISCONNECTED;
- if (m_pctl & PCTL_BUS_FREE_IE) {
- LOG("disconnect IE\n");
- m_ints |= INTS_DISCONNECTED;
- }
update_ints();
update_state(State::Idle);
}
@@ -234,22 +232,20 @@ void mb87030_device::step(bool timeout)
return;
}
-
if ((m_ssts & SSTS_INIT_CONNECTED) && !(ctrl & S_BSY)) {
LOG("SCSI disconnect\n");
scsi_disconnect();
scsi_set_ctrl(0, S_ALL);
}
-
- switch(m_state) {
+ switch (m_state) {
case State::Idle:
-
if (ctrl == 0 && (m_pctl & PCTL_BUS_FREE_IE)) {
m_ints |= INTS_DISCONNECTED;
update_ints();
}
break;
+
case State::ArbitrationWaitBusFree:
if (!(ctrl & (S_BSY|S_SEL)))
update_state(State::ArbitrationAssertBSY, 1);
@@ -262,7 +258,6 @@ void mb87030_device::step(bool timeout)
break;
case State::ArbitrationWait:
-
for (int id = (2 << m_bdid); id <= 0x80; id <<= 1) {
LOG("check %d\n", id);
if (data & id) {
@@ -320,18 +315,13 @@ void mb87030_device::step(bool timeout)
break;
case State::TransferWaitReq:
-
-
- if (!m_tc && (m_fifo.empty() || m_dma_transfer)) {
+ if (!m_tc && !(m_scmd & SCMD_TERM_MODE)) {
LOG("TransferWaitReq: tc == 0\n");
scsi_bus->data_w(scsi_refid, 0);
scsi_command_complete();
break;
}
- if (m_tc < 0)
- break;
-
if (m_scsi_phase != (ctrl & S_PHASE_MASK)) {
LOG("SCSI phase change during transfer\n");
m_ints |= INTS_SERVICE_REQUIRED;
@@ -345,7 +335,7 @@ void mb87030_device::step(bool timeout)
break;
}
- if (!m_dma_transfer) {
+ if (!m_dma_transfer || (m_scmd & SCMD_TERM_MODE)) {
update_state((ctrl & S_INP) ? State::TransferRecvData : State::TransferSendData, 1);
} else {
update_state((ctrl & S_INP) ? State::TransferRecvDataDMAReq : State::TransferSendDataDMAReq, 1);
@@ -353,6 +343,11 @@ void mb87030_device::step(bool timeout)
break;
case State::TransferRecvData:
+ if (!m_tc && (m_scmd & SCMD_TERM_MODE)) {
+ update_state(State::TransferSendAck, 10);
+ break;
+ }
+
if (!m_tc || m_fifo.full())
break;
@@ -379,15 +374,18 @@ void mb87030_device::step(bool timeout)
break;
case State::TransferSendData:
-
- if (m_tc < 0 || m_fifo.empty()) {
- LOG("fifo empty or m_tc(%d) zero\n", m_tc);
+ if (m_tc && !m_fifo.empty()) {
+ scsi_bus->data_w(scsi_refid, m_fifo.dequeue());
+ m_tc--;
+ update_state(State::TransferSendAck, 10);
break;
}
- scsi_bus->data_w(scsi_refid, m_fifo.dequeue());
- m_tc--;
- update_state(State::TransferSendAck, 10);
+ if (!m_tc && (m_scmd & SCMD_TERM_MODE)) {
+ scsi_bus->data_w(scsi_refid, m_temp);
+ update_state(State::TransferSendAck, 10);
+ break;
+ }
break;
case State::TransferSendDataDMAReq:
@@ -407,12 +405,11 @@ void mb87030_device::step(bool timeout)
break;
case State::TransferSendAck:
+ if (!(m_scmd & SCMD_TERM_MODE) && !(ctrl & S_INP))
+ m_temp = data;
- if (!(ctrl & S_INP))
- m_temp = data;
-
- scsi_set_ctrl(S_ACK, S_ACK);
- scsi_bus->ctrl_wait(scsi_refid, 0, S_REQ);
+ scsi_set_ctrl(S_ACK, S_ACK);
+ scsi_bus->ctrl_wait(scsi_refid, 0, S_REQ);
update_state(State::TransferWaitDeassertREQ, 10);
break;
@@ -423,9 +420,9 @@ void mb87030_device::step(bool timeout)
break;
case State::TransferDeassertACK:
- scsi_set_ctrl(0, S_ACK);
- scsi_bus->ctrl_wait(scsi_refid, S_REQ, S_REQ);
update_state(State::TransferWaitReq, 10);
+ scsi_bus->ctrl_wait(scsi_refid, S_REQ, S_REQ);
+ scsi_set_ctrl(0, S_ACK);
break;
}
@@ -504,7 +501,7 @@ void mb87030_device::update_ints()
READ8_MEMBER(mb87030_device::bdid_r)
{
LOG("%s %02X\n", __FUNCTION__, (1 << m_bdid));
- return (1 << m_bdid);
+ return 1 << m_bdid;
}
WRITE8_MEMBER(mb87030_device::bdid_w)
@@ -537,10 +534,11 @@ WRITE8_MEMBER(mb87030_device::scmd_w)
LOG("%s: %02X\n", __FUNCTION__, data);
m_scmd = data;
- switch(m_scmd & SCMD_CMD_MASK) {
+ switch (m_scmd & SCMD_CMD_MASK) {
case SCMD_CMD_BUS_RELEASE:
LOG("%s: Bus release\n", __FUNCTION__);
break;
+
case SCMD_CMD_SELECT:
LOG("%s: Select\n", __FUNCTION__);
if (m_sctl & SCTL_ARBITRATION_ENABLE)
@@ -549,6 +547,7 @@ WRITE8_MEMBER(mb87030_device::scmd_w)
update_state(State::SelectionWaitBusFree, 10);
step(false);
break;
+
case SCMD_CMD_RESET_ATN:
LOG("%s: Reset ATN\n", __FUNCTION__);
// if (m_state == State::Idle)
@@ -556,6 +555,7 @@ WRITE8_MEMBER(mb87030_device::scmd_w)
// else
scsi_set_ctrl(0, S_ATN);
break;
+
case SCMD_CMD_SET_ATN:
LOG("%s: Set ATN\n", __FUNCTION__);
if (m_state == State::Idle)
@@ -563,6 +563,7 @@ WRITE8_MEMBER(mb87030_device::scmd_w)
else
scsi_set_ctrl(S_ATN, S_ATN);
break;
+
case SCMD_CMD_TRANSFER:
if (!(m_ssts & (SSTS_INIT_CONNECTED|SSTS_TARG_CONNECTED)))
break;
@@ -572,9 +573,11 @@ WRITE8_MEMBER(mb87030_device::scmd_w)
m_ssts |= SSTS_SPC_BUSY|SSTS_XFER_IN_PROGRESS;
update_state(State::TransferWaitReq, 5);
break;
+
case SCMD_CMD_TRANSFER_PAUSE:
LOG("%s: Transfer Pause\n", __FUNCTION__);
break;
+
case SCMD_CMD_RESET_ACK_REQ:
LOG("%s: Reset ACK/REQ\n", __FUNCTION__);
if (m_ssts & SSTS_INIT_CONNECTED)
@@ -582,6 +585,7 @@ WRITE8_MEMBER(mb87030_device::scmd_w)
if (m_ssts & SSTS_TARG_CONNECTED)
scsi_set_ctrl(0, S_REQ);
break;
+
case SCMD_CMD_SET_ACK_REQ:
LOG("%s: Set ACK/REQ\n", __FUNCTION__);
if (m_ssts & SSTS_INIT_CONNECTED) {
@@ -674,7 +678,6 @@ WRITE8_MEMBER(mb87030_device::pctl_w)
m_scsi_phase = m_pctl & 7;
if (m_pctl & PCTL_BUS_FREE_IE)
step(false);
-
}
READ8_MEMBER(mb87030_device::mbc_r)
@@ -685,7 +688,6 @@ READ8_MEMBER(mb87030_device::mbc_r)
READ8_MEMBER(mb87030_device::dreg_r)
{
-
step(false);
if (!m_fifo.empty())
m_dreg = m_fifo.dequeue();
@@ -707,7 +709,6 @@ READ8_MEMBER(mb87030_device::temp_r)
step(false);
LOG("%s: %02X\n", __FUNCTION__, m_temp);
return m_temp;
-
}
WRITE8_MEMBER(mb87030_device::temp_w)
diff --git a/src/devices/machine/pdc.h b/src/devices/machine/pdc.h
index 8f2b958ce2b..df205ae0b29 100644
--- a/src/devices/machine/pdc.h
+++ b/src/devices/machine/pdc.h
@@ -113,10 +113,5 @@ private:
/* Device type */
DECLARE_DEVICE_TYPE(PDC, pdc_device)
-/* MCFG defines */
-#define MCFG_PDC_R_CB(_devcb) \
- downcast<pdc_device &>(*device).m68k_r_callback(DEVCB_##_devcb);
-#define MCFG_PDC_W_CB(_devcb) \
- downcast<pdc_device &>(*device).m68k_w_callback(DEVCB_##_devcb);
#endif // MAME_MACHINE_PDC_H
diff --git a/src/devices/machine/phi.h b/src/devices/machine/phi.h
index ea3cad4c09a..c75fbe08427 100644
--- a/src/devices/machine/phi.h
+++ b/src/devices/machine/phi.h
@@ -11,47 +11,6 @@
#ifndef MAME_MACHINE_PHI_H
#define MAME_MACHINE_PHI_H
-// Set read and write callbacks to access DIO bus on IEEE-488
-#define MCFG_PHI_DIO_READWRITE_CB(_read , _write) \
- downcast<phi_device &>(*device).set_dio_read_cb(DEVCB_##_read); \
- downcast<phi_device &>(*device).set_dio_write_cb(DEVCB_##_write);
-
-// Set write callbacks to access uniline signals on IEEE-488
-#define MCFG_PHI_EOI_WRITE_CB(_write) \
- downcast<phi_device &>(*device).set_488_signal_write_cb(phi_device::PHI_488_EOI , DEVCB_##_write);
-
-#define MCFG_PHI_DAV_WRITE_CB(_write) \
- downcast<phi_device &>(*device).set_488_signal_write_cb(phi_device::PHI_488_DAV , DEVCB_##_write);
-
-#define MCFG_PHI_NRFD_WRITE_CB(_write) \
- downcast<phi_device &>(*device).set_488_signal_write_cb(phi_device::PHI_488_NRFD , DEVCB_##_write);
-
-#define MCFG_PHI_NDAC_WRITE_CB(_write) \
- downcast<phi_device &>(*device).set_488_signal_write_cb(phi_device::PHI_488_NDAC , DEVCB_##_write);
-
-#define MCFG_PHI_IFC_WRITE_CB(_write) \
- downcast<phi_device &>(*device).set_488_signal_write_cb(phi_device::PHI_488_IFC , DEVCB_##_write);
-
-#define MCFG_PHI_SRQ_WRITE_CB(_write) \
- downcast<phi_device &>(*device).set_488_signal_write_cb(phi_device::PHI_488_SRQ , DEVCB_##_write);
-
-#define MCFG_PHI_ATN_WRITE_CB(_write) \
- downcast<phi_device &>(*device).set_488_signal_write_cb(phi_device::PHI_488_ATN , DEVCB_##_write);
-
-#define MCFG_PHI_REN_WRITE_CB(_write) \
- downcast<phi_device &>(*device).set_488_signal_write_cb(phi_device::PHI_488_REN , DEVCB_##_write);
-
-// Set write callback for INT signal
-#define MCFG_PHI_INT_WRITE_CB(_write) \
- downcast<phi_device &>(*device).set_int_write_cb(DEVCB_##_write);
-
-// Set write callback for DMARQ signal
-#define MCFG_PHI_DMARQ_WRITE_CB(_write) \
- downcast<phi_device &>(*device).set_dmarq_write_cb(DEVCB_##_write);
-
-// Set read callback for SYS_CNTRL signal
-#define MCFG_PHI_SYS_CNTRL_READ_CB(_read) \
- downcast<phi_device &>(*device).set_sys_cntrl_read_cb(DEVCB_##_read);
class phi_device : public device_t
{
@@ -72,18 +31,16 @@ public:
PHI_488_SIGNAL_COUNT
};
- template <class Object> devcb_base& set_dio_read_cb(Object &&cb) { return m_dio_read_func.set_callback(std::forward<Object>(cb)); }
- template <class Object> devcb_base& set_dio_write_cb(Object &&cb) { return m_dio_write_func.set_callback(std::forward<Object>(cb)); }
- template <class Object> devcb_base& set_488_signal_write_cb(phi_488_signal_t signal , Object &&cb) { return m_signal_wr_fns[ signal ].set_callback(std::forward<Object>(cb)); }
- template <class Object> devcb_base& set_int_write_cb(Object &&cb) { return m_int_write_func.set_callback(std::forward<Object>(cb)); }
- template <class Object> devcb_base& set_dmarq_write_cb(Object &&cb) { return m_dmarq_write_func.set_callback(std::forward<Object>(cb)); }
- template <class Object> devcb_base &set_sys_cntrl_read_cb(Object &&cb) { return m_sys_cntrl_read_func.set_callback(std::forward<Object>(cb)); }
-
+ // Set read and write callbacks to access DIO bus on IEEE-488
auto dio_read_cb() { return m_dio_read_func.bind(); }
auto dio_write_cb() { return m_dio_write_func.bind(); }
+ // Set write callbacks to access uniline signals on IEEE-488
template <phi_488_signal_t Signal> auto signal_write_cb() { return m_signal_wr_fns[ Signal ].bind(); }
+ // Set write callback for INT signal
auto int_write_cb() { return m_int_write_func.bind(); }
+ // Set write callback for DMARQ signal
auto dmarq_write_cb() { return m_dmarq_write_func.bind(); }
+ // Set read callback for SYS_CNTRL signal
auto sys_cntrl_read_cb() { return m_sys_cntrl_read_func.bind(); }
DECLARE_WRITE_LINE_MEMBER(eoi_w);
diff --git a/src/devices/machine/pic8259.cpp b/src/devices/machine/pic8259.cpp
index 22cc5e4862a..40653cdf254 100644
--- a/src/devices/machine/pic8259.cpp
+++ b/src/devices/machine/pic8259.cpp
@@ -57,7 +57,6 @@ void pic8259_device::device_timer(emu_timer &timer, device_timer_id id, int para
m_out_int_func(0);
}
-
void pic8259_device::set_irq_line(int irq, int state)
{
uint8_t mask = (1 << irq);
@@ -65,7 +64,7 @@ void pic8259_device::set_irq_line(int irq, int state)
if (state)
{
/* setting IRQ line */
- LOG("pic8259_set_irq_line(): PIC set IRQ line #%d\n", irq);
+ LOG("set_irq_line(): PIC set IRQ line #%d\n", irq);
if(m_level_trig_mode || (!m_level_trig_mode && !(m_irq_lines & mask)))
{
@@ -76,7 +75,7 @@ void pic8259_device::set_irq_line(int irq, int state)
else
{
/* clearing IRQ line */
- LOG("pic8259_device::set_irq_line(): PIC cleared IRQ line #%d\n", irq);
+ LOG("set_irq_line(): PIC cleared IRQ line #%d\n", irq);
m_irq_lines &= ~mask;
m_irr &= ~mask;
@@ -110,7 +109,7 @@ uint32_t pic8259_device::acknowledge()
}
else
{
- if (m_is_x86)
+ if (is_x86())
{
/* For x86 mode*/
return irq + m_base;
@@ -124,7 +123,7 @@ uint32_t pic8259_device::acknowledge()
}
}
logerror("Spurious IRQ\n");
- if (m_is_x86)
+ if (is_x86())
return m_base + 7;
else
return 0xcd0000 + (m_vector_addr_high << 8) + m_vector_addr_low + (7 << (3-m_vector_size));
@@ -409,9 +408,10 @@ void pic8259_device::device_reset()
}
DEFINE_DEVICE_TYPE(PIC8259, pic8259_device, "pic8259", "Intel 8259 PIC")
+DEFINE_DEVICE_TYPE(V5X_ICU, v5x_icu_device, "v5x_icu", "NEC V5X ICU")
-pic8259_device::pic8259_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
- : device_t(mconfig, PIC8259, tag, owner, clock)
+pic8259_device::pic8259_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
+ : device_t(mconfig, type, tag, owner, clock)
, m_out_int_func(*this)
, m_in_sp_func(*this)
, m_read_slave_ack_func(*this)
@@ -420,3 +420,13 @@ pic8259_device::pic8259_device(const machine_config &mconfig, const char *tag, d
, m_level_trig_mode(0)
{
}
+
+pic8259_device::pic8259_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+ : pic8259_device(mconfig, PIC8259, tag, owner, clock)
+{
+}
+
+v5x_icu_device::v5x_icu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+ : pic8259_device(mconfig, V5X_ICU, tag, owner, clock)
+{
+}
diff --git a/src/devices/machine/pic8259.h b/src/devices/machine/pic8259.h
index 24e5b1f6e59..73a13e9d757 100644
--- a/src/devices/machine/pic8259.h
+++ b/src/devices/machine/pic8259.h
@@ -28,31 +28,11 @@
#define MAME_MACHINE_PIC8259_H
-/***************************************************************************
- DEVICE CONFIGURATION MACROS
-***************************************************************************/
-
-// Interrupt request output to CPU or master 8259 (active high)
-#define MCFG_PIC8259_OUT_INT_CB(_devcb) \
- downcast<pic8259_device &>(*device).set_out_int_callback(DEVCB_##_devcb);
-
-// Slave program select (VCC = master; GND = slave; pin becomes EN output in buffered mode)
-#define MCFG_PIC8259_IN_SP_CB(_devcb) \
- downcast<pic8259_device &>(*device).set_in_sp_callback(DEVCB_##_devcb);
-
-// Cascaded interrupt acknowledge request for slave 8259 to place vector on data bus
-#define MCFG_PIC8259_CASCADE_ACK_CB(_devcb) \
- downcast<pic8259_device &>(*device).set_read_slave_ack_callback(DEVCB_##_devcb);
-
-
class pic8259_device : public device_t
{
public:
pic8259_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
- template <class Object> devcb_base &set_out_int_callback(Object &&cb) { return m_out_int_func.set_callback(std::forward<Object>(cb)); }
- template <class Object> devcb_base &set_in_sp_callback(Object &&cb) { return m_in_sp_func.set_callback(std::forward<Object>(cb)); }
- template <class Object> devcb_base &set_read_slave_ack_callback(Object &&cb) { return m_read_slave_ack_func.set_callback(std::forward<Object>(cb)); }
auto out_int_callback() { return m_out_int_func.bind(); }
auto in_sp_callback() { return m_in_sp_func.bind(); }
auto read_slave_ack_callback() { return m_read_slave_ack_func.bind(); }
@@ -73,12 +53,16 @@ public:
IRQ_CALLBACK_MEMBER(inta_cb);
protected:
+ pic8259_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
+
// device-level overrides
virtual void device_resolve_objects() override;
virtual void device_start() override;
virtual void device_reset() override;
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override;
+ virtual bool is_x86() const { return m_is_x86; }
+
private:
static constexpr device_timer_id TIMER_CHECK_IRQ = 0;
@@ -131,6 +115,16 @@ private:
uint8_t m_is_x86;
};
+class v5x_icu_device : public pic8259_device
+{
+public:
+ v5x_icu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+protected:
+ virtual bool is_x86() const override { return true; }
+};
+
DECLARE_DEVICE_TYPE(PIC8259, pic8259_device)
+DECLARE_DEVICE_TYPE(V5X_ICU, v5x_icu_device)
#endif // MAME_MACHINE_PIC8259_H
diff --git a/src/devices/machine/pit8253.h b/src/devices/machine/pit8253.h
index 722cfa5233d..eebee4edbb3 100644
--- a/src/devices/machine/pit8253.h
+++ b/src/devices/machine/pit8253.h
@@ -30,29 +30,6 @@
#pragma once
-/***************************************************************************
- DEVICE CONFIGURATION MACROS
-***************************************************************************/
-
-#define MCFG_PIT8253_CLK0(_clk) \
- downcast<pit8253_device &>(*device).set_clk<0>(_clk);
-
-#define MCFG_PIT8253_CLK1(_clk) \
- downcast<pit8253_device &>(*device).set_clk<1>(_clk);
-
-#define MCFG_PIT8253_CLK2(_clk) \
- downcast<pit8253_device &>(*device).set_clk<2>(_clk);
-
-#define MCFG_PIT8253_OUT0_HANDLER(_devcb) \
- downcast<pit8253_device &>(*device).set_out_handler<0>(DEVCB_##_devcb);
-
-#define MCFG_PIT8253_OUT1_HANDLER(_devcb) \
- downcast<pit8253_device &>(*device).set_out_handler<1>(DEVCB_##_devcb);
-
-#define MCFG_PIT8253_OUT2_HANDLER(_devcb) \
- downcast<pit8253_device &>(*device).set_out_handler<2>(DEVCB_##_devcb);
-
-
enum class pit_type
{
I8254,
@@ -132,7 +109,6 @@ public:
// configuration helpers
template <unsigned N> void set_clk(double clk) { m_clk[N] = clk; }
template <unsigned N> void set_clk(const XTAL &xtal) { set_clk<N>(xtal.dvalue()); }
- template <unsigned N, class Object> devcb_base &set_out_handler(Object &&cb) { return m_out_handler[N].set_callback(std::forward<Object>(cb)); }
template <unsigned N> auto out_handler() { return m_out_handler[N].bind(); }
uint8_t read(offs_t offset);
diff --git a/src/devices/machine/smioc.cpp b/src/devices/machine/smioc.cpp
index dee1b7d751a..3a426e8405b 100644
--- a/src/devices/machine/smioc.cpp
+++ b/src/devices/machine/smioc.cpp
@@ -158,7 +158,7 @@ void smioc_device::device_add_mconfig(machine_config &config)
scc2698b_device &scc2698b(SCC2698B(config, "scc2698b", XTAL(3'686'400)));
scc2698b.tx_callback<'a'>().set("rs232_p1", FUNC(rs232_port_device::write_txd));
scc2698b.mpp1_callback<'a'>().set("dma8237_2", FUNC(am9517a_device::dreq1_w)).invert();
- scc2698b.mpp1_callback<'a'>().set("dma8237_2", FUNC(am9517a_device::dreq0_w)).invert();
+ scc2698b.mpp2_callback<'a'>().set("dma8237_2", FUNC(am9517a_device::dreq0_w)).invert();
scc2698b.tx_callback<'b'>().set("rs232_p2", FUNC(rs232_port_device::write_txd));
scc2698b.mpp1_callback<'b'>().set("dma8237_2", FUNC(am9517a_device::dreq3_w)).invert();
scc2698b.mpp2_callback<'b'>().set("dma8237_2", FUNC(am9517a_device::dreq2_w)).invert();
diff --git a/src/devices/sound/dac.cpp b/src/devices/sound/dac.cpp
index c095ba3ee05..c2dfe37ce0a 100644
--- a/src/devices/sound/dac.cpp
+++ b/src/devices/sound/dac.cpp
@@ -12,8 +12,9 @@
***************************************************************************/
+#include "emu.h"
+
#define DAC_GENERATOR_EPILOG(_dac_type, _dac_class, _dac_description, _dac_shortname) \
DEFINE_DEVICE_TYPE(_dac_type, _dac_class, _dac_shortname, _dac_description)
-#include "emu.h"
#include "dac.h"
diff --git a/src/devices/video/cgapal.cpp b/src/devices/video/cgapal.cpp
index 396c313c1ba..b726db23335 100644
--- a/src/devices/video/cgapal.cpp
+++ b/src/devices/video/cgapal.cpp
@@ -11,6 +11,7 @@
*
*/
+#include "emu.h"
#include "video/cgapal.h"
const unsigned char cga_palette[16 * CGA_PALETTE_SETS][3] =
diff --git a/src/emu/attotime.cpp b/src/emu/attotime.cpp
index e756aa9653d..057a840454b 100644
--- a/src/emu/attotime.cpp
+++ b/src/emu/attotime.cpp
@@ -8,9 +8,7 @@
***************************************************************************/
-#include "emucore.h"
-#include "eminline.h"
-#include "attotime.h"
+#include "emu.h"
//**************************************************************************
diff --git a/src/emu/debug/textbuf.cpp b/src/emu/debug/textbuf.cpp
index 279ce8dead6..32d86cbce32 100644
--- a/src/emu/debug/textbuf.cpp
+++ b/src/emu/debug/textbuf.cpp
@@ -8,7 +8,7 @@
***************************************************************************/
-#include "corealloc.h"
+#include "emu.h"
#include "textbuf.h"
diff --git a/src/emu/emualloc.cpp b/src/emu/emualloc.cpp
index 3993121e9bc..c15f6db7bf4 100644
--- a/src/emu/emualloc.cpp
+++ b/src/emu/emualloc.cpp
@@ -8,7 +8,7 @@
***************************************************************************/
-#include "emucore.h"
+#include "emu.h"
//**************************************************************************
diff --git a/src/emu/video/rgbgen.cpp b/src/emu/video/rgbgen.cpp
index 1882493b698..db4cd95de61 100644
--- a/src/emu/video/rgbgen.cpp
+++ b/src/emu/video/rgbgen.cpp
@@ -8,9 +8,11 @@
***************************************************************************/
+#include "emu.h"
+
+
#if !(defined(__ALTIVEC__) || ((!defined(MAME_DEBUG) || defined(__OPTIMIZE__)) && (defined(__SSE2__) || defined(_MSC_VER)) && defined(PTR64)))
-#include "emu.h"
#include "rgbgen.h"
/***************************************************************************
diff --git a/src/emu/video/rgbsse.cpp b/src/emu/video/rgbsse.cpp
index 24c09fc68c3..719310ff144 100644
--- a/src/emu/video/rgbsse.cpp
+++ b/src/emu/video/rgbsse.cpp
@@ -10,9 +10,10 @@
***************************************************************************/
+#include "emu.h"
+
#if (!defined(MAME_DEBUG) || defined(__OPTIMIZE__)) && (defined(__SSE2__) || defined(_MSC_VER)) && defined(PTR64)
-#include "emu.h"
#include <emmintrin.h>
#include "rgbsse.h"
diff --git a/src/emu/video/rgbvmx.cpp b/src/emu/video/rgbvmx.cpp
index 5673e82a7bf..6de183b66c2 100644
--- a/src/emu/video/rgbvmx.cpp
+++ b/src/emu/video/rgbvmx.cpp
@@ -8,9 +8,10 @@
***************************************************************************/
+#include "emu.h"
+
#if defined(__ALTIVEC__)
-#include "emu.h"
#include "rgbutil.h"
/***************************************************************************
diff --git a/src/frontend/mame/luaengine.cpp b/src/frontend/mame/luaengine.cpp
index 44c4fc94b3a..0f0728902e1 100644
--- a/src/frontend/mame/luaengine.cpp
+++ b/src/frontend/mame/luaengine.cpp
@@ -925,7 +925,7 @@ void lua_engine::initialize()
* thread.result() - get thread result as string
* thread.busy - check if thread is running
* thread.yield - check if thread is yielded
-*/
+ */
emu.new_usertype<context>("thread", sol::call_constructor, sol::constructors<sol::types<>>(),
"start", [](context &ctx, const char *scr) {
@@ -981,6 +981,15 @@ void lua_engine::initialize()
"busy", sol::readonly(&context::busy),
"yield", sol::readonly(&context::yield));
+/*
+ * emu.item(item_index)
+ * item.size - size of the raw data type
+ * item.count - number of entries
+ * item:read(offset) - read entry value by index
+ * item:read_block(offset, count) - read a block of entry values as a string (byte addressing)
+ * item:write(offset, value) - write entry value by index
+ */
+
emu.new_usertype<save_item>("item", sol::call_constructor, sol::initializers([this](save_item &item, int index) {
if(!machine().save().indexed_item(index, item.base, item.size, item.count))
{
@@ -1017,7 +1026,7 @@ void lua_engine::initialize()
if(!item.base || ((offset + buff->get_len()) > (item.size * item.count)))
buff->set_len(0);
else
- memcpy(buff->get_ptr(), item.base, buff->get_len());
+ memcpy(buff->get_ptr(), (uint8_t *)item.base + offset, buff->get_len());
return buff;
},
"write", [](save_item &item, int offset, uint64_t value) {
@@ -1340,7 +1349,7 @@ void lua_engine::initialize()
* device:debug() - debug interface, cpus only
* device.spaces[] - device address spaces table
* device.state[] - device state entries table
- * device.items[] - device save state items table
+ * device.items[] - device save state items table (item name is key, item index is value)
*/
sol().registry().new_usertype<device_t>("device", "new", sol::no_constructor,
@@ -1702,20 +1711,20 @@ void lua_engine::initialize()
* render:max_update_rate() -
* render:ui_target() - target for ui drawing
* render:ui_container() - container for ui drawing
- * render.target[] - render_target table
+ * render.targets[] - render_target table
*/
sol().registry().new_usertype<render_manager>("render", "new", sol::no_constructor,
"max_update_rate", &render_manager::max_update_rate,
"ui_target", &render_manager::ui_target,
"ui_container", &render_manager::ui_container,
- "targets", [this](render_manager &r) {
+ "targets", sol::property([this](render_manager &r) {
sol::table target_table = sol().create_table();
int tc = 0;
for(render_target &curr_rt : r.targets())
target_table[tc++] = &curr_rt;
return target_table;
- });
+ }));
/* machine.screens[screen_tag]
* screen:draw_box(x1, y1, x2, y2, fillcol, linecol) - draw box from (x1, y1)-(x2, y2) colored linecol filled with fillcol
diff --git a/src/lib/formats/dsk_dsk.cpp b/src/lib/formats/dsk_dsk.cpp
index d661e1cd105..9fa334fbfd8 100644
--- a/src/lib/formats/dsk_dsk.cpp
+++ b/src/lib/formats/dsk_dsk.cpp
@@ -420,10 +420,8 @@ bool dsk_format::load(io_generic *io, uint32_t form_factor, floppy_image *image)
else
sects[j].actual_size = 128 << tr.sector_size_code;
- if (sector.fdc_status_reg2 & 0x40)
- sects[j].deleted = 1;
- if ((sector.fdc_status_reg1 & 0x20) || (sector.fdc_status_reg2 & 0x20))
- sects[j].bad_crc = 1;
+ sects[j].deleted = (sector.fdc_status_reg2 & 0x40);
+ sects[j].bad_crc = ((sector.fdc_status_reg1 & 0x20) || (sector.fdc_status_reg2 & 0x20));
if(!(sector.fdc_status_reg1 & 0x04)) {
sects[j].data = sect_data + sdatapos;
diff --git a/src/mame/audio/hng64.cpp b/src/mame/audio/hng64.cpp
index 4642dc5f8c7..5af0531c01c 100644
--- a/src/mame/audio/hng64.cpp
+++ b/src/mame/audio/hng64.cpp
@@ -201,7 +201,7 @@ WRITE16_MEMBER(hng64_state::hng64_sound_port_0008_w)
// seems to one or more of the DMARQ on the V53, writes here when it expects DMA channel 3 to transfer ~0x20 bytes just after startup
/* TODO: huh? */
- m_audiocpu->dreq3_w(data&0x1);
+ m_audiocpu->dreq_w<3>(data&0x1);
m_dsp->l7a1045_sound_w(space,8/2,data,mem_mask);
// m_audiocpu->hack_w(1);
@@ -388,23 +388,23 @@ WRITE_LINE_MEMBER(hng64_state::tcu_tm2_cb)
-MACHINE_CONFIG_START(hng64_state::hng64_audio)
- MCFG_DEVICE_ADD("audiocpu", V53A, 32000000/2) // V53A, 16? mhz!
- MCFG_DEVICE_PROGRAM_MAP(hng_sound_map)
- MCFG_DEVICE_IO_MAP(hng_sound_io)
- MCFG_V53_DMAU_OUT_HREQ_CB(WRITELINE(*this, hng64_state, dma_hreq_cb))
- MCFG_V53_DMAU_IN_MEMR_CB(READ8(*this, hng64_state, dma_memr_cb))
- MCFG_V53_DMAU_OUT_IOW_3_CB(WRITE8(*this, hng64_state,dma_iow3_cb))
+void hng64_state::hng64_audio(machine_config &config)
+{
+ V53A(config, m_audiocpu, 32000000/2); // V53A, 16? mhz!
+ m_audiocpu->set_addrmap(AS_PROGRAM, &hng64_state::hng_sound_map);
+ m_audiocpu->set_addrmap(AS_IO, &hng64_state::hng_sound_io);
+ m_audiocpu->out_hreq_cb().set(FUNC(hng64_state::dma_hreq_cb));
+ m_audiocpu->in_memr_cb().set(FUNC(hng64_state::dma_memr_cb));
+ m_audiocpu->out_iow_cb<3>().set(FUNC(hng64_state::dma_iow3_cb));
- MCFG_V53_TCU_OUT0_HANDLER(WRITELINE(*this, hng64_state, tcu_tm0_cb))
- MCFG_V53_TCU_OUT1_HANDLER(WRITELINE(*this, hng64_state, tcu_tm1_cb))
- MCFG_V53_TCU_OUT2_HANDLER(WRITELINE(*this, hng64_state, tcu_tm2_cb))
+ m_audiocpu->out_handler<0>().set(FUNC(hng64_state::tcu_tm0_cb));
+ m_audiocpu->out_handler<1>().set(FUNC(hng64_state::tcu_tm1_cb));
+ m_audiocpu->out_handler<2>().set(FUNC(hng64_state::tcu_tm2_cb));
SPEAKER(config, "lspeaker").front_left();
SPEAKER(config, "rspeaker").front_right();
- MCFG_DEVICE_ADD("l7a1045", L7A1045, 32000000/2 ) // ??
- MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
- MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
-
-MACHINE_CONFIG_END
+ L7A1045(config, m_dsp, 32000000/2); // ??
+ m_dsp->add_route(0, "lspeaker", 1.0);
+ m_dsp->add_route(1, "rspeaker", 1.0);
+}
diff --git a/src/mame/audio/leland.cpp b/src/mame/audio/leland.cpp
index 8019b0c514e..f686e7c6b5f 100644
--- a/src/mame/audio/leland.cpp
+++ b/src/mame/audio/leland.cpp
@@ -163,21 +163,21 @@ MACHINE_CONFIG_START(leland_80186_sound_device::device_add_mconfig)
MCFG_SOUND_ROUTE(0, "dac6vol", 1.0, DAC_VREF_POS_INPUT)
MCFG_SOUND_ROUTE(0, "dac9", 1.0, DAC_VREF_POS_INPUT) MCFG_SOUND_ROUTE(0, "dac9", -1.0, DAC_VREF_NEG_INPUT)
- MCFG_DEVICE_ADD("pit0", PIT8254, 0)
- MCFG_PIT8253_CLK0(4000000)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE("audiocpu", i80186_cpu_device, drq0_w))
- MCFG_PIT8253_CLK1(4000000)
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE("audiocpu", i80186_cpu_device, drq1_w))
- MCFG_PIT8253_CLK2(4000000)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, leland_80186_sound_device, pit0_2_w))
-
- MCFG_DEVICE_ADD("pit1", PIT8254, 0)
- MCFG_PIT8253_CLK0(4000000)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, leland_80186_sound_device, pit1_0_w))
- MCFG_PIT8253_CLK1(4000000)
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(*this, leland_80186_sound_device, pit1_1_w))
- MCFG_PIT8253_CLK2(4000000)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, leland_80186_sound_device, pit1_2_w))
+ PIT8254(config, m_pit[0], 0);
+ m_pit[0]->set_clk<0>(4000000);
+ m_pit[0]->out_handler<0>().set(m_audiocpu, FUNC(i80186_cpu_device::drq0_w));
+ m_pit[0]->set_clk<1>(4000000);
+ m_pit[0]->out_handler<1>().set(m_audiocpu, FUNC(i80186_cpu_device::drq1_w));
+ m_pit[0]->set_clk<2>(4000000);
+ m_pit[0]->out_handler<2>().set(FUNC(leland_80186_sound_device::pit0_2_w));
+
+ PIT8254(config, m_pit[1], 0);
+ m_pit[1]->set_clk<0>(4000000);
+ m_pit[1]->out_handler<0>().set(FUNC(leland_80186_sound_device::pit1_0_w));
+ m_pit[1]->set_clk<1>(4000000);
+ m_pit[1]->out_handler<1>().set(FUNC(leland_80186_sound_device::pit1_1_w));
+ m_pit[1]->set_clk<2>(4000000);
+ m_pit[1]->out_handler<2>().set(FUNC(leland_80186_sound_device::pit1_2_w));
MCFG_GENERIC_LATCH_16_ADD("soundlatch")
MACHINE_CONFIG_END
@@ -215,26 +215,26 @@ MACHINE_CONFIG_START(redline_80186_sound_device::device_add_mconfig)
MCFG_SOUND_ROUTE(0, "dac7vol", 1.0, DAC_VREF_POS_INPUT)
MCFG_SOUND_ROUTE(0, "dac8vol", 1.0, DAC_VREF_POS_INPUT)
- MCFG_DEVICE_ADD("pit0", PIT8254, 0)
- MCFG_PIT8253_CLK0(7000000)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE("audiocpu", i80186_cpu_device, drq0_w))
- MCFG_PIT8253_CLK1(7000000)
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE("audiocpu", i80186_cpu_device, drq1_w))
- MCFG_PIT8253_CLK2(7000000)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, leland_80186_sound_device, pit0_2_w))
-
- MCFG_DEVICE_ADD("pit1", PIT8254, 0)
- MCFG_PIT8253_CLK0(7000000)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, leland_80186_sound_device, pit1_0_w))
- MCFG_PIT8253_CLK1(7000000)
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(*this, leland_80186_sound_device, pit1_1_w))
- MCFG_PIT8253_CLK2(7000000)
-
- MCFG_DEVICE_ADD("pit2", PIT8254, 0)
- MCFG_PIT8253_CLK0(7000000)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, leland_80186_sound_device, pit1_2_w))
- MCFG_PIT8253_CLK1(7000000)
- MCFG_PIT8253_CLK2(7000000)
+ PIT8254(config, m_pit[0], 0);
+ m_pit[0]->set_clk<0>(7000000);
+ m_pit[0]->out_handler<0>().set(m_audiocpu, FUNC(i80186_cpu_device::drq0_w));
+ m_pit[0]->set_clk<1>(7000000);
+ m_pit[0]->out_handler<1>().set(m_audiocpu, FUNC(i80186_cpu_device::drq1_w));
+ m_pit[0]->set_clk<2>(7000000);
+ m_pit[0]->out_handler<2>().set(FUNC(leland_80186_sound_device::pit0_2_w));
+
+ PIT8254(config, m_pit[1], 0);
+ m_pit[1]->set_clk<0>(7000000);
+ m_pit[1]->out_handler<0>().set(FUNC(leland_80186_sound_device::pit1_0_w));
+ m_pit[1]->set_clk<1>(7000000);
+ m_pit[1]->out_handler<1>().set(FUNC(leland_80186_sound_device::pit1_1_w));
+ m_pit[1]->set_clk<2>(7000000);
+
+ PIT8254(config, m_pit[2], 0);
+ m_pit[2]->set_clk<0>(7000000);
+ m_pit[2]->out_handler<0>().set(FUNC(leland_80186_sound_device::pit1_2_w));
+ m_pit[2]->set_clk<1>(7000000);
+ m_pit[2]->set_clk<2>(7000000);
MCFG_GENERIC_LATCH_16_ADD("soundlatch")
MACHINE_CONFIG_END
@@ -263,13 +263,13 @@ MACHINE_CONFIG_START(ataxx_80186_sound_device::device_add_mconfig)
MCFG_SOUND_ROUTE(0, "dac4vol", 1.0, DAC_VREF_POS_INPUT)
MCFG_SOUND_ROUTE(0, "dac9", 1.0, DAC_VREF_POS_INPUT) MCFG_SOUND_ROUTE(0, "dac9", -1.0, DAC_VREF_NEG_INPUT)
- MCFG_DEVICE_ADD("pit0", PIT8254, 0)
- MCFG_PIT8253_CLK0(4000000)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE("audiocpu", i80186_cpu_device, drq0_w))
- MCFG_PIT8253_CLK1(4000000)
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE("audiocpu", i80186_cpu_device, drq1_w))
- MCFG_PIT8253_CLK2(4000000)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, leland_80186_sound_device, pit0_2_w))
+ PIT8254(config, m_pit[0], 0);
+ m_pit[0]->set_clk<0>(4000000);
+ m_pit[0]->out_handler<0>().set(m_audiocpu, FUNC(i80186_cpu_device::drq0_w));
+ m_pit[0]->set_clk<1>(4000000);
+ m_pit[0]->out_handler<1>().set(m_audiocpu, FUNC(i80186_cpu_device::drq1_w));
+ m_pit[0]->set_clk<2>(4000000);
+ m_pit[0]->out_handler<2>().set(FUNC(leland_80186_sound_device::pit0_2_w));
MCFG_GENERIC_LATCH_16_ADD("soundlatch")
MACHINE_CONFIG_END
@@ -304,13 +304,13 @@ MACHINE_CONFIG_START(wsf_80186_sound_device::device_add_mconfig)
MCFG_SOUND_ROUTE(0, "speaker", 0.40)
MCFG_SOUND_ROUTE(1, "speaker", 0.40)
- MCFG_DEVICE_ADD("pit0", PIT8254, 0)
- MCFG_PIT8253_CLK0(4000000)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE("audiocpu", i80186_cpu_device, drq0_w))
- MCFG_PIT8253_CLK1(4000000)
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE("audiocpu", i80186_cpu_device, drq1_w))
- MCFG_PIT8253_CLK2(4000000)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, leland_80186_sound_device, pit0_2_w))
+ PIT8254(config, m_pit[0], 0);
+ m_pit[0]->set_clk<0>(4000000);
+ m_pit[0]->out_handler<0>().set(m_audiocpu, FUNC(i80186_cpu_device::drq0_w));
+ m_pit[0]->set_clk<1>(4000000);
+ m_pit[0]->out_handler<1>().set(m_audiocpu, FUNC(i80186_cpu_device::drq1_w));
+ m_pit[0]->set_clk<2>(4000000);
+ m_pit[0]->out_handler<2>().set(FUNC(leland_80186_sound_device::pit0_2_w));
MCFG_GENERIC_LATCH_16_ADD("soundlatch")
MACHINE_CONFIG_END
@@ -398,8 +398,8 @@ leland_80186_sound_device::leland_80186_sound_device(const machine_config &mconf
, m_dac9(*this, "dac9")
, m_dacvol(*this, "dac%uvol", 1U)
, m_pit(*this, "pit%u", 0U)
- , m_ymsnd(*this, "ymsnd")
, m_audiocpu(*this, "audiocpu")
+ , m_ymsnd(*this, "ymsnd")
, m_master(*this, ":master")
{
}
diff --git a/src/mame/audio/leland.h b/src/mame/audio/leland.h
index f532521a03e..bf660b6eeed 100644
--- a/src/mame/audio/leland.h
+++ b/src/mame/audio/leland.h
@@ -60,6 +60,8 @@ protected:
optional_device_array<dac_byte_interface, 8> m_dac;
optional_device<dac_word_interface> m_dac9;
optional_device_array<dac_byte_interface, 8> m_dacvol;
+ optional_device_array<pit8254_device, 3> m_pit;
+ optional_device<i80186_cpu_device> m_audiocpu;
void ataxx_80186_map_io(address_map &map);
void leland_80186_map_io(address_map &map);
@@ -81,9 +83,7 @@ private:
uint8_t m_ext_active;
uint8_t* m_ext_base;
- optional_device_array<pit8254_device, 3> m_pit;
optional_device<ym2151_device> m_ymsnd;
- optional_device<i80186_cpu_device> m_audiocpu;
required_device<cpu_device> m_master;
};
diff --git a/src/mame/drivers/a7150.cpp b/src/mame/drivers/a7150.cpp
index dc139a21d32..8deb48f8adb 100644
--- a/src/mame/drivers/a7150.cpp
+++ b/src/mame/drivers/a7150.cpp
@@ -477,11 +477,11 @@ MACHINE_CONFIG_START(a7150_state::a7150)
i8087_device &i8087(I8087(config, "i8087", XTAL(9'832'000)/2));
i8087.set_addrmap(AS_PROGRAM, &a7150_state::a7150_mem);
i8087.set_data_width(16);
- i8087.irq().set("pic8259", FUNC(pic8259_device::ir0_w));
+ i8087.irq().set(m_pic8259, FUNC(pic8259_device::ir0_w));
i8087.busy().set_inputline("maincpu", INPUT_LINE_TEST);
- MCFG_DEVICE_ADD("pic8259", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE("maincpu", 0))
+ PIC8259(config, m_pic8259, 0);
+ m_pic8259->out_int_callback().set_inputline(m_maincpu, 0);
// IFSP port on processor card
i8255_device &ppi(I8255(config, "ppi8255"));
diff --git a/src/mame/drivers/akaiax80.cpp b/src/mame/drivers/akaiax80.cpp
index b3d2fdcbe95..7d26b54139c 100644
--- a/src/mame/drivers/akaiax80.cpp
+++ b/src/mame/drivers/akaiax80.cpp
@@ -92,20 +92,21 @@ void ax80_state::ax80_map(address_map &map)
map(0xc000, 0xc7ff).mirror(0x3800).ram();
}
-MACHINE_CONFIG_START(ax80_state::ax80)
- MCFG_DEVICE_ADD("maincpu", UPD7810, XTAL(12'000'000))
- MCFG_DEVICE_PROGRAM_MAP(ax80_map)
- //MCFG_DEVICE_IO_MAP(ax80_io)
+void ax80_state::ax80(machine_config &config)
+{
+ UPD7810(config, m_maincpu, XTAL(12'000'000));
+ m_maincpu->set_addrmap(AS_PROGRAM, &ax80_state::ax80_map);
+ //m_maincpu->set_addrmap(AS_IO, &ax80_state::ax80_io);
- MCFG_DEVICE_ADD(PIT0_TAG, PIT8253, 0)
- MCFG_DEVICE_ADD(PIT1_TAG, PIT8253, 0)
- MCFG_DEVICE_ADD(PIT2_TAG, PIT8253, 0)
- MCFG_DEVICE_ADD(PIT3_TAG, PIT8253, 0)
- MCFG_DEVICE_ADD(PIT4_TAG, PIT8253, 0)
- MCFG_DEVICE_ADD(PIT5_TAG, PIT8253, 0)
+ PIT8253(config, PIT0_TAG, 0);
+ PIT8253(config, PIT1_TAG, 0);
+ PIT8253(config, PIT2_TAG, 0);
+ PIT8253(config, PIT3_TAG, 0);
+ PIT8253(config, PIT4_TAG, 0);
+ PIT8253(config, PIT5_TAG, 0);
- MCFG_DEVICE_ADD(PPI0_TAG, I8255A, 0)
- MCFG_DEVICE_ADD(PPI1_TAG, I8255A, 0)
+ I8255A(config, PPI0_TAG);
+ I8255A(config, PPI1_TAG);
I8279(config, "kdc", 6554800 / 8); // Keyboard/Display Controller
//kdc.out_irq_calback().set_inputline("maincpu", UPD7810_INTF1); // irq
@@ -114,7 +115,7 @@ MACHINE_CONFIG_START(ax80_state::ax80)
//kdc.in_rl_callback().set(FUNC(ax80_state::kbd_r)) // kbd RL lines
//kdc.in_shift_callback().set_constant(1); // not connected
//kdc.in_ctrl_callback().set_constant(1); // not connected
-MACHINE_CONFIG_END
+}
static INPUT_PORTS_START( ax80 )
INPUT_PORTS_END
diff --git a/src/mame/drivers/alg.cpp b/src/mame/drivers/alg.cpp
index 3f9a997c96c..96578f72bfa 100644
--- a/src/mame/drivers/alg.cpp
+++ b/src/mame/drivers/alg.cpp
@@ -877,5 +877,5 @@ GAME( 199?, aplatoon, alg_bios, alg_r2, alg, alg_state, init_aplatoon,
/* Web Picmatic games PAL tv standard, own rom board */
GAME( 1994, zortonbr, alg_bios, picmatic, alg, alg_state, init_pal, ROT0, "Web Picmatic", "Zorton Brothers v1.01 (Los Justicieros)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND | MACHINE_IMPERFECT_GRAPHICS )
-GAME( 1993, zortonbr_100, alg_bios, picmatic, alg, alg_state, init_pal, ROT0, "Web Picmatic", "Zorton Brothers v1.00 (Los Justicieros)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND | MACHINE_IMPERFECT_GRAPHICS )
+GAME( 1993, zortonbr_100, zortonbr, picmatic, alg, alg_state, init_pal, ROT0, "Web Picmatic", "Zorton Brothers v1.00 (Los Justicieros)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND | MACHINE_IMPERFECT_GRAPHICS )
GAME( 1994, marvice, alg_bios, picmatic, alg, alg_state, init_pal, ROT0, "Web Picmatic", "Marbella Vice", MACHINE_NOT_WORKING | MACHINE_NO_SOUND | MACHINE_IMPERFECT_GRAPHICS )
diff --git a/src/mame/drivers/alphatpx.cpp b/src/mame/drivers/alphatpx.cpp
index 6376b1b318a..34bbcde86de 100644
--- a/src/mame/drivers/alphatpx.cpp
+++ b/src/mame/drivers/alphatpx.cpp
@@ -1325,24 +1325,25 @@ MACHINE_CONFIG_START(alphatp_34_state::alphatp3)
MCFG_FLOPPY_DRIVE_ADD("fdc:1", alphatp3_floppies, "525qd", floppy_image_device::default_floppy_formats)
MACHINE_CONFIG_END
-MACHINE_CONFIG_START(alphatp_34_state::alphatp30)
+void alphatp_34_state::alphatp30(machine_config &config)
+{
alphatp3(config);
- MCFG_DEVICE_ADD("i8088", I8088, 6000000) // unknown clock
- MCFG_DEVICE_PROGRAM_MAP(alphatp30_8088_map)
- MCFG_DEVICE_IO_MAP(alphatp30_8088_io)
- MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE("pic8259", pic8259_device, inta_cb)
- MCFG_DEVICE_DISABLE()
-
- MCFG_DEVICE_ADD("pic8259", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE("i8088", 0))
- MCFG_PIC8259_IN_SP_CB(CONSTANT(0))
-
- MCFG_DEVICE_ADD("pit", PIT8253, 0)
- MCFG_PIT8253_CLK0(100000) // 15Mhz osc with unknown divisor
- MCFG_PIT8253_CLK1(100000)
- MCFG_PIT8253_CLK2(100000)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE("pic8259", pic8259_device, ir0_w))
-MACHINE_CONFIG_END
+ I8088(config, m_i8088, 6000000); // unknown clock
+ m_i8088->set_addrmap(AS_PROGRAM, &alphatp_34_state::alphatp30_8088_map);
+ m_i8088->set_addrmap(AS_IO, &alphatp_34_state::alphatp30_8088_io);
+ m_i8088->set_irq_acknowledge_callback("pic8259", FUNC(pic8259_device::inta_cb));
+ m_i8088->set_disable();
+
+ PIC8259(config, m_pic, 0);
+ m_pic->out_int_callback().set_inputline(m_i8088, 0);
+ m_pic->in_sp_callback().set_constant(0);
+
+ pit8253_device &pit(PIT8253(config, "pit", 0));
+ pit.set_clk<0>(100000); // 15Mhz osc with unknown divisor
+ pit.set_clk<1>(100000);
+ pit.set_clk<2>(100000);
+ pit.out_handler<0>().set(m_pic, FUNC(pic8259_device::ir0_w));
+}
//**************************************************************************
// ROM DEFINITIONS
diff --git a/src/mame/drivers/altos486.cpp b/src/mame/drivers/altos486.cpp
index 01fbd01ebb0..5764c531423 100644
--- a/src/mame/drivers/altos486.cpp
+++ b/src/mame/drivers/altos486.cpp
@@ -131,15 +131,16 @@ void altos486_state::altos486_z80_io(address_map &map)
//AM_RANGE(0x08, 0x0b) AM_DEVREADWRITE("sio2", z80sio0_device, read, write)
}
-MACHINE_CONFIG_START(altos486_state::altos486)
- MCFG_DEVICE_ADD(m_maincpu, I80186, XTAL(8'000'000))
- MCFG_DEVICE_PROGRAM_MAP(altos486_mem)
- MCFG_DEVICE_IO_MAP(altos486_io)
- MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE("pic8259", pic8259_device, inta_cb) // yes, really
+void altos486_state::altos486(machine_config &config)
+{
+ I80186(config, m_maincpu, XTAL(8'000'000));
+ m_maincpu->set_addrmap(AS_PROGRAM, &altos486_state::altos486_mem);
+ m_maincpu->set_addrmap(AS_IO, &altos486_state::altos486_io);
+ m_maincpu->set_irq_acknowledge_callback("pic8259", FUNC(pic8259_device::inta_cb)); // yes, really
- MCFG_DEVICE_ADD("iocpu", Z80, XTAL(8'000'000) / 2)
- MCFG_DEVICE_PROGRAM_MAP(altos486_z80_mem)
- MCFG_DEVICE_IO_MAP(altos486_z80_io)
+ z80_device &iocpu(Z80(config, "iocpu", XTAL(8'000'000) / 2));
+ iocpu.set_addrmap(AS_PROGRAM, &altos486_state::altos486_z80_mem);
+ iocpu.set_addrmap(AS_IO, &altos486_state::altos486_z80_io);
pic8259_device &pic8259(PIC8259(config, "pic8259", 0));
pic8259.out_int_callback().set(m_maincpu, FUNC(i80186_cpu_device::int0_w));
@@ -149,8 +150,7 @@ MACHINE_CONFIG_START(altos486_state::altos486)
I8255(config, "ppi8255");
UPD765A(config, "fdc", false, false);
- MCFG_FLOPPY_DRIVE_ADD("fdc:0", altos486_floppies, "525qd", altos486_state::floppy_formats)
- MCFG_SLOT_FIXED(true)
+ FLOPPY_CONNECTOR(config, "fdc:0", altos486_floppies, "525qd", altos486_state::floppy_formats).set_fixed(true);
z80sio0_device& sio0(Z80SIO0(config, "sio0", 4000000));
sio0.out_txda_callback().set("rs232a", FUNC(rs232_port_device::write_txd));
@@ -213,15 +213,16 @@ MACHINE_CONFIG_START(altos486_state::altos486)
rs422_wn.dcd_handler().set("i8274", FUNC(z80dart_device::dcda_w));
rs422_wn.cts_handler().set("i8274", FUNC(z80dart_device::ctsa_w));
- MCFG_DEVICE_ADD("pit0", PIT8253, 0)
- MCFG_PIT8253_CLK0(XTAL(22'118'400)/18)
- MCFG_PIT8253_CLK1(XTAL(22'118'400)/144)
- MCFG_PIT8253_CLK2(XTAL(22'118'400)/18)
- MCFG_DEVICE_ADD("pit1", PIT8253, 0)
- MCFG_PIT8253_CLK0(XTAL(22'118'400)/18)
- MCFG_PIT8253_CLK1(XTAL(22'118'400)/144)
- MCFG_PIT8253_CLK2(XTAL(22'118'400)/18)
-MACHINE_CONFIG_END
+ pit8253_device &pit0(PIT8253(config, "pit0", 0));
+ pit0.set_clk<0>(XTAL(22'118'400)/18);
+ pit0.set_clk<1>(XTAL(22'118'400)/144);
+ pit0.set_clk<2>(XTAL(22'118'400)/18);
+
+ pit8253_device &pit1(PIT8253(config, "pit1", 0));
+ pit1.set_clk<0>(XTAL(22'118'400)/18);
+ pit1.set_clk<1>(XTAL(22'118'400)/144);
+ pit1.set_clk<2>(XTAL(22'118'400)/18);
+}
ROM_START( altos486 )
diff --git a/src/mame/drivers/altos8600.cpp b/src/mame/drivers/altos8600.cpp
index 2aab3feb743..c72cb58c2de 100644
--- a/src/mame/drivers/altos8600.cpp
+++ b/src/mame/drivers/altos8600.cpp
@@ -22,9 +22,7 @@ public:
driver_device(mconfig, type, tag),
m_maincpu(*this, "maincpu"),
m_dmac(*this, "dmac"),
- m_pic1(*this, "pic8259_1"),
- m_pic2(*this, "pic8259_2"),
- m_pic3(*this, "pic8259_3"),
+ m_pic(*this, "pic8259%u", 1U),
m_uart8274(*this, "uart8274"),
m_fdc(*this, "fd1797"),
m_ram(*this, RAM_TAG),
@@ -91,9 +89,7 @@ private:
void format_sector();
required_device<i8086_cpu_device> m_maincpu;
required_device<i8089_device> m_dmac;
- required_device<pic8259_device> m_pic1;
- required_device<pic8259_device> m_pic2;
- required_device<pic8259_device> m_pic3;
+ required_device_array<pic8259_device, 3> m_pic;
required_device<i8274_new_device> m_uart8274;
required_device<fd1797_device> m_fdc;
required_device<ram_device> m_ram;
@@ -205,7 +201,7 @@ u8 altos8600_state::read_sector()
if(secoff >= 511)
{
m_dmac->drq1_w(CLEAR_LINE);
- m_pic2->ir0_w(ASSERT_LINE);
+ m_pic[1]->ir0_w(ASSERT_LINE);
m_stat &= ~1;
m_stat |= 2;
}
@@ -225,7 +221,7 @@ bool altos8600_state::write_sector(u8 data)
m_stat |= 2;
hard_disk_write(m_hdd->get_hard_disk_file(), m_lba, m_sector);
m_dmac->drq1_w(CLEAR_LINE);
- m_pic2->ir0_w(ASSERT_LINE);
+ m_pic[1]->ir0_w(ASSERT_LINE);
return true;
}
return false;
@@ -240,7 +236,7 @@ READ8_MEMBER(altos8600_state::hd_r)
return read_sector();
break;
case 3:
- m_pic2->ir0_w(CLEAR_LINE);
+ m_pic[1]->ir0_w(CLEAR_LINE);
return m_stat;
}
return 0;
@@ -332,7 +328,7 @@ WRITE8_MEMBER(altos8600_state::hd_w)
m_dmac->drq1_w(ASSERT_LINE);
break;
}
- m_pic2->ir0_w(ASSERT_LINE);
+ m_pic[1]->ir0_w(ASSERT_LINE);
break;
}
}
@@ -360,13 +356,13 @@ WRITE_LINE_MEMBER(altos8600_state::sintr1_w)
if(state)
{
m_dmac->drq1_w(CLEAR_LINE);
- m_pic2->ir0_w(ASSERT_LINE);
- m_pic2->ir3_w(ASSERT_LINE);
+ m_pic[1]->ir0_w(ASSERT_LINE);
+ m_pic[1]->ir3_w(ASSERT_LINE);
m_stat &= ~1;
m_stat |= 2;
}
else
- m_pic2->ir3_w(CLEAR_LINE);
+ m_pic[1]->ir3_w(CLEAR_LINE);
}
READ16_MEMBER(altos8600_state::fault_r)
@@ -480,7 +476,7 @@ WRITE8_MEMBER(altos8600_state::romport_w)
WRITE8_MEMBER(altos8600_state::clrsys_w)
{
- m_pic1->ir0_w(CLEAR_LINE);
+ m_pic[0]->ir0_w(CLEAR_LINE);
}
WRITE8_MEMBER(altos8600_state::ics_attn_w)
@@ -502,9 +498,9 @@ WRITE16_MEMBER(altos8600_state::mode_w)
READ8_MEMBER(altos8600_state::get_slave_ack)
{
if(offset == 2)
- return m_pic2->acknowledge();
+ return m_pic[1]->acknowledge();
else if(offset == 3)
- return m_pic3->acknowledge();
+ return m_pic[2]->acknowledge();
return 0x00;
}
@@ -605,7 +601,7 @@ READ16_MEMBER(altos8600_state::cpuio_r)
{
if(m_user && !machine().side_effects_disabled())
{
- m_pic1->ir0_w(ASSERT_LINE);
+ m_pic[0]->ir0_w(ASSERT_LINE);
return 0;
}
return m_dmac->space(AS_IO).read_word_unaligned(offset << 1, mem_mask);
@@ -615,7 +611,7 @@ WRITE16_MEMBER(altos8600_state::cpuio_w)
{
if(m_user && !machine().side_effects_disabled())
{
- m_pic1->ir0_w(ASSERT_LINE);
+ m_pic[0]->ir0_w(ASSERT_LINE);
return;
}
m_dmac->space(AS_IO).write_word_unaligned(offset << 1, data, mem_mask);
@@ -661,7 +657,7 @@ IRQ_CALLBACK_MEMBER(altos8600_state::inta)
{
m_user = false;
m_mode &= ~1;
- return m_pic1->acknowledge();
+ return m_pic[0]->acknowledge();
}
void altos8600_state::cpu_mem(address_map &map)
@@ -709,10 +705,10 @@ void altos8600_state::dmac_io(address_map &map)
map(0x0048, 0x004f).rw(m_uart8274, FUNC(i8274_new_device::cd_ba_r), FUNC(i8274_new_device::cd_ba_w)).umask16(0x00ff);
map(0x0048, 0x004f).rw("pit", FUNC(pit8253_device::read), FUNC(pit8253_device::write)).umask16(0xff00);
map(0x0050, 0x0057).rw(FUNC(altos8600_state::romport_r), FUNC(altos8600_state::romport_w));
- map(0x0058, 0x005f).rw(m_pic1, FUNC(pic8259_device::read), FUNC(pic8259_device::write)).umask16(0x00ff);
+ map(0x0058, 0x005f).rw(m_pic[0], FUNC(pic8259_device::read), FUNC(pic8259_device::write)).umask16(0x00ff);
map(0x0058, 0x005f).w(FUNC(altos8600_state::clrsys_w)).umask16(0xff00);
- map(0x0060, 0x0067).rw(m_pic2, FUNC(pic8259_device::read), FUNC(pic8259_device::write)).umask16(0x00ff);
- map(0x0068, 0x006f).rw(m_pic3, FUNC(pic8259_device::read), FUNC(pic8259_device::write)).umask16(0x00ff);
+ map(0x0060, 0x0067).rw(m_pic[1], FUNC(pic8259_device::read), FUNC(pic8259_device::write)).umask16(0x00ff);
+ map(0x0068, 0x006f).rw(m_pic[2], FUNC(pic8259_device::read), FUNC(pic8259_device::write)).umask16(0x00ff);
map(0x0070, 0x0077).noprw();
map(0x0078, 0x0079).w(FUNC(altos8600_state::ics_attn_w));
map(0x0200, 0x03ff).rw(FUNC(altos8600_state::mmuflags_r), FUNC(altos8600_state::mmuflags_w));
@@ -740,20 +736,20 @@ MACHINE_CONFIG_START(altos8600_state::altos8600)
MCFG_DEVICE_IO_MAP(dmac_io)
MCFG_I8089_DATA_WIDTH(16)
MCFG_I8089_SINTR1(WRITELINE(*this, altos8600_state, sintr1_w))
- MCFG_I8089_SINTR2(WRITELINE(m_pic2, pic8259_device, ir4_w))
+ MCFG_I8089_SINTR2(WRITELINE(m_pic[1], pic8259_device, ir4_w))
- PIC8259(config, m_pic1, 0);
- m_pic1->out_int_callback().set_inputline(m_maincpu, 0);
- m_pic1->in_sp_callback().set_constant(1);
- m_pic1->read_slave_ack_callback().set(FUNC(altos8600_state::get_slave_ack));
+ PIC8259(config, m_pic[0], 0);
+ m_pic[0]->out_int_callback().set_inputline(m_maincpu, 0);
+ m_pic[0]->in_sp_callback().set_constant(1);
+ m_pic[0]->read_slave_ack_callback().set(FUNC(altos8600_state::get_slave_ack));
- PIC8259(config, m_pic2, 0);
- m_pic2->out_int_callback().set(m_pic1, FUNC(pic8259_device::ir2_w));
- m_pic2->in_sp_callback().set_constant(0);
+ PIC8259(config, m_pic[1], 0);
+ m_pic[1]->out_int_callback().set(m_pic[0], FUNC(pic8259_device::ir2_w));
+ m_pic[1]->in_sp_callback().set_constant(0);
- PIC8259(config, m_pic3, 0);
- m_pic3->out_int_callback().set(m_pic1, FUNC(pic8259_device::ir3_w));
- m_pic3->in_sp_callback().set_constant(0);
+ PIC8259(config, m_pic[2], 0);
+ m_pic[2]->out_int_callback().set(m_pic[0], FUNC(pic8259_device::ir3_w));
+ m_pic[2]->in_sp_callback().set_constant(0);
RAM(config, RAM_TAG).set_default_size("1M");//.set_extra_options("512K");
@@ -764,7 +760,7 @@ MACHINE_CONFIG_START(altos8600_state::altos8600)
m_uart8274->out_txdb_callback().set("rs232b", FUNC(rs232_port_device::write_txd));
m_uart8274->out_dtrb_callback().set("rs232b", FUNC(rs232_port_device::write_dtr));
m_uart8274->out_rtsb_callback().set("rs232b", FUNC(rs232_port_device::write_rts));
- m_uart8274->out_int_callback().set("pic8259_1", FUNC(pic8259_device::ir7_w));
+ m_uart8274->out_int_callback().set(m_pic[0], FUNC(pic8259_device::ir7_w));
rs232_port_device &rs232a(RS232_PORT(config, "rs232a", default_rs232_devices, nullptr));
rs232a.rxd_handler().set(m_uart8274, FUNC(i8274_new_device::rxa_w));
@@ -785,10 +781,10 @@ MACHINE_CONFIG_START(altos8600_state::altos8600)
pit.set_clk<1>(1228800);
pit.out_handler<1>().set(m_uart8274, FUNC(i8274_new_device::rxtxcb_w));
pit.set_clk<2>(1228800);
- pit.out_handler<1>().set(m_pic1, FUNC(pic8259_device::ir1_w));
+ pit.out_handler<1>().set(m_pic[0], FUNC(pic8259_device::ir1_w));
FD1797(config, m_fdc, 2000000);
- m_fdc->intrq_wr_callback().set(m_pic2, FUNC(pic8259_device::ir1_w));
+ m_fdc->intrq_wr_callback().set(m_pic[1], FUNC(pic8259_device::ir1_w));
m_fdc->drq_wr_callback().set(FUNC(altos8600_state::fddrq_w));
MCFG_FLOPPY_DRIVE_ADD("fd1797:0", altos8600_floppies, "8dd", floppy_image_device::default_floppy_formats)
MCFG_FLOPPY_DRIVE_ADD("fd1797:1", altos8600_floppies, "8dd", floppy_image_device::default_floppy_formats)
@@ -797,8 +793,8 @@ MACHINE_CONFIG_START(altos8600_state::altos8600)
ACS8600_ICS(config, m_ics, 0);
m_ics->set_host_space(m_dmac, AS_PROGRAM); // TODO: fixme
- m_ics->irq1_callback().set(m_pic1, FUNC(pic8259_device::ir5_w));
- m_ics->irq2_callback().set(m_pic1, FUNC(pic8259_device::ir6_w));
+ m_ics->irq1_callback().set(m_pic[0], FUNC(pic8259_device::ir5_w));
+ m_ics->irq2_callback().set(m_pic[0], FUNC(pic8259_device::ir6_w));
MCFG_HARDDISK_ADD("hdd")
MACHINE_CONFIG_END
diff --git a/src/mame/drivers/amusco.cpp b/src/mame/drivers/amusco.cpp
index ca7a0a4b692..34a529fca09 100644
--- a/src/mame/drivers/amusco.cpp
+++ b/src/mame/drivers/amusco.cpp
@@ -534,19 +534,19 @@ PALETTE_INIT_MEMBER(amusco_state,amusco)
MACHINE_CONFIG_START(amusco_state::amusco)
/* basic machine hardware */
- MCFG_DEVICE_ADD("maincpu", I8088, CPU_CLOCK) // 5 MHz ?
- MCFG_DEVICE_PROGRAM_MAP(amusco_mem_map)
- MCFG_DEVICE_IO_MAP(amusco_io_map)
- MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE("pic8259", pic8259_device, inta_cb)
+ I8088(config, m_maincpu, CPU_CLOCK); // 5 MHz ?
+ m_maincpu->set_addrmap(AS_PROGRAM, &amusco_state::amusco_mem_map);
+ m_maincpu->set_addrmap(AS_IO, &amusco_state::amusco_io_map);
+ m_maincpu->set_irq_acknowledge_callback("pic8259", FUNC(pic8259_device::inta_cb));
- MCFG_DEVICE_ADD("pic8259", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE("maincpu", 0))
+ PIC8259(config, m_pic, 0);
+ m_pic->out_int_callback().set_inputline(m_maincpu, 0);
- MCFG_DEVICE_ADD("pit8253", PIT8253, 0)
- MCFG_PIT8253_CLK0(PIT_CLOCK0)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE("pic8259", pic8259_device, ir0_w))
- MCFG_PIT8253_CLK1(PIT_CLOCK1)
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE("pic8259", pic8259_device, ir2_w))
+ PIT8253(config, m_pit, 0);
+ m_pit->set_clk<0>(PIT_CLOCK0);
+ m_pit->out_handler<0>().set(m_pic, FUNC(pic8259_device::ir0_w));
+ m_pit->set_clk<1>(PIT_CLOCK1);
+ m_pit->out_handler<1>().set(m_pic, FUNC(pic8259_device::ir2_w));
i8255_device &ppi_outputs(I8255(config, "ppi_outputs"));
ppi_outputs.out_pa_callback().set(FUNC(amusco_state::output_a_w));
@@ -563,12 +563,12 @@ MACHINE_CONFIG_START(amusco_state::amusco)
i8155a.in_pb_callback().set(FUNC(amusco_state::lpt_status_r));
// Port C uses ALT 3 mode, which MAME does not currently emulate
- MCFG_DEVICE_ADD("rtc", MSM5832, 32.768_kHz_XTAL)
+ MSM5832(config, m_rtc, 32.768_kHz_XTAL);
i8155_device &i8155b(I8155(config, "rtc_interface", 0));
i8155b.out_pa_callback().set(FUNC(amusco_state::rtc_control_w));
- i8155b.in_pc_callback().set("rtc", FUNC(msm5832_device::data_r));
- i8155b.out_pc_callback().set("rtc", FUNC(msm5832_device::data_w));
+ i8155b.in_pc_callback().set(m_rtc, FUNC(msm5832_device::data_r));
+ i8155b.out_pc_callback().set(m_rtc, FUNC(msm5832_device::data_w));
MCFG_TICKET_DISPENSER_ADD("hopper", attotime::from_msec(30), TICKET_MOTOR_ACTIVE_LOW, TICKET_STATUS_ACTIVE_HIGH)
@@ -589,7 +589,7 @@ MACHINE_CONFIG_START(amusco_state::amusco)
MCFG_MC6845_SHOW_BORDER_AREA(false)
MCFG_MC6845_CHAR_WIDTH(8)
MCFG_MC6845_ADDR_CHANGED_CB(amusco_state, crtc_addr)
- MCFG_MC6845_OUT_DE_CB(WRITELINE("pic8259", pic8259_device, ir1_w)) // IRQ1 sets 0x918 bit 3
+ MCFG_MC6845_OUT_DE_CB(WRITELINE(m_pic, pic8259_device, ir1_w)) // IRQ1 sets 0x918 bit 3
MCFG_MC6845_UPDATE_ROW_CB(amusco_state, update_row)
/* sound hardware */
diff --git a/src/mame/drivers/apogee.cpp b/src/mame/drivers/apogee.cpp
index 5ee10d36367..02fad5ec953 100644
--- a/src/mame/drivers/apogee.cpp
+++ b/src/mame/drivers/apogee.cpp
@@ -220,13 +220,13 @@ MACHINE_CONFIG_START(apogee_state::apogee)
MCFG_DEVICE_ADD("maincpu", I8080, XTAL(16'000'000) / 9)
MCFG_DEVICE_PROGRAM_MAP(apogee_mem)
- MCFG_DEVICE_ADD("pit8253", PIT8253, 0)
- MCFG_PIT8253_CLK0(XTAL(16'000'000)/9)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, apogee_state,pit8253_out0_changed))
- MCFG_PIT8253_CLK1(XTAL(16'000'000)/9)
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(*this, apogee_state,pit8253_out1_changed))
- MCFG_PIT8253_CLK2(XTAL(16'000'000)/9)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, apogee_state,pit8253_out2_changed))
+ pit8253_device &pit8253(PIT8253(config, "pit8253", 0));
+ pit8253.set_clk<0>(XTAL(16'000'000)/9);
+ pit8253.out_handler<0>().set(FUNC(apogee_state::pit8253_out0_changed));
+ pit8253.set_clk<1>(XTAL(16'000'000)/9);
+ pit8253.out_handler<1>().set(FUNC(apogee_state::pit8253_out1_changed));
+ pit8253.set_clk<2>(XTAL(16'000'000)/9);
+ pit8253.out_handler<2>().set(FUNC(apogee_state::pit8253_out2_changed));
I8255(config, m_ppi8255_1);
m_ppi8255_1->out_pa_callback().set(FUNC(radio86_state::radio86_8255_porta_w2));
diff --git a/src/mame/drivers/apricot.cpp b/src/mame/drivers/apricot.cpp
index 4578a5f35cc..32627f0b1dc 100644
--- a/src/mame/drivers/apricot.cpp
+++ b/src/mame/drivers/apricot.cpp
@@ -370,8 +370,8 @@ MACHINE_CONFIG_START(apricot_state::apricot)
MCFG_DEVICE_PROGRAM_MAP(apricot_mem)
MCFG_DEVICE_IO_MAP(apricot_io)
MCFG_I8089_DATA_WIDTH(16)
- MCFG_I8089_SINTR1(WRITELINE("ic31", pic8259_device, ir0_w))
- MCFG_I8089_SINTR2(WRITELINE("ic31", pic8259_device, ir1_w))
+ MCFG_I8089_SINTR1(WRITELINE(m_pic, pic8259_device, ir0_w))
+ MCFG_I8089_SINTR2(WRITELINE(m_pic, pic8259_device, ir1_w))
// ram
RAM(config, RAM_TAG).set_default_size("256K");
@@ -409,7 +409,7 @@ MACHINE_CONFIG_START(apricot_state::apricot)
PIT8253(config, m_pit, 0);
m_pit->set_clk<0>(4_MHz_XTAL / 16);
- m_pit->out_handler<0>().set("ic31", FUNC(pic8259_device::ir6_w));
+ m_pit->out_handler<0>().set(m_pic, FUNC(pic8259_device::ir6_w));
m_pit->set_clk<1>(4_MHz_XTAL / 2);
m_pit->out_handler<1>().set("ic14", FUNC(ttl153_device::i0a_w));
m_pit->set_clk<2>(4_MHz_XTAL / 2);
diff --git a/src/mame/drivers/apricotp.cpp b/src/mame/drivers/apricotp.cpp
index 99f76374459..d61eeac5b0b 100644
--- a/src/mame/drivers/apricotp.cpp
+++ b/src/mame/drivers/apricotp.cpp
@@ -608,7 +608,7 @@ MACHINE_CONFIG_START(fp_state::fp)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 1.00)
/* Devices */
- MCFG_DEVICE_ADD(APRICOT_KEYBOARD_TAG, APRICOT_KEYBOARD, 0)
+ APRICOT_KEYBOARD(config, APRICOT_KEYBOARD_TAG, 0);
AM9517A(config, m_dmac, 250000);
m_dmac->out_eop_callback().set(m_pic, FUNC(pic8259_device::ir7_w));
diff --git a/src/mame/drivers/atvtrack.cpp b/src/mame/drivers/atvtrack.cpp
index 1111fb04371..0eac7cdbd48 100644
--- a/src/mame/drivers/atvtrack.cpp
+++ b/src/mame/drivers/atvtrack.cpp
@@ -695,7 +695,12 @@ REF 010131
*/
-ROM_START( smashdrv )
+/*
+ PRG ROM useful locations:
+ 0x64C44 Country: 0 - no information, 1 - Spain, 2 - UK (this dump), 3 - Italy, 4 - USA
+ 0x727AC 1 - enable Develop/debug option in test mode
+*/
+ROM_START( smashdrv ) // Version: 3.3, Version 3D: 1.9, Checksum: 707C
ROM_REGION64_LE( 0x0400000, "data", ROMREGION_ERASEFF)
ROM_LOAD("prg.ic23", 0x0000000, 0x0400000, CRC(5cc6d3ac) SHA1(0c8426774212d891796b59c95b8c70f64db5b67a) )
diff --git a/src/mame/drivers/b2m.cpp b/src/mame/drivers/b2m.cpp
index f3c7b2ab6a6..bc22a8bfefd 100644
--- a/src/mame/drivers/b2m.cpp
+++ b/src/mame/drivers/b2m.cpp
@@ -207,13 +207,13 @@ MACHINE_CONFIG_START(b2m_state::b2m)
MCFG_PALETTE_ADD("palette", 4)
MCFG_PALETTE_INIT_OWNER(b2m_state, b2m)
- MCFG_DEVICE_ADD("pit8253", PIT8253, 0)
- MCFG_PIT8253_CLK0(0)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE("pic8259", pic8259_device, ir1_w))
- MCFG_PIT8253_CLK1(2000000)
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(*this, b2m_state,bm2_pit_out1))
- MCFG_PIT8253_CLK2(2000000)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE("pit8253", pit8253_device, write_clk0))
+ PIT8253(config, m_pit, 0);
+ m_pit->set_clk<0>(0);
+ m_pit->out_handler<0>().set(m_pic, FUNC(pic8259_device::ir1_w));
+ m_pit->set_clk<1>(2000000);
+ m_pit->out_handler<1>().set(FUNC(b2m_state::bm2_pit_out1));
+ m_pit->set_clk<2>(2000000);
+ m_pit->out_handler<2>().set(m_pit, FUNC(pit8253_device::write_clk0));
i8255_device &ppi1(I8255(config, "ppi8255_1"));
ppi1.out_pa_callback().set(FUNC(b2m_state::b2m_8255_porta_w));
@@ -229,8 +229,8 @@ MACHINE_CONFIG_START(b2m_state::b2m)
ppi3.out_pb_callback().set(FUNC(b2m_state::b2m_romdisk_portb_w));
ppi3.out_pc_callback().set(FUNC(b2m_state::b2m_romdisk_portc_w));
- MCFG_DEVICE_ADD("pic8259", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE("maincpu", 0))
+ PIC8259(config, m_pic, 0);
+ m_pic->out_int_callback().set_inputline(m_maincpu, 0);
/* sound */
SPEAKER(config, "mono").front_center();
diff --git a/src/mame/drivers/balsente.cpp b/src/mame/drivers/balsente.cpp
index b21aad77268..5a661470e8f 100644
--- a/src/mame/drivers/balsente.cpp
+++ b/src/mame/drivers/balsente.cpp
@@ -304,7 +304,7 @@ void balsente_state::cpu2_map(address_map &map)
void balsente_state::cpu2_io_map(address_map &map)
{
map.global_mask(0xff);
- map(0x00, 0x03).rw("pit", FUNC(pit8253_device::read), FUNC(pit8253_device::write));
+ map(0x00, 0x03).rw(m_pit, FUNC(pit8253_device::read), FUNC(pit8253_device::write));
map(0x08, 0x0f).r(FUNC(balsente_state::counter_state_r));
map(0x08, 0x09).w(FUNC(balsente_state::counter_control_w));
map(0x0a, 0x0b).w(FUNC(balsente_state::dac_data_w));
@@ -1338,11 +1338,11 @@ MACHINE_CONFIG_START(balsente_state::balsente)
MCFG_TIMER_DRIVER_ADD("scan_timer", balsente_state, interrupt_timer)
MCFG_TIMER_DRIVER_ADD("8253_0_timer", balsente_state, clock_counter_0_ff)
- MCFG_DEVICE_ADD("pit", PIT8253, 0)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, balsente_state, counter_0_set_out))
- MCFG_PIT8253_OUT2_HANDLER(INPUTLINE("audiocpu", INPUT_LINE_IRQ0))
- MCFG_PIT8253_CLK1(8_MHz_XTAL / 4)
- MCFG_PIT8253_CLK2(8_MHz_XTAL / 4)
+ PIT8253(config, m_pit, 0);
+ m_pit->out_handler<0>().set(FUNC(balsente_state::counter_0_set_out));
+ m_pit->out_handler<2>().set_inputline(m_audiocpu, INPUT_LINE_IRQ0);
+ m_pit->set_clk<1>(8_MHz_XTAL / 4);
+ m_pit->set_clk<2>(8_MHz_XTAL / 4);
LS259(config, m_outlatch); // U9H
// these outputs are generally used to control the various lamps
@@ -2470,7 +2470,7 @@ GAME( 1984, triviag1, 0, balsente, triviag1, balsente_state, init_trivia
GAME( 1984, triviag2, 0, balsente, triviag1, balsente_state, init_triviag2, ROT0, "Bally/Sente", "Trivial Pursuit (Genus II Edition)", MACHINE_SUPPORTS_SAVE )
GAME( 1984, triviasp, 0, balsente, triviag1, balsente_state, init_triviag2, ROT0, "Bally/Sente", "Trivial Pursuit (All Star Sports Edition)", MACHINE_SUPPORTS_SAVE )
GAME( 1984, triviayp, 0, balsente, triviag1, balsente_state, init_triviag2, ROT0, "Bally/Sente", "Trivial Pursuit (Young Players Edition)", MACHINE_SUPPORTS_SAVE )
-GAME( 1987, triviaes, 0, balsente, triviaes, balsente_state, init_triviaes, ROT0, "Bally/Sente", "Trivial Pursuit (Spanish)", MACHINE_SUPPORTS_SAVE )
+GAME( 1987, triviaes, 0, balsente, triviaes, balsente_state, init_triviaes, ROT0, "Bally/Sente (Maibesa license)", "Trivial Pursuit (Spanish, Maibesa license)", MACHINE_SUPPORTS_SAVE )
GAME( 1985, toggle, 0, balsente, toggle, balsente_state, init_toggle, ROT0, "Bally/Sente", "Toggle (prototype)", MACHINE_SUPPORTS_SAVE )
GAME( 1986, nametune, 0, balsente, nametune, balsente_state, init_nametune, ROT0, "Bally/Sente", "Name That Tune (set 1)", MACHINE_SUPPORTS_SAVE )
diff --git a/src/mame/drivers/bw12.cpp b/src/mame/drivers/bw12.cpp
index dc4b8ad955e..e362d85f1ac 100644
--- a/src/mame/drivers/bw12.cpp
+++ b/src/mame/drivers/bw12.cpp
@@ -598,13 +598,13 @@ MACHINE_CONFIG_START(bw12_state::common)
m_sio->out_rtsb_callback().set(RS232_B_TAG, FUNC(rs232_port_device::write_rts));
m_sio->out_int_callback().set_inputline(m_maincpu, INPUT_LINE_IRQ0);
- MCFG_DEVICE_ADD(PIT8253_TAG, PIT8253, 0)
- MCFG_PIT8253_CLK0(XTAL(1'843'200))
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, bw12_state, pit_out0_w))
- MCFG_PIT8253_CLK1(XTAL(1'843'200))
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(m_sio, z80dart_device, rxtxcb_w))
- MCFG_PIT8253_CLK2(XTAL(1'843'200))
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, bw12_state, pit_out2_w))
+ PIT8253(config, m_pit, 0);
+ m_pit->set_clk<0>(XTAL(1'843'200));
+ m_pit->out_handler<0>().set(FUNC(bw12_state::pit_out0_w));
+ m_pit->set_clk<1>(XTAL(1'843'200));
+ m_pit->out_handler<1>().set(m_sio, FUNC(z80dart_device::rxtxcb_w));
+ m_pit->set_clk<2>(XTAL(1'843'200));
+ m_pit->out_handler<2>().set(FUNC(bw12_state::pit_out2_w));
AY3600(config, m_kbc, 0);
m_kbc->x0().set_ioport("X0");
diff --git a/src/mame/drivers/cbm2.cpp b/src/mame/drivers/cbm2.cpp
index d79d7bffc87..3afa0298410 100644
--- a/src/mame/drivers/cbm2.cpp
+++ b/src/mame/drivers/cbm2.cpp
@@ -1169,7 +1169,7 @@ void cbm2_state::ext_mem(address_map &map)
void cbm2_state::ext_io(address_map &map)
{
map.global_mask(0xff);
- map(0x0000, 0x0001).mirror(0x1e).rw(EXT_I8259A_TAG, FUNC(pic8259_device::read), FUNC(pic8259_device::write));
+ map(0x0000, 0x0001).mirror(0x1e).rw(m_ext_pic, FUNC(pic8259_device::read), FUNC(pic8259_device::write));
map(0x0020, 0x0027).mirror(0x18).rw(EXT_MOS6525_TAG, FUNC(tpi6525_device::read), FUNC(tpi6525_device::write));
}
@@ -2715,13 +2715,13 @@ MACHINE_CONFIG_START(cbm2hp_state::bx256hp)
b256hp(config);
MCFG_MACHINE_START_OVERRIDE(cbm2_state, cbm2x_ntsc)
- MCFG_DEVICE_ADD(EXT_I8088_TAG, I8088, XTAL(12'000'000))
+ MCFG_DEVICE_ADD(m_ext_cpu, I8088, XTAL(12'000'000))
MCFG_DEVICE_PROGRAM_MAP(ext_mem)
MCFG_DEVICE_IO_MAP(ext_io)
MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE(EXT_I8259A_TAG, pic8259_device, inta_cb)
- MCFG_DEVICE_ADD(EXT_I8259A_TAG, PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE(EXT_I8088_TAG, INPUT_LINE_IRQ0))
+ PIC8259(config, m_ext_pic, 0);
+ m_ext_pic->out_int_callback().set_inputline(m_ext_cpu, INPUT_LINE_IRQ0);
TPI6525(config, m_ext_tpi, 0);
m_ext_tpi->in_pa_cb().set(EXT_MOS6526_TAG, FUNC(mos6526_device::pa_r));
@@ -2784,13 +2784,13 @@ MACHINE_CONFIG_START(cbm2hp_state::cbm730)
cbm720(config);
MCFG_MACHINE_START_OVERRIDE(cbm2_state, cbm2x_pal)
- MCFG_DEVICE_ADD(EXT_I8088_TAG, I8088, XTAL(12'000'000))
+ MCFG_DEVICE_ADD(m_ext_cpu, I8088, XTAL(12'000'000))
MCFG_DEVICE_PROGRAM_MAP(ext_mem)
MCFG_DEVICE_IO_MAP(ext_io)
MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE(EXT_I8259A_TAG, pic8259_device, inta_cb)
- MCFG_DEVICE_ADD(EXT_I8259A_TAG, PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE(EXT_I8088_TAG, INPUT_LINE_IRQ0))
+ PIC8259(config, m_ext_pic, 0);
+ m_ext_pic->out_int_callback().set_inputline(m_ext_cpu, INPUT_LINE_IRQ0);
TPI6525(config, m_ext_tpi, 0);
m_ext_tpi->in_pa_cb().set(EXT_MOS6526_TAG, FUNC(mos6526_device::pa_r));
diff --git a/src/mame/drivers/compc.cpp b/src/mame/drivers/compc.cpp
index 68a80da6c4b..0f77f7e78db 100644
--- a/src/mame/drivers/compc.cpp
+++ b/src/mame/drivers/compc.cpp
@@ -200,13 +200,13 @@ MACHINE_CONFIG_START(compc_state::compc)
MCFG_PCNOPPI_MOTHERBOARD_ADD("mb", "maincpu")
MCFG_DEVICE_REMOVE("mb:pit8253")
- MCFG_DEVICE_ADD("mb:pit8253", FE2010_PIT, 0)
- MCFG_PIT8253_CLK0(XTAL(14'318'181)/12.0) /* heartbeat IRQ */
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE("mb:pic8259", pic8259_device, ir0_w))
- MCFG_PIT8253_CLK1(XTAL(14'318'181)/12.0) /* dram refresh */
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE("mb", ibm5160_mb_device, pc_pit8253_out1_changed))
- MCFG_PIT8253_CLK2(XTAL(14'318'181)/12.0) /* pio port c pin 4, and speaker polling enough */
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE("mb", ibm5160_mb_device, pc_pit8253_out2_changed))
+ fe2010_pit_device &pit(FE2010_PIT(config, "mb:pit8253", 0));
+ pit.set_clk<0>(XTAL(14'318'181)/12.0); /* heartbeat IRQ */
+ pit.out_handler<0>().set("mb:pic8259", FUNC(pic8259_device::ir0_w));
+ pit.set_clk<1>(XTAL(14'318'181)/12.0); /* dram refresh */
+ pit.out_handler<1>().set(m_mb, FUNC(ibm5160_mb_device::pc_pit8253_out1_changed));
+ pit.set_clk<2>(XTAL(14'318'181)/12.0); /* pio port c pin 4, and speaker polling enough */
+ pit.out_handler<2>().set(m_mb, FUNC(ibm5160_mb_device::pc_pit8253_out2_changed));
// FIXME: determine ISA bus clock
MCFG_DEVICE_ADD("isa1", ISA8_SLOT, 0, "mb:isa", pc_isa8_cards, "mda", false)
diff --git a/src/mame/drivers/compis.cpp b/src/mame/drivers/compis.cpp
index ce6b4accee4..e69b66244d9 100644
--- a/src/mame/drivers/compis.cpp
+++ b/src/mame/drivers/compis.cpp
@@ -408,7 +408,7 @@ void compis_state::compis_io(address_map &map)
{
map.unmap_value_high();
map(0x0000, 0x0007) /* PCS0 */ .mirror(0x78).rw(m_ppi, FUNC(i8255_device::read), FUNC(i8255_device::write)).umask16(0xff00);
- map(0x0080, 0x0087) /* PCS1 */ .mirror(0x78).rw(I8253_TAG, FUNC(pit8253_device::read), FUNC(pit8253_device::write)).umask16(0x00ff);
+ map(0x0080, 0x0087) /* PCS1 */ .mirror(0x78).rw(m_pit, FUNC(pit8253_device::read), FUNC(pit8253_device::write)).umask16(0x00ff);
map(0x0100, 0x011f) /* PCS2 */ .mirror(0x60).rw(MM58174A_TAG, FUNC(mm58274c_device::read), FUNC(mm58274c_device::write)).umask16(0x00ff);
map(0x0180, 0x01ff) /* PCS3 */ .rw(GRAPHICS_TAG, FUNC(compis_graphics_slot_device::pcs3_r), FUNC(compis_graphics_slot_device::pcs3_w));
//map(0x0200, 0x0201) /* PCS4 */ .mirror(0x7e);
@@ -753,12 +753,12 @@ MACHINE_CONFIG_START(compis_state::compis)
m_osp->delay().set(I80130_TAG, FUNC(i80130_device::ir7_w));
m_osp->baud().set(FUNC(compis_state::tmr2_w));
- MCFG_DEVICE_ADD(I8253_TAG, PIT8253, 0)
- MCFG_PIT8253_CLK0(15.36_MHz_XTAL/8)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(m_mpsc, i8274_device, rxtxcb_w))
- MCFG_PIT8253_CLK1(15.36_MHz_XTAL/8)
- MCFG_PIT8253_CLK2(15.36_MHz_XTAL/8)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, compis_state, tmr5_w))
+ PIT8253(config, m_pit, 0);
+ m_pit->set_clk<0>(15.36_MHz_XTAL/8);
+ m_pit->out_handler<0>().set(m_mpsc, FUNC(i8274_device::rxtxcb_w));
+ m_pit->set_clk<1>(15.36_MHz_XTAL/8);
+ m_pit->set_clk<2>(15.36_MHz_XTAL/8);
+ m_pit->out_handler<2>().set(FUNC(compis_state::tmr5_w));
I8255(config, m_ppi);
m_ppi->out_pa_callback().set("cent_data_out", FUNC(output_latch_device::bus_w));
diff --git a/src/mame/drivers/crystal.cpp b/src/mame/drivers/crystal.cpp
index 13eea7fa338..7f8e8326e6f 100644
--- a/src/mame/drivers/crystal.cpp
+++ b/src/mame/drivers/crystal.cpp
@@ -541,7 +541,7 @@ READ32_MEMBER(crystal_state::crtc_r)
switch (offset)
{
case 0: // CRTC Status / Mode
- if ((m_crtcregs[0x30 / 4] & 1) == 0) // Interrace
+ if ((m_crtcregs[0x30 / 4] & 1) == 0) // Interlace
vdisp <<= 1;
if (m_screen->vpos() <= vdisp) // Vertical display enable status
@@ -635,12 +635,11 @@ void crystal_state::crtc_update()
// TODO : Implement other CRTC parameters
uint32_t hdisp = m_crtcregs[0x0c / 4] + 1;
uint32_t vdisp = m_crtcregs[0x1c / 4] + 1;
- if ((m_crtcregs[0x30 / 4] & 1) == 0) // Interrace
+ if ((m_crtcregs[0x30 / 4] & 1) == 0) // Interlace
vdisp <<= 1;
- rectangle visarea;
- visarea.set(0, hdisp - 1, 0, vdisp - 1);
- m_screen->configure(hdisp, vdisp, visarea, m_screen->frame_period().attoseconds() );
+ rectangle const visarea(0, hdisp - 1, 0, vdisp - 1);
+ m_screen->configure(hdisp, vdisp, visarea, m_screen->frame_period().attoseconds());
}
void crystal_state::internal_map(address_map &map)
diff --git a/src/mame/drivers/dai.cpp b/src/mame/drivers/dai.cpp
index 27c4c73df38..2c08f556e9f 100644
--- a/src/mame/drivers/dai.cpp
+++ b/src/mame/drivers/dai.cpp
@@ -195,15 +195,15 @@ MACHINE_CONFIG_START(dai_state::dai)
MCFG_DEVICE_IRQ_ACKNOWLEDGE_DRIVER(dai_state,int_ack)
MCFG_QUANTUM_TIME(attotime::from_hz(60))
- MCFG_DEVICE_ADD("pit8253", PIT8253, 0)
- MCFG_PIT8253_CLK0(2000000)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE("custom", dai_sound_device, set_input_ch0))
- MCFG_PIT8253_CLK1(2000000)
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE("custom", dai_sound_device, set_input_ch1))
- MCFG_PIT8253_CLK2(2000000)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE("custom", dai_sound_device, set_input_ch2))
+ PIT8253(config, m_pit, 0);
+ m_pit->set_clk<0>(2000000);
+ m_pit->out_handler<0>().set(m_sound, FUNC(dai_sound_device::set_input_ch0));
+ m_pit->set_clk<1>(2000000);
+ m_pit->out_handler<1>().set(m_sound, FUNC(dai_sound_device::set_input_ch1));
+ m_pit->set_clk<2>(2000000);
+ m_pit->out_handler<2>().set(m_sound, FUNC(dai_sound_device::set_input_ch2));
- MCFG_DEVICE_ADD("ppi8255", I8255, 0)
+ I8255(config, "ppi8255");
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
@@ -224,7 +224,7 @@ MACHINE_CONFIG_START(dai_state::dai)
WAVE(config, "wave", "cassette").add_route(ALL_OUTPUTS, "mono", 0.25);
SPEAKER(config, "lspeaker").front_left();
SPEAKER(config, "rspeaker").front_right();
- DAI_SOUND(config, "custom").add_route(0, "lspeaker", 0.50).add_route(1, "rspeaker", 0.50);
+ DAI_SOUND(config, m_sound).add_route(0, "lspeaker", 0.50).add_route(1, "rspeaker", 0.50);
/* cassette */
MCFG_CASSETTE_ADD( "cassette" )
diff --git a/src/mame/drivers/dmv.cpp b/src/mame/drivers/dmv.cpp
index 23a5c3ead87..0fd7dc22a84 100644
--- a/src/mame/drivers/dmv.cpp
+++ b/src/mame/drivers/dmv.cpp
@@ -827,11 +827,11 @@ MACHINE_CONFIG_START(dmv_state::dmv)
MCFG_FLOPPY_DRIVE_ADD("i8272:0", dmv_floppies, "525dd", dmv_state::floppy_formats)
MCFG_FLOPPY_DRIVE_ADD("i8272:1", dmv_floppies, "525dd", dmv_state::floppy_formats)
- MCFG_DEVICE_ADD("pit8253", PIT8253, 0)
- MCFG_PIT8253_CLK0(50)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, dmv_state, pit_out0))
- MCFG_PIT8253_CLK2(XTAL(24'000'000) / 3 / 16)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, dmv_state, timint_w))
+ PIT8253(config, m_pit, 0);
+ m_pit->set_clk<0>(50);
+ m_pit->out_handler<0>().set(FUNC(dmv_state::pit_out0));
+ m_pit->set_clk<2>(XTAL(24'000'000) / 3 / 16);
+ m_pit->out_handler<2>().set(FUNC(dmv_state::timint_w));
/* sound hardware */
SPEAKER(config, "mono").front_center();
diff --git a/src/mame/drivers/dvk_ksm.cpp b/src/mame/drivers/dvk_ksm.cpp
index ca204512c90..762b9662565 100644
--- a/src/mame/drivers/dvk_ksm.cpp
+++ b/src/mame/drivers/dvk_ksm.cpp
@@ -435,8 +435,8 @@ MACHINE_CONFIG_START(ksm_state::ksm)
MCFG_DEVICE_ADD("gfxdecode", GFXDECODE, "palette", gfx_ksm)
MCFG_PALETTE_ADD_MONOCHROME("palette")
- MCFG_DEVICE_ADD("pic8259", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE("maincpu", 0))
+ PIC8259(config, m_pic8259, 0);
+ m_pic8259->out_int_callback().set_inputline(m_maincpu, 0);
// D30
i8255_device &ppi(I8255(config, "ppi8255"));
@@ -448,7 +448,7 @@ MACHINE_CONFIG_START(ksm_state::ksm)
// D42 - serial connection to host
I8251(config, m_i8251line, 0);
m_i8251line->txd_handler().set(m_rs232, FUNC(rs232_port_device::write_txd));
- m_i8251line->rxrdy_handler().set("pic8259", FUNC(pic8259_device::ir3_w));
+ m_i8251line->rxrdy_handler().set(m_pic8259, FUNC(pic8259_device::ir3_w));
RS232_PORT(config, m_rs232, default_rs232_devices, "null_modem");
m_rs232->rxd_handler().set(m_i8251line, FUNC(i8251_device::write_rxd));
@@ -457,7 +457,7 @@ MACHINE_CONFIG_START(ksm_state::ksm)
// D41 - serial connection to MS7004 keyboard
I8251(config, m_i8251kbd, 0);
- m_i8251kbd->rxrdy_handler().set("pic8259", FUNC(pic8259_device::ir1_w));
+ m_i8251kbd->rxrdy_handler().set(m_pic8259, FUNC(pic8259_device::ir1_w));
m_i8251kbd->rts_handler().set(FUNC(ksm_state::write_brga));
m_i8251kbd->dtr_handler().set(FUNC(ksm_state::write_brgb));
diff --git a/src/mame/drivers/excali64.cpp b/src/mame/drivers/excali64.cpp
index 8111dc96b40..fc4e8851594 100644
--- a/src/mame/drivers/excali64.cpp
+++ b/src/mame/drivers/excali64.cpp
@@ -563,12 +563,12 @@ MACHINE_CONFIG_START(excali64_state::excali64)
//uart.txd_handler().set("rs232", FUNC(rs232_port_device::write_txd));
//uart.rts_handler().set("rs232", FUNC(rs232_port_device::write_rts));
- MCFG_DEVICE_ADD("pit", PIT8253, 0)
- MCFG_PIT8253_CLK0(16_MHz_XTAL / 16) /* Timer 0: tone gen for speaker */
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE("speaker", speaker_sound_device, level_w))
- //MCFG_PIT8253_CLK1(16_MHz_XTAL / 16) /* Timer 1: baud rate gen for 8251 */
- //MCFG_PIT8253_OUT1_HANDLER(WRITELINE(*this, excali64_state, write_uart_clock))
- //MCFG_PIT8253_CLK2(16_MHz_XTAL / 16) /* Timer 2: not used */
+ pit8253_device &pit(PIT8253(config, "pit", 0));
+ pit.set_clk<0>(16_MHz_XTAL / 16); /* Timer 0: tone gen for speaker */
+ pit.out_handler<0>().set("speaker", FUNC(speaker_sound_device::level_w));
+ //pit.set_clk<1>(16_MHz_XTAL / 16); /* Timer 1: baud rate gen for 8251 */
+ //pit.out_handler<1>().set(FUNC(excali64_state::write_uart_clock));
+ //pit.set_clk<2>(16_MHz_XTAL / 16); /* Timer 2: not used */
i8255_device &ppi(I8255A(config, "ppi"));
ppi.out_pa_callback().set("cent_data_out", FUNC(output_latch_device::bus_w)); // parallel port
diff --git a/src/mame/drivers/fantland.cpp b/src/mame/drivers/fantland.cpp
index 83d74c7d199..36301c00534 100644
--- a/src/mame/drivers/fantland.cpp
+++ b/src/mame/drivers/fantland.cpp
@@ -64,7 +64,7 @@ Year + Game Main CPU Sound CPU Sound Video
***************************************************************************/
-WRITE8_MEMBER(fantland_state::fantland_nmi_enable_w)
+WRITE8_MEMBER(fantland_state::nmi_enable_w)
{
m_nmi_enable = data;
@@ -72,72 +72,53 @@ WRITE8_MEMBER(fantland_state::fantland_nmi_enable_w)
logerror("CPU #0 PC = %04X: nmi_enable = %02x\n", m_maincpu->pc(), data);
}
-WRITE16_MEMBER(fantland_state::fantland_nmi_enable_16_w)
-{
- if (ACCESSING_BITS_0_7)
- fantland_nmi_enable_w(space, offset * 2, data);
-}
-
-WRITE8_MEMBER(fantland_state::fantland_soundlatch_w)
+WRITE8_MEMBER(fantland_state::soundlatch_w)
{
m_soundlatch->write(space, 0, data);
m_audiocpu->pulse_input_line(INPUT_LINE_NMI, attotime::zero);
}
-WRITE16_MEMBER(fantland_state::fantland_soundlatch_16_w)
-{
- if (ACCESSING_BITS_0_7)
- fantland_soundlatch_w(space, offset * 2, data);
-}
-
/***************************************************************************
Fantasy Land
***************************************************************************/
-READ16_MEMBER(fantland_state::spriteram_16_r)
+READ8_MEMBER(fantland_state::spriteram_r)
{
- uint8_t *spriteram = m_spriteram;
- return spriteram[2 * offset + 0] | (spriteram[2 * offset + 1] << 8);
+ return m_spriteram[offset];
}
-READ16_MEMBER(fantland_state::spriteram2_16_r)
+READ8_MEMBER(fantland_state::spriteram2_r)
{
- uint8_t *spriteram_2 = m_spriteram2;
- return spriteram_2[2 * offset + 0] | (spriteram_2[2 * offset + 1] << 8);
+ return m_spriteram2[offset];
}
-WRITE16_MEMBER(fantland_state::spriteram_16_w)
+WRITE8_MEMBER(fantland_state::spriteram_w)
{
- uint8_t *spriteram = m_spriteram;
- if (ACCESSING_BITS_0_7)
- spriteram[2 * offset + 0] = data;
- if (ACCESSING_BITS_8_15)
- spriteram[2 * offset + 1] = data >> 8;
+ COMBINE_DATA(&m_spriteram[offset]);
}
-WRITE16_MEMBER(fantland_state::spriteram2_16_w)
+WRITE8_MEMBER(fantland_state::spriteram2_w)
{
- uint8_t *spriteram_2 = m_spriteram2;
- if (ACCESSING_BITS_0_7)
- spriteram_2[2 * offset + 0] = data;
- if (ACCESSING_BITS_8_15)
- spriteram_2[2 * offset + 1] = data >> 8;
+ COMBINE_DATA(&m_spriteram2[offset]);
}
void fantland_state::fantland_map(address_map &map)
{
map(0x00000, 0x07fff).ram();
- map(0x08000, 0x7ffff).rom();
+ map(0x08000, 0x3ffff).rom().region("maincpu", 0x08000);
+ map(0x40000, 0x7ffff).rom().region("maincpu", 0x00000);
map(0xa2000, 0xa21ff).ram().w(m_palette, FUNC(palette_device::write16)).share("palette");
- map(0xa3000, 0xa3001).portr("a3000").w(FUNC(fantland_state::fantland_nmi_enable_16_w));
- map(0xa3002, 0xa3003).portr("a3002").w(FUNC(fantland_state::fantland_soundlatch_16_w));
+ map(0xa3000, 0xa3000).w(FUNC(fantland_state::nmi_enable_w));
+ map(0xa3000, 0xa3001).portr("a3000");
+ map(0xa3002, 0xa3002).w(FUNC(fantland_state::soundlatch_w));
+ map(0xa3002, 0xa3003).portr("a3002");
- map(0xa4000, 0xa67ff).rw(FUNC(fantland_state::spriteram_16_r), FUNC(fantland_state::spriteram_16_w)).share("spriteram");
- map(0xc0000, 0xcffff).rw(FUNC(fantland_state::spriteram2_16_r), FUNC(fantland_state::spriteram2_16_w)).share("spriteram2");
+ map(0xa4000, 0xa67ff).rw(FUNC(fantland_state::spriteram_r), FUNC(fantland_state::spriteram_w)).share("spriteram");
+ map(0xc0000, 0xcffff).rw(FUNC(fantland_state::spriteram2_r), FUNC(fantland_state::spriteram2_w)).share("spriteram2");
- map(0xe0000, 0xfffff).rom();
+ map(0xe0000, 0xfffff).rom().region("maincpu", 0xe0000);
}
@@ -148,20 +129,19 @@ void fantland_state::fantland_map(address_map &map)
void fantland_state::galaxygn_map(address_map &map)
{
map(0x00000, 0x07fff).ram();
- map(0x10000, 0x2ffff).rom();
+ map(0x10000, 0x2ffff).rom().region("maincpu", 0x10000);
map(0x52000, 0x521ff).ram().w(m_palette, FUNC(palette_device::write8)).share("palette");
- map(0x53000, 0x53000).portr("P1").w(FUNC(fantland_state::fantland_nmi_enable_w));
+ map(0x53000, 0x53000).portr("P1").w(FUNC(fantland_state::nmi_enable_w));
map(0x53001, 0x53001).portr("P2");
- map(0x53002, 0x53002).portr("DSW1").w(FUNC(fantland_state::fantland_soundlatch_w));
+ map(0x53002, 0x53002).portr("DSW1").w(FUNC(fantland_state::soundlatch_w));
map(0x53003, 0x53003).portr("DSW2");
map(0x54000, 0x567ff).ram().share("spriteram");
map(0x60000, 0x6ffff).ram().share("spriteram2");
- map(0x70000, 0x7ffff).rom();
- map(0xf0000, 0xfffff).rom();
+ map(0x70000, 0x7ffff).rom().region("maincpu", 0x70000).mirror(0x80000);
}
@@ -169,20 +149,21 @@ void fantland_state::galaxygn_map(address_map &map)
Born To Fight
***************************************************************************/
-WRITE8_MEMBER(fantland_state::borntofi_nmi_enable_w)
+// data & 0x31 changes when lightgun fires
+#if 0
+WRITE8_MEMBER(borntofi_state::nmi_enable_w)
{
m_nmi_enable = data;
- // data & 0x31 changes when lightgun fires
-
if ((m_nmi_enable != 0) && (m_nmi_enable != 8))
logerror("CPU #0 PC = %04X: nmi_enable = %02x\n", m_maincpu->pc(), data);
// popmessage("%02X", data);
}
+#endif
// Trackball doesn't work correctly
-READ8_MEMBER(fantland_state::borntofi_inputs_r)
+READ8_MEMBER(borntofi_state::inputs_r)
{
int x, y, f;
@@ -238,14 +219,14 @@ READ8_MEMBER(fantland_state::borntofi_inputs_r)
return m_input_ret[offset];
}
-void fantland_state::borntofi_map(address_map &map)
+void borntofi_state::main_map(address_map &map)
{
map(0x00000, 0x07fff).ram();
- map(0x10000, 0x2ffff).rom();
+ map(0x10000, 0x2ffff).rom().region("maincpu", 0x10000);
map(0x52000, 0x521ff).ram().w(m_palette, FUNC(palette_device::write8)).share("palette");
- map(0x53000, 0x53001).rw(FUNC(fantland_state::borntofi_inputs_r), FUNC(fantland_state::borntofi_nmi_enable_w));
- map(0x53002, 0x53002).portr("DSW").w(FUNC(fantland_state::fantland_soundlatch_w));
+ map(0x53000, 0x53001).rw(FUNC(borntofi_state::inputs_r), FUNC(borntofi_state::nmi_enable_w));
+ map(0x53002, 0x53002).portr("DSW").w(FUNC(borntofi_state::soundlatch_w));
map(0x53003, 0x53003).portr("Controls");
map(0x54000, 0x567ff).ram().share("spriteram");
@@ -257,8 +238,7 @@ void fantland_state::borntofi_map(address_map &map)
map(0x60000, 0x6ffff).ram().share("spriteram2");
- map(0x70000, 0x7ffff).rom();
- map(0xf0000, 0xfffff).rom();
+ map(0x70000, 0x7ffff).rom().region("maincpu", 0x70000).mirror(0x80000);
}
@@ -270,20 +250,19 @@ void fantland_state::wheelrun_map(address_map &map)
{
map(0x00000, 0x07fff).ram();
- map(0x30000, 0x3ffff).rom();
- map(0x70000, 0x7ffff).rom();
+ map(0x30000, 0x3ffff).rom().region("maincpu", 0x30000);
map(0x52000, 0x521ff).ram().w(m_palette, FUNC(palette_device::write8)).share("palette");
- map(0x53000, 0x53000).portr("53000").w(FUNC(fantland_state::borntofi_nmi_enable_w));
+ map(0x53000, 0x53000).portr("53000").w(FUNC(fantland_state::nmi_enable_w));
map(0x53001, 0x53001).portr("53001");
- map(0x53002, 0x53002).portr("53002").w(FUNC(fantland_state::fantland_soundlatch_w));
+ map(0x53002, 0x53002).portr("53002").w(FUNC(fantland_state::soundlatch_w));
map(0x53003, 0x53003).portr("53003").nopw();
map(0x54000, 0x567ff).ram().share("spriteram");
map(0x60000, 0x6ffff).ram().share("spriteram2");
- map(0xf0000, 0xfffff).rom();
+ map(0x70000, 0x7ffff).rom().region("maincpu", 0x70000).mirror(0x80000);
}
@@ -297,8 +276,8 @@ void fantland_state::wheelrun_map(address_map &map)
void fantland_state::fantland_sound_map(address_map &map)
{
map(0x00000, 0x01fff).ram();
- map(0x80000, 0x9ffff).rom();
- map(0xc0000, 0xfffff).rom();
+ map(0x80000, 0x9ffff).rom().region("audiocpu", 0x80000);
+ map(0xc0000, 0xfffff).rom().region("audiocpu", 0xc0000);
}
void fantland_state::fantland_sound_iomap(address_map &map)
@@ -319,42 +298,32 @@ void fantland_state::galaxygn_sound_iomap(address_map &map)
Born To Fight
***************************************************************************/
-void fantland_state::borntofi_adpcm_start( msm5205_device *device, int voice )
+void borntofi_state::adpcm_start(int voice)
{
- device->reset_w(0);
+ m_msm[voice]->reset_w(0);
m_adpcm_playing[voice] = 1;
m_adpcm_nibble[voice] = 0;
// logerror("%s: adpcm start = %06x, stop = %06x\n", device->machine().describe_context(), m_adpcm_addr[0][voice], m_adpcm_addr[1][voice]);
}
-void fantland_state::borntofi_adpcm_stop( msm5205_device *device, int voice )
+void borntofi_state::adpcm_stop(int voice)
{
- device->reset_w(1);
+ m_msm[voice]->reset_w(1);
m_adpcm_playing[voice] = 0;
}
-WRITE8_MEMBER(fantland_state::borntofi_msm5205_w)
+WRITE8_MEMBER(borntofi_state::msm5205_w)
{
int voice = offset / 8;
int reg = offset % 8;
- msm5205_device *msm;
-
- switch (voice)
- {
- default:
- case 0: msm = m_msm1; break;
- case 1: msm = m_msm2; break;
- case 2: msm = m_msm3; break;
- case 3: msm = m_msm4; break;
- }
if (reg == 0)
{
// Play / Stop
switch(data)
{
- case 0x00: borntofi_adpcm_stop(msm, voice); break;
- case 0x03: borntofi_adpcm_start(msm, voice); break;
+ case 0x00: adpcm_stop(voice); break;
+ case 0x03: adpcm_start(voice); break;
default: logerror("CPU #0 PC = %04X: adpcm reg %d <- %02x\n", m_audiocpu->pc(), reg, data);
}
}
@@ -368,52 +337,43 @@ WRITE8_MEMBER(fantland_state::borntofi_msm5205_w)
}
}
-void fantland_state::borntofi_adpcm_int( msm5205_device *device, int voice )
+template<int Voice>
+WRITE_LINE_MEMBER(borntofi_state::adpcm_int)
{
- uint8_t *rom;
- size_t len;
- int start, stop;
-
- if (!m_adpcm_playing[voice])
+ if (!m_adpcm_playing[Voice])
return;
- rom = memregion("adpcm")->base();
- len = memregion("adpcm")->bytes() * 2;
+ size_t const len = m_adpcm_rom.bytes() * 2;
- start = m_adpcm_addr[0][voice] + m_adpcm_nibble[voice];
- stop = m_adpcm_addr[1][voice];
+ int const start = m_adpcm_addr[0][Voice] + m_adpcm_nibble[Voice];
+ int const stop = m_adpcm_addr[1][Voice];
if (start >= len)
{
- borntofi_adpcm_stop(device, voice);
+ adpcm_stop(Voice);
logerror("adpcm address out of range: %06x\n", start);
return;
}
if (start >= stop)
{
- borntofi_adpcm_stop(device, voice);
+ adpcm_stop(Voice);
}
else
{
- device->write_data(rom[start / 2] >> ((start & 1) * 4));
- m_adpcm_nibble[voice]++;
+ m_msm[Voice]->write_data(m_adpcm_rom[start / 2] >> ((start & 1) * 4));
+ m_adpcm_nibble[Voice]++;
}
}
-WRITE_LINE_MEMBER(fantland_state::borntofi_adpcm_int_0) { borntofi_adpcm_int(m_msm1, 0); }
-WRITE_LINE_MEMBER(fantland_state::borntofi_adpcm_int_1) { borntofi_adpcm_int(m_msm2, 1); }
-WRITE_LINE_MEMBER(fantland_state::borntofi_adpcm_int_2) { borntofi_adpcm_int(m_msm3, 2); }
-WRITE_LINE_MEMBER(fantland_state::borntofi_adpcm_int_3) { borntofi_adpcm_int(m_msm4, 3); }
-
-void fantland_state::borntofi_sound_map(address_map &map)
+void borntofi_state::sound_map(address_map &map)
{
map(0x00000, 0x003ff).ram();
map(0x04000, 0x04000).r(m_soundlatch, FUNC(generic_latch_8_device::read));
- map(0x04000, 0x0401f).w(FUNC(fantland_state::borntofi_msm5205_w));
- map(0x08000, 0x0ffff).rom();
- map(0xf8000, 0xfffff).rom();
+ map(0x04000, 0x0401f).w(FUNC(borntofi_state::msm5205_w));
+ map(0x08000, 0x0ffff).rom().region("audiocpu", 0x08000);
+ map(0xf8000, 0xfffff).rom().region("audiocpu", 0x08000);
}
@@ -423,7 +383,7 @@ void fantland_state::borntofi_sound_map(address_map &map)
void fantland_state::wheelrun_sound_map(address_map &map)
{
- map(0x0000, 0x7fff).rom();
+ map(0x0000, 0x7fff).rom().region("audiocpu", 0);
map(0x8000, 0x87ff).ram();
map(0xa000, 0xa001).rw("ymsnd", FUNC(ym3526_device::read), FUNC(ym3526_device::write));
@@ -827,17 +787,17 @@ GFXDECODE_END
***************************************************************************/
-MACHINE_START_MEMBER(fantland_state,fantland)
+void fantland_state::machine_start()
{
save_item(NAME(m_nmi_enable));
}
-MACHINE_RESET_MEMBER(fantland_state,fantland)
+void fantland_state::machine_reset()
{
m_nmi_enable = 0;
}
-WRITE_LINE_MEMBER(fantland_state::fantland_irq)
+WRITE_LINE_MEMBER(fantland_state::vblank_irq)
{
if (state && BIT(m_nmi_enable, 3))
m_maincpu->pulse_input_line(INPUT_LINE_NMI, attotime::zero);
@@ -860,9 +820,6 @@ MACHINE_CONFIG_START(fantland_state::fantland)
MCFG_DEVICE_PERIODIC_INT_DRIVER(fantland_state, fantland_sound_irq, 8000)
// NMI when soundlatch is written
- MCFG_MACHINE_START_OVERRIDE(fantland_state,fantland)
- MCFG_MACHINE_RESET_OVERRIDE(fantland_state,fantland)
-
MCFG_QUANTUM_TIME(attotime::from_hz(8000)) // sound irq must feed the DAC at 8kHz
/* video hardware */
@@ -871,9 +828,9 @@ MACHINE_CONFIG_START(fantland_state::fantland)
MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
MCFG_SCREEN_SIZE(352,256)
MCFG_SCREEN_VISIBLE_AREA(0, 352-1, 0, 256-1)
- MCFG_SCREEN_UPDATE_DRIVER(fantland_state, screen_update_fantland)
+ MCFG_SCREEN_UPDATE_DRIVER(fantland_state, screen_update)
MCFG_SCREEN_PALETTE("palette")
- MCFG_SCREEN_VBLANK_CALLBACK(WRITELINE(*this, fantland_state, fantland_irq))
+ MCFG_SCREEN_VBLANK_CALLBACK(WRITELINE(*this, fantland_state, vblank_irq))
MCFG_DEVICE_ADD("gfxdecode", GFXDECODE, "palette", gfx_fantland)
MCFG_PALETTE_ADD("palette", 256)
@@ -910,18 +867,15 @@ MACHINE_CONFIG_START(fantland_state::galaxygn)
MCFG_DEVICE_IO_MAP(galaxygn_sound_iomap)
// IRQ by YM2151, NMI when soundlatch is written
- MCFG_MACHINE_START_OVERRIDE(fantland_state,fantland)
- MCFG_MACHINE_RESET_OVERRIDE(fantland_state,fantland)
-
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(60)
MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
MCFG_SCREEN_SIZE(352,256)
MCFG_SCREEN_VISIBLE_AREA(0, 352-1, 0, 256-1)
- MCFG_SCREEN_UPDATE_DRIVER(fantland_state, screen_update_fantland)
+ MCFG_SCREEN_UPDATE_DRIVER(fantland_state, screen_update)
MCFG_SCREEN_PALETTE("palette")
- MCFG_SCREEN_VBLANK_CALLBACK(WRITELINE(*this, fantland_state, fantland_irq))
+ MCFG_SCREEN_VBLANK_CALLBACK(WRITELINE(*this, fantland_state, vblank_irq))
MCFG_DEVICE_ADD("gfxdecode", GFXDECODE, "palette", gfx_fantland)
MCFG_PALETTE_ADD("palette", 256)
@@ -939,9 +893,9 @@ MACHINE_CONFIG_START(fantland_state::galaxygn)
MACHINE_CONFIG_END
-MACHINE_START_MEMBER(fantland_state,borntofi)
+void borntofi_state::machine_start()
{
- MACHINE_START_CALL_MEMBER(fantland);
+ fantland_state::machine_start();
save_item(NAME(m_old_x));
save_item(NAME(m_old_y));
@@ -953,11 +907,11 @@ MACHINE_START_MEMBER(fantland_state,borntofi)
save_item(NAME(m_adpcm_nibble));
}
-MACHINE_RESET_MEMBER(fantland_state,borntofi)
+void borntofi_state::machine_reset()
{
int i;
- MACHINE_RESET_CALL_MEMBER(fantland);
+ fantland_state::machine_reset();
for (i = 0; i < 2; i++)
{
@@ -975,23 +929,20 @@ MACHINE_RESET_MEMBER(fantland_state,borntofi)
m_adpcm_nibble[i] = 0;
}
- borntofi_adpcm_stop(m_msm1, 0);
- borntofi_adpcm_stop(m_msm2, 1);
- borntofi_adpcm_stop(m_msm3, 2);
- borntofi_adpcm_stop(m_msm4, 3);
+ adpcm_stop(0);
+ adpcm_stop(1);
+ adpcm_stop(2);
+ adpcm_stop(3);
}
-MACHINE_CONFIG_START(fantland_state::borntofi)
+MACHINE_CONFIG_START(borntofi_state::borntofi)
/* basic machine hardware */
MCFG_DEVICE_ADD("maincpu", V20, 16000000/2) // D701080C-8 - NEC D70108C-8 V20 CPU, running at 8.000MHz [16/2]
- MCFG_DEVICE_PROGRAM_MAP(borntofi_map)
+ MCFG_DEVICE_PROGRAM_MAP(main_map)
MCFG_DEVICE_ADD("audiocpu", I8088, 18432000/3) // 8088 - AMD P8088-2 CPU, running at 6.144MHz [18.432/3]
- MCFG_DEVICE_PROGRAM_MAP(borntofi_sound_map)
-
- MCFG_MACHINE_START_OVERRIDE(fantland_state,borntofi)
- MCFG_MACHINE_RESET_OVERRIDE(fantland_state,borntofi)
+ MCFG_DEVICE_PROGRAM_MAP(sound_map)
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
@@ -999,9 +950,9 @@ MACHINE_CONFIG_START(fantland_state::borntofi)
MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
MCFG_SCREEN_SIZE(352,256)
MCFG_SCREEN_VISIBLE_AREA(0, 352-1, 0, 256-1)
- MCFG_SCREEN_UPDATE_DRIVER(fantland_state, screen_update_fantland)
+ MCFG_SCREEN_UPDATE_DRIVER(borntofi_state, screen_update)
MCFG_SCREEN_PALETTE("palette")
- MCFG_SCREEN_VBLANK_CALLBACK(WRITELINE(*this, fantland_state, fantland_irq))
+ MCFG_SCREEN_VBLANK_CALLBACK(WRITELINE(*this, borntofi_state, vblank_irq))
MCFG_DEVICE_ADD("gfxdecode", GFXDECODE, "palette", gfx_fantland)
MCFG_PALETTE_ADD("palette", 256)
@@ -1014,22 +965,22 @@ MACHINE_CONFIG_START(fantland_state::borntofi)
// OKI M5205 running at 384kHz [18.432/48]. Sample rate = 384000 / 48
MCFG_DEVICE_ADD("msm1", MSM5205, 384000)
- MCFG_MSM5205_VCLK_CB(WRITELINE(*this, fantland_state, borntofi_adpcm_int_0)) /* IRQ handler */
+ MCFG_MSM5205_VCLK_CB(WRITELINE(*this, borntofi_state, adpcm_int<0>)) /* IRQ handler */
MCFG_MSM5205_PRESCALER_SELECTOR(S48_4B) /* 8 kHz, 4 Bits */
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "speaker", 1.0)
MCFG_DEVICE_ADD("msm2", MSM5205, 384000)
- MCFG_MSM5205_VCLK_CB(WRITELINE(*this, fantland_state, borntofi_adpcm_int_1)) /* IRQ handler */
+ MCFG_MSM5205_VCLK_CB(WRITELINE(*this, borntofi_state, adpcm_int<1>)) /* IRQ handler */
MCFG_MSM5205_PRESCALER_SELECTOR(S48_4B) /* 8 kHz, 4 Bits */
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "speaker", 1.0)
MCFG_DEVICE_ADD("msm3", MSM5205, 384000)
- MCFG_MSM5205_VCLK_CB(WRITELINE(*this, fantland_state, borntofi_adpcm_int_2)) /* IRQ handler */
+ MCFG_MSM5205_VCLK_CB(WRITELINE(*this, borntofi_state, adpcm_int<2>)) /* IRQ handler */
MCFG_MSM5205_PRESCALER_SELECTOR(S48_4B) /* 8 kHz, 4 Bits */
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "speaker", 1.0)
MCFG_DEVICE_ADD("msm4", MSM5205, 384000)
- MCFG_MSM5205_VCLK_CB(WRITELINE(*this, fantland_state, borntofi_adpcm_int_3)) /* IRQ handler */
+ MCFG_MSM5205_VCLK_CB(WRITELINE(*this, borntofi_state, adpcm_int<3>)) /* IRQ handler */
MCFG_MSM5205_PRESCALER_SELECTOR(S48_4B) /* 8 kHz, 4 Bits */
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "speaker", 1.0)
MACHINE_CONFIG_END
@@ -1045,18 +996,15 @@ MACHINE_CONFIG_START(fantland_state::wheelrun)
MCFG_DEVICE_PROGRAM_MAP(wheelrun_sound_map)
// IRQ by YM3526, NMI when soundlatch is written
- MCFG_MACHINE_START_OVERRIDE(fantland_state,fantland)
- MCFG_MACHINE_RESET_OVERRIDE(fantland_state,fantland)
-
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_REFRESH_RATE(60)
MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(0))
MCFG_SCREEN_SIZE(256,224)
MCFG_SCREEN_VISIBLE_AREA(0, 256-1, 0, 224-1)
- MCFG_SCREEN_UPDATE_DRIVER(fantland_state, screen_update_fantland)
+ MCFG_SCREEN_UPDATE_DRIVER(fantland_state, screen_update)
MCFG_SCREEN_PALETTE("palette")
- MCFG_SCREEN_VBLANK_CALLBACK(WRITELINE(*this, fantland_state, fantland_irq))
+ MCFG_SCREEN_VBLANK_CALLBACK(WRITELINE(*this, fantland_state, vblank_irq))
MCFG_DEVICE_ADD("gfxdecode", GFXDECODE, "palette", gfx_fantland)
MCFG_PALETTE_ADD("palette", 256)
@@ -1106,14 +1054,13 @@ ROM_START( fantland )
ROM_REGION( 0x100000, "maincpu", 0 ) // Main CPU
ROM_LOAD16_BYTE( "fantasyl.ev2", 0x00000, 0x20000, CRC(f5bdca0e) SHA1(d05cf6f68d4d1a3dcc0171f7cf220c4920bd47bb) )
ROM_LOAD16_BYTE( "fantasyl.od2", 0x00001, 0x20000, CRC(9db35023) SHA1(81e2accd67dcf8563a68b2c4e35526f23a40150c) )
- ROM_COPY( "maincpu", 0x000000, 0x40000, 0x40000 )
ROM_LOAD16_BYTE( "fantasyl.ev1", 0xe0000, 0x10000, CRC(70e0ee30) SHA1(5253213da56b3f97e2811f2b10927d0e542447f0) )
ROM_LOAD16_BYTE( "fantasyl.od1", 0xe0001, 0x10000, CRC(577b4bd7) SHA1(1f08202d99c3e39e0dd1ed4947b928b695a5b411) )
ROM_REGION( 0x100000, "audiocpu", 0 ) // Sound CPU
ROM_LOAD( "fantasyl.s2", 0x80000, 0x20000, CRC(f23837d8) SHA1(4048784f759781e50ae445ea61f1ca908e8e6ac1) ) // samples (8 bit unsigned)
ROM_LOAD( "fantasyl.s1", 0xc0000, 0x20000, CRC(1a324a69) SHA1(06f6877af6cd19bfaac8a4ea8057ef8faee276f5) )
- ROM_COPY( "audiocpu", 0xc0000, 0xe0000, 0x20000 )
+ ROM_COPY( "audiocpu", 0xc0000, 0xe0000, 0x20000 )
ROM_REGION( 0x480000, "gfx1", 0 ) // Sprites
ROMX_LOAD( "fantasyl.m00", 0x000000, 0x80000, CRC(82d819ff) SHA1(2b5b0759de8260eaa84ddded9dc2d12a6e0f5ec9) , ROM_GROUPWORD | ROM_SKIP(1) )
@@ -1135,14 +1082,13 @@ ROM_START( fantlanda )
ROM_REGION( 0x100000, "maincpu", 0 ) // Main CPU
ROM_LOAD16_BYTE( "fantasyl.ev2", 0x00000, 0x20000, CRC(f5bdca0e) SHA1(d05cf6f68d4d1a3dcc0171f7cf220c4920bd47bb) ) // 04.bin (was first half only)
ROM_LOAD16_BYTE( "fantasyl.od2", 0x00001, 0x20000, CRC(9db35023) SHA1(81e2accd67dcf8563a68b2c4e35526f23a40150c) ) // 03.bin (was first half only)
- ROM_COPY( "maincpu", 0x000000, 0x40000, 0x40000 )
ROM_LOAD16_BYTE( "02.bin", 0xe0000, 0x10000, CRC(8b835eed) SHA1(6a6b3fe116145f685b91dcd5301165f17973697c) )
ROM_LOAD16_BYTE( "01.bin", 0xe0001, 0x10000, CRC(4fa3eb8b) SHA1(56da42a4e2972a696ef28811116cbc20bb5ba3e8) )
ROM_REGION( 0x100000, "audiocpu", 0 ) // Sound CPU
ROM_LOAD( "fantasyl.s2", 0x80000, 0x20000, CRC(f23837d8) SHA1(4048784f759781e50ae445ea61f1ca908e8e6ac1) ) // 05.bin (was first half only)
ROM_LOAD( "fantasyl.s1", 0xc0000, 0x20000, CRC(1a324a69) SHA1(06f6877af6cd19bfaac8a4ea8057ef8faee276f5) ) // 06.bin (was first half only)
- ROM_COPY( "audiocpu", 0xc0000, 0xe0000, 0x20000 )
+ ROM_COPY( "audiocpu", 0xc0000, 0xe0000, 0x20000 )
ROM_REGION( 0x480000, "gfx1", 0 ) // Sprites
ROMX_LOAD( "fantasyl.m00", 0x000000, 0x80000, CRC(82d819ff) SHA1(2b5b0759de8260eaa84ddded9dc2d12a6e0f5ec9) , ROM_GROUPWORD | ROM_SKIP(1) )
@@ -1164,11 +1110,10 @@ ROM_END
***************************************************************************/
ROM_START( galaxygn )
- ROM_REGION( 0x100000, "maincpu", 0 ) // Main CPU
+ ROM_REGION( 0x80000, "maincpu", 0 ) // Main CPU
ROM_LOAD( "gg03.bin", 0x10000, 0x10000, CRC(9e469189) SHA1(07e5d36ca9665bdd13e3bb4241d34b9042371b79) )
ROM_LOAD( "gg02.bin", 0x20000, 0x10000, CRC(b87a438f) SHA1(96c39cc4d51a2fc0779f148971220117967173c0) )
- ROM_LOAD( "gg01.bin", 0xf0000, 0x10000, CRC(ad0e5b29) SHA1(f9a7ebce9f47a009af213e4e10811bb1c26f891a) )
- ROM_COPY( "maincpu",0xf0000, 0x70000, 0x10000 )
+ ROM_LOAD( "gg01.bin", 0x70000, 0x10000, CRC(ad0e5b29) SHA1(f9a7ebce9f47a009af213e4e10811bb1c26f891a) )
ROM_REGION( 0x100000, "audiocpu", 0 ) // Sound CPU
ROM_LOAD( "gg20.bin", 0xc0000, 0x10000, CRC(f5c65a85) SHA1(a094fa9531ea4e68ec0a448568e7d4b2307c8185) )
@@ -1285,15 +1230,13 @@ Notes:
*/
ROM_START( borntofi )
- ROM_REGION( 0x100000, "maincpu", 0 ) /* V20 */
+ ROM_REGION( 0x80000, "maincpu", 0 ) /* V20 */
ROM_LOAD( "3.bin", 0x10000, 0x10000, CRC(5f07f4a2) SHA1(240864d1d5d9e26d229bc21aa39ee03f4bd25814) )
ROM_LOAD( "2.bin", 0x20000, 0x10000, CRC(5d2b3395) SHA1(ac87f352f380b67802c26232824663063549ac7b) )
- ROM_LOAD( "1.bin", 0xf0000, 0x10000, CRC(0a5e2f32) SHA1(5167a85329e5ea35c686af85e44d62227cf5800e) )
- ROM_COPY( "maincpu", 0xf0000, 0x70000, 0x10000 )
+ ROM_LOAD( "1.bin", 0x70000, 0x10000, CRC(0a5e2f32) SHA1(5167a85329e5ea35c686af85e44d62227cf5800e) )
- ROM_REGION( 0x100000, "audiocpu", 0 ) /* 8088 */
- ROM_LOAD( "5.bin", 0xf8000, 0x08000, CRC(b5d587ce) SHA1(07687abd264ec80a6eb473cb3f3ab97ec6b365a2) )
- ROM_COPY( "audiocpu", 0xf8000, 0x08000, 0x08000 )
+ ROM_REGION( 0x10000, "audiocpu", 0 ) /* 8088 */
+ ROM_LOAD( "5.bin", 0x08000, 0x08000, CRC(b5d587ce) SHA1(07687abd264ec80a6eb473cb3f3ab97ec6b365a2) )
ROM_REGION( 0xc0000, "adpcm", 0 ) /* m5205 samples */
ROM_LOAD( "6.bin", 0x00000, 0x10000, CRC(731c523b) SHA1(b649a838ce70d5af607f8b9faf8b012e2ff1104b) )
@@ -1381,12 +1324,11 @@ Hardware info by f205v
***************************************************************************/
ROM_START( wheelrun )
- ROM_REGION( 0x100000, "maincpu", 0 ) // V20
+ ROM_REGION( 0x80000, "maincpu", 0 ) // V20
ROM_LOAD( "4.4", 0x30000, 0x10000, CRC(359303df) SHA1(583b70f65b775e99856ffda61334be3b85046ed1) )
ROM_LOAD( "3.3", 0x70000, 0x10000, CRC(c28d0b31) SHA1(add8c4ffe529755c101b72a3b0530e796948876b) )
- ROM_COPY( "maincpu", 0x70000, 0xf0000, 0x10000 )
- ROM_REGION( 0x100000, "audiocpu", 0 ) // Z80
+ ROM_REGION( 0x10000, "audiocpu", 0 ) // Z80
ROM_LOAD( "1.1", 0x00000, 0x10000, CRC(67b5f31f) SHA1(5553b132077686221fb7a21a0246fd55cb443332) ) // 1xxxxxxxxxxxxxxx = 0xFF
ROM_REGION( 0xc0000, "gfx1",0 ) // gfx
@@ -1425,7 +1367,7 @@ ROM_START( wheelrun )
ROM_END
-GAME( 19??, borntofi, 0, borntofi, borntofi, fantland_state, empty_init, ROT0, "International Games", "Born To Fight", MACHINE_SUPPORTS_SAVE )
+GAME( 19??, borntofi, 0, borntofi, borntofi, borntofi_state, empty_init, ROT0, "International Games", "Born To Fight", MACHINE_SUPPORTS_SAVE )
GAME( 19??, fantland, 0, fantland, fantland, fantland_state, empty_init, ROT0, "Electronic Devices Italy", "Fantasy Land (set 1)", MACHINE_SUPPORTS_SAVE )
GAME( 19??, fantlanda, fantland, fantland, fantland, fantland_state, empty_init, ROT0, "Electronic Devices Italy", "Fantasy Land (set 2)", MACHINE_SUPPORTS_SAVE )
GAME( 19??, wheelrun, 0, wheelrun, wheelrun, fantland_state, empty_init, ROT0, "International Games", "Wheels Runner", MACHINE_SUPPORTS_SAVE )
diff --git a/src/mame/drivers/fanucspmg.cpp b/src/mame/drivers/fanucspmg.cpp
index 9733705191d..d651d1d2a8d 100644
--- a/src/mame/drivers/fanucspmg.cpp
+++ b/src/mame/drivers/fanucspmg.cpp
@@ -548,14 +548,6 @@ the keypad symbols seem to use a different matrix pattern from the rest?
#define MAINCPU_TAG "maincpu"
#define SUBCPU_TAG "subcpu"
-#define USART0_TAG "usart0"
-#define USART1_TAG "usart1"
-#define USART2_TAG "usart2"
-#define USART3_TAG "usart3"
-#define PIT0_TAG "pit0"
-#define PIT1_TAG "pit1"
-#define PIC0_TAG "pic0"
-#define PIC1_TAG "pic1"
#define DMAC_TAG "dmac"
#define CRTC_TAG "crtc"
#define FDC_TAG "fdc"
@@ -570,14 +562,9 @@ public:
: driver_device(mconfig, type, tag)
, m_maincpu(*this, MAINCPU_TAG)
, m_subcpu(*this, SUBCPU_TAG)
- , m_usart0(*this, USART0_TAG)
- , m_usart1(*this, USART1_TAG)
- , m_usart2(*this, USART2_TAG)
- , m_usart3(*this, USART3_TAG)
- , m_pit0(*this, PIT0_TAG)
- , m_pit1(*this, PIT1_TAG)
- , m_pic0(*this, PIC0_TAG)
- , m_pic1(*this, PIC1_TAG)
+ , m_usart(*this, "usart%u", 0U)
+ , m_pit(*this, "pit%u", 0U)
+ , m_pic(*this, "pic%u", 0U)
, m_dmac(*this, DMAC_TAG)
, m_crtc(*this, CRTC_TAG)
, m_fdc(*this, FDC_TAG)
@@ -593,14 +580,9 @@ public:
private:
required_device<i8086_cpu_device> m_maincpu;
required_device<i8085a_cpu_device> m_subcpu;
- required_device<i8251_device> m_usart0;
- required_device<i8251_device> m_usart1;
- required_device<i8251_device> m_usart2;
- required_device<i8251_device> m_usart3;
- required_device<pit8253_device> m_pit0;
- required_device<pit8253_device> m_pit1;
- required_device<pic8259_device> m_pic0;
- required_device<pic8259_device> m_pic1;
+ required_device_array<i8251_device, 4> m_usart;
+ required_device_array<pit8253_device, 2> m_pit;
+ required_device_array<pic8259_device, 2> m_pic;
required_device<i8257_device> m_dmac;
required_device<mc6845_device> m_crtc;
required_device<upd765a_device> m_fdc;
@@ -676,7 +658,7 @@ WRITE8_MEMBER(fanucspmg_state::shared_w)
READ8_MEMBER(fanucspmg_state::get_slave_ack)
{
if(offset == 7)
- return m_pic1->acknowledge();
+ return m_pic[1]->acknowledge();
return 0x00;
}
@@ -725,18 +707,18 @@ void fanucspmg_state::maincpu_mem(address_map &map)
map(0x80000, 0x81fff).ram(); // believed to be shared RAM with a CPU inside the Program File
map(0x88000, 0x88001).noprw(); // Program File "ready" bit
- map(0xf0000, 0xf0003).rw(m_pic0, FUNC(pic8259_device::read), FUNC(pic8259_device::write)).umask16(0x00ff);
+ map(0xf0000, 0xf0003).rw(m_pic[0], FUNC(pic8259_device::read), FUNC(pic8259_device::write)).umask16(0x00ff);
map(0xf0004, 0xf0007).m(m_fdc, FUNC(upd765a_device::map)).umask16(0x00ff);
- map(0xf0008, 0xf000f).rw(m_pit0, FUNC(pit8253_device::read), FUNC(pit8253_device::write)).umask16(0x00ff);
- map(0xf0010, 0xf0013).rw(m_usart0, FUNC(i8251_device::read), FUNC(i8251_device::write)).umask16(0x00ff);
- map(0xf0014, 0xf0017).rw(m_usart1, FUNC(i8251_device::read), FUNC(i8251_device::write)).umask16(0x00ff);
- map(0xf0018, 0xf001b).rw(m_usart2, FUNC(i8251_device::read), FUNC(i8251_device::write)).umask16(0x00ff);
- map(0xf001c, 0xf001f).rw(m_usart3, FUNC(i8251_device::read), FUNC(i8251_device::write)).umask16(0x00ff);
+ map(0xf0008, 0xf000f).rw(m_pit[0], FUNC(pit8253_device::read), FUNC(pit8253_device::write)).umask16(0x00ff);
+ map(0xf0010, 0xf0013).rw(m_usart[0], FUNC(i8251_device::read), FUNC(i8251_device::write)).umask16(0x00ff);
+ map(0xf0014, 0xf0017).rw(m_usart[1], FUNC(i8251_device::read), FUNC(i8251_device::write)).umask16(0x00ff);
+ map(0xf0018, 0xf001b).rw(m_usart[2], FUNC(i8251_device::read), FUNC(i8251_device::write)).umask16(0x00ff);
+ map(0xf001c, 0xf001f).rw(m_usart[3], FUNC(i8251_device::read), FUNC(i8251_device::write)).umask16(0x00ff);
map(0xf0020, 0xf0029).rw(m_dmac, FUNC(i8257_device::read), FUNC(i8257_device::write));
map(0xf0042, 0xf0043).r(FUNC(fanucspmg_state::magic_r));
map(0xf0046, 0xf0046).w(FUNC(fanucspmg_state::dma_page_w));
- map(0xf0048, 0xf004f).rw(m_pit1, FUNC(pit8253_device::read), FUNC(pit8253_device::write)).umask16(0x00ff);
- map(0xf2000, 0xf2003).rw(m_pic1, FUNC(pic8259_device::read), FUNC(pic8259_device::write)).umask16(0x00ff);
+ map(0xf0048, 0xf004f).rw(m_pit[1], FUNC(pit8253_device::read), FUNC(pit8253_device::write)).umask16(0x00ff);
+ map(0xf2000, 0xf2003).rw(m_pic[1], FUNC(pic8259_device::read), FUNC(pic8259_device::write)).umask16(0x00ff);
map(0xf8000, 0xf9fff).rw(FUNC(fanucspmg_state::shared_r), FUNC(fanucspmg_state::shared_w));
map(0xfc000, 0xfffff).rom().region(MAINCPU_TAG, 0);
@@ -967,7 +949,7 @@ MACHINE_CONFIG_START(fanucspmg_state::fanucspmg)
MCFG_DEVICE_ADD(MAINCPU_TAG, I8086, XTAL(15'000'000)/3)
MCFG_DEVICE_PROGRAM_MAP(maincpu_mem)
MCFG_DEVICE_IO_MAP(maincpu_io)
- MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE(PIC0_TAG, pic8259_device, inta_cb)
+ MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE("pic0", pic8259_device, inta_cb)
MCFG_I8086_ESC_OPCODE_HANDLER(WRITE32("i8087", i8087_device, insn_w))
MCFG_I8086_ESC_DATA_HANDLER(WRITE32("i8087", i8087_device, addr_w))
@@ -980,19 +962,20 @@ MACHINE_CONFIG_START(fanucspmg_state::fanucspmg)
MCFG_DEVICE_ADD(SUBCPU_TAG, I8085A, XTAL(16'000'000)/2/2)
MCFG_DEVICE_PROGRAM_MAP(subcpu_mem)
- MCFG_DEVICE_ADD(USART0_TAG, I8251, 0)
- MCFG_DEVICE_ADD(USART1_TAG, I8251, 0)
- MCFG_DEVICE_ADD(USART2_TAG, I8251, 0)
- MCFG_DEVICE_ADD(USART3_TAG, I8251, 0)
+ I8251(config, m_usart[0], 0);
+ I8251(config, m_usart[1], 0);
+ I8251(config, m_usart[2], 0);
+ I8251(config, m_usart[3], 0);
- MCFG_DEVICE_ADD(PIT0_TAG, PIT8253, 0)
- MCFG_PIT8253_CLK0(XTAL(15'000'000)/12)
- MCFG_PIT8253_CLK1(XTAL(15'000'000)/12)
- MCFG_PIT8253_CLK2(XTAL(15'000'000)/12)
- MCFG_DEVICE_ADD(PIT1_TAG, PIT8253, 0)
- MCFG_PIT8253_CLK0(XTAL(15'000'000)/12)
- MCFG_PIT8253_CLK1(XTAL(15'000'000)/12)
- MCFG_PIT8253_CLK2(XTAL(15'000'000)/12)
+ PIT8253(config, m_pit[0], 0);
+ m_pit[0]->set_clk<0>(XTAL(15'000'000)/12);
+ m_pit[0]->set_clk<1>(XTAL(15'000'000)/12);
+ m_pit[0]->set_clk<2>(XTAL(15'000'000)/12);
+
+ PIT8253(config, m_pit[1], 0);
+ m_pit[1]->set_clk<0>(XTAL(15'000'000)/12);
+ m_pit[1]->set_clk<1>(XTAL(15'000'000)/12);
+ m_pit[1]->set_clk<2>(XTAL(15'000'000)/12);
I8257(config, m_dmac, XTAL(15'000'000) / 5);
m_dmac->out_hrq_cb().set(FUNC(fanucspmg_state::hrq_w));
@@ -1002,17 +985,17 @@ MACHINE_CONFIG_START(fanucspmg_state::fanucspmg)
m_dmac->in_ior_cb<0>().set(FUNC(fanucspmg_state::fdcdma_r));
m_dmac->out_iow_cb<0>().set(FUNC(fanucspmg_state::fdcdma_w));
- MCFG_DEVICE_ADD(PIC0_TAG, PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE("maincpu", 0))
- MCFG_PIC8259_IN_SP_CB(CONSTANT(1))
- MCFG_PIC8259_CASCADE_ACK_CB(READ8(*this, fanucspmg_state, get_slave_ack))
+ PIC8259(config, m_pic[0], 0);
+ m_pic[0]->out_int_callback().set_inputline(m_maincpu, 0);
+ m_pic[0]->in_sp_callback().set_constant(1);
+ m_pic[0]->read_slave_ack_callback().set(FUNC(fanucspmg_state::get_slave_ack));
- MCFG_DEVICE_ADD(PIC1_TAG, PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(WRITELINE(PIC0_TAG, pic8259_device, ir7_w))
- MCFG_PIC8259_IN_SP_CB(CONSTANT(0))
+ PIC8259(config, m_pic[1], 0);
+ m_pic[1]->out_int_callback().set(m_pic[0], FUNC(pic8259_device::ir7_w));
+ m_pic[1]->in_sp_callback().set_constant(0);
UPD765A(config, m_fdc, true, true);
- m_fdc->intrq_wr_callback().set(m_pic0, FUNC(pic8259_device::ir3_w));
+ m_fdc->intrq_wr_callback().set(m_pic[0], FUNC(pic8259_device::ir3_w));
m_fdc->drq_wr_callback().set(m_dmac, FUNC(i8257_device::dreq0_w));
MCFG_FLOPPY_DRIVE_ADD(FDC_TAG":0", fanuc_floppies, "525dd", fanucspmg_state::floppy_formats)
MCFG_FLOPPY_DRIVE_ADD(FDC_TAG":1", fanuc_floppies, "525dd", fanucspmg_state::floppy_formats)
diff --git a/src/mame/drivers/fastinvaders.cpp b/src/mame/drivers/fastinvaders.cpp
index 0bb623a7a43..be7a1c7abc1 100644
--- a/src/mame/drivers/fastinvaders.cpp
+++ b/src/mame/drivers/fastinvaders.cpp
@@ -649,11 +649,11 @@ MACHINE_CONFIG_START(fastinvaders_state::fastinvaders)
// MCFG_DEVICE_IO_MAP(fastinvaders_io_map)
// MCFG_DEVICE_VBLANK_INT_DRIVER("screen", fastinvaders_state, irq0_line_hold)
MCFG_I8085A_SID(READLINE(*this, fastinvaders_state, sid_read))
-MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE("pic8259", pic8259_device, inta_cb)
-MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", fastinvaders_state, scanline_timer, "screen", 0, 1)
+ MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE("pic8259", pic8259_device, inta_cb)
+ MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", fastinvaders_state, scanline_timer, "screen", 0, 1)
- MCFG_DEVICE_ADD("pic8259", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE("maincpu", 0))
+ PIC8259(config, m_pic8259, 0);
+ m_pic8259->out_int_callback().set_inputline(m_maincpu, 0);
I8257(config, m_dma8257, 6144100);
m_dma8257->in_memr_cb().set(FUNC(fastinvaders_state::memory_read_byte));
diff --git a/src/mame/drivers/fk1.cpp b/src/mame/drivers/fk1.cpp
index 982f5155c43..e24b4e2a819 100644
--- a/src/mame/drivers/fk1.cpp
+++ b/src/mame/drivers/fk1.cpp
@@ -430,13 +430,13 @@ MACHINE_CONFIG_START(fk1_state::fk1)
MCFG_PALETTE_ADD_MONOCHROME("palette")
- MCFG_DEVICE_ADD("pit8253", PIT8253, 0)
- MCFG_PIT8253_CLK0(50)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, fk1_state, fk1_pit_out0))
- MCFG_PIT8253_CLK1(1000000)
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(*this, fk1_state, fk1_pit_out1))
- MCFG_PIT8253_CLK2(0)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, fk1_state, fk1_pit_out2))
+ pit8253_device &pit8253(PIT8253(config, "pit8253", 0));
+ pit8253.set_clk<0>(50);
+ pit8253.out_handler<0>().set(FUNC(fk1_state::fk1_pit_out0));
+ pit8253.set_clk<1>(1000000);
+ pit8253.out_handler<1>().set(FUNC(fk1_state::fk1_pit_out1));
+ pit8253.set_clk<2>(0);
+ pit8253.out_handler<2>().set(FUNC(fk1_state::fk1_pit_out2));
i8255_device &ppi1(I8255(config, "ppi8255_1"));
ppi1.in_pa_callback().set(FUNC(fk1_state::fk1_ppi_1_a_r));
@@ -461,7 +461,7 @@ MACHINE_CONFIG_START(fk1_state::fk1)
ppi3.out_pc_callback().set(FUNC(fk1_state::fk1_ppi_3_c_w));
/* uart */
- MCFG_DEVICE_ADD("uart", I8251, 0)
+ I8251(config, "uart", 0);
/* internal ram */
RAM(config, RAM_TAG).set_default_size("80K"); // 64 + 16
diff --git a/src/mame/drivers/fmtowns.cpp b/src/mame/drivers/fmtowns.cpp
index 4d4c470d875..118dedd4ce7 100644
--- a/src/mame/drivers/fmtowns.cpp
+++ b/src/mame/drivers/fmtowns.cpp
@@ -776,8 +776,6 @@ READ8_MEMBER(towns_state::towns_port60_r)
WRITE8_MEMBER(towns_state::towns_port60_w)
{
- //device_t* dev = m_pic_master;
-
if(data & 0x80)
{
//towns_pic_irq(dev,0);
@@ -2793,28 +2791,28 @@ MACHINE_CONFIG_START(towns_state::towns_base)
MCFG_SOUND_ROUTE(1, "rspeaker", 1.00)
SPEAKER_SOUND(config, "speaker").add_route(ALL_OUTPUTS, "lspeaker", 0.50).add_route(ALL_OUTPUTS, "rspeaker", 0.50);
- MCFG_DEVICE_ADD("pit", PIT8253, 0)
- MCFG_PIT8253_CLK0(307200)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, towns_state, towns_pit_out0_changed))
- MCFG_PIT8253_CLK1(307200)
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(*this, towns_state, towns_pit_out1_changed))
- MCFG_PIT8253_CLK2(307200)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, towns_state, pit_out2_changed))
-
- MCFG_DEVICE_ADD("pit2", PIT8253, 0)
- MCFG_PIT8253_CLK0(307200) // reserved
- MCFG_PIT8253_CLK1(1228800) // RS-232
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(*this, towns_state, pit2_out1_changed))
- MCFG_PIT8253_CLK2(307200) // reserved
-
- MCFG_DEVICE_ADD("pic8259_master", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE("maincpu", 0))
- MCFG_PIC8259_IN_SP_CB(CONSTANT(1))
- MCFG_PIC8259_CASCADE_ACK_CB(READ8(*this, towns_state, get_slave_ack))
-
- MCFG_DEVICE_ADD("pic8259_slave", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(WRITELINE("pic8259_master", pic8259_device, ir7_w))
- MCFG_PIC8259_IN_SP_CB(CONSTANT(0))
+ PIT8253(config, m_pit, 0);
+ m_pit->set_clk<0>(307200);
+ m_pit->out_handler<0>().set(FUNC(towns_state::towns_pit_out0_changed));
+ m_pit->set_clk<1>(307200);
+ m_pit->out_handler<1>().set(FUNC(towns_state::towns_pit_out1_changed));
+ m_pit->set_clk<2>(307200);
+ m_pit->out_handler<2>().set(FUNC(towns_state::pit_out2_changed));
+
+ pit8253_device &pit2(PIT8253(config, "pit2", 0));
+ pit2.set_clk<0>(307200); // reserved
+ pit2.set_clk<1>(1228800); // RS-232
+ pit2.out_handler<1>().set(FUNC(towns_state::pit2_out1_changed));
+ pit2.set_clk<2>(307200); // reserved
+
+ PIC8259(config, m_pic_master, 0);
+ m_pic_master->out_int_callback().set_inputline(m_maincpu, 0);
+ m_pic_master->in_sp_callback().set_constant(1);
+ m_pic_master->read_slave_ack_callback().set(FUNC(towns_state::get_slave_ack));
+
+ PIC8259(config, m_pic_slave, 0);
+ m_pic_slave->out_int_callback().set(m_pic_master, FUNC(pic8259_device::ir7_w));
+ m_pic_slave->in_sp_callback().set_constant(0);
MB8877(config, m_fdc, 8'000'000 / 4); // clock unknown
m_fdc->intrq_wr_callback().set(FUNC(towns_state::mb8877a_irq_w));
diff --git a/src/mame/drivers/hp64k.cpp b/src/mame/drivers/hp64k.cpp
index 23139325f1d..9ae8ad5ee7c 100644
--- a/src/mame/drivers/hp64k.cpp
+++ b/src/mame/drivers/hp64k.cpp
@@ -1449,29 +1449,31 @@ MACHINE_CONFIG_START(hp64k_state::hp64k)
m_rs232->dcd_handler().set(FUNC(hp64k_state::hp64k_rs232_dcd_w));
m_rs232->cts_handler().set(FUNC(hp64k_state::hp64k_rs232_cts_w));
- MCFG_DEVICE_ADD("phi", PHI, 0)
- MCFG_PHI_INT_WRITE_CB(WRITELINE(*this, hp64k_state, hp64k_phi_int_w))
- MCFG_PHI_DMARQ_WRITE_CB(WRITELINE("cpu" , hp_5061_3011_cpu_device, halt_w))
- MCFG_PHI_SYS_CNTRL_READ_CB(READLINE(*this, hp64k_state, hp64k_phi_sys_ctrl_r))
- MCFG_PHI_DIO_READWRITE_CB(READ8(IEEE488_TAG, ieee488_device, dio_r), WRITE8(IEEE488_TAG, ieee488_device, host_dio_w))
- MCFG_PHI_EOI_WRITE_CB(WRITELINE(IEEE488_TAG, ieee488_device, host_eoi_w))
- MCFG_PHI_DAV_WRITE_CB(WRITELINE(IEEE488_TAG, ieee488_device, host_dav_w))
- MCFG_PHI_NRFD_WRITE_CB(WRITELINE(IEEE488_TAG, ieee488_device, host_nrfd_w))
- MCFG_PHI_NDAC_WRITE_CB(WRITELINE(IEEE488_TAG, ieee488_device, host_ndac_w))
- MCFG_PHI_IFC_WRITE_CB(WRITELINE(IEEE488_TAG, ieee488_device, host_ifc_w))
- MCFG_PHI_SRQ_WRITE_CB(WRITELINE(IEEE488_TAG, ieee488_device, host_srq_w))
- MCFG_PHI_ATN_WRITE_CB(WRITELINE(IEEE488_TAG, ieee488_device, host_atn_w))
- MCFG_PHI_REN_WRITE_CB(WRITELINE(IEEE488_TAG, ieee488_device, host_ren_w))
+ PHI(config, m_phi, 0);
+ m_phi->int_write_cb().set(FUNC(hp64k_state::hp64k_phi_int_w));
+ m_phi->dmarq_write_cb().set(m_cpu, FUNC(hp_5061_3011_cpu_device::halt_w));
+ m_phi->sys_cntrl_read_cb().set(FUNC(hp64k_state::hp64k_phi_sys_ctrl_r));
+ m_phi->dio_read_cb().set(IEEE488_TAG, FUNC(ieee488_device::dio_r));
+ m_phi->dio_write_cb().set(IEEE488_TAG, FUNC(ieee488_device::host_dio_w));
+ m_phi->signal_write_cb<phi_device::PHI_488_EOI>().set(IEEE488_TAG, FUNC(ieee488_device::host_eoi_w));
+ m_phi->signal_write_cb<phi_device::PHI_488_DAV>().set(IEEE488_TAG, FUNC(ieee488_device::host_dav_w));
+ m_phi->signal_write_cb<phi_device::PHI_488_NRFD>().set(IEEE488_TAG, FUNC(ieee488_device::host_nrfd_w));
+ m_phi->signal_write_cb<phi_device::PHI_488_NDAC>().set(IEEE488_TAG, FUNC(ieee488_device::host_ndac_w));
+ m_phi->signal_write_cb<phi_device::PHI_488_IFC>().set(IEEE488_TAG, FUNC(ieee488_device::host_ifc_w));
+ m_phi->signal_write_cb<phi_device::PHI_488_SRQ>().set(IEEE488_TAG, FUNC(ieee488_device::host_srq_w));
+ m_phi->signal_write_cb<phi_device::PHI_488_ATN>().set(IEEE488_TAG, FUNC(ieee488_device::host_atn_w));
+ m_phi->signal_write_cb<phi_device::PHI_488_REN>().set(IEEE488_TAG, FUNC(ieee488_device::host_ren_w));
+
MCFG_IEEE488_BUS_ADD()
- MCFG_IEEE488_EOI_CALLBACK(WRITELINE("phi", phi_device, eoi_w))
- MCFG_IEEE488_DAV_CALLBACK(WRITELINE("phi", phi_device, dav_w))
- MCFG_IEEE488_NRFD_CALLBACK(WRITELINE("phi", phi_device, nrfd_w))
- MCFG_IEEE488_NDAC_CALLBACK(WRITELINE("phi", phi_device, ndac_w))
- MCFG_IEEE488_IFC_CALLBACK(WRITELINE("phi", phi_device, ifc_w))
- MCFG_IEEE488_SRQ_CALLBACK(WRITELINE("phi", phi_device, srq_w))
- MCFG_IEEE488_ATN_CALLBACK(WRITELINE("phi", phi_device, atn_w))
- MCFG_IEEE488_REN_CALLBACK(WRITELINE("phi", phi_device, ren_w))
- MCFG_IEEE488_DIO_CALLBACK(WRITE8("phi", phi_device , bus_dio_w))
+ MCFG_IEEE488_EOI_CALLBACK(WRITELINE(m_phi, phi_device, eoi_w))
+ MCFG_IEEE488_DAV_CALLBACK(WRITELINE(m_phi, phi_device, dav_w))
+ MCFG_IEEE488_NRFD_CALLBACK(WRITELINE(m_phi, phi_device, nrfd_w))
+ MCFG_IEEE488_NDAC_CALLBACK(WRITELINE(m_phi, phi_device, ndac_w))
+ MCFG_IEEE488_IFC_CALLBACK(WRITELINE(m_phi, phi_device, ifc_w))
+ MCFG_IEEE488_SRQ_CALLBACK(WRITELINE(m_phi, phi_device, srq_w))
+ MCFG_IEEE488_ATN_CALLBACK(WRITELINE(m_phi, phi_device, atn_w))
+ MCFG_IEEE488_REN_CALLBACK(WRITELINE(m_phi, phi_device, ren_w))
+ MCFG_IEEE488_DIO_CALLBACK(WRITE8(m_phi, phi_device , bus_dio_w))
MCFG_IEEE488_SLOT_ADD("ieee_rem" , 0 , remote488_devices , nullptr)
MACHINE_CONFIG_END
diff --git a/src/mame/drivers/hp9k_3xx.cpp b/src/mame/drivers/hp9k_3xx.cpp
index 4c05ae2c237..cea948ebe22 100644
--- a/src/mame/drivers/hp9k_3xx.cpp
+++ b/src/mame/drivers/hp9k_3xx.cpp
@@ -285,6 +285,9 @@ void hp9k3xx_state::add_dio32_bus(machine_config &config)
void hp9k3xx_state::set_bus_error(uint32_t address, bool write, uint16_t mem_mask)
{
+ if (m_maincpu->m68851_buserror())
+ return;
+
if (m_bus_error)
return;
diff --git a/src/mame/drivers/i7000.cpp b/src/mame/drivers/i7000.cpp
index 20a6a684eaa..f80420d8a4f 100644
--- a/src/mame/drivers/i7000.cpp
+++ b/src/mame/drivers/i7000.cpp
@@ -367,17 +367,16 @@ MACHINE_CONFIG_START(i7000_state::i7000)
/* sound hardware */
SPEAKER(config, "mono").front_center();
- MCFG_DEVICE_ADD("speaker", SPEAKER_SOUND)
- MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
+ SPEAKER_SOUND(config, "speaker").add_route(ALL_OUTPUTS, "mono", 0.50);
/* Programmable timer */
- MCFG_DEVICE_ADD("pit8253", PIT8253, 0)
-// MCFG_PIT8253_CLK0(XTAL(4'000'000) / 2) /* TODO: verify on PCB */
-// MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, i7000_state,i7000_pit_out0))
-// MCFG_PIT8253_CLK1(XTAL(4'000'000) / 2) /* TODO: verify on PCB */
-// MCFG_PIT8253_OUT1_HANDLER(WRITELINE(*this, i7000_state,i7000_pit_out1))
- MCFG_PIT8253_CLK2(XTAL(4'000'000) / 2) /* TODO: verify on PCB */
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE("speaker", speaker_sound_device, level_w))
+ pit8253_device &pit8253(PIT8253(config, "pit8253", 0));
+// pit8253.set_clk<0>(XTAL(4'000'000) / 2); /* TODO: verify on PCB */
+// pit8253.out_handler<0>().set(FUNC(i7000_state::i7000_pit_out0));
+// pit8253.set_clk<1>(XTAL(4'000'000) / 2); /* TODO: verify on PCB */
+// pit8253.out_handler<1>().set(FUNC(i7000_state::i7000_pit_out1));
+ pit8253.set_clk<2>(XTAL(4'000'000) / 2); /* TODO: verify on PCB */
+ pit8253.out_handler<2>().set("speaker", FUNC(speaker_sound_device::level_w));
/* Keyboard interface */
i8279_device &kbdc(I8279(config, "i8279", 4000000)); /* guessed value. TODO: verify on PCB */
diff --git a/src/mame/drivers/ibm6580.cpp b/src/mame/drivers/ibm6580.cpp
index 747218fc43e..6bad9e72d5b 100644
--- a/src/mame/drivers/ibm6580.cpp
+++ b/src/mame/drivers/ibm6580.cpp
@@ -899,8 +899,8 @@ MACHINE_CONFIG_START(ibm6580_state::ibm6580)
MCFG_PALETTE_ADD("palette", 3)
MCFG_PALETTE_INIT_OWNER(ibm6580_state, ibm6580)
- MCFG_DEVICE_ADD("pic8259", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE("maincpu", 0))
+ PIC8259(config, m_pic8259, 0);
+ m_pic8259->out_int_callback().set_inputline(m_maincpu, 0);
i8255_device &ppi(I8255(config, "ppi8255"));
ppi.in_pa_callback().set(FUNC(ibm6580_state::ppi_a_r));
@@ -926,7 +926,7 @@ MACHINE_CONFIG_START(ibm6580_state::ibm6580)
UPD765A(config, m_fdc, false, false);
m_fdc->intrq_wr_callback().set(FUNC(ibm6580_state::floppy_intrq));
-// m_fdc->intrq_wr_callback().append("pic8259", FUNC(pic8259_device::ir4_w));
+// m_fdc->intrq_wr_callback().append(m_pic8259, FUNC(pic8259_device::ir4_w));
m_fdc->drq_wr_callback().set(m_dma8257, FUNC(i8257_device::dreq0_w));
MCFG_FLOPPY_DRIVE_ADD(UPD765_TAG ":0", dw_floppies, "8sssd", floppy_image_device::default_floppy_formats)
MCFG_FLOPPY_DRIVE_ADD(UPD765_TAG ":1", dw_floppies, "8sssd", floppy_image_device::default_floppy_formats)
@@ -935,8 +935,8 @@ MACHINE_CONFIG_START(ibm6580_state::ibm6580)
upd8251a.txd_handler().set("rs232a", FUNC(rs232_port_device::write_txd));
upd8251a.dtr_handler().set("rs232a", FUNC(rs232_port_device::write_dtr));
upd8251a.rts_handler().set("rs232a", FUNC(rs232_port_device::write_rts));
- upd8251a.rxrdy_handler().set("pic8259", FUNC(pic8259_device::ir2_w));
- upd8251a.txrdy_handler().set("pic8259", FUNC(pic8259_device::ir2_w));
+ upd8251a.rxrdy_handler().set(m_pic8259, FUNC(pic8259_device::ir2_w));
+ upd8251a.txrdy_handler().set(m_pic8259, FUNC(pic8259_device::ir2_w));
rs232_port_device &rs232a(RS232_PORT(config, "rs232a", default_rs232_devices, nullptr));
rs232a.rxd_handler().set("upd8251a", FUNC(i8251_device::write_rxd));
@@ -947,8 +947,8 @@ MACHINE_CONFIG_START(ibm6580_state::ibm6580)
upd8251b.txd_handler().set("rs232b", FUNC(rs232_port_device::write_txd));
upd8251b.dtr_handler().set("rs232b", FUNC(rs232_port_device::write_dtr));
upd8251b.rts_handler().set("rs232b", FUNC(rs232_port_device::write_rts));
- upd8251b.rxrdy_handler().set("pic8259", FUNC(pic8259_device::ir2_w));
- upd8251b.txrdy_handler().set("pic8259", FUNC(pic8259_device::ir2_w));
+ upd8251b.rxrdy_handler().set(m_pic8259, FUNC(pic8259_device::ir2_w));
+ upd8251b.txrdy_handler().set(m_pic8259, FUNC(pic8259_device::ir2_w));
rs232_port_device &rs232b(RS232_PORT(config, "rs232b", default_rs232_devices, nullptr));
rs232b.rxd_handler().set("upd8251b", FUNC(i8251_device::write_rxd));
diff --git a/src/mame/drivers/ibmpcjr.cpp b/src/mame/drivers/ibmpcjr.cpp
index 7e5f16ed9c0..8829ed707c6 100644
--- a/src/mame/drivers/ibmpcjr.cpp
+++ b/src/mame/drivers/ibmpcjr.cpp
@@ -599,25 +599,25 @@ void pcjr_state::ibmpcjx_io(address_map &map)
MACHINE_CONFIG_START(pcjr_state::ibmpcjr)
/* basic machine hardware */
- MCFG_DEVICE_ADD("maincpu", I8088, 4900000)
- MCFG_DEVICE_PROGRAM_MAP(ibmpcjr_map)
- MCFG_DEVICE_IO_MAP(ibmpcjr_io)
- MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE("pic8259", pic8259_device, inta_cb)
+ I8088(config, m_maincpu, 4900000);
+ m_maincpu->set_addrmap(AS_PROGRAM, &pcjr_state::ibmpcjr_map);
+ m_maincpu->set_addrmap(AS_IO, &pcjr_state::ibmpcjr_io);
+ m_maincpu->set_irq_acknowledge_callback("pic8259", FUNC(pic8259_device::inta_cb));
/*
On the PC Jr the input for clock 1 seems to be selectable
based on bit 4(/5?) written to output port A0h. This is not
supported yet.
*/
- MCFG_DEVICE_ADD("pit8253", PIT8253, 0)
- MCFG_PIT8253_CLK0(XTAL(14'318'181)/12)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(m_pic8259, pic8259_device, ir0_w))
- MCFG_PIT8253_CLK1(XTAL(14'318'181)/12)
- MCFG_PIT8253_CLK2(XTAL(14'318'181)/12)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, pcjr_state, out2_changed))
-
- MCFG_DEVICE_ADD(m_pic8259, PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(WRITELINE(*this, pcjr_state, pic8259_set_int_line))
+ PIT8253(config, m_pit8253, 0);
+ m_pit8253->set_clk<0>(XTAL(14'318'181)/12);
+ m_pit8253->out_handler<0>().set(m_pic8259, FUNC(pic8259_device::ir0_w));
+ m_pit8253->set_clk<1>(XTAL(14'318'181)/12);
+ m_pit8253->set_clk<2>(XTAL(14'318'181)/12);
+ m_pit8253->out_handler<2>().set(FUNC(pcjr_state::out2_changed));
+
+ PIC8259(config, m_pic8259, 0);
+ m_pic8259->out_int_callback().set(FUNC(pcjr_state::pic8259_set_int_line));
i8255_device &ppi(I8255(config, "ppi8255"));
ppi.in_pa_callback().set_constant(0xff);
diff --git a/src/mame/drivers/if800.cpp b/src/mame/drivers/if800.cpp
index 5ca27f8f116..e218ec31a65 100644
--- a/src/mame/drivers/if800.cpp
+++ b/src/mame/drivers/if800.cpp
@@ -97,7 +97,7 @@ MACHINE_CONFIG_START(if800_state::if800)
MCFG_DEVICE_IO_MAP(if800_io)
-// MCFG_PIC8259_ADD( "pic8259", if800_pic8259_config )
+// PIC8259(config, "pic8259", 0);
MCFG_DEVICE_ADD("upd7220", UPD7220, 8000000/4)
MCFG_DEVICE_ADDRESS_MAP(0, upd7220_map)
MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(if800_state, hgdc_display_pixels)
diff --git a/src/mame/drivers/iq151.cpp b/src/mame/drivers/iq151.cpp
index 0c2f60197c7..72277e40d77 100644
--- a/src/mame/drivers/iq151.cpp
+++ b/src/mame/drivers/iq151.cpp
@@ -390,11 +390,11 @@ static void iq151_cart(device_slot_interface &device)
MACHINE_CONFIG_START(iq151_state::iq151)
/* basic machine hardware */
- MCFG_DEVICE_ADD("maincpu",I8080, XTAL(2'000'000))
- MCFG_DEVICE_PROGRAM_MAP(iq151_mem)
- MCFG_DEVICE_IO_MAP(iq151_io)
- MCFG_DEVICE_VBLANK_INT_DRIVER("screen", iq151_state, iq151_vblank_interrupt)
- MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE("pic8259", pic8259_device, inta_cb)
+ I8080(config, m_maincpu, XTAL(2'000'000));
+ m_maincpu->set_addrmap(AS_PROGRAM, &iq151_state::iq151_mem);
+ m_maincpu->set_addrmap(AS_IO, &iq151_state::iq151_io);
+ m_maincpu->set_vblank_int("screen", FUNC(iq151_state::iq151_vblank_interrupt));
+ m_maincpu->set_irq_acknowledge_callback("pic8259", FUNC(pic8259_device::inta_cb));
/* video hardware */
MCFG_SCREEN_ADD_MONOCHROME("screen", RASTER, rgb_t::green())
@@ -412,8 +412,8 @@ MACHINE_CONFIG_START(iq151_state::iq151)
MCFG_DEVICE_ADD("speaker", SPEAKER_SOUND)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
- MCFG_DEVICE_ADD("pic8259", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE("maincpu", 0))
+ PIC8259(config, m_pic, 0);
+ m_pic->out_int_callback().set_inputline(m_maincpu, 0);
i8255_device &ppi(I8255(config, "ppi8255"));
ppi.in_pa_callback().set(FUNC(iq151_state::keyboard_row_r));
@@ -431,43 +431,43 @@ MACHINE_CONFIG_START(iq151_state::iq151)
MCFG_DEVICE_ADD("slot1", IQ151CART_SLOT, 0)
MCFG_DEVICE_SLOT_INTERFACE(iq151_cart, nullptr, false)
MCFG_IQ151CART_SLOT_SCREEN_TAG("screen")
- MCFG_IQ151CART_SLOT_OUT_IRQ0_CB(WRITELINE("pic8259", pic8259_device, ir0_w))
- MCFG_IQ151CART_SLOT_OUT_IRQ1_CB(WRITELINE("pic8259", pic8259_device, ir1_w))
- MCFG_IQ151CART_SLOT_OUT_IRQ2_CB(WRITELINE("pic8259", pic8259_device, ir2_w))
- MCFG_IQ151CART_SLOT_OUT_IRQ3_CB(WRITELINE("pic8259", pic8259_device, ir3_w))
- MCFG_IQ151CART_SLOT_OUT_IRQ4_CB(WRITELINE("pic8259", pic8259_device, ir4_w))
+ MCFG_IQ151CART_SLOT_OUT_IRQ0_CB(WRITELINE(m_pic, pic8259_device, ir0_w))
+ MCFG_IQ151CART_SLOT_OUT_IRQ1_CB(WRITELINE(m_pic, pic8259_device, ir1_w))
+ MCFG_IQ151CART_SLOT_OUT_IRQ2_CB(WRITELINE(m_pic, pic8259_device, ir2_w))
+ MCFG_IQ151CART_SLOT_OUT_IRQ3_CB(WRITELINE(m_pic, pic8259_device, ir3_w))
+ MCFG_IQ151CART_SLOT_OUT_IRQ4_CB(WRITELINE(m_pic, pic8259_device, ir4_w))
MCFG_DEVICE_ADD("slot2", IQ151CART_SLOT, 0)
MCFG_DEVICE_SLOT_INTERFACE(iq151_cart, nullptr, false)
MCFG_IQ151CART_SLOT_SCREEN_TAG("screen")
- MCFG_IQ151CART_SLOT_OUT_IRQ0_CB(WRITELINE("pic8259", pic8259_device, ir0_w))
- MCFG_IQ151CART_SLOT_OUT_IRQ1_CB(WRITELINE("pic8259", pic8259_device, ir1_w))
- MCFG_IQ151CART_SLOT_OUT_IRQ2_CB(WRITELINE("pic8259", pic8259_device, ir2_w))
- MCFG_IQ151CART_SLOT_OUT_IRQ3_CB(WRITELINE("pic8259", pic8259_device, ir3_w))
- MCFG_IQ151CART_SLOT_OUT_IRQ4_CB(WRITELINE("pic8259", pic8259_device, ir4_w))
+ MCFG_IQ151CART_SLOT_OUT_IRQ0_CB(WRITELINE(m_pic, pic8259_device, ir0_w))
+ MCFG_IQ151CART_SLOT_OUT_IRQ1_CB(WRITELINE(m_pic, pic8259_device, ir1_w))
+ MCFG_IQ151CART_SLOT_OUT_IRQ2_CB(WRITELINE(m_pic, pic8259_device, ir2_w))
+ MCFG_IQ151CART_SLOT_OUT_IRQ3_CB(WRITELINE(m_pic, pic8259_device, ir3_w))
+ MCFG_IQ151CART_SLOT_OUT_IRQ4_CB(WRITELINE(m_pic, pic8259_device, ir4_w))
MCFG_DEVICE_ADD("slot3", IQ151CART_SLOT, 0)
MCFG_DEVICE_SLOT_INTERFACE(iq151_cart, nullptr, false)
MCFG_IQ151CART_SLOT_SCREEN_TAG("screen")
- MCFG_IQ151CART_SLOT_OUT_IRQ0_CB(WRITELINE("pic8259", pic8259_device, ir0_w))
- MCFG_IQ151CART_SLOT_OUT_IRQ1_CB(WRITELINE("pic8259", pic8259_device, ir1_w))
- MCFG_IQ151CART_SLOT_OUT_IRQ2_CB(WRITELINE("pic8259", pic8259_device, ir2_w))
- MCFG_IQ151CART_SLOT_OUT_IRQ3_CB(WRITELINE("pic8259", pic8259_device, ir3_w))
- MCFG_IQ151CART_SLOT_OUT_IRQ4_CB(WRITELINE("pic8259", pic8259_device, ir4_w))
+ MCFG_IQ151CART_SLOT_OUT_IRQ0_CB(WRITELINE(m_pic, pic8259_device, ir0_w))
+ MCFG_IQ151CART_SLOT_OUT_IRQ1_CB(WRITELINE(m_pic, pic8259_device, ir1_w))
+ MCFG_IQ151CART_SLOT_OUT_IRQ2_CB(WRITELINE(m_pic, pic8259_device, ir2_w))
+ MCFG_IQ151CART_SLOT_OUT_IRQ3_CB(WRITELINE(m_pic, pic8259_device, ir3_w))
+ MCFG_IQ151CART_SLOT_OUT_IRQ4_CB(WRITELINE(m_pic, pic8259_device, ir4_w))
MCFG_DEVICE_ADD("slot4", IQ151CART_SLOT, 0)
MCFG_DEVICE_SLOT_INTERFACE(iq151_cart, nullptr, false)
MCFG_IQ151CART_SLOT_SCREEN_TAG("screen")
- MCFG_IQ151CART_SLOT_OUT_IRQ0_CB(WRITELINE("pic8259", pic8259_device, ir0_w))
- MCFG_IQ151CART_SLOT_OUT_IRQ1_CB(WRITELINE("pic8259", pic8259_device, ir1_w))
- MCFG_IQ151CART_SLOT_OUT_IRQ2_CB(WRITELINE("pic8259", pic8259_device, ir2_w))
- MCFG_IQ151CART_SLOT_OUT_IRQ3_CB(WRITELINE("pic8259", pic8259_device, ir3_w))
- MCFG_IQ151CART_SLOT_OUT_IRQ4_CB(WRITELINE("pic8259", pic8259_device, ir4_w))
+ MCFG_IQ151CART_SLOT_OUT_IRQ0_CB(WRITELINE(m_pic, pic8259_device, ir0_w))
+ MCFG_IQ151CART_SLOT_OUT_IRQ1_CB(WRITELINE(m_pic, pic8259_device, ir1_w))
+ MCFG_IQ151CART_SLOT_OUT_IRQ2_CB(WRITELINE(m_pic, pic8259_device, ir2_w))
+ MCFG_IQ151CART_SLOT_OUT_IRQ3_CB(WRITELINE(m_pic, pic8259_device, ir3_w))
+ MCFG_IQ151CART_SLOT_OUT_IRQ4_CB(WRITELINE(m_pic, pic8259_device, ir4_w))
MCFG_DEVICE_ADD("slot5", IQ151CART_SLOT, 0)
MCFG_DEVICE_SLOT_INTERFACE(iq151_cart, "video32", false)
MCFG_IQ151CART_SLOT_SCREEN_TAG("screen")
- MCFG_IQ151CART_SLOT_OUT_IRQ0_CB(WRITELINE("pic8259", pic8259_device, ir0_w))
- MCFG_IQ151CART_SLOT_OUT_IRQ1_CB(WRITELINE("pic8259", pic8259_device, ir1_w))
- MCFG_IQ151CART_SLOT_OUT_IRQ2_CB(WRITELINE("pic8259", pic8259_device, ir2_w))
- MCFG_IQ151CART_SLOT_OUT_IRQ3_CB(WRITELINE("pic8259", pic8259_device, ir3_w))
- MCFG_IQ151CART_SLOT_OUT_IRQ4_CB(WRITELINE("pic8259", pic8259_device, ir4_w))
+ MCFG_IQ151CART_SLOT_OUT_IRQ0_CB(WRITELINE(m_pic, pic8259_device, ir0_w))
+ MCFG_IQ151CART_SLOT_OUT_IRQ1_CB(WRITELINE(m_pic, pic8259_device, ir1_w))
+ MCFG_IQ151CART_SLOT_OUT_IRQ2_CB(WRITELINE(m_pic, pic8259_device, ir2_w))
+ MCFG_IQ151CART_SLOT_OUT_IRQ3_CB(WRITELINE(m_pic, pic8259_device, ir3_w))
+ MCFG_IQ151CART_SLOT_OUT_IRQ4_CB(WRITELINE(m_pic, pic8259_device, ir4_w))
/* Software lists */
MCFG_SOFTWARE_LIST_ADD("cart_list", "iq151_cart")
diff --git a/src/mame/drivers/irisha.cpp b/src/mame/drivers/irisha.cpp
index ed792c68df7..545be9f4d6f 100644
--- a/src/mame/drivers/irisha.cpp
+++ b/src/mame/drivers/irisha.cpp
@@ -388,7 +388,7 @@ MACHINE_CONFIG_START(irisha_state::irisha)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
/* Devices */
- MCFG_DEVICE_ADD("uart", I8251, 0)
+ I8251(config, "uart", 0);
PIT8253(config, m_pit, 0);
m_pit->set_clk<0>(16_MHz_XTAL / 9);
@@ -406,8 +406,8 @@ MACHINE_CONFIG_START(irisha_state::irisha)
ppi.in_pc_callback().set(FUNC(irisha_state::irisha_8255_portc_r));
ppi.out_pc_callback().set(FUNC(irisha_state::irisha_8255_portc_w));
- MCFG_DEVICE_ADD("pic8259", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE("maincpu", 0))
+ pic8259_device &pic8259(PIC8259(config, "pic8259", 0));
+ pic8259.out_int_callback().set_inputline(m_maincpu, 0);
MACHINE_CONFIG_END
/* ROM definition */
diff --git a/src/mame/drivers/isbc.cpp b/src/mame/drivers/isbc.cpp
index aeef4555fb9..7c243b6bf40 100644
--- a/src/mame/drivers/isbc.cpp
+++ b/src/mame/drivers/isbc.cpp
@@ -331,12 +331,12 @@ MACHINE_CONFIG_START(isbc_state::isbc86)
PIC8259(config, m_pic_0, 0);
m_pic_0->out_int_callback().set_inputline(m_maincpu, 0);
- MCFG_DEVICE_ADD("pit", PIT8253, 0)
- MCFG_PIT8253_CLK0(XTAL(22'118'400)/18)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE("pic_0", pic8259_device, ir0_w))
- MCFG_PIT8253_CLK1(XTAL(22'118'400)/18)
- MCFG_PIT8253_CLK2(XTAL(22'118'400)/18)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, isbc_state, isbc86_tmr2_w))
+ pit8253_device &pit(PIT8253(config, "pit", 0));
+ pit.set_clk<0>(XTAL(22'118'400)/18);
+ pit.out_handler<0>().set(m_pic_0, FUNC(pic8259_device::ir0_w));
+ pit.set_clk<1>(XTAL(22'118'400)/18);
+ pit.set_clk<2>(XTAL(22'118'400)/18);
+ pit.out_handler<2>().set(FUNC(isbc_state::isbc86_tmr2_w));
I8255A(config, "ppi");
@@ -364,12 +364,12 @@ MACHINE_CONFIG_START(isbc_state::rpc86)
PIC8259(config, m_pic_0, 0);
m_pic_0->out_int_callback().set_inputline(m_maincpu, 0);
- MCFG_DEVICE_ADD("pit", PIT8253, 0)
- MCFG_PIT8253_CLK0(XTAL(22'118'400)/18)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE("pic_0", pic8259_device, ir2_w))
- MCFG_PIT8253_CLK1(XTAL(22'118'400)/144)
- MCFG_PIT8253_CLK2(XTAL(22'118'400)/18)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, isbc_state, isbc86_tmr2_w))
+ pit8253_device &pit(PIT8253(config, "pit", 0));
+ pit.set_clk<0>(XTAL(22'118'400)/18);
+ pit.out_handler<0>().set(m_pic_0, FUNC(pic8259_device::ir2_w));
+ pit.set_clk<1>(XTAL(22'118'400)/144);
+ pit.set_clk<2>(XTAL(22'118'400)/18);
+ pit.out_handler<2>().set(FUNC(isbc_state::isbc86_tmr2_w));
I8255A(config, "ppi");
@@ -440,26 +440,26 @@ MACHINE_CONFIG_START(isbc_state::isbc286)
m_pic_1->out_int_callback().set(m_pic_0, FUNC(pic8259_device::ir7_w));
m_pic_1->in_sp_callback().set_constant(0);
- MCFG_DEVICE_ADD("pit", PIT8254, 0)
- MCFG_PIT8253_CLK0(XTAL(22'118'400)/18)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE("pic_0", pic8259_device, ir0_w))
- MCFG_PIT8253_CLK1(XTAL(22'118'400)/18)
-// MCFG_PIT8253_OUT1_HANDLER(WRITELINE("uart8274", z80dart_device, rxtxcb_w))
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(m_uart8274, i8274_new_device, rxtxcb_w))
- MCFG_PIT8253_CLK2(XTAL(22'118'400)/18)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, isbc_state, isbc286_tmr2_w))
+ pit8254_device &pit(PIT8254(config, "pit", 0));
+ pit.set_clk<0>(XTAL(22'118'400)/18);
+ pit.out_handler<0>().set(m_pic_0, FUNC(pic8259_device::ir0_w));
+ pit.set_clk<1>(XTAL(22'118'400)/18);
+// pit.out_handler<1>().set(m_uart8274, FUNC(z80dart_device::rxtxcb_w));
+ pit.out_handler<1>().set(m_uart8274, FUNC(i8274_new_device::rxtxcb_w));
+ pit.set_clk<2>(XTAL(22'118'400)/18);
+ pit.out_handler<2>().set(FUNC(isbc_state::isbc286_tmr2_w));
i8255_device &ppi(I8255A(config, "ppi"));
ppi.out_pa_callback().set("cent_data_out", FUNC(output_latch_device::bus_w));
- ppi.in_pb_callback().set("cent_status_in", FUNC(input_buffer_device::bus_r));
+ ppi.in_pb_callback().set(m_cent_status_in, FUNC(input_buffer_device::bus_r));
ppi.out_pc_callback().set(FUNC(isbc_state::ppi_c_w));
MCFG_DEVICE_ADD(m_centronics, CENTRONICS, centronics_devices, "printer")
MCFG_CENTRONICS_ACK_HANDLER(WRITELINE(*this, isbc_state, write_centronics_ack))
- MCFG_CENTRONICS_BUSY_HANDLER(WRITELINE("cent_status_in", input_buffer_device, write_bit7))
- MCFG_CENTRONICS_FAULT_HANDLER(WRITELINE("cent_status_in", input_buffer_device, write_bit6))
+ MCFG_CENTRONICS_BUSY_HANDLER(WRITELINE(m_cent_status_in, input_buffer_device, write_bit7))
+ MCFG_CENTRONICS_FAULT_HANDLER(WRITELINE(m_cent_status_in, input_buffer_device, write_bit6))
- MCFG_DEVICE_ADD("cent_status_in", INPUT_BUFFER, 0)
+ INPUT_BUFFER(config, m_cent_status_in, 0);
MCFG_CENTRONICS_OUTPUT_LATCH_ADD("cent_data_out", "centronics")
@@ -481,7 +481,7 @@ MACHINE_CONFIG_START(isbc_state::isbc286)
m_uart8274->out_dtrb_callback().set("rs232b", FUNC(rs232_port_device::write_dtr));
m_uart8274->out_rtsb_callback().set("rs232b", FUNC(rs232_port_device::write_rts));
// m_uart8274->out_int_callback().set(FUNC(isbc_state::isbc_uart8274_irq));
- m_uart8274->out_int_callback().set("pic_0", FUNC(pic8259_device::ir6_w));
+ m_uart8274->out_int_callback().set(m_pic_0, FUNC(pic8259_device::ir6_w));
#endif
rs232_port_device &rs232a(RS232_PORT(config, "rs232a", default_rs232_devices, nullptr));
diff --git a/src/mame/drivers/jtc.cpp b/src/mame/drivers/jtc.cpp
index ad083dec1ae..98a02e52840 100644
--- a/src/mame/drivers/jtc.cpp
+++ b/src/mame/drivers/jtc.cpp
@@ -910,7 +910,7 @@ ROM_START( jtc )
ROM_REGION( 0x10000, UB8830D_TAG, 0 )
ROM_LOAD( "u883rom.bin", 0x0000, 0x0800, CRC(2453c8c1) SHA1(816f5d08f8064b69b1779eb6661fde091aa58ba8) )
ROM_LOAD( "os2k_0800.bin", 0x0800, 0x0800, CRC(c81a2e19) SHA1(97c3b36c7b555081e084403e8f800fc9dbf5e68d) ) // u2716c1.bin
- ROM_LOAD_OPTIONAL( "u2716c2.bin", 0x2000, 0x0800, NO_DUMP ) // doesn't seem to be needed?
+ ROM_LOAD( "u2716c2.bin", 0x2000, 0x0800, NO_DUMP ) // doesn't seem to be needed?
ROM_END
ROM_START( jtces88 )
diff --git a/src/mame/drivers/konmedal.cpp b/src/mame/drivers/konmedal.cpp
index d587335a6e5..2479b83d3d5 100644
--- a/src/mame/drivers/konmedal.cpp
+++ b/src/mame/drivers/konmedal.cpp
@@ -664,6 +664,11 @@ ROM_START( shuriboy )
ROM_REGION( 0x200000, "upd", 0 )
ROM_LOAD( "341-a02.13c", 0x000000, 0x020000, CRC(e1f5c8f1) SHA1(323a078720e09a7326e82cb623b6c90e2674e800) )
+
+ ROM_REGION( 0x300, "proms", 0 )
+ ROM_LOAD( "am27s21apc.2d", 0x000, 0x100, NO_DUMP )
+ ROM_LOAD( "am27s21apc.3d", 0x100, 0x100, NO_DUMP )
+ ROM_LOAD( "am27s21apc.4d", 0x200, 0x100, NO_DUMP )
ROM_END
GAME( 1995, tsukande, 0, tsukande, konmedal, konmedal_state, empty_init, ROT0, "Konami", "Tsukande Toru Chicchi", MACHINE_NOT_WORKING)
diff --git a/src/mame/drivers/laserbas.cpp b/src/mame/drivers/laserbas.cpp
index a40e0af7211..5ff58f9cbef 100644
--- a/src/mame/drivers/laserbas.cpp
+++ b/src/mame/drivers/laserbas.cpp
@@ -77,12 +77,7 @@ public:
: driver_device(mconfig, type, tag),
m_maincpu(*this, "maincpu"),
m_palette(*this, "palette"),
- m_dac1(*this, "dac1"),
- m_dac2(*this, "dac2"),
- m_dac3(*this, "dac3"),
- m_dac4(*this, "dac4"),
- m_dac5(*this, "dac5"),
- m_dac6(*this, "dac6")
+ m_dac(*this, "dac%u", 1U)
{ }
void laserbas(machine_config &config);
@@ -101,7 +96,6 @@ private:
int m_scl;
bool m_flipscreen;
uint64_t m_z1data;
- void write_pit_out(int num, int state);
DECLARE_READ8_MEMBER(vram_r);
DECLARE_WRITE8_MEMBER(vram_w);
DECLARE_WRITE8_MEMBER(videoctrl_w);
@@ -109,12 +103,7 @@ private:
DECLARE_READ8_MEMBER(track_lo_r);
DECLARE_READ8_MEMBER(track_hi_r);
DECLARE_WRITE8_MEMBER(out_w);
- DECLARE_WRITE_LINE_MEMBER(pit_out_0_w);
- DECLARE_WRITE_LINE_MEMBER(pit_out_1_w);
- DECLARE_WRITE_LINE_MEMBER(pit_out_2_w);
- DECLARE_WRITE_LINE_MEMBER(pit_out_3_w);
- DECLARE_WRITE_LINE_MEMBER(pit_out_4_w);
- DECLARE_WRITE_LINE_MEMBER(pit_out_5_w);
+ template<uint8_t Which> DECLARE_WRITE_LINE_MEMBER(pit_out_w);
TIMER_DEVICE_CALLBACK_MEMBER(laserbas_scanline);
MC6845_UPDATE_ROW(crtc_update_row);
@@ -123,12 +112,7 @@ private:
required_device<cpu_device> m_maincpu;
required_device<palette_device> m_palette;
- required_device<dac_byte_interface> m_dac1;
- required_device<dac_byte_interface> m_dac2;
- required_device<dac_byte_interface> m_dac3;
- required_device<dac_byte_interface> m_dac4;
- required_device<dac_byte_interface> m_dac5;
- required_device<dac_byte_interface> m_dac6;
+ required_device_array<dac_byte_interface, 6> m_dac;
void laserbas_io(address_map &map);
void laserbas_memory(address_map &map);
};
@@ -286,51 +270,19 @@ void laserbas_state::machine_reset()
m_scl = 0;
}
-void laserbas_state::write_pit_out(int num, int state)
+template<uint8_t Which>
+WRITE_LINE_MEMBER(laserbas_state::pit_out_w)
{
state^=1; // 7404 (6G)
- if((!state)& m_cnt_out[num]){ // 0->1 rising edge CLK
- m_counter[num] = (m_counter[num]+1)&0x0f; // 4 bit counters 74393
+ if((!state)& m_cnt_out[Which]){ // 0->1 rising edge CLK
+ m_counter[Which] = (m_counter[Which]+1)&0x0f; // 4 bit counters 74393
}
- int data =(state) | ((m_counter[num]&7)<<1); // combine output from 8253 with counter bits 0-3
+ int data =(state) | ((m_counter[Which]&7)<<1); // combine output from 8253 with counter bits 0-3
data<<=4;
- if(m_counter[num]&8) data^=0x0f; // counter bit 4 xors the data ( 7486 x 6)
- switch(num){
- case 0: m_dac1->write(data);break; // 4 resistor packs : 47k, 100k, 220k, 470k
- case 1: m_dac2->write(data);break;
- case 2: m_dac3->write(data);break;
- case 3: m_dac4->write(data);break;
- case 4: m_dac5->write(data);break;
- case 5: m_dac6->write(data);break;
- }
-
- m_cnt_out[num]=state;
-}
-
-WRITE_LINE_MEMBER(laserbas_state::pit_out_0_w)
-{
- write_pit_out(0,state);
-}
+ if(m_counter[Which]&8) data^=0x0f; // counter bit 4 xors the data ( 7486 x 6)
+ m_dac[Which]->write(data); // 4 resistor packs : 47k, 100k, 220k, 470k
-WRITE_LINE_MEMBER(laserbas_state::pit_out_1_w)
-{
- write_pit_out(1,state);
-}
-WRITE_LINE_MEMBER(laserbas_state::pit_out_2_w)
-{
- write_pit_out(2,state);
-}
-WRITE_LINE_MEMBER(laserbas_state::pit_out_3_w)
-{
- write_pit_out(3,state);
-}
-WRITE_LINE_MEMBER(laserbas_state::pit_out_4_w)
-{
- write_pit_out(4,state);
-}
-WRITE_LINE_MEMBER(laserbas_state::pit_out_5_w)
-{
- write_pit_out(5,state);
+ m_cnt_out[Which]=state;
}
void laserbas_state::laserbas_memory(address_map &map)
@@ -421,21 +373,21 @@ MACHINE_CONFIG_START(laserbas_state::laserbas)
MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", laserbas_state, laserbas_scanline, "screen", 0, 1)
/* TODO: clocks aren't known */
- MCFG_DEVICE_ADD("pit0", PIT8253, 0)
- MCFG_PIT8253_CLK0(PIT_CLOCK)
- MCFG_PIT8253_CLK1(PIT_CLOCK)
- MCFG_PIT8253_CLK2(PIT_CLOCK)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, laserbas_state, pit_out_0_w))
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(*this, laserbas_state, pit_out_1_w))
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, laserbas_state, pit_out_2_w))
-
- MCFG_DEVICE_ADD("pit1", PIT8253, 0)
- MCFG_PIT8253_CLK0(PIT_CLOCK)
- MCFG_PIT8253_CLK1(PIT_CLOCK)
- MCFG_PIT8253_CLK2(PIT_CLOCK)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, laserbas_state, pit_out_3_w))
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(*this, laserbas_state, pit_out_4_w))
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, laserbas_state, pit_out_5_w))
+ pit8253_device &pit0(PIT8253(config, "pit0", 0));
+ pit0.set_clk<0>(PIT_CLOCK);
+ pit0.set_clk<1>(PIT_CLOCK);
+ pit0.set_clk<2>(PIT_CLOCK);
+ pit0.out_handler<0>().set(FUNC(laserbas_state::pit_out_w<0>));
+ pit0.out_handler<1>().set(FUNC(laserbas_state::pit_out_w<1>));
+ pit0.out_handler<2>().set(FUNC(laserbas_state::pit_out_w<2>));
+
+ pit8253_device &pit1(PIT8253(config, "pit1", 0));
+ pit1.set_clk<0>(PIT_CLOCK);
+ pit1.set_clk<1>(PIT_CLOCK);
+ pit1.set_clk<2>(PIT_CLOCK);
+ pit1.out_handler<0>().set(FUNC(laserbas_state::pit_out_w<3>));
+ pit1.out_handler<1>().set(FUNC(laserbas_state::pit_out_w<4>));
+ pit1.out_handler<2>().set(FUNC(laserbas_state::pit_out_w<5>));
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_RAW_PARAMS(4000000, 256, 0, 256, 256, 0, 256) /* temporary, CRTC will configure screen */
@@ -451,12 +403,12 @@ MACHINE_CONFIG_START(laserbas_state::laserbas)
/* sound hardware */
SPEAKER(config, "speaker").front_center();
- MCFG_DEVICE_ADD("dac1", DAC_4BIT_R2R, 0) MCFG_SOUND_ROUTE(ALL_OUTPUTS, "speaker", 0.16)
- MCFG_DEVICE_ADD("dac2", DAC_4BIT_R2R, 0) MCFG_SOUND_ROUTE(ALL_OUTPUTS, "speaker", 0.16)
- MCFG_DEVICE_ADD("dac3", DAC_4BIT_R2R, 0) MCFG_SOUND_ROUTE(ALL_OUTPUTS, "speaker", 0.16)
- MCFG_DEVICE_ADD("dac4", DAC_4BIT_R2R, 0) MCFG_SOUND_ROUTE(ALL_OUTPUTS, "speaker", 0.16)
- MCFG_DEVICE_ADD("dac5", DAC_4BIT_R2R, 0) MCFG_SOUND_ROUTE(ALL_OUTPUTS, "speaker", 0.16)
- MCFG_DEVICE_ADD("dac6", DAC_4BIT_R2R, 0) MCFG_SOUND_ROUTE(ALL_OUTPUTS, "speaker", 0.16)
+ MCFG_DEVICE_ADD(m_dac[0], DAC_4BIT_R2R, 0) MCFG_SOUND_ROUTE(ALL_OUTPUTS, "speaker", 0.16)
+ MCFG_DEVICE_ADD(m_dac[1], DAC_4BIT_R2R, 0) MCFG_SOUND_ROUTE(ALL_OUTPUTS, "speaker", 0.16)
+ MCFG_DEVICE_ADD(m_dac[2], DAC_4BIT_R2R, 0) MCFG_SOUND_ROUTE(ALL_OUTPUTS, "speaker", 0.16)
+ MCFG_DEVICE_ADD(m_dac[3], DAC_4BIT_R2R, 0) MCFG_SOUND_ROUTE(ALL_OUTPUTS, "speaker", 0.16)
+ MCFG_DEVICE_ADD(m_dac[4], DAC_4BIT_R2R, 0) MCFG_SOUND_ROUTE(ALL_OUTPUTS, "speaker", 0.16)
+ MCFG_DEVICE_ADD(m_dac[5], DAC_4BIT_R2R, 0) MCFG_SOUND_ROUTE(ALL_OUTPUTS, "speaker", 0.16)
MCFG_DEVICE_ADD("vref", VOLTAGE_REGULATOR, 0) MCFG_VOLTAGE_REGULATOR_OUTPUT(5.0)
MCFG_SOUND_ROUTE(0, "dac1", 1.0, DAC_VREF_POS_INPUT) MCFG_SOUND_ROUTE(0, "dac1", -1.0, DAC_VREF_NEG_INPUT)
MCFG_SOUND_ROUTE(0, "dac2", 1.0, DAC_VREF_POS_INPUT) MCFG_SOUND_ROUTE(0, "dac2", -1.0, DAC_VREF_NEG_INPUT)
diff --git a/src/mame/drivers/m107.cpp b/src/mame/drivers/m107.cpp
index 4b831afd528..9eab26207e9 100644
--- a/src/mame/drivers/m107.cpp
+++ b/src/mame/drivers/m107.cpp
@@ -742,8 +742,8 @@ MACHINE_CONFIG_START(m107_state::firebarr)
MCFG_DEVICE_PROGRAM_MAP(sound_map)
MCFG_V25_CONFIG(rtypeleo_decryption_table)
- MCFG_DEVICE_ADD("upd71059c", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE("maincpu", 0))
+ PIC8259(config, m_upd71059c, 0);
+ m_upd71059c->out_int_callback().set_inputline(m_maincpu, 0);
MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", m107_state, scanline_interrupt, "screen", 0, 1)
@@ -772,7 +772,7 @@ MACHINE_CONFIG_START(m107_state::firebarr)
MCFG_GENERIC_LATCH_SEPARATE_ACKNOWLEDGE(true)
MCFG_GENERIC_LATCH_8_ADD("soundlatch2")
- MCFG_GENERIC_LATCH_DATA_PENDING_CB(WRITELINE("upd71059c", pic8259_device, ir3_w))
+ MCFG_GENERIC_LATCH_DATA_PENDING_CB(WRITELINE(m_upd71059c, pic8259_device, ir3_w))
MCFG_DEVICE_ADD("ymsnd", YM2151, XTAL(14'318'181)/4)
MCFG_YM2151_IRQ_HANDLER(INPUTLINE("soundcpu", NEC_INPUT_LINE_INTP0))
diff --git a/src/mame/drivers/m20.cpp b/src/mame/drivers/m20.cpp
index 06888db0a48..df3c6befd40 100644
--- a/src/mame/drivers/m20.cpp
+++ b/src/mame/drivers/m20.cpp
@@ -819,7 +819,7 @@ MACHINE_CONFIG_START(m20_state::m20)
MCFG_MC6845_CHAR_WIDTH(16)
MCFG_MC6845_UPDATE_ROW_CB(m20_state, update_row)
- MCFG_DEVICE_ADD("ppi8255", I8255A, 0)
+ I8255A(config, m_i8255, 0);
I8251(config, m_kbdi8251, 0);
m_kbdi8251->txd_handler().set("kbd", FUNC(rs232_port_device::write_txd));
@@ -830,16 +830,16 @@ MACHINE_CONFIG_START(m20_state::m20)
m_ttyi8251->rxrdy_handler().set(m_i8259, FUNC(pic8259_device::ir3_w));
m_ttyi8251->txrdy_handler().set(m_i8259, FUNC(pic8259_device::ir5_w));
- MCFG_DEVICE_ADD("pit8253", PIT8253, 0)
- MCFG_PIT8253_CLK0(1230782)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, m20_state, tty_clock_tick_w))
- MCFG_PIT8253_CLK1(1230782)
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(*this, m20_state, kbd_clock_tick_w))
- MCFG_PIT8253_CLK2(1230782)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, m20_state, timer_tick_w))
+ pit8253_device &pit8253(PIT8253(config, "pit8253", 0));
+ pit8253.set_clk<0>(1230782);
+ pit8253.out_handler<0>().set(FUNC(m20_state::tty_clock_tick_w));
+ pit8253.set_clk<1>(1230782);
+ pit8253.out_handler<1>().set(FUNC(m20_state::kbd_clock_tick_w));
+ pit8253.set_clk<2>(1230782);
+ pit8253.out_handler<2>().set(FUNC(m20_state::timer_tick_w));
- MCFG_DEVICE_ADD(m_i8259, PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(WRITELINE(*this, m20_state, int_w))
+ PIC8259(config, m_i8259, 0);
+ m_i8259->out_int_callback().set(FUNC(m20_state::int_w));
rs232_port_device &kbd(RS232_PORT(config, "kbd", keyboard, "m20"));
kbd.rxd_handler().set(m_kbdi8251, FUNC(i8251_device::write_rxd));
diff --git a/src/mame/drivers/m52.cpp b/src/mame/drivers/m52.cpp
index d48079b913b..60250437104 100644
--- a/src/mame/drivers/m52.cpp
+++ b/src/mame/drivers/m52.cpp
@@ -50,10 +50,8 @@
#include "includes/iremipt.h"
#include "includes/m52.h"
-
#define MASTER_CLOCK XTAL(18'432'000)
-
/*************************************
*
* Memory maps
@@ -66,7 +64,7 @@ void m52_state::main_map(address_map &map)
map(0x8000, 0x83ff).ram().w(FUNC(m52_state::m52_videoram_w)).share("videoram");
map(0x8400, 0x87ff).ram().w(FUNC(m52_state::m52_colorram_w)).share("colorram");
map(0x8800, 0x8800).mirror(0x07ff).r(FUNC(m52_state::m52_protection_r));
- map(0xc800, 0xcbff).mirror(0x0400).writeonly().share("spriteram");
+ map(0xc800, 0xcbff).mirror(0x0400).writeonly().share("spriteram"); // only 0x100 of this used by video code?
map(0xd000, 0xd000).mirror(0x07fc).w("irem_audio", FUNC(irem_audio_device::cmd_w));
map(0xd001, 0xd001).mirror(0x07fc).w(FUNC(m52_state::m52_flipscreen_w)); /* + coin counters */
map(0xd000, 0xd000).mirror(0x07f8).portr("IN0");
@@ -78,15 +76,15 @@ void m52_state::main_map(address_map &map)
}
-void m52_state::alpha1v_map(address_map &map)
+void m52_alpha1v_state::alpha1v_map(address_map &map)
{
map(0x0000, 0x6fff).rom();
map(0x8000, 0x83ff).ram().w(FUNC(m52_state::m52_videoram_w)).share("videoram");
map(0x8400, 0x87ff).ram().w(FUNC(m52_state::m52_colorram_w)).share("colorram");
map(0x8800, 0x8800).mirror(0x07ff).r(FUNC(m52_state::m52_protection_r)); // result is ignored
- map(0xc800, 0xc9ff).writeonly().share("spriteram"); // bigger or mirrored?
+ map(0xc800, 0xc9ff).writeonly().share("spriteram");
map(0xd000, 0xd000).portr("IN0").w("irem_audio", FUNC(irem_audio_device::cmd_w));
- map(0xd001, 0xd001).portr("IN1").w(FUNC(m52_state::alpha1v_flipscreen_w));
+ map(0xd001, 0xd001).portr("IN1").w(FUNC(m52_alpha1v_state::alpha1v_flipscreen_w));
map(0xd002, 0xd002).portr("IN2");
map(0xd003, 0xd003).portr("DSW1");
map(0xd004, 0xd004).portr("DSW2");
@@ -106,7 +104,6 @@ void m52_state::main_portmap(address_map &map)
}
-
/*************************************
*
* Port definitions
@@ -302,12 +299,11 @@ static INPUT_PORTS_START( alpha1v )
INPUT_PORTS_END
-
/*************************************
- *
- * Graphics layouts
- *
- *************************************/
+*
+* Graphics layouts
+*
+*************************************/
static const gfx_layout charlayout =
{
@@ -317,18 +313,18 @@ static const gfx_layout charlayout =
{ RGN_FRAC(0,2), RGN_FRAC(1,2) },
{ STEP8(0,1) },
{ STEP8(0,8) },
- 8*8
+ 8 * 8
};
static const gfx_layout spritelayout =
{
16,16,
- RGN_FRAC(1,2),
- 2,
- { RGN_FRAC(0,2), RGN_FRAC(1,2) },
- { STEP8(0,1), STEP8(16*8,1) },
+ RGN_FRAC(1,3),
+ 3,
+ { RGN_FRAC(2,3), RGN_FRAC(0,3), RGN_FRAC(1,3) },
+ { STEP8(0,1), STEP8(16 * 8,1) },
{ STEP16(0,8) },
- 32*8
+ 32 * 8
};
static const uint32_t bgcharlayout_xoffset[256] =
@@ -351,14 +347,14 @@ static const uint32_t bgcharlayout_xoffset[256] =
STEP4(0x1e0,1), STEP4(0x1e8,1), STEP4(0x1f0,1), STEP4(0x1f8,1)
};
-static const uint32_t bgcharlayout_yoffset[64] =
+static const uint32_t bgcharlayout_yoffset[128] =
{
- STEP32(0x0000,0x200), STEP32(0x4000,0x200)
+ STEP32(0x0000,0x200), STEP32(0x4000,0x200), STEP32(0x8000,0x200), STEP32(0xc000,0x200)
};
static const gfx_layout bgcharlayout =
{
- 256, 64, /* 256x64 image format */
+ 256, 128, /* 256x64 image format */
1, /* 1 image */
2, /* 2 bits per pixel */
{ 4, 0 }, /* the two bitplanes for 4 pixels are packed into one byte */
@@ -370,21 +366,28 @@ static const gfx_layout bgcharlayout =
};
-static GFXDECODE_START( gfx_m52 )
- GFXDECODE_ENTRY( "gfx1", 0x0000, charlayout, 0, 128 )
- GFXDECODE_ENTRY( "gfx2", 0x0000, spritelayout, 128*4, 16 )
- GFXDECODE_ENTRY( "gfx3", 0x0000, bgcharlayout, 128*4+16*4+0*4, 1 )
- GFXDECODE_ENTRY( "gfx4", 0x0000, bgcharlayout, 128*4+16*4+1*4, 1 )
- GFXDECODE_ENTRY( "gfx5", 0x0000, bgcharlayout, 128*4+16*4+2*4, 1 )
+static GFXDECODE_START(gfx_m52_sp)
+ GFXDECODE_ENTRY("sp", 0x0000, spritelayout, 0, 16)
+GFXDECODE_END
+
+static GFXDECODE_START(gfx_m52_tx)
+ GFXDECODE_ENTRY("tx", 0x0000, charlayout, 0, 128)
+GFXDECODE_END
+
+static GFXDECODE_START(gfx_m52_bg)
+ GFXDECODE_ENTRY("bg0", 0x0000, bgcharlayout, 0 * 4, 1)
+ GFXDECODE_ENTRY("bg1", 0x0000, bgcharlayout, 1 * 4, 1)
+ GFXDECODE_ENTRY("bg2", 0x0000, bgcharlayout, 2 * 4, 1)
GFXDECODE_END
+
/*************************************
- *
- * Machine drivers
- *
- *************************************/
+*
+* Machine drivers
+*
+*************************************/
void m52_state::machine_reset()
{
@@ -398,21 +401,26 @@ void m52_state::machine_reset()
MACHINE_CONFIG_START(m52_state::m52)
/* basic machine hardware */
- MCFG_DEVICE_ADD("maincpu", Z80, MASTER_CLOCK/6)
+ MCFG_DEVICE_ADD("maincpu", Z80, MASTER_CLOCK / 6)
MCFG_DEVICE_PROGRAM_MAP(main_map)
MCFG_DEVICE_IO_MAP(main_portmap)
- MCFG_DEVICE_VBLANK_INT_DRIVER("screen", m52_state, irq0_line_hold)
+ MCFG_DEVICE_VBLANK_INT_DRIVER("screen", m52_state, irq0_line_hold)
/* video hardware */
- MCFG_DEVICE_ADD("gfxdecode", GFXDECODE, "palette", gfx_m52)
- MCFG_PALETTE_ADD("palette", 128*4+16*4+3*4)
- MCFG_PALETTE_INDIRECT_ENTRIES(512+32+32)
- MCFG_PALETTE_INIT_OWNER(m52_state, m52)
+ MCFG_PALETTE_ADD("sp_palette", 256)
+ MCFG_PALETTE_INDIRECT_ENTRIES(32)
+ MCFG_DEVICE_ADD("sp_gfxdecode", GFXDECODE, "sp_palette", gfx_m52_sp)
+
+ MCFG_PALETTE_ADD("tx_palette", 512)
+ MCFG_DEVICE_ADD("tx_gfxdecode", GFXDECODE, "tx_palette", gfx_m52_tx)
+
+ MCFG_PALETTE_ADD("bg_palette", 3 * 4)
+ MCFG_PALETTE_INDIRECT_ENTRIES(32)
+ MCFG_DEVICE_ADD("bg_gfxdecode", GFXDECODE, "bg_palette", gfx_m52_bg)
MCFG_SCREEN_ADD("screen", RASTER)
- MCFG_SCREEN_RAW_PARAMS(MASTER_CLOCK/3, 384, 136, 376, 282, 22, 274)
+ MCFG_SCREEN_RAW_PARAMS(MASTER_CLOCK / 3, 384, 136, 376, 282, 22, 274)
MCFG_SCREEN_UPDATE_DRIVER(m52_state, screen_update_m52)
- MCFG_SCREEN_PALETTE("palette")
/* sound hardware */
//m52_sound_c_audio(config);
@@ -421,176 +429,208 @@ MACHINE_CONFIG_START(m52_state::m52)
MACHINE_CONFIG_END
-MACHINE_CONFIG_START(m52_state::alpha1v)
+MACHINE_CONFIG_START(m52_alpha1v_state::alpha1v)
m52(config);
/* basic machine hardware */
MCFG_DEVICE_MODIFY("maincpu")
MCFG_DEVICE_PROGRAM_MAP(alpha1v_map)
MCFG_SCREEN_MODIFY("screen")
- MCFG_SCREEN_RAW_PARAMS(MASTER_CLOCK/3, 384, 136, 376, 282, 16, 272)
+ MCFG_SCREEN_RAW_PARAMS(MASTER_CLOCK / 3, 384, 136, 376, 282, 16, 272)
+
MACHINE_CONFIG_END
/*************************************
- *
- * ROM definitions
- *
- *************************************/
+*
+* ROM definitions
+*
+*************************************/
-ROM_START( mpatrol )
- ROM_REGION( 0x10000, "maincpu", 0 )
- ROM_LOAD( "mpa-1.3m", 0x0000, 0x1000, CRC(5873a860) SHA1(8c03726d6e049c3edbc277440184e31679f78258) )
- ROM_LOAD( "mpa-2.3l", 0x1000, 0x1000, CRC(f4b85974) SHA1(dfb2efb57378a20af6f20569f4360cde95596f93) )
- ROM_LOAD( "mpa-3.3k", 0x2000, 0x1000, CRC(2e1a598c) SHA1(112c3c9678db8a8540a8df3708020c87fd10c91b) )
- ROM_LOAD( "mpa-4.3j", 0x3000, 0x1000, CRC(dd05b587) SHA1(727961b0dafa4a96b580d51013336db2a18aff1e) )
+ROM_START(mpatrol)
+ ROM_REGION(0x10000, "maincpu", 0)
+ ROM_LOAD("mpa-1.3m", 0x0000, 0x1000, CRC(5873a860) SHA1(8c03726d6e049c3edbc277440184e31679f78258))
+ ROM_LOAD("mpa-2.3l", 0x1000, 0x1000, CRC(f4b85974) SHA1(dfb2efb57378a20af6f20569f4360cde95596f93))
+ ROM_LOAD("mpa-3.3k", 0x2000, 0x1000, CRC(2e1a598c) SHA1(112c3c9678db8a8540a8df3708020c87fd10c91b))
+ ROM_LOAD("mpa-4.3j", 0x3000, 0x1000, CRC(dd05b587) SHA1(727961b0dafa4a96b580d51013336db2a18aff1e))
- ROM_REGION( 0x8000, "irem_audio:iremsound", 0 )
- ROM_LOAD( "mp-s1.1a", 0x7000, 0x1000, CRC(561d3108) SHA1(4998c68a9e9a8002251fa8f07aa1082444a9dc80) )
+ ROM_REGION(0x8000, "irem_audio:iremsound", 0)
+ ROM_LOAD("mp-s1.1a", 0x7000, 0x1000, CRC(561d3108) SHA1(4998c68a9e9a8002251fa8f07aa1082444a9dc80))
- ROM_REGION( 0x2000, "gfx1", 0 )
- ROM_LOAD( "mpe-5.3e", 0x0000, 0x1000, CRC(e3ee7f75) SHA1(b03d0d56150d3e9da4a4c871338097b4f450b649) ) /* chars */
- ROM_LOAD( "mpe-4.3f", 0x1000, 0x1000, CRC(cca6d023) SHA1(fecb3059fb09897a096add9452b50aec55c07545) )
+ ROM_REGION(0x2000, "tx", 0)
+ ROM_LOAD("mpe-5.3e", 0x0000, 0x1000, CRC(e3ee7f75) SHA1(b03d0d56150d3e9da4a4c871338097b4f450b649))
+ ROM_LOAD("mpe-4.3f", 0x1000, 0x1000, CRC(cca6d023) SHA1(fecb3059fb09897a096add9452b50aec55c07545))
- ROM_REGION( 0x2000, "gfx2", 0 )
- ROM_LOAD( "mpb-2.3m", 0x0000, 0x1000, CRC(707ace5e) SHA1(93c682e13e74bce29ced3a87bffb29569c114c3b) ) /* sprites */
- ROM_LOAD( "mpb-1.3n", 0x1000, 0x1000, CRC(9b72133a) SHA1(1393ef92ae1ad58a4b62ca1660c0793d30a8b5e2) )
+ /* 0x2000-0x2fff is intentionally left as 0x00 fill, unused bitplane */
+ ROM_REGION(0x3000, "sp", ROMREGION_ERASE00)
+ ROM_LOAD("mpb-2.3m", 0x0000, 0x1000, CRC(707ace5e) SHA1(93c682e13e74bce29ced3a87bffb29569c114c3b))
+ ROM_LOAD("mpb-1.3n", 0x1000, 0x1000, CRC(9b72133a) SHA1(1393ef92ae1ad58a4b62ca1660c0793d30a8b5e2))
- ROM_REGION( 0x1000, "gfx3", 0 )
- ROM_LOAD( "mpe-1.3l", 0x0000, 0x1000, CRC(c46a7f72) SHA1(8bb7c9acaf6833fb6c0575b015991b873a305a84) ) /* background graphics */
+ /* 0x1000-01fff is intentionally left as 0xff fill for the bg regions */
+ ROM_REGION(0x2000, "bg0", ROMREGION_ERASEFF)
+ ROM_LOAD("mpe-1.3l", 0x0000, 0x1000, CRC(c46a7f72) SHA1(8bb7c9acaf6833fb6c0575b015991b873a305a84))
- ROM_REGION( 0x1000, "gfx4", 0 )
- ROM_LOAD( "mpe-2.3k", 0x0000, 0x1000, CRC(c7aa1fb0) SHA1(14c6c76e1d0db2c0745e5d6d33ea6945fac8e9ee) )
+ ROM_REGION(0x2000, "bg1", ROMREGION_ERASEFF)
+ ROM_LOAD("mpe-2.3k", 0x0000, 0x1000, CRC(c7aa1fb0) SHA1(14c6c76e1d0db2c0745e5d6d33ea6945fac8e9ee))
- ROM_REGION( 0x1000, "gfx5", 0 )
- ROM_LOAD( "mpe-3.3h", 0x0000, 0x1000, CRC(a0919392) SHA1(8a090cb8d483a3d67c7360058e3fdd70e151cd62) )
+ ROM_REGION(0x2000, "bg2", ROMREGION_ERASEFF)
+ ROM_LOAD("mpe-3.3h", 0x0000, 0x1000, CRC(a0919392) SHA1(8a090cb8d483a3d67c7360058e3fdd70e151cd62))
- ROM_REGION( 0x0340, "proms", 0 )
- ROM_LOAD( "mpc-4.2a", 0x0000, 0x0200, CRC(07f99284) SHA1(dfc52958f2520e1ce4446dd4c84c91413bbacf76) )
- ROM_LOAD( "mpc-3.1m", 0x0200, 0x0020, CRC(6a57eff2) SHA1(2d1c12dab5915da2ccd466e39436c88be434d634) ) /* background palette */
- ROM_LOAD( "mpc-1.1f", 0x0220, 0x0020, CRC(26979b13) SHA1(8c41a8cce4f3384c392a9f7a223a50d7be0e14a5) ) /* sprite palette */
- ROM_LOAD( "mpc-2.2h", 0x0240, 0x0100, CRC(7ae4cd97) SHA1(bc0662fac82ffe65f02092d912b2c2b0c7a8ac2b) ) /* sprite lookup table */
+ ROM_REGION(0x0200, "tx_pal", 0)
+ ROM_LOAD("mpc-4.2a", 0x0000, 0x0200, CRC(07f99284) SHA1(dfc52958f2520e1ce4446dd4c84c91413bbacf76))
+
+ ROM_REGION(0x0020, "bg_pal", 0)
+ ROM_LOAD("mpc-3.1m", 0x0000, 0x0020, CRC(6a57eff2) SHA1(2d1c12dab5915da2ccd466e39436c88be434d634))
+
+ ROM_REGION(0x0020, "spr_pal", 0)
+ ROM_LOAD("mpc-1.1f", 0x0000, 0x0020, CRC(26979b13) SHA1(8c41a8cce4f3384c392a9f7a223a50d7be0e14a5))
+
+ ROM_REGION(0x0100, "spr_clut", 0)
+ ROM_LOAD("mpc-2.2h", 0x0000, 0x0100, CRC(7ae4cd97) SHA1(bc0662fac82ffe65f02092d912b2c2b0c7a8ac2b))
ROM_END
-ROM_START( mpatrolw )
- ROM_REGION( 0x10000, "maincpu", 0 )
- ROM_LOAD( "mpa-1w.3m", 0x0000, 0x1000, CRC(baa1a1d4) SHA1(7968a7f221e7f4c9c81ddc8de17f6568e17b9ea8) )
- ROM_LOAD( "mpa-2w.3l", 0x1000, 0x1000, CRC(52459e51) SHA1(ae685b7848baa1b87a3f2bce97356286171e16d4) )
- ROM_LOAD( "mpa-3w.3k", 0x2000, 0x1000, CRC(9b249fe5) SHA1(c01e0d572c4c163f3cf4b2aa9f4246427811b78d) )
- ROM_LOAD( "mpa-4w.3j", 0x3000, 0x1000, CRC(fee76972) SHA1(c3166b027f89f61964ead804d3c2da387454c4c2) )
+ROM_START(mpatrolw)
+ ROM_REGION(0x10000, "maincpu", 0)
+ ROM_LOAD("mpa-1w.3m", 0x0000, 0x1000, CRC(baa1a1d4) SHA1(7968a7f221e7f4c9c81ddc8de17f6568e17b9ea8))
+ ROM_LOAD("mpa-2w.3l", 0x1000, 0x1000, CRC(52459e51) SHA1(ae685b7848baa1b87a3f2bce97356286171e16d4))
+ ROM_LOAD("mpa-3w.3k", 0x2000, 0x1000, CRC(9b249fe5) SHA1(c01e0d572c4c163f3cf4b2aa9f4246427811b78d))
+ ROM_LOAD("mpa-4w.3j", 0x3000, 0x1000, CRC(fee76972) SHA1(c3166b027f89f61964ead804d3c2da387454c4c2))
+
+ ROM_REGION(0x8000, "irem_audio:iremsound", 0)
+ ROM_LOAD("mp-s1.1a", 0x7000, 0x1000, CRC(561d3108) SHA1(4998c68a9e9a8002251fa8f07aa1082444a9dc80))
+
+ ROM_REGION(0x2000, "tx", 0)
+ ROM_LOAD("mpe-5w.3e", 0x0000, 0x1000, CRC(f56e01fe) SHA1(93f582d63b9cd5c6dca207aa57b213c939cdda1d))
+ ROM_LOAD("mpe-4w.3f", 0x1000, 0x1000, CRC(caaba2d9) SHA1(7016a26c2d01e3209749598e993cd8ce91f12c88))
+
+ /* 0x2000-0x2fff is intentionally left as 0x00 fill, unused bitplane */
+ ROM_REGION(0x3000, "sp", ROMREGION_ERASE00)
+ ROM_LOAD("mpb-2.3m", 0x0000, 0x1000, CRC(707ace5e) SHA1(93c682e13e74bce29ced3a87bffb29569c114c3b))
+ ROM_LOAD("mpb-1.3n", 0x1000, 0x1000, CRC(9b72133a) SHA1(1393ef92ae1ad58a4b62ca1660c0793d30a8b5e2))
- ROM_REGION( 0x8000, "irem_audio:iremsound", 0 )
- ROM_LOAD( "mp-s1.1a", 0x7000, 0x1000, CRC(561d3108) SHA1(4998c68a9e9a8002251fa8f07aa1082444a9dc80) )
+ /* 0x1000-01fff is intentionally left as 0xff fill for the bg regions */
+ ROM_REGION(0x2000, "bg0", ROMREGION_ERASEFF)
+ ROM_LOAD("mpe-1.3l", 0x0000, 0x1000, CRC(c46a7f72) SHA1(8bb7c9acaf6833fb6c0575b015991b873a305a84))
- ROM_REGION( 0x2000, "gfx1", 0 )
- ROM_LOAD( "mpe-5w.3e", 0x0000, 0x1000, CRC(f56e01fe) SHA1(93f582d63b9cd5c6dca207aa57b213c939cdda1d) ) /* chars */
- ROM_LOAD( "mpe-4w.3f", 0x1000, 0x1000, CRC(caaba2d9) SHA1(7016a26c2d01e3209749598e993cd8ce91f12c88) )
+ ROM_REGION(0x2000, "bg1", ROMREGION_ERASEFF)
+ ROM_LOAD("mpe-2.3k", 0x0000, 0x1000, CRC(c7aa1fb0) SHA1(14c6c76e1d0db2c0745e5d6d33ea6945fac8e9ee))
- ROM_REGION( 0x2000, "gfx2", 0 )
- ROM_LOAD( "mpb-2.3m", 0x0000, 0x1000, CRC(707ace5e) SHA1(93c682e13e74bce29ced3a87bffb29569c114c3b) ) /* sprites */
- ROM_LOAD( "mpb-1.3n", 0x1000, 0x1000, CRC(9b72133a) SHA1(1393ef92ae1ad58a4b62ca1660c0793d30a8b5e2) )
+ ROM_REGION(0x2000, "bg2", ROMREGION_ERASEFF)
+ ROM_LOAD("mpe-3.3h", 0x0000, 0x1000, CRC(a0919392) SHA1(8a090cb8d483a3d67c7360058e3fdd70e151cd62))
- ROM_REGION( 0x1000, "gfx3", 0 )
- ROM_LOAD( "mpe-1.3l", 0x0000, 0x1000, CRC(c46a7f72) SHA1(8bb7c9acaf6833fb6c0575b015991b873a305a84) ) /* background graphics */
+ ROM_REGION(0x0200, "tx_pal", 0)
+ ROM_LOAD("mpc-4a.2a", 0x0000, 0x0200, CRC(cb0a5ff3) SHA1(d3f88b4e0c4858abac8b52105656ecece0cf4df9))
- ROM_REGION( 0x1000, "gfx4", 0 )
- ROM_LOAD( "mpe-2.3k", 0x0000, 0x1000, CRC(c7aa1fb0) SHA1(14c6c76e1d0db2c0745e5d6d33ea6945fac8e9ee) )
+ ROM_REGION(0x0020, "bg_pal", 0)
+ ROM_LOAD("mpc-3.1m", 0x0000, 0x0020, CRC(6a57eff2) SHA1(2d1c12dab5915da2ccd466e39436c88be434d634))
- ROM_REGION( 0x1000, "gfx5", 0 )
- ROM_LOAD( "mpe-3.3h", 0x0000, 0x1000, CRC(a0919392) SHA1(8a090cb8d483a3d67c7360058e3fdd70e151cd62) )
+ ROM_REGION(0x0020, "spr_pal", 0)
+ ROM_LOAD("mpc-1.1f", 0x0000, 0x0020, CRC(26979b13) SHA1(8c41a8cce4f3384c392a9f7a223a50d7be0e14a5))
- ROM_REGION( 0x0340, "proms", 0 )
- ROM_LOAD( "mpc-4a.2a", 0x0000, 0x0200, CRC(cb0a5ff3) SHA1(d3f88b4e0c4858abac8b52105656ecece0cf4df9) )
- ROM_LOAD( "mpc-3.1m", 0x0200, 0x0020, CRC(6a57eff2) SHA1(2d1c12dab5915da2ccd466e39436c88be434d634) ) /* background palette */
- ROM_LOAD( "mpc-1.1f", 0x0220, 0x0020, CRC(26979b13) SHA1(8c41a8cce4f3384c392a9f7a223a50d7be0e14a5) ) /* sprite palette */
- ROM_LOAD( "mpc-2.2h", 0x0240, 0x0100, CRC(7ae4cd97) SHA1(bc0662fac82ffe65f02092d912b2c2b0c7a8ac2b) ) /* sprite lookup table */
+ ROM_REGION(0x0100, "spr_clut", 0)
+ ROM_LOAD("mpc-2.2h", 0x0000, 0x0100, CRC(7ae4cd97) SHA1(bc0662fac82ffe65f02092d912b2c2b0c7a8ac2b))
ROM_END
-ROM_START( mranger )
- ROM_REGION( 0x10000, "maincpu", 0 )
- ROM_LOAD( "mpa-1.3m", 0x0000, 0x1000, CRC(5873a860) SHA1(8c03726d6e049c3edbc277440184e31679f78258) )
- ROM_LOAD( "mra-2.3l", 0x1000, 0x1000, CRC(217dd431) SHA1(7b81f854209afc1fd3df11b7375f36de6bc4a7c3) )
- ROM_LOAD( "mra-3.3k", 0x2000, 0x1000, CRC(9f0af7b2) SHA1(3daaec15b0d3bc30723ebb14b50f66f288f0d096) )
- ROM_LOAD( "mra-4.3j", 0x3000, 0x1000, CRC(7fe8e2cd) SHA1(4ffad9c7a9360999b213b790c6c76cc79c8e49d5) )
+ROM_START(mranger)
+ ROM_REGION(0x10000, "maincpu", 0)
+ ROM_LOAD("mpa-1.3m", 0x0000, 0x1000, CRC(5873a860) SHA1(8c03726d6e049c3edbc277440184e31679f78258))
+ ROM_LOAD("mra-2.3l", 0x1000, 0x1000, CRC(217dd431) SHA1(7b81f854209afc1fd3df11b7375f36de6bc4a7c3))
+ ROM_LOAD("mra-3.3k", 0x2000, 0x1000, CRC(9f0af7b2) SHA1(3daaec15b0d3bc30723ebb14b50f66f288f0d096))
+ ROM_LOAD("mra-4.3j", 0x3000, 0x1000, CRC(7fe8e2cd) SHA1(4ffad9c7a9360999b213b790c6c76cc79c8e49d5))
- ROM_REGION( 0x8000, "irem_audio:iremsound", 0 )
- ROM_LOAD( "mp-s1.1a", 0x7000, 0x1000, CRC(561d3108) SHA1(4998c68a9e9a8002251fa8f07aa1082444a9dc80) )
+ ROM_REGION(0x8000, "irem_audio:iremsound", 0)
+ ROM_LOAD("mp-s1.1a", 0x7000, 0x1000, CRC(561d3108) SHA1(4998c68a9e9a8002251fa8f07aa1082444a9dc80))
- ROM_REGION( 0x2000, "gfx1", 0 )
- ROM_LOAD( "mpe-5.3e", 0x0000, 0x1000, CRC(e3ee7f75) SHA1(b03d0d56150d3e9da4a4c871338097b4f450b649) ) /* chars */
- ROM_LOAD( "mpe-4.3f", 0x1000, 0x1000, CRC(cca6d023) SHA1(fecb3059fb09897a096add9452b50aec55c07545) )
+ ROM_REGION(0x2000, "tx", 0)
+ ROM_LOAD("mpe-5.3e", 0x0000, 0x1000, CRC(e3ee7f75) SHA1(b03d0d56150d3e9da4a4c871338097b4f450b649))
+ ROM_LOAD("mpe-4.3f", 0x1000, 0x1000, CRC(cca6d023) SHA1(fecb3059fb09897a096add9452b50aec55c07545))
- ROM_REGION( 0x2000, "gfx2", 0 )
- ROM_LOAD( "mpb-2.3m", 0x0000, 0x1000, CRC(707ace5e) SHA1(93c682e13e74bce29ced3a87bffb29569c114c3b) ) /* sprites */
- ROM_LOAD( "mpb-1.3n", 0x1000, 0x1000, CRC(9b72133a) SHA1(1393ef92ae1ad58a4b62ca1660c0793d30a8b5e2) )
+ /* 0x2000-0x2fff is intentionally left as 0x00 fill, unused bitplane */
+ ROM_REGION(0x3000, "sp", ROMREGION_ERASE00)
+ ROM_LOAD("mpb-2.3m", 0x0000, 0x1000, CRC(707ace5e) SHA1(93c682e13e74bce29ced3a87bffb29569c114c3b))
+ ROM_LOAD("mpb-1.3n", 0x1000, 0x1000, CRC(9b72133a) SHA1(1393ef92ae1ad58a4b62ca1660c0793d30a8b5e2))
- ROM_REGION( 0x1000, "gfx3", 0 )
- ROM_LOAD( "mpe-1.3l", 0x0000, 0x1000, CRC(c46a7f72) SHA1(8bb7c9acaf6833fb6c0575b015991b873a305a84) ) /* background graphics */
+ /* 0x1000-01fff is intentionally left as 0xff fill for the bg regions */
+ ROM_REGION(0x2000, "bg0", ROMREGION_ERASEFF)
+ ROM_LOAD("mpe-1.3l", 0x0000, 0x1000, CRC(c46a7f72) SHA1(8bb7c9acaf6833fb6c0575b015991b873a305a84))
- ROM_REGION( 0x1000, "gfx4", 0 )
- ROM_LOAD( "mpe-2.3k", 0x0000, 0x1000, CRC(c7aa1fb0) SHA1(14c6c76e1d0db2c0745e5d6d33ea6945fac8e9ee) )
+ ROM_REGION(0x2000, "bg1", ROMREGION_ERASEFF)
+ ROM_LOAD("mpe-2.3k", 0x0000, 0x1000, CRC(c7aa1fb0) SHA1(14c6c76e1d0db2c0745e5d6d33ea6945fac8e9ee))
- ROM_REGION( 0x1000, "gfx5", 0 )
- ROM_LOAD( "mpe-3.3h", 0x0000, 0x1000, CRC(a0919392) SHA1(8a090cb8d483a3d67c7360058e3fdd70e151cd62) )
+ ROM_REGION(0x2000, "bg2", ROMREGION_ERASEFF)
+ ROM_LOAD("mpe-3.3h", 0x0000, 0x1000, CRC(a0919392) SHA1(8a090cb8d483a3d67c7360058e3fdd70e151cd62))
- ROM_REGION( 0x0340, "proms", 0 )
- ROM_LOAD( "mpc-4.2a", 0x0000, 0x0200, CRC(07f99284) SHA1(dfc52958f2520e1ce4446dd4c84c91413bbacf76) )
- ROM_LOAD( "mpc-3.1m", 0x0200, 0x0020, CRC(6a57eff2) SHA1(2d1c12dab5915da2ccd466e39436c88be434d634) ) /* background palette */
- ROM_LOAD( "mpc-1.1f", 0x0220, 0x0020, CRC(26979b13) SHA1(8c41a8cce4f3384c392a9f7a223a50d7be0e14a5) ) /* sprite palette */
- ROM_LOAD( "mpc-2.2h", 0x0240, 0x0100, CRC(7ae4cd97) SHA1(bc0662fac82ffe65f02092d912b2c2b0c7a8ac2b) ) /* sprite lookup table */
-ROM_END
+ ROM_REGION(0x0200, "tx_pal", 0)
+ ROM_LOAD("mpc-4.2a", 0x0000, 0x0200, CRC(07f99284) SHA1(dfc52958f2520e1ce4446dd4c84c91413bbacf76))
+
+ ROM_REGION(0x0020, "bg_pal", 0)
+ ROM_LOAD("mpc-3.1m", 0x0000, 0x0020, CRC(6a57eff2) SHA1(2d1c12dab5915da2ccd466e39436c88be434d634))
+ ROM_REGION(0x0020, "spr_pal", 0)
+ ROM_LOAD("mpc-1.1f", 0x0000, 0x0020, CRC(26979b13) SHA1(8c41a8cce4f3384c392a9f7a223a50d7be0e14a5))
-ROM_START( alpha1v )
- ROM_REGION( 0x10000, "maincpu", 0 )
- ROM_LOAD( "2-m3", 0x0000, 0x1000, CRC(3a679d34) SHA1(1a54a43070c56dc91d4d258f29e29613bb309f1c) )
- ROM_LOAD( "3-l3", 0x1000, 0x1000, CRC(2f09df64) SHA1(e91602e9e41ad24dd1d7f384ed81b9bdaadd03e1) )
- ROM_LOAD( "4-k3", 0x2000, 0x1000, CRC(64fb9c8a) SHA1(735fd00cc42193a417e6cde75f12b4cf2e804942) )
- ROM_LOAD( "5-j3", 0x3000, 0x1000, CRC(d1643d18) SHA1(7c794b82e17e2ba0a6237e3fc20d8314f6c2481c) )
- ROM_LOAD( "6-h3", 0x4000, 0x1000, CRC(cf34ab51) SHA1(3696da71e2bc7edd1ee7aeaac87be5386608c09e) )
- ROM_LOAD( "7-f3", 0x5000, 0x1000, CRC(99db9781) SHA1(a56a675cc4cbc9681bfe8052f51f19336eb2a0a6) )
- ROM_LOAD( "7a e3", 0x6000, 0x1000, CRC(3b0b4b0d) SHA1(0d8eea1e2db269943611289b3490a578ee347f85) )
-
- ROM_REGION( 0x8000, "irem_audio:iremsound", 0 )
- ROM_LOAD( "1-a1", 0x7000, 0x1000, CRC(9e07fdd5) SHA1(ed4f462fcfe91fa8e88bfeaaba0a0c11fa0b4601) )
-
- ROM_REGION( 0x2000, "gfx1", 0 )
- ROM_LOAD( "14-e3", 0x0000, 0x1000, CRC(cf00c737) SHA1(415e90289039cac4d04cb1d559f1378ca6a32132) ) /* chars */
- ROM_LOAD( "13-f3", 0x1000, 0x1000, CRC(4b799229) SHA1(42cbdcf787b08b041d30504d699a12c378224933) )
-
- ROM_REGION( 0x3000, "gfx2", 0 ) // 3bpp? (mpatrol is 2bpp..)
- ROM_LOAD( "15-n3", 0x0000, 0x1000, CRC(dc26df76) SHA1(dd1cff7935f5559f9d1b440e02d5e5aa521b0054) )
- ROM_LOAD( "16-l3", 0x1000, 0x1000, CRC(39b9863b) SHA1(da9da9a1066188f050c422dfed1bbbd3ba612ccc) )
- ROM_LOAD( "17-k3", 0x2000, 0x1000, CRC(cfd90773) SHA1(052e126888b6de636db9c521a090699c282b620b) )
-
- /* all the background roms just contain stars.. */
- ROM_REGION( 0x1000, "gfx3", 0 )
- ROM_LOAD( "11-k3", 0x0000, 0x1000, CRC(7659440a) SHA1(2efd27c82913513dd03e799f1ed3c10b0863677d) ) // these two match..
- ROM_LOAD( "12-jh3", 0x0000, 0x1000, CRC(7659440a) SHA1(2efd27c82913513dd03e799f1ed3c10b0863677d) )
-
- ROM_REGION( 0x1000, "gfx4", 0 )
- ROM_LOAD( "9-n3", 0x0000, 0x1000, CRC(0fdb7d13) SHA1(e828254a4f94df633d338b5772719276d41c6b7f) )
-
- ROM_REGION( 0x1000, "gfx5", 0 )
- ROM_LOAD( "10-lm3", 0x0000, 0x1000, CRC(9dde3a75) SHA1(293d093485be19bfb20685d76a08ac78e24062bf) )
-
- ROM_REGION( 0x0340, "proms", 0 )
- ROM_LOAD( "63s481-a2", 0x0000, 0x0200, CRC(58678ea8) SHA1(b13a78a5bca8ad5bdec1293512b53654768a7a7a) )
- ROM_LOAD( "18s030-m1", 0x0200, 0x0020, CRC(6a57eff2) SHA1(2d1c12dab5915da2ccd466e39436c88be434d634) ) /* background palette */
- ROM_LOAD( "mb7051-f1", 0x0220, 0x0020, CRC(d8bdd0df) SHA1(ca522428927911808214d319af314f601497ded4) ) /* sprite palette */
- ROM_LOAD( "mb7052-h2", 0x0240, 0x0100, CRC(ce9f0ef9) SHA1(3afb94ed033f272983bbed22a59856df7824ef8a) ) /* sprite lookup table */
+ ROM_REGION(0x0100, "spr_clut", 0)
+ ROM_LOAD("mpc-2.2h", 0x0000, 0x0100, CRC(7ae4cd97) SHA1(bc0662fac82ffe65f02092d912b2c2b0c7a8ac2b))
ROM_END
+ROM_START(alpha1v)
+ ROM_REGION(0x10000, "maincpu", 0)
+ ROM_LOAD("2-m3", 0x0000, 0x1000, CRC(3a679d34) SHA1(1a54a43070c56dc91d4d258f29e29613bb309f1c))
+ ROM_LOAD("3-l3", 0x1000, 0x1000, CRC(2f09df64) SHA1(e91602e9e41ad24dd1d7f384ed81b9bdaadd03e1))
+ ROM_LOAD("4-k3", 0x2000, 0x1000, CRC(64fb9c8a) SHA1(735fd00cc42193a417e6cde75f12b4cf2e804942))
+ ROM_LOAD("5-j3", 0x3000, 0x1000, CRC(d1643d18) SHA1(7c794b82e17e2ba0a6237e3fc20d8314f6c2481c))
+ ROM_LOAD("6-h3", 0x4000, 0x1000, CRC(cf34ab51) SHA1(3696da71e2bc7edd1ee7aeaac87be5386608c09e))
+ ROM_LOAD("7-f3", 0x5000, 0x1000, CRC(99db9781) SHA1(a56a675cc4cbc9681bfe8052f51f19336eb2a0a6))
+ ROM_LOAD("7a e3", 0x6000, 0x1000, CRC(3b0b4b0d) SHA1(0d8eea1e2db269943611289b3490a578ee347f85))
+
+ ROM_REGION(0x8000, "irem_audio:iremsound", 0)
+ ROM_LOAD("1-a1", 0x7000, 0x1000, CRC(9e07fdd5) SHA1(ed4f462fcfe91fa8e88bfeaaba0a0c11fa0b4601))
+
+ ROM_REGION(0x2000, "tx", 0)
+ ROM_LOAD("14-e3", 0x0000, 0x1000, CRC(cf00c737) SHA1(415e90289039cac4d04cb1d559f1378ca6a32132))
+ ROM_LOAD("13-f3", 0x1000, 0x1000, CRC(4b799229) SHA1(42cbdcf787b08b041d30504d699a12c378224933))
+
+ ROM_REGION(0x3000, "sp", 0) // 3bpp (mpatrol is 2bpp)
+ ROM_LOAD("15-n3", 0x0000, 0x1000, CRC(dc26df76) SHA1(dd1cff7935f5559f9d1b440e02d5e5aa521b0054))
+ ROM_LOAD("16-l3", 0x1000, 0x1000, CRC(39b9863b) SHA1(da9da9a1066188f050c422dfed1bbbd3ba612ccc))
+ ROM_LOAD("17-k3", 0x2000, 0x1000, CRC(cfd90773) SHA1(052e126888b6de636db9c521a090699c282b620b))
+
+ /* all the background roms just contain stars, looks like it wants 2x128 px high images, instead of 3x64, arrangement unclear */
+ ROM_REGION(0x2000, "bg0", ROMREGION_ERASEFF)
+ ROM_LOAD("11-k3", 0x0000, 0x1000, CRC(7659440a) SHA1(2efd27c82913513dd03e799f1ed3c10b0863677d)) // rom is duplicated
+ ROM_LOAD("12-jh3", 0x1000, 0x1000, CRC(7659440a) SHA1(2efd27c82913513dd03e799f1ed3c10b0863677d))
+
+ ROM_REGION(0x2000, "bg1", ROMREGION_ERASEFF)
+ ROM_LOAD("9-n3", 0x0000, 0x1000, CRC(0fdb7d13) SHA1(e828254a4f94df633d338b5772719276d41c6b7f))
+ ROM_LOAD("10-lm3", 0x1000, 0x1000, CRC(9dde3a75) SHA1(293d093485be19bfb20685d76a08ac78e24062bf))
+
+ ROM_REGION(0x2000, "bg2", ROMREGION_ERASEFF)
+ // unused layer
+
+ ROM_REGION(0x0200, "tx_pal", 0)
+ ROM_LOAD("63s481-a2", 0x0000, 0x0200, CRC(58678ea8) SHA1(b13a78a5bca8ad5bdec1293512b53654768a7a7a))
+
+ ROM_REGION(0x0020, "bg_pal", 0)
+ ROM_LOAD("18s030-m1", 0x0000, 0x0020, CRC(6a57eff2) SHA1(2d1c12dab5915da2ccd466e39436c88be434d634))
+
+ ROM_REGION(0x0020, "spr_pal", 0)
+ ROM_LOAD("mb7051-f1", 0x0000, 0x0020, CRC(d8bdd0df) SHA1(ca522428927911808214d319af314f601497ded4))
+
+ ROM_REGION(0x0100, "spr_clut", 0)
+ ROM_LOAD("mb7052-h2", 0x0000, 0x0100, CRC(ce9f0ef9) SHA1(3afb94ed033f272983bbed22a59856df7824ef8a))
+ROM_END
+
/*************************************
- *
- * Game drivers
- *
- *************************************/
+*
+* Game drivers
+*
+*************************************/
+
+GAME(1982, mpatrol, 0, m52, mpatrol, m52_state, empty_init, ROT0, "Irem", "Moon Patrol", MACHINE_SUPPORTS_SAVE)
+GAME(1982, mpatrolw, mpatrol, m52, mpatrolw, m52_state, empty_init, ROT0, "Irem (Williams license)", "Moon Patrol (Williams)", MACHINE_SUPPORTS_SAVE) // USA
+GAME(1982, mranger, mpatrol, m52, mpatrol, m52_state, empty_init, ROT0, "bootleg", "Moon Ranger (bootleg of Moon Patrol)", MACHINE_SUPPORTS_SAVE) // Italy
-GAME( 1982, mpatrol, 0, m52, mpatrol, m52_state, empty_init, ROT0, "Irem", "Moon Patrol", MACHINE_SUPPORTS_SAVE )
-GAME( 1982, mpatrolw, mpatrol, m52, mpatrolw, m52_state, empty_init, ROT0, "Irem (Williams license)", "Moon Patrol (Williams)", MACHINE_SUPPORTS_SAVE ) // USA
-GAME( 1982, mranger, mpatrol, m52, mpatrol, m52_state, empty_init, ROT0, "bootleg", "Moon Ranger (bootleg of Moon Patrol)", MACHINE_SUPPORTS_SAVE ) // Italy
-GAME( 1988, alpha1v, 0, alpha1v, alpha1v, m52_state, empty_init, ROT0, "Vision Electronics", "Alpha One (Vision Electronics)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND | MACHINE_SUPPORTS_SAVE )
+GAME(1988, alpha1v, 0, alpha1v, alpha1v, m52_alpha1v_state, empty_init, ROT0, "Vision Electronics", "Alpha One (Vision Electronics)", MACHINE_SUPPORTS_SAVE)
diff --git a/src/mame/drivers/m72.cpp b/src/mame/drivers/m72.cpp
index ef60eed7877..bdd3c946c47 100644
--- a/src/mame/drivers/m72.cpp
+++ b/src/mame/drivers/m72.cpp
@@ -1847,8 +1847,8 @@ MACHINE_CONFIG_START(m72_state::m72_base)
MCFG_DEVICE_PROGRAM_MAP(sound_ram_map)
MCFG_DEVICE_IO_MAP(sound_portmap)
- MCFG_DEVICE_ADD("upd71059c", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE("maincpu", 0))
+ PIC8259(config, m_upd71059c, 0);
+ m_upd71059c->out_int_callback().set_inputline(m_maincpu, 0);
/* video hardware */
MCFG_DEVICE_ADD("gfxdecode", GFXDECODE, "palette", gfx_m72)
@@ -1878,7 +1878,7 @@ MACHINE_CONFIG_START(m72_state::m72_8751)
MCFG_DEVICE_IO_MAP(m72_protected_portmap)
MB8421_MB8431_16BIT(config, m_dpram);
- //m_dpram->intl_callback().set("upd71059c", FUNC(pic8259_device::ir3_w)); // not actually used?
+ //m_dpram->intl_callback().set(m_upd71059c, FUNC(pic8259_device::ir3_w)); // not actually used?
m_dpram->intr_callback().set_inputline("mcu", MCS51_INT0_LINE);
MCFG_GENERIC_LATCH_8_ADD("mculatch")
@@ -1983,8 +1983,8 @@ MACHINE_CONFIG_START(m72_state::rtype2)
MCFG_DEVICE_PERIODIC_INT_DRIVER(m72_state, nmi_line_pulse, 128*55) /* clocked by V1? (Vigilante) */
/* IRQs are generated by main Z80 and YM2151 */
- MCFG_DEVICE_ADD("upd71059c", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE("maincpu", 0))
+ PIC8259(config, m_upd71059c, 0);
+ m_upd71059c->out_int_callback().set_inputline(m_maincpu, 0);
/* video hardware */
MCFG_DEVICE_ADD("gfxdecode", GFXDECODE, "palette", gfx_rtype2)
@@ -2029,7 +2029,7 @@ MACHINE_CONFIG_START(m72_state::cosmccop)
MCFG_MACHINE_START_OVERRIDE(m72_state,kengo)
MCFG_MACHINE_RESET_OVERRIDE(m72_state,kengo)
- // upd71059c isn't needed beacuse the V35 has its own IRQ controller
+ // upd71059c isn't needed because the V35 has its own IRQ controller
/* video hardware */
MCFG_DEVICE_ADD("gfxdecode", GFXDECODE, "palette", gfx_rtype2)
@@ -2073,8 +2073,8 @@ MACHINE_CONFIG_START(m72_state::m82)
MCFG_DEVICE_PERIODIC_INT_DRIVER(m72_state, nmi_line_pulse, 128*55) /* clocked by V1? (Vigilante) */
/* IRQs are generated by main Z80 and YM2151 */
- MCFG_DEVICE_ADD("upd71059c", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE("maincpu", 0))
+ PIC8259(config, m_upd71059c, 0);
+ m_upd71059c->out_int_callback().set_inputline(m_maincpu, 0);
/* video hardware */
MCFG_DEVICE_ADD("gfxdecode", GFXDECODE, "palette", gfx_majtitle)
@@ -2108,8 +2108,8 @@ MACHINE_CONFIG_START(m72_state::poundfor)
MCFG_DEVICE_PERIODIC_INT_DRIVER(m72_state, fake_nmi, 128*55) /* clocked by V1? (Vigilante) */
/* IRQs are generated by main Z80 and YM2151 */
- MCFG_DEVICE_ADD("upd71059c", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE("maincpu", 0))
+ PIC8259(config, m_upd71059c, 0);
+ m_upd71059c->out_int_callback().set_inputline(m_maincpu, 0);
UPD4701A(config, m_upd4701[0]);
m_upd4701[0]->set_portx_tag("TRACK0_X");
diff --git a/src/mame/drivers/m92.cpp b/src/mame/drivers/m92.cpp
index 7045b7bc98a..293470ccb66 100644
--- a/src/mame/drivers/m92.cpp
+++ b/src/mame/drivers/m92.cpp
@@ -925,8 +925,8 @@ MACHINE_CONFIG_START(m92_state::m92)
MCFG_DEVICE_ADD("soundcpu" ,V35, XTAL(14'318'181))
MCFG_DEVICE_PROGRAM_MAP(sound_map)
- MCFG_DEVICE_ADD("upd71059c", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE("maincpu", 0))
+ PIC8259(config, m_upd71059c, 0);
+ m_upd71059c->out_int_callback().set_inputline(m_maincpu, 0);
MCFG_MACHINE_RESET_OVERRIDE(m92_state,m92)
@@ -957,7 +957,7 @@ MACHINE_CONFIG_START(m92_state::m92)
MCFG_GENERIC_LATCH_SEPARATE_ACKNOWLEDGE(true)
MCFG_GENERIC_LATCH_8_ADD("soundlatch2")
- MCFG_GENERIC_LATCH_DATA_PENDING_CB(WRITELINE("upd71059c", pic8259_device, ir3_w))
+ MCFG_GENERIC_LATCH_DATA_PENDING_CB(WRITELINE(m_upd71059c, pic8259_device, ir3_w))
MCFG_DEVICE_ADD("ymsnd", YM2151, XTAL(14'318'181)/4)
MCFG_YM2151_IRQ_HANDLER(INPUTLINE("soundcpu", NEC_INPUT_LINE_INTP0))
diff --git a/src/mame/drivers/mbc55x.cpp b/src/mame/drivers/mbc55x.cpp
index c12bdf9e0e1..704b5155bfa 100644
--- a/src/mame/drivers/mbc55x.cpp
+++ b/src/mame/drivers/mbc55x.cpp
@@ -243,10 +243,10 @@ static void mbc55x_floppies(device_slot_interface &device)
MACHINE_CONFIG_START(mbc55x_state::mbc55x)
/* basic machine hardware */
- MCFG_DEVICE_ADD(MAINCPU_TAG, I8088, 3600000)
- MCFG_DEVICE_PROGRAM_MAP(mbc55x_mem)
- MCFG_DEVICE_IO_MAP(mbc55x_io)
- MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE(PIC8259_TAG, pic8259_device, inta_cb)
+ I8088(config, m_maincpu, 3600000);
+ m_maincpu->set_addrmap(AS_PROGRAM, &mbc55x_state::mbc55x_mem);
+ m_maincpu->set_addrmap(AS_IO, &mbc55x_state::mbc55x_io);
+ m_maincpu->set_irq_acknowledge_callback(PIC8259_TAG, FUNC(pic8259_device::inta_cb));
/* video hardware */
MCFG_SCREEN_ADD(SCREEN_TAG, RASTER)
@@ -267,18 +267,18 @@ MACHINE_CONFIG_START(mbc55x_state::mbc55x)
/* Devices */
I8251(config, m_kb_uart, 0);
- m_kb_uart->rxrdy_handler().set(PIC8259_TAG, FUNC(pic8259_device::ir3_w));
-
- MCFG_DEVICE_ADD(PIT8253_TAG, PIT8253, 0)
- MCFG_PIT8253_CLK0(PIT_C0_CLOCK)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(PIC8259_TAG, pic8259_device, ir0_w))
- MCFG_PIT8253_CLK1(PIT_C1_CLOCK)
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(PIC8259_TAG, pic8259_device, ir1_w))
- MCFG_PIT8253_CLK2(PIT_C2_CLOCK)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, mbc55x_state, pit8253_t2))
-
- MCFG_DEVICE_ADD(PIC8259_TAG, PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE(MAINCPU_TAG, INPUT_LINE_IRQ0))
+ m_kb_uart->rxrdy_handler().set(m_pic, FUNC(pic8259_device::ir3_w));
+
+ PIT8253(config, m_pit, 0);
+ m_pit->set_clk<0>(PIT_C0_CLOCK);
+ m_pit->out_handler<0>().set(m_pic, FUNC(pic8259_device::ir0_w));
+ m_pit->set_clk<1>(PIT_C1_CLOCK);
+ m_pit->out_handler<1>().set(m_pic, FUNC(pic8259_device::ir1_w));
+ m_pit->set_clk<2>(PIT_C2_CLOCK);
+ m_pit->out_handler<2>().set(FUNC(mbc55x_state::pit8253_t2));
+
+ PIC8259(config, m_pic, 0);
+ m_pic->out_int_callback().set_inputline(m_maincpu, INPUT_LINE_IRQ0);
I8255(config, m_ppi);
m_ppi->in_pa_callback().set(FUNC(mbc55x_state::mbc55x_ppi_porta_r));
diff --git a/src/mame/drivers/mc1502.cpp b/src/mame/drivers/mc1502.cpp
index 2b377058b87..9a209483353 100644
--- a/src/mame/drivers/mc1502.cpp
+++ b/src/mame/drivers/mc1502.cpp
@@ -2,7 +2,7 @@
// copyright-holders:Sergey Svishchev
/***************************************************************************
- drivers/mc1502.c
+ drivers/mc1502.cpp
Driver file for Elektronika MS 1502
@@ -230,24 +230,24 @@ static INPUT_PORTS_START( mc1502 )
INPUT_PORTS_END
MACHINE_CONFIG_START(mc1502_state::mc1502)
- MCFG_DEVICE_ADD("maincpu", I8088, XTAL(16'000'000)/3)
- MCFG_DEVICE_PROGRAM_MAP(mc1502_map)
- MCFG_DEVICE_IO_MAP(mc1502_io)
- MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE("pic8259", pic8259_device, inta_cb)
+ I8088(config, m_maincpu, XTAL(16'000'000)/3);
+ m_maincpu->set_addrmap(AS_PROGRAM, &mc1502_state::mc1502_map);
+ m_maincpu->set_addrmap(AS_IO, &mc1502_state::mc1502_io);
+ m_maincpu->set_irq_acknowledge_callback("pic8259", FUNC(pic8259_device::inta_cb));
MCFG_MACHINE_START_OVERRIDE( mc1502_state, mc1502 )
MCFG_MACHINE_RESET_OVERRIDE( mc1502_state, mc1502 )
- MCFG_DEVICE_ADD("pit8253", PIT8253, 0)
- MCFG_PIT8253_CLK0(XTAL(16'000'000)/12) /* heartbeat IRQ */
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE("pic8259", pic8259_device, ir0_w))
- MCFG_PIT8253_CLK1(XTAL(16'000'000)/12) /* serial port */
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(*this, mc1502_state, mc1502_pit8253_out1_changed))
- MCFG_PIT8253_CLK2(XTAL(16'000'000)/12) /* pio port c pin 4, and speaker polling enough */
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, mc1502_state, mc1502_pit8253_out2_changed))
+ PIT8253(config, m_pit8253, 0);
+ m_pit8253->set_clk<0>(XTAL(16'000'000)/12); /* heartbeat IRQ */
+ m_pit8253->out_handler<0>().set(m_pic8259, FUNC(pic8259_device::ir0_w));
+ m_pit8253->set_clk<1>(XTAL(16'000'000)/12); /* serial port */
+ m_pit8253->out_handler<1>().set(FUNC(mc1502_state::mc1502_pit8253_out1_changed));
+ m_pit8253->set_clk<2>(XTAL(16'000'000)/12); /* pio port c pin 4, and speaker polling enough */
+ m_pit8253->out_handler<2>().set(FUNC(mc1502_state::mc1502_pit8253_out2_changed));
- MCFG_DEVICE_ADD("pic8259", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE("maincpu", 0))
+ PIC8259(config, m_pic8259, 0);
+ m_pic8259->out_int_callback().set_inputline(m_maincpu, 0);
I8255(config, m_ppi8255n1);
m_ppi8255n1->out_pa_callback().set("cent_data_out", FUNC(output_latch_device::bus_w));
@@ -266,8 +266,8 @@ MACHINE_CONFIG_START(mc1502_state::mc1502)
m_upd8251->dtr_handler().set("rs232", FUNC(rs232_port_device::write_dtr));
m_upd8251->rts_handler().set("rs232", FUNC(rs232_port_device::write_rts));
/* XXX RxD data are accessible via PPI port C, bit 7 */
- m_upd8251->rxrdy_handler().set("pic8259", FUNC(pic8259_device::ir7_w)); /* default handler does nothing */
- m_upd8251->txrdy_handler().set("pic8259", FUNC(pic8259_device::ir7_w));
+ m_upd8251->rxrdy_handler().set(m_pic8259, FUNC(pic8259_device::ir7_w)); /* default handler does nothing */
+ m_upd8251->txrdy_handler().set(m_pic8259, FUNC(pic8259_device::ir7_w));
m_upd8251->syndet_handler().set(FUNC(mc1502_state::mc1502_i8251_syndet));
rs232_port_device &rs232(RS232_PORT(config, "rs232", default_rs232_devices, nullptr));
@@ -277,12 +277,12 @@ MACHINE_CONFIG_START(mc1502_state::mc1502)
MCFG_DEVICE_ADD("isa", ISA8, 0)
MCFG_ISA8_CPU("maincpu")
- MCFG_ISA_OUT_IRQ2_CB(WRITELINE("pic8259", pic8259_device, ir2_w))
- MCFG_ISA_OUT_IRQ3_CB(WRITELINE("pic8259", pic8259_device, ir3_w))
- MCFG_ISA_OUT_IRQ4_CB(WRITELINE("pic8259", pic8259_device, ir4_w))
- MCFG_ISA_OUT_IRQ5_CB(WRITELINE("pic8259", pic8259_device, ir5_w))
- MCFG_ISA_OUT_IRQ6_CB(WRITELINE("pic8259", pic8259_device, ir6_w))
- MCFG_ISA_OUT_IRQ7_CB(WRITELINE("pic8259", pic8259_device, ir7_w))
+ MCFG_ISA_OUT_IRQ2_CB(WRITELINE(m_pic8259, pic8259_device, ir2_w))
+ MCFG_ISA_OUT_IRQ3_CB(WRITELINE(m_pic8259, pic8259_device, ir3_w))
+ MCFG_ISA_OUT_IRQ4_CB(WRITELINE(m_pic8259, pic8259_device, ir4_w))
+ MCFG_ISA_OUT_IRQ5_CB(WRITELINE(m_pic8259, pic8259_device, ir5_w))
+ MCFG_ISA_OUT_IRQ6_CB(WRITELINE(m_pic8259, pic8259_device, ir6_w))
+ MCFG_ISA_OUT_IRQ7_CB(WRITELINE(m_pic8259, pic8259_device, ir7_w))
MCFG_DEVICE_ADD("board0", ISA8_SLOT, 0, "isa", mc1502_isa8_cards, "cga_mc1502", true) // FIXME: determine ISA bus clock
MCFG_DEVICE_ADD("isa1", ISA8_SLOT, 0, "isa", mc1502_isa8_cards, "fdc", false)
diff --git a/src/mame/drivers/mikie.cpp b/src/mame/drivers/mikie.cpp
index 86612a0e223..613f2f3f4b1 100644
--- a/src/mame/drivers/mikie.cpp
+++ b/src/mame/drivers/mikie.cpp
@@ -362,6 +362,32 @@ ROM_START( mikiej )
ROM_LOAD( "d18.f9", 0x0400, 0x0100, CRC(7396b374) SHA1(fedcc421a61d6623dc9c41b0a3e164efeb50ec7c) ) // sprite lookup table
ROM_END
+ROM_START( mikiek )
+ ROM_REGION( 0x10000, "maincpu", 0 )
+ ROM_LOAD( "n14.11c", 0x6000, 0x2000, CRC(f698e6dd) SHA1(99220eeee4e7b88caa26f2d08502689e1f1fcdf8) )
+ ROM_LOAD( "o13.12a", 0x8000, 0x4000, CRC(826e7035) SHA1(bd62783cb1ba4e7f0196f337280461bb7627f70f) )
+ ROM_LOAD( "o17.12d", 0xc000, 0x4000, CRC(161c25c8) SHA1(373a92b8412676ad9870cb562c73e47db7b40bea) )
+
+ ROM_REGION( 0x10000, "audiocpu", 0 )
+ ROM_LOAD( "n10.6e", 0x0000, 0x2000, CRC(2cf9d670) SHA1(b324b92aff70d7878160128611dd5fdec6949659) )
+
+ ROM_REGION( 0x4000, "gfx1", 0 )
+ ROM_LOAD( "q11.8i", 0x0000, 0x4000, CRC(29286fce) SHA1(699706cf7300c98352e355f81ba40635b4380d7a) )
+
+ ROM_REGION( 0x10000, "gfx2", 0 )
+ ROM_LOAD( "q01.f1", 0x0000, 0x4000, CRC(31551987) SHA1(b6cbdb8b511d99b27546a6c4d01f2948d5ad3a42) )
+ ROM_LOAD( "q03.f3", 0x4000, 0x4000, CRC(707cc98e) SHA1(850c973053f3ae8a93e7c630d69298f25708941e) )
+ ROM_LOAD( "q05.h1", 0x8000, 0x4000, CRC(f9e1ebb1) SHA1(c88c1fc22f21b3e7d558c47de2716dac01fdd621) )
+ ROM_LOAD( "q07.h3", 0xc000, 0x4000, CRC(44502ca9) SHA1(452e38512a4463602d98301f660dc7bf662e49f4) )
+
+ ROM_REGION( 0x500, "proms", 0 )
+ ROM_LOAD( "d19.1i", 0x0000, 0x0100, CRC(8b83e7cf) SHA1(4fce779947f9f318023c7c54a71a4751f6bb8eb1) ) // red component
+ ROM_LOAD( "d21.3i", 0x0100, 0x0100, CRC(3556304a) SHA1(6f4fc3ef6b1b44278e7c8c1034ee4fbef90cf85a) ) // green component
+ ROM_LOAD( "d20.2i", 0x0200, 0x0100, CRC(676a0669) SHA1(14236a831204d52cdf8c2ef318a565d6c5587ce0) ) // blue component
+ ROM_LOAD( "d22.12h", 0x0300, 0x0100, CRC(872be05c) SHA1(1525303589d7ed909bc6e2827fbaa2c16ad4030b) ) // character lookup table
+ ROM_LOAD( "d18.f9", 0x0400, 0x0100, CRC(7396b374) SHA1(fedcc421a61d6623dc9c41b0a3e164efeb50ec7c) ) // sprite lookup table
+ROM_END
+
ROM_START( mikiehs )
ROM_REGION( 0x10000, "maincpu", 0 )
ROM_LOAD( "l14.11c", 0x6000, 0x2000, CRC(633f3a6d) SHA1(9255e0cb8d53773a52cade2fbd2e4c1968164313) )
@@ -394,6 +420,7 @@ ROM_END
*
*************************************/
-GAME( 1984, mikie, 0, mikie, mikie, mikie_state, empty_init, ROT270, "Konami", "Mikie", MACHINE_SUPPORTS_SAVE )
-GAME( 1984, mikiej, mikie, mikie, mikie, mikie_state, empty_init, ROT270, "Konami", "Shinnyuushain Tooru-kun", MACHINE_SUPPORTS_SAVE )
-GAME( 1984, mikiehs, mikie, mikie, mikie, mikie_state, empty_init, ROT270, "Konami", "Mikie (High School Graffiti)", MACHINE_SUPPORTS_SAVE )
+GAME( 1984, mikie, 0, mikie, mikie, mikie_state, empty_init, ROT270, "Konami", "Mikie", MACHINE_SUPPORTS_SAVE )
+GAME( 1984, mikiej, mikie, mikie, mikie, mikie_state, empty_init, ROT270, "Konami", "Shinnyuushain Tooru-kun", MACHINE_SUPPORTS_SAVE )
+GAME( 1984, mikiek, mikie, mikie, mikie, mikie_state, empty_init, ROT270, "bootleg", "Shin Ib Sa Won - Seok Dol I", MACHINE_SUPPORTS_SAVE )
+GAME( 1984, mikiehs, mikie, mikie, mikie, mikie_state, empty_init, ROT270, "Konami", "Mikie (High School Graffiti)", MACHINE_SUPPORTS_SAVE )
diff --git a/src/mame/drivers/mikrosha.cpp b/src/mame/drivers/mikrosha.cpp
index 81e899688c6..fa810323ace 100644
--- a/src/mame/drivers/mikrosha.cpp
+++ b/src/mame/drivers/mikrosha.cpp
@@ -225,11 +225,11 @@ MACHINE_CONFIG_START(mikrosha_state::mikrosha)
MCFG_I8275_DRAW_CHARACTER_CALLBACK_OWNER(mikrosha_state, display_pixels)
MCFG_I8275_DRQ_CALLBACK(WRITELINE(m_dma8257,i8257_device, dreq2_w))
- MCFG_DEVICE_ADD("pit8253", PIT8253, 0)
- MCFG_PIT8253_CLK0(0)
- MCFG_PIT8253_CLK1(0)
- MCFG_PIT8253_CLK2(2000000)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, mikrosha_state, mikrosha_pit_out2))
+ pit8253_device &pit8253(PIT8253(config, "pit8253", 0));
+ pit8253.set_clk<0>(0);
+ pit8253.set_clk<1>(0);
+ pit8253.set_clk<2>(2000000);
+ pit8253.out_handler<2>().set(FUNC(mikrosha_state::mikrosha_pit_out2));
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
diff --git a/src/mame/drivers/miniframe.cpp b/src/mame/drivers/miniframe.cpp
index 0397f233673..92e76c4bd30 100644
--- a/src/mame/drivers/miniframe.cpp
+++ b/src/mame/drivers/miniframe.cpp
@@ -224,10 +224,11 @@ static void miniframe_floppies(device_slot_interface &device)
device.option_add("525dd", FLOPPY_525_DD);
}
-MACHINE_CONFIG_START(miniframe_state::miniframe)
+void miniframe_state::miniframe(machine_config &config)
+{
// basic machine hardware
- MCFG_DEVICE_ADD("maincpu", M68010, XTAL(10'000'000))
- MCFG_DEVICE_PROGRAM_MAP(miniframe_mem)
+ M68010(config, m_maincpu, XTAL(10'000'000));
+ m_maincpu->set_addrmap(AS_PROGRAM, &miniframe_state::miniframe_mem);
// internal ram
RAM(config, RAM_TAG).set_default_size("1M").set_extra_options("2M");
@@ -239,7 +240,7 @@ MACHINE_CONFIG_START(miniframe_state::miniframe)
WD2797(config, m_wd2797, 1000000);
// m_wd2797->intrq_wr_callback().set(FUNC(miniframe_state::wd2797_intrq_w));
// m_wd2797->drq_wr_callback().set(FUNC(miniframe_state::wd2797_drq_w));
- MCFG_FLOPPY_DRIVE_ADD("wd2797:0", miniframe_floppies, "525dd", floppy_image_device::default_floppy_formats)
+ FLOPPY_CONNECTOR(config, "wd2797:0", miniframe_floppies, "525dd", floppy_image_device::default_floppy_formats);
// 8263s
pit8253_device &pit8253(PIT8253(config, "pit8253", 0));
@@ -257,10 +258,10 @@ MACHINE_CONFIG_START(miniframe_state::miniframe)
baudgen.set_clk<2>(1228800);
// PIC8259s
- MCFG_DEVICE_ADD("pic8259", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE("maincpu", M68K_IRQ_4))
- MCFG_PIC8259_IN_SP_CB(CONSTANT(1))
-MACHINE_CONFIG_END
+ pic8259_device &pic8259(PIC8259(config, "pic8259", 0));
+ pic8259.out_int_callback().set_inputline(m_maincpu, M68K_IRQ_4);
+ pic8259.in_sp_callback().set_constant(1);
+}
/***************************************************************************
diff --git a/src/mame/drivers/mips.cpp b/src/mame/drivers/mips.cpp
index 2a184bf2af6..ed9b67ef0b5 100644
--- a/src/mame/drivers/mips.cpp
+++ b/src/mame/drivers/mips.cpp
@@ -38,31 +38,82 @@
* http://www.jp.netbsd.org/ports/mipsco/models.html
*
* TODO
- * - everything (skeleton only)
+ * - implement cpu tlb
+ * - remaining iop interface
+ * - figure out the brcond0 signal
+ * - keyboard controller and keyboard
+ * - floppy drive
+ * - buzzer
*
* Ref Part Function
*
* System board:
*
+ * MIPS R2000A Main CPU
+ * PACEMIPS PR2010A Floating point unit
+ * 33.3330 MHz crystal CPU clock
+ * DL15CC200
+ * DDU7F-25 Delay line (10 taps @ 2.5ns per tap)
+ * VLSI VL85C30-08PC Serial port controller
+ * ST Z8038AB1 FIO Parallel port controller
+ * 1.8432 MHz crystal Serial clock
+ * NEC D70216L-10 I/O processor
+ * Adaptec AIC-6250DL SCSI controller
+ * AMD AM7990DCB/80 Ethernet controller
+ * 20 MHz crystal
+ * 2VP5U9 DC/DC converter (Ethernet transceiver power?)
+ * WDC WD37C65BJW Floppy controller
+ * Intel P8742AH Keyboard controller
+ * Dallas DS1287 RTC and NVRAM
+ * buzzer Connected to keyboard controller?
+ *
+ * P4C164-25PC Cache RAM? (8Kx8, total 112KiB)
+ * U?-U? 14 parts
+ *
+ * 27C512 64K EPROM V50 IPL (64Kx8, total 256KiB)
+ * U139-U142 4 parts
+ *
+ * M5M4464 V50 RAM (64Kx4, total 128KiB)
+ * U164-U167 4 parts
+ *
* Video board:
+ * Idt75C458 256x24 Color RAMDAC
+ * Bt438KC Clock generator
+ * 108.180 MHz crystal
*
+ * D41264V-12 Video RAM (64Kx4, total 1280KiB)
+ * U?-U? 40 parts
*/
/*
* WIP notes
*
- * nvram must be prepped with 0x74, 0x61 or 0x31 at offset 0x29
- *
- * Currently fails during IOP address path diagnostic. Bypass with:
- * bp f7c51; g
- * pc=f7c54; aw=0; g
+ * status: loads RISC/os, but dies probably due to missing R2000A TLB
*
* V50 internal peripherals:
* base = 0xfe00
* serial (sula): fe00
* timer (tula): fe08
* int (iula): fe10
- * dma (dula): fe20 - unimplemented in uPD71037 mode (sctl & 2)
+ * dma (dula): fe20
+ *
+ * V50 IPL diagnostic routines
+ * NVRAM f8dc4
+ * Ethernet ID f8b58
+ * Parallel f8c5c
+ * Keyboard f4cbc
+ * SCC ec0fc
+ * Floppy ee3ea
+ * SCSI f426e
+ * LANCE f8f68
*
+ * V50 interrupts:
+ * intp1 <- SCU
+ * intp2 <- CPU interface
+ * intp3 <- SCC
+ * intp4 <- FIO
+ * intp5 <- LANCE
+ * intp6 <- floppy?
+ * intp7 <- SCSI
*/
#include "emu.h"
@@ -71,56 +122,80 @@
#include "debugger.h"
+#define LOG_GENERAL (1U << 0)
+#define LOG_MMU (1U << 1)
+#define LOG_IOCB (1U << 2)
+
#define VERBOSE 0
#include "logmacro.h"
void rx2030_state::machine_start()
{
+ save_item(NAME(m_mmu));
+ save_item(NAME(m_iop_interface));
}
void rx2030_state::machine_reset()
{
+ m_cpu->set_input_line(INPUT_LINE_RESET, 1);
}
void rx2030_state::rx2030_init()
{
+ m_iop_interface = IOP_NERR | DBG_ABSENT;
+
// map the configured ram and vram
- m_maincpu->space(0).install_ram(0x00000000, 0x00000000 | m_ram->mask(), m_ram->pointer());
+ m_cpu->space(0).install_ram(0x00000000, m_ram->mask(), m_ram->pointer());
- if (m_vram)
- m_maincpu->space(0).install_ram(0x01000000, 0x01000000 | m_vram->mask(), m_vram->pointer());
+ // page zero of prom space is mapped to ram page zero
+ m_cpu->space(0).install_rom(0x1fc00000, 0x1fc00fff, m_ram->pointer());
+
+ if (!m_vram)
+ m_iop_interface |= VID_ABSENT;
}
-void rx2030_state::iop_program_map(address_map &map)
+u16 rx2030_state::mmu_r(offs_t offset, u16 mem_mask)
{
- map(0x00000, 0x1ffff).ram();
+ offs_t const address = (m_mmu[(offset >> 11) & 0x1f] << 12) | ((offset << 1) & 0xfff);
- map(0x20000, 0xbffff).lrw16("shared",
- [this](offs_t offset, u16 mem_mask)
- {
- offs_t const address = 0x1000 + (offset << 1);
+ u16 const data = (m_ram->read(BYTE4_XOR_BE(address + 1)) << 8) | m_ram->read(BYTE4_XOR_BE(address + 0));
- u16 const data = (m_ram->read(address + 1) << 8) | m_ram->read(address + 0);
- //logerror("shared_r 0x%04x data 0x%04x mask 0x%04x\n", address, data, mem_mask);
- return data;
- },
- [this](offs_t offset, u16 data, u16 mem_mask)
- {
- offs_t const address = 0x1000 + (offset << 1);
+ LOGMASKED(LOG_MMU, "mmu_r offset 0x%06x reg %d page 0x%04x mapped 0x%06x data 0x%04x\n",
+ (offset << 1), (offset >> 11) & 0x1f, m_mmu[(offset >> 11) & 0x1f], address, data);
- //logerror("shared_w 0x%04x data 0x%04x mask 0x%04x\n", address, data, mem_mask);
- m_ram->write(address + 0, data);
- m_ram->write(address + 1, data >> 8);
- });
- map(0xc0000, 0xfffff).rom().region("eprom", 0);
+ return data;
+}
+
+void rx2030_state::mmu_w(offs_t offset, u16 data, u16 mem_mask)
+{
+ offs_t const address = (m_mmu[(offset >> 11) & 0x1f] << 12) | ((offset << 1) & 0xfff);
+
+ LOGMASKED(LOG_MMU, "mmu_w offset 0x%06x reg %d page 0x%04x mapped 0x%06x data 0x%04x\n",
+ (offset << 1), (offset >> 11) & 0x1f, m_mmu[(offset >> 11) & 0x1f], address, data);
+
+ if (ACCESSING_BITS_0_7)
+ m_ram->write(BYTE4_XOR_BE(address + 0), data);
+
+ if (ACCESSING_BITS_8_15)
+ m_ram->write(BYTE4_XOR_BE(address + 1), data >> 8);
+}
+
+void rx2030_state::iop_program_map(address_map &map)
+{
+ // 00000:1ffff 128k ram (64kx4, 4 parts)
+ // 20000:3ffff 128k shared (32x4k mapped pages, bits 0-11 offset, bits 12-16 mmu register)
+ // 80000:fffff 512k eprom (256k x 2 copies)
+
+ map(0x00000, 0x1ffff).ram();
+ map(0x20000, 0x3ffff).rw(FUNC(rx2030_state::mmu_r), FUNC(rx2030_state::mmu_w));
+
+ map(0x80000, 0xbffff).rom().region("v50_ipl", 0).mirror(0x40000);
}
void rx2030_state::iop_io_map(address_map &map)
{
// 0x180-18a ? .umask16(0xff)
- // 0x1c0 ?
- // 0x044
- // 0x2c0
+ // 0x040, 0x044
map(0x0000, 0x003f).lrw16("mmu",
[this](offs_t offset, u16 mem_mask)
@@ -129,49 +204,162 @@ void rx2030_state::iop_io_map(address_map &map)
},
[this](offs_t offset, u16 data, u16 mem_mask)
{
- //logerror("mmu_w %d data 0x%04x\n", offset, data);
-
m_mmu[offset] = data;
});
+ //map(0x0040, 0x0041).r(m_fdc, FUNC(wd37c65c_device::msr_r)).umask16(0xff);
+ //map(0x0044, 0x0045).w(m_fdc, FUNC(wd37c65c_device::dor_w)).umask16(0xff);
+
+ map(0x0080, 0x0083).rw(m_scsi, FUNC(aic6250_device::read), FUNC(aic6250_device::write)).umask16(0xff);
+
map(0x00c0, 0x00c1).rw(m_kbdc, FUNC(at_keyboard_controller_device::data_r), FUNC(at_keyboard_controller_device::data_w)).umask16(0xff);
map(0x00c4, 0x00c5).rw(m_kbdc, FUNC(at_keyboard_controller_device::status_r), FUNC(at_keyboard_controller_device::command_w)).umask16(0xff);
- map(0x0080, 0x0083).rw(m_scsi, FUNC(wd33c93_device::read), FUNC(wd33c93_device::write)).umask16(0xff);
-
map(0x0100, 0x0107).rw(m_scc, FUNC(z80scc_device::ba_cd_inv_r), FUNC(z80scc_device::ba_cd_inv_w)).umask16(0xff);
+
map(0x0140, 0x0143).rw(m_net, FUNC(am7990_device::regs_r), FUNC(am7990_device::regs_w));
- //map(0x0200, 0x0203).rw(m_lpt, FUNC(::read), FUNC(::write));
+
+ // iop tests bits 0x04, 0x10 and 0x20
+ map(0x01c0, 0x01c1).lr8("?", [this]() { return m_iop_interface; }); // maybe?
+
+ map(0x0200, 0x0201).rw(m_fio, FUNC(z8038_device::fifo_r<1>), FUNC(z8038_device::fifo_w<1>)).umask16(0xff);
+ map(0x0202, 0x0203).rw(m_fio, FUNC(z8038_device::reg_r<1>), FUNC(z8038_device::reg_w<1>)).umask16(0xff);
map(0x0240, 0x0241).lw8("rtc", [this](address_space &space, offs_t offset, u8 data) { m_rtc->write(space, 0, data); }).umask16(0xff00);
map(0x0280, 0x0281).lrw8("rtc",
[this](address_space &space, offs_t offset) { return m_rtc->read(space, 1); },
[this](address_space &space, offs_t offset, u8 data) { m_rtc->write(space, 1, data); }).umask16(0xff00);
+ map(0x02c0, 0x2c1).lw8("cpu_interface", [this](u8 data)
+ {
+ switch (data)
+ {
+ case 0: LOG("cpu interrupt 0 asserted\n"); m_cpu->set_input_line(R3000_IRQ0, ASSERT_LINE); break;
+ case 1: LOG("cpu interrupt 1 asserted\n"); m_cpu->set_input_line(R3000_IRQ1, ASSERT_LINE); break;
+ case 2: LOG("cpu interrupt 2 asserted\n"); m_cpu->set_input_line(R3000_IRQ2, ASSERT_LINE); break;
+ case 3: LOG("cpu interrupt 4 asserted\n"); m_cpu->set_input_line(R3000_IRQ4, ASSERT_LINE); break;
+
+ case 4:
+ if (m_cpu->suspended())
+ {
+ LOG("cpu reset released\n");
+ m_cpu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
+ }
+ else
+ m_iop->set_input_line(INPUT_LINE_IRQ2, CLEAR_LINE);
+ m_iop_interface |= IOP_IACK;
+ m_iop_interface &= ~IOP_IRQ; // maybe?
+ break;
+
+ default:
+ LOG("cpu interface command 0x%02x\n", data);
+ break;
+
+ //case 5: break; // unknown
+ //case 6:
+ //case 7:
+ // something to do with shared memory access?
+ //break;
+ }
+ }).umask16(0xff);
+
map(0x0380, 0x0381).lw8("led", [this](u8 data) { logerror("led_w 0x%02x\n", data); }).umask16(0xff00);
}
-void rx2030_state::cpu_map(address_map &map)
+void rx2030_state::rx2030_map(address_map &map)
{
- //map(0x01ff0000, 0x01ffffff).m() // ramdac
- //map(0x1fc00000, 0x1fc3ffff).rom().region("eprom", 0);
+ map(0x02000000, 0x02000003).lrw8("iop_interface",
+ [this]() { return m_iop_interface; },
+ [this](u8 data)
+ {
+ switch (data)
+ {
+ case 0: LOG("cpu interrupt 0 cleared\n"); m_cpu->set_input_line(R3000_IRQ0, CLEAR_LINE); break;
+ case 1: LOG("cpu interrupt 1 cleared\n"); m_cpu->set_input_line(R3000_IRQ1, CLEAR_LINE); break;
+ case 2: LOG("cpu interrupt 2 cleared\n"); m_cpu->set_input_line(R3000_IRQ2, CLEAR_LINE); break;
+ case 3: LOG("cpu interrupt 4 cleared\n"); m_cpu->set_input_line(R3000_IRQ4, CLEAR_LINE); break;
+ break;
+
+ case 4:
+ if (VERBOSE & LOG_IOCB)
+ {
+ static char const *const iop_commands[] =
+ {
+ "IOP", "UART0", "UART1", "NVRAM", "LED", "CLOCK", "TOD", "SCSI0",
+ "SCSI1", "SCSI2", "SCSI3", "SCSI4", "SCSI5", "SCSI6", "SCSI7", "FLOPPY0",
+ "FLOPPY1", "LANCE", "PP", "KYBD", "MOUSE", "BUZZER", "UNK22", "UNK23"
+ };
+
+ for (int iocb = 0; iocb < 24; iocb++)
+ {
+ // check if command semaphore set
+ if (m_ram->read(0x1000 + iocb * 16 + 10) || m_ram->read(0x1000 + iocb * 16 + 11))
+ {
+ u32 const iocb_cmdparam = m_ram->read(0x1000 + iocb * 16 + 0)
+ | (m_ram->read(0x1000 + iocb * 16 + 1) << 8)
+ | (m_ram->read(0x1000 + iocb * 16 + 2) << 16)
+ | (m_ram->read(0x1000 + iocb * 16 + 3) << 24);
+
+ u16 const iop_cmd = m_ram->read(0x1000 + iocb_cmdparam + 2) | (m_ram->read(0x1000 + iocb_cmdparam + 3) << 8);
+
+ LOGMASKED(LOG_IOCB, "iocb %s command 0x%04x (%s)\n",
+ iop_commands[iocb], iop_cmd, machine().describe_context());
+ }
+ }
+ }
+
+ // interrupt the iop
+ m_iop_interface &= ~IOP_IACK;
+ m_iop_interface |= IOP_IRQ; // maybe?
+ m_iop->set_input_line(INPUT_LINE_IRQ2, ASSERT_LINE);
+ break;
+
+ case 6: LOG("led on\n"); break;
+ case 7: LOG("led off\n"); break;
+
+ default:
+ LOG("iop interface command 0x%02x (%s)\n", data, machine().describe_context());
+ break;
+ }
+ }
+ ).umask32(0xff);
+}
+
+void rx2030_state::rs2030_map(address_map &map)
+{
+ rx2030_map(map);
- //map(0x10003000, 0x1003ffff).rom().region("eprom", 0); // mirror?
+ // video hardware
+ map(0x01000000, 0x011fffff).ram().share("vram");
+ map(0x01ffff00, 0x01ffffff).m(m_ramdac, FUNC(bt458_device::map)).umask32(0xff);
+}
+
+static void rx2030_scsi_devices(device_slot_interface &device)
+{
+ device.option_add("harddisk", NSCSI_HARDDISK);
+ device.option_add("cdrom", NSCSI_CDROM);
}
void rx2030_state::rx2030(machine_config &config)
{
- // FIXME: main cpu disabled for now
- R2000(config, m_maincpu, 16.6698_MHz_XTAL);
- m_maincpu->set_addrmap(AS_PROGRAM, &rx2030_state::cpu_map);
- m_maincpu->in_brcond0().set([]() { return ASSERT_LINE; });
- m_maincpu->set_disable();
-
- // TODO: mouse connects to v50 serial?
- V53(config, m_iop, 20_MHz_XTAL / 2);
+ R2000A(config, m_cpu, 33.333_MHz_XTAL / 2, 32768, 32768);
+ m_cpu->set_fpurev(0x0315); // 0x0315 == R2010A v1.5
+ m_cpu->in_brcond0().set([this]() { logerror("brcond0 sampled (%s)\n", machine().describe_context()); return ASSERT_LINE; });
+
+ V50(config, m_iop, 20_MHz_XTAL / 2);
m_iop->set_addrmap(AS_PROGRAM, &rx2030_state::iop_program_map);
m_iop->set_addrmap(AS_IO, &rx2030_state::iop_io_map);
+ // general dma configuration
+ m_iop->out_hreq_cb().set(m_iop, FUNC(v50_device::hack_w));
+ m_iop->in_mem16r_cb().set(FUNC(rx2030_state::mmu_r));
+ m_iop->out_mem16w_cb().set(FUNC(rx2030_state::mmu_w));
+
+ // dma channel 1: scsi
+ m_iop->in_io16r_cb<1>().set(m_scsi, FUNC(aic6250_device::dma16_r));
+ m_iop->out_io16w_cb<1>().set(m_scsi, FUNC(aic6250_device::dma16_w));
+ m_iop->out_dack_cb<1>().set(m_scsi, FUNC(aic6250_device::back_w));
+
RAM(config, m_ram);
m_ram->set_default_size("16M");
m_ram->set_extra_options("4M,8M,12M");
@@ -180,8 +368,9 @@ void rx2030_state::rx2030(machine_config &config)
// rtc and nvram
MC146818(config, m_rtc, 32.768_kHz_XTAL);
- // TODO: ethernet id prom
- // TODO: parallel port
+ // parallel port
+ Z8038(config, m_fio, 0);
+ m_fio->out_int_cb<1>().set_inputline(m_iop, INPUT_LINE_IRQ4);
// keyboard
pc_kbdc_device &kbdc(PC_KBDC(config, "pc_kbdc", 0));
@@ -197,10 +386,9 @@ void rx2030_state::rx2030(machine_config &config)
m_kbdc->kbd_clk().set(kbdc, FUNC(pc_kbdc_device::clock_write_from_mb));
m_kbdc->kbd_data().set(kbdc, FUNC(pc_kbdc_device::data_write_from_mb));
- // TODO: verify scc device and clock
- SCC85C30(config, m_scc, 4.9152_MHz_XTAL);
- m_scc->configure_channels(1'843'200, 1'843'200, 1'843'200, 1'843'200);
- //m_scc->out_int_callback().set(m_iop, FUNC(v53_device::intp1_w));
+ SCC85C30(config, m_scc, 1.8432_MHz_XTAL);
+ m_scc->configure_channels(m_scc->clock(), m_scc->clock(), m_scc->clock(), m_scc->clock());
+ m_scc->out_int_callback().set_inputline(m_iop, INPUT_LINE_IRQ3);
// scc channel A (tty0)
RS232_PORT(config, m_tty[0], default_rs232_devices, nullptr);
@@ -209,7 +397,6 @@ void rx2030_state::rx2030(machine_config &config)
m_tty[0]->rxd_handler().set(m_scc, FUNC(z80scc_device::rxa_w));
m_scc->out_rtsa_callback().set(m_tty[0], FUNC(rs232_port_device::write_rts));
m_scc->out_txda_callback().set(m_tty[0], FUNC(rs232_port_device::write_txd));
- //m_scc->out_wreqa_callback().set(m_ioga, FUNC(interpro_ioga_device::drq_serial1)).invert();
// scc channel B (tty1)
RS232_PORT(config, m_tty[1], default_rs232_devices, nullptr);
@@ -218,32 +405,60 @@ void rx2030_state::rx2030(machine_config &config)
m_tty[1]->rxd_handler().set(m_scc, FUNC(z80scc_device::rxb_w));
m_scc->out_rtsb_callback().set(m_tty[1], FUNC(rs232_port_device::write_rts));
m_scc->out_txdb_callback().set(m_tty[1], FUNC(rs232_port_device::write_txd));
- //m_scc->out_wreqb_callback().set(m_ioga, FUNC(interpro_ioga_device::drq_serial2)).invert();
// floppy controller and drive
WD37C65C(config, m_fdc, 16_MHz_XTAL);
- //m_fdc->intrq_wr_callback().set(m_mct_adr, FUNC(jazz_mct_adr_device::irq<1>));
- //m_fdc->drq_wr_callback().set(m_mct_adr, FUNC(jazz_mct_adr_device::drq<1>));
+ //m_fdc->intrq_wr_callback().set_inputline(m_iop, INPUT_LINE_IRQ6);
+ //m_fdc->drq_wr_callback().set();
FLOPPY_CONNECTOR(config, "fdc:0", "35hd", FLOPPY_35_HD, true, &FLOPPY_PC_FORMAT).enable_sound(false);
- //m_mct_adr->dma_r_cb<1>().set(m_fdc, FUNC(n82077aa_device::dma_r));
- //m_mct_adr->dma_w_cb<1>().set(m_fdc, FUNC(n82077aa_device::dma_w));
- // scsi controller and port
- scsi_port_device &scsi_port(SCSI_PORT(config, "scsi_port"));
- WD33C93(config, m_scsi);
- m_scsi->set_scsi_port(scsi_port);
- //m_scsi->irq_cb().set_inputline()
+ // scsi bus and devices
+ NSCSI_BUS(config, m_scsibus, 0);
+
+ nscsi_connector &harddisk(NSCSI_CONNECTOR(config, "scsi:0", 0));
+ rx2030_scsi_devices(harddisk);
+ harddisk.set_default_option("harddisk");
+
+ rx2030_scsi_devices(NSCSI_CONNECTOR(config, "scsi:1", 0));
+ rx2030_scsi_devices(NSCSI_CONNECTOR(config, "scsi:2", 0));
+ rx2030_scsi_devices(NSCSI_CONNECTOR(config, "scsi:3", 0));
+ rx2030_scsi_devices(NSCSI_CONNECTOR(config, "scsi:4", 0));
+ rx2030_scsi_devices(NSCSI_CONNECTOR(config, "scsi:5", 0));
+ rx2030_scsi_devices(NSCSI_CONNECTOR(config, "scsi:6", 0));
+
+ // scsi host adapter
+ nscsi_connector &adapter(NSCSI_CONNECTOR(config, "scsi:7", 0));
+ adapter.option_add_internal("aic6250", AIC6250);
+ adapter.set_default_option("aic6250");
+ adapter.set_fixed(true);
+ adapter.set_option_machine_config("aic6250", [this](device_t *device)
+ {
+ aic6250_device &adapter = downcast<aic6250_device &>(*device);
+
+ adapter.set_clock(10_MHz_XTAL); // clock assumed
+
+ adapter.int_cb().set_inputline(m_iop, INPUT_LINE_IRQ7).invert();
+ adapter.breq_cb().set(m_iop, FUNC(v50_device::dreq_w<1>));
+ });
// ethernet
AM7990(config, m_net);
- //m_net->dma_in().set(FUNC(rx2030_state::lance_dma_r));
- //m_net->dma_out().set(FUNC(rx2030_state::lance_dma_w));
+ m_net->irq_out().set_inputline(m_iop, INPUT_LINE_IRQ5);
+ //m_net->dma_in().set(FUNC(rx2030_state::mmu_r));
+ //m_net->dma_out().set(FUNC(rx2030_state::mmu_w));
+
+ // buzzer
+ SPEAKER(config, "mono").front_center();
+ SPEAKER_SOUND(config, m_buzzer);
+ m_buzzer->add_route(ALL_OUTPUTS, "mono", 0.50);
}
void rx2030_state::rc2030(machine_config &config)
{
rx2030(config);
+ m_cpu->set_addrmap(AS_PROGRAM, &rx2030_state::rx2030_map);
+
// no keyboard
m_kbd->set_default_option(nullptr);
@@ -254,6 +469,8 @@ void rx2030_state::rs2030(machine_config &config)
{
rx2030(config);
+ m_cpu->set_addrmap(AS_PROGRAM, &rx2030_state::rs2030_map);
+
m_kbd->set_default_option(STR_KBD_MICROSOFT_NATURAL);
// video hardware (1280x1024x8bpp @ 60Hz), 40 parts vram
@@ -263,26 +480,41 @@ void rx2030_state::rs2030(machine_config &config)
SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
m_screen->set_raw(pixclock, 1688, 248, 1528, 1066, 38, 1062);
m_screen->set_screen_update(FUNC(rx2030_state::screen_update));
- m_screen->screen_vblank().set([](int state) {});
+ m_screen->screen_vblank().set_inputline(m_cpu, R3000_IRQ5);
BT458(config, m_ramdac, pixclock);
- RAM(config, m_vram, 0).set_default_size("2M");
}
u32 rx2030_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
{
- u8 *pixel_data = m_vram->pointer();
+ /*
+ * The graphics board has 1280KiB of video ram fitted, which is organised
+ * such that each 1280 pixel line occupies 2048 bytes of the address space;
+ * the remaining 768 addresses are presumably not mapped to anything.
+ */
+ u32 *pixel_pointer = m_vram;
for (int y = screen.visible_area().min_y; y <= screen.visible_area().max_y; y++)
- for (int x = screen.visible_area().min_x; x <= screen.visible_area().max_x; x++)
- bitmap.pix(y, x) = m_ramdac->pen_color(*pixel_data++);
+ {
+ for (int x = screen.visible_area().min_x; x <= screen.visible_area().max_x; x += 4)
+ {
+ u32 const pixel_data = *pixel_pointer++;
+
+ bitmap.pix(y, x + 0) = m_ramdac->pen_color((pixel_data >> 24) & 0xff);
+ bitmap.pix(y, x + 1) = m_ramdac->pen_color((pixel_data >> 16) & 0xff);
+ bitmap.pix(y, x + 2) = m_ramdac->pen_color((pixel_data >> 8) & 0xff);
+ bitmap.pix(y, x + 3) = m_ramdac->pen_color((pixel_data >> 0) & 0xff);
+ }
+
+ // compensate by 2048 - 1280 pixels per line
+ pixel_pointer += 0xc0;
+ }
return 0;
}
ROM_START(rx2030)
- ROM_REGION(0x40000, "eprom", 0)
-
+ ROM_REGION16_LE(0x40000, "v50_ipl", 0)
ROM_SYSTEM_BIOS(0, "v4.32", "Rx2030 v4.32, Jan 1991")
ROMX_LOAD("50-00121__005.u139", 0x00000, 0x10000, CRC(b2f42665) SHA1(81c83aa6b8865338fda5c03733ede91749997648), ROM_BIOS(0) | ROM_SKIP(1))
ROMX_LOAD("50-00120__005.u140", 0x00001, 0x10000, CRC(0ffa485e) SHA1(7cdfb81d1a547c5ccc88e1e0ef73d447cd03e9e2), ROM_BIOS(0) | ROM_SKIP(1))
@@ -294,10 +526,37 @@ ROM_START(rx2030)
ROMX_LOAD("50-00120__003.u140", 0x00001, 0x10000, CRC(e1991721) SHA1(028d33be271c95f198473b650f7800f9ca4a60b2), ROM_BIOS(1) | ROM_SKIP(1))
ROMX_LOAD("50-00119__003.u141", 0x20001, 0x10000, CRC(c8469906) SHA1(69bbf4b5c415b2e2156a4467bf9cb30e79f586ef), ROM_BIOS(1) | ROM_SKIP(1))
ROMX_LOAD("50-00118__003.u142", 0x20000, 0x10000, CRC(18cc001a) SHA1(198023e92e1e3ba2fc8637f5dd6f370e7e023fdd), ROM_BIOS(1) | ROM_SKIP(1))
+
+ ROM_REGION(0x800, "i8742_eprom", 0)
+ ROM_LOAD("keyboard_1.5.bin", 0x000, 0x800, CRC(f86ba0f7) SHA1(1ad475451db35a76d929824c035d582279fbe3a3))
+
+ /*
+ * The following isn't a real dump, but a hand-made nvram image that allows
+ * entry to the boot monitor. Variables can be adjusted via the monitor,
+ * and are laid out as follows:
+ *
+ * Offset Length Variable
+ * 0x0e 4 netaddr
+ * 0x12 1 lbaud
+ * 0x13 1 rbaud
+ * 0x14 20 bootfile
+ * 0x28 1 bootmode
+ * 0x29 1 console
+ * 0x2a 1 ponmask? or something similar
+ * 0x2b 3 unused?
+ * 0x2e 4 resetepc
+ * 0x32 4 resetra
+ * 0x36 1 keyswtch
+ * 0x37 1 flag
+ * 0x38 8 unused?
+ *
+ */
+ ROM_REGION(0x40, "rtc", 0)
+ ROM_LOAD("ds1287.bin", 0x00, 0x40, CRC(28369bf3) SHA1(64f24e1d8fb7103ab0bd3023c66490447bdcbf89))
ROM_END
#define rom_rc2030 rom_rx2030
#define rom_rs2030 rom_rx2030
/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
-COMP(1989, rc2030, 0, 0, rc2030, 0, rx2030_state, rx2030_init, "MIPS", "RC2030", MACHINE_IS_SKELETON )
-COMP(1989, rs2030, 0, 0, rs2030, 0, rx2030_state, rx2030_init, "MIPS", "RS2030", MACHINE_IS_SKELETON )
+COMP(1989, rc2030, 0, 0, rc2030, 0, rx2030_state, rx2030_init, "MIPS", "RC2030", MACHINE_NOT_WORKING)
+COMP(1989, rs2030, 0, 0, rs2030, 0, rx2030_state, rx2030_init, "MIPS", "RS2030", MACHINE_NOT_WORKING)
diff --git a/src/mame/drivers/mod8.cpp b/src/mame/drivers/mod8.cpp
index c9e5e03dcdf..d2320f6961c 100644
--- a/src/mame/drivers/mod8.cpp
+++ b/src/mame/drivers/mod8.cpp
@@ -122,7 +122,6 @@ void mod8_state::mod8_mem(address_map &map)
void mod8_state::mod8_io(address_map &map)
{
map.unmap_value_high();
- map.global_mask(0xff);
map(0x00, 0x00).r(FUNC(mod8_state::tty_r));
map(0x0a, 0x0a).w(FUNC(mod8_state::out_w));
map(0x0b, 0x0b).w(FUNC(mod8_state::tty_w));
diff --git a/src/mame/drivers/model3.cpp b/src/mame/drivers/model3.cpp
index 40af0d28e40..22317f05e91 100644
--- a/src/mame/drivers/model3.cpp
+++ b/src/mame/drivers/model3.cpp
@@ -3971,6 +3971,77 @@ ROM_START( von2a ) /* Step 2.0, Sega game ID# is 833-13346, ROM board ID# 834-
ROM_PARAMETER( ":315_5881:key", "292a0e97" )
ROM_END
+ROM_START( von2o ) /* Step 2.0, Sega game ID# is 833-13346, ROM board ID# 834-13347 VOT, Security board ID# 837-13379-COM */
+ ROM_REGION64_BE( 0x8800000, "user1", 0 ) /* program + data ROMs */
+ // CROM
+ ROM_LOAD64_WORD_SWAP( "epr-20683.17", 0x000006, 0x200000, CRC(bb21aea7) SHA1(8d75a79411f37c921b923329fa499fb96c3084b2) )
+ ROM_LOAD64_WORD_SWAP( "epr-20684.18", 0x000004, 0x200000, CRC(5d40fedb) SHA1(cae9215d27e6432ddc1c13221ce7947d821a59d0) )
+ ROM_LOAD64_WORD_SWAP( "epr-20685.19", 0x000002, 0x200000, CRC(0664c568) SHA1(0cdf445be783e939f4e8c32837e0c44d279e7a91) )
+ ROM_LOAD64_WORD_SWAP( "epr-20686.20", 0x000000, 0x200000, CRC(e1b0ff65) SHA1(8dab5c88ef213cc13e42a9b3762443ea467a65f9) )
+
+ // CROM0:
+ ROM_LOAD64_WORD_SWAP( "mpr-20647.1", 0x800006, 0x400000, CRC(e8586380) SHA1(67dd49975b31ba2c3f889ff38a3bc4663145934a) )
+ ROM_LOAD64_WORD_SWAP( "mpr-20648.2", 0x800004, 0x400000, CRC(107309e0) SHA1(61657814a30020c0d4ea77625cb8f11a1db7e866) )
+ ROM_LOAD64_WORD_SWAP( "mpr-20649.3", 0x800002, 0x400000, CRC(b8fd56ba) SHA1(5e5051d4b752463e1da632f8294a6c8f9250dbc8) )
+ ROM_LOAD64_WORD_SWAP( "mpr-20650.4", 0x800000, 0x400000, CRC(81f96649) SHA1(0d7aba7654237b68de6e43811832fafaf61e2bec) )
+
+ // CROM1
+ ROM_LOAD64_WORD_SWAP( "mpr-20651.5", 0x1800006, 0x400000, CRC(8373cab3) SHA1(1d36612668a3004e2448f99ab27d7184ff859478) )
+ ROM_LOAD64_WORD_SWAP( "mpr-20652.6", 0x1800004, 0x400000, CRC(64c6fbb6) SHA1(c8682bda20d3119b4f95bbd2dbde301bfd036608) )
+ ROM_LOAD64_WORD_SWAP( "mpr-20653.7", 0x1800002, 0x400000, CRC(858e6bba) SHA1(22b71826799249a577124a49d5a276908a53ce61) )
+ ROM_LOAD64_WORD_SWAP( "mpr-20654.8", 0x1800000, 0x400000, CRC(763ef905) SHA1(4d5f6b1770cf9bf6cecd4d3a91a822e5cc658464) )
+
+ // CROM2
+ ROM_LOAD64_WORD_SWAP( "mpr-20655.9", 0x2800006, 0x400000, CRC(f0a471e9) SHA1(8a40c9381e8b3733be297738c825b82abcb476d0) )
+ ROM_LOAD64_WORD_SWAP( "mpr-20656.10", 0x2800004, 0x400000, CRC(466bee13) SHA1(bc2087a138037188f462fa1cecc898e5efb3e8b8) )
+ ROM_LOAD64_WORD_SWAP( "mpr-20657.11", 0x2800002, 0x400000, CRC(14bf8964) SHA1(84444f7c489344ad1dd980b860364b5a4ed53038) )
+ ROM_LOAD64_WORD_SWAP( "mpr-20658.12", 0x2800000, 0x400000, CRC(b80175b9) SHA1(26dc97f6a6e8415cbb7e9e1f64389d80a2b761a1) )
+
+ // CROM3
+ ROM_LOAD64_WORD_SWAP( "mpr-20659.13", 0x3800006, 0x400000, CRC(edb63e7b) SHA1(761abcfc213e813967d053475c965459a9724a24) )
+ ROM_LOAD64_WORD_SWAP( "mpr-20660.14", 0x3800004, 0x400000, CRC(d961d385) SHA1(7e341c2cf24715c5cecb276c42166bf426860819) )
+ ROM_LOAD64_WORD_SWAP( "mpr-20661.15", 0x3800002, 0x400000, CRC(50e6189e) SHA1(04be5ff1379af4972edec3b320f148bdf09bfbb5) )
+ ROM_LOAD64_WORD_SWAP( "mpr-20662.16", 0x3800000, 0x400000, CRC(7130cb61) SHA1(39de0e3c2086f339156bfd734a196b667df7f5ac) )
+
+ ROM_REGION( 0x2000000, "user3", 0 ) /* Video ROMs Part 1 */
+ ROM_LOAD_VROM( "mpr-20667.26", 0x000002, 0x400000, CRC(321e006f) SHA1(687165bd2d2d22f861cd79083adcab62eb827c0f) )
+ ROM_LOAD_VROM( "mpr-20668.27", 0x000000, 0x400000, CRC(c2dd8053) SHA1(52bc88d172d335b47e3ae3d582233382e9608de2) )
+ ROM_LOAD_VROM( "mpr-20669.28", 0x000006, 0x400000, CRC(63432497) SHA1(b072741fe9ba49f1a7eed03301c8b1956af94d26) )
+ ROM_LOAD_VROM( "mpr-20670.29", 0x000004, 0x400000, CRC(f7b554fd) SHA1(84fb08413345e0f3afb6e20c723aa8aa8156fdc7) )
+ ROM_LOAD_VROM( "mpr-20671.30", 0x00000a, 0x400000, CRC(fee1a49b) SHA1(a024a0564df65e065e8b1830e85513d17ebd8635) )
+ ROM_LOAD_VROM( "mpr-20672.31", 0x000008, 0x400000, CRC(e4b8c6e6) SHA1(674d4d26285f2825050fd27dd3382ca6245d54c7) )
+ ROM_LOAD_VROM( "mpr-20673.32", 0x00000e, 0x400000, CRC(e7b6403b) SHA1(0f74f7a916c091d49eed8222050981a6b73d4bdd) )
+ ROM_LOAD_VROM( "mpr-20674.33", 0x00000c, 0x400000, CRC(9be22e13) SHA1(a00b0c69b6ed086f3f61d4f767df6c4ddea45052) )
+
+ ROM_REGION( 0x2000000, "user4", 0 ) /* Video ROMs Part 2 */
+ ROM_LOAD_VROM( "mpr-20675.34", 0x000002, 0x400000, CRC(6a7c3862) SHA1(f77145c2a5e373f567783cf5db70e25b71e77bf5) )
+ ROM_LOAD_VROM( "mpr-20676.35", 0x000000, 0x400000, CRC(dd299648) SHA1(c222c10cb23753ac3d6d1c779b2d026a64c61bc4) )
+ ROM_LOAD_VROM( "mpr-20677.36", 0x000006, 0x400000, CRC(3fc5f330) SHA1(778c1932b093a4de96c76ea704463b7c67cdcb33) )
+ ROM_LOAD_VROM( "mpr-20678.37", 0x000004, 0x400000, CRC(62f794a1) SHA1(fc7adafb49056b23b6cc483978ffe4fd3635977d) )
+ ROM_LOAD_VROM( "mpr-20679.38", 0x00000a, 0x400000, CRC(35a37c53) SHA1(cd727a8914c3c01e302378048e3998b4cd849c4a) )
+ ROM_LOAD_VROM( "mpr-20680.39", 0x000008, 0x400000, CRC(81fec46e) SHA1(43b3fbb544d920a87f77437860e32a628ae2865b) )
+ ROM_LOAD_VROM( "mpr-20681.40", 0x00000e, 0x400000, CRC(d517873b) SHA1(8e50dd149716ae6b0b8d7ac99cd425a17b3c0a46) )
+ ROM_LOAD_VROM( "mpr-20682.41", 0x00000c, 0x400000, CRC(5b43250c) SHA1(fccb40cd03c096360ca3c565e8621d4110b273ab) )
+
+ ROM_REGION( 0x080000, "audiocpu", 0 ) /* 68000 code */
+ ROM_LOAD16_WORD_SWAP( "epr-20687.21", 0x000000, 0x080000, CRC(fa084de5) SHA1(8a760b76bc12d60d4727f93106830f19179c9046) )
+
+ ROM_REGION16_BE( 0x1000000, "samples", 0 ) /* SCSP samples */
+ ROM_LOAD16_WORD_SWAP( "mpr-20663.22", 0x000000, 0x400000, CRC(977eb6a4) SHA1(9dbba51630cbef2351d79b82ab6ae3af4aed99f0) )
+ ROM_LOAD16_WORD_SWAP( "mpr-20665.24", 0x400000, 0x400000, CRC(0efc0ca8) SHA1(1414becad21eb7d03d816a8cba47506f941b3c29) )
+ ROM_LOAD16_WORD_SWAP( "mpr-20664.23", 0x800000, 0x400000, CRC(89220782) SHA1(18a3585af960a76eb08f187223e9b69ad16809a1) )
+ ROM_LOAD16_WORD_SWAP( "mpr-20666.25", 0xc00000, 0x400000, CRC(3ecb2606) SHA1(a38d1f61933c8873deaff0a913c657b768f9783d) )
+
+ ROM_REGION( 0x20000, "cpu2", 0 ) /* Z80 code */
+ ROM_FILL( 0x000000, 0x20000, 0x0000 )
+
+ ROM_REGION( 0x800000, "dsb", 0 ) /* DSB samples */
+ ROM_FILL( 0x000000, 0x800000, 0x0000 )
+
+ // ???? 317-0234-COM Model 3
+ ROM_PARAMETER( ":315_5881:key", "292a0e97" )
+ROM_END
+
ROM_START( von254g ) /* Step 2.0, Sega game ID# is 833-13789 */
ROM_REGION64_BE( 0x8800000, "user1", 0 ) /* program + data ROMs */
// CROM
@@ -4243,6 +4314,64 @@ ROM_START( swtrilgya ) /* Step 2.1, Sega game ID# is 833-13586, ROM board ID# 8
ROM_PARAMETER( ":315_5881:key", "31272a01" )
ROM_END
+ROM_START( swtrilgyp ) // Step 2.1, Sega game ID# is 833-13586-T, ROM board ID# 934-13587-T
+ ROM_REGION64_BE( 0x8800000, "user1", 0 ) /* program + data ROMs */
+ // CROM
+ ROM_LOAD64_WORD_SWAP( "epr-crom3.17", 0x000006, 0x200000, CRC(84734e94) SHA1(53c11ecd95292bbb5aa1466db24d6a11d7fc4abd) )
+ ROM_LOAD64_WORD_SWAP( "epr-crom2.18", 0x000004, 0x200000, CRC(e4147534) SHA1(dd61d80996692a50c84839da4f751fe4c68a38df) )
+ ROM_LOAD64_WORD_SWAP( "epr-crom1.19", 0x000002, 0x200000, CRC(322b67a5) SHA1(fa049b2a5b1726b92618dc400fad33e3fcdd5bfe) )
+ ROM_LOAD64_WORD_SWAP( "epr-crom0.20", 0x000000, 0x200000, CRC(da7d49fa) SHA1(92b366775ca2eec8c9134c8679354c39c7468ffa) )
+
+ // CROM0, flash modules
+ ROM_LOAD64_WORD_SWAP( "epr-crom03.01", 0x800006, 0x400000, CRC(0ddf1f80) SHA1(a940e1960dd555d2d31790f6fb0155949533c26b) )
+ ROM_LOAD64_WORD_SWAP( "epr-crom02.02", 0x800004, 0x400000, CRC(1d69c716) SHA1(ac9adfe0ef888a0903e79198c1116febbdf90ef8) )
+ ROM_LOAD64_WORD_SWAP( "epr-crom01.03", 0x800002, 0x400000, CRC(4d13685d) SHA1(c4826447297996c7034fba731ea4582be634e957) )
+ ROM_LOAD64_WORD_SWAP( "epr-crom00.04", 0x800000, 0x400000, CRC(dc0d974d) SHA1(f67feaf19ebe6735fb7acc7227a33a3100617fd8) )
+
+ // CROM1, flash modules
+ ROM_LOAD64_WORD_SWAP( "epr-crom13.05", 0x1800006, 0x400000, CRC(ead1d983) SHA1(d353e7e8cd073bec4d7200e8bc4eec229765a831) )
+ ROM_LOAD64_WORD_SWAP( "epr-crom12.06", 0x1800004, 0x400000, CRC(fe2f392e) SHA1(29a55d93c33a801b9170f840226b12209d2f3e75) )
+ ROM_LOAD64_WORD_SWAP( "epr-crom11.07", 0x1800002, 0x400000, CRC(a04f3b5e) SHA1(822b80f03a35c0f41a90a3fddcd1ea3edb3b8c4e) )
+ ROM_LOAD64_WORD_SWAP( "epr-crom10.08", 0x1800000, 0x400000, CRC(7ac2dfe6) SHA1(9467d7fffdc9c9f198adda8a39aa6fee53b3dc4c) )
+
+ ROM_REGION( 0x2000000, "user3", 0 ) // Video ROMs Part 1, flash modules
+ ROM_LOAD_VROM( "epr-vrom01.26", 0x000002, 0x400000, CRC(750287bb) SHA1(d5284f5e97e70b8a9380d876c44c73487f310cc9) )
+ ROM_LOAD_VROM( "epr-vrom00.27", 0x000000, 0x400000, CRC(ac5d8de5) SHA1(4194ebbd220f538aa7a8f49cf4b260ff49719d3d) )
+ ROM_LOAD_VROM( "epr-vrom03.28", 0x000006, 0x400000, CRC(9fc09636) SHA1(7ec10f929e0cdf2bb67ba72fada719131b9c5a1b) )
+ ROM_LOAD_VROM( "epr-vrom02.29", 0x000004, 0x400000, CRC(34190386) SHA1(8d76a242773f6a48962baf3887878848a1478d09) )
+ ROM_LOAD_VROM( "epr-vrom05.30", 0x00000a, 0x400000, CRC(2c941427) SHA1(cfaec32ca2b8dc3ad630cefad3bdadd16e9cf8cf) )
+ ROM_LOAD_VROM( "epr-vrom04.31", 0x000008, 0x400000, CRC(ee0733e2) SHA1(aec2a401b1e20e775ed5c8625bab20655cf528ce) )
+ ROM_LOAD_VROM( "epr-vrom07.32", 0x00000e, 0x400000, CRC(50b9f673) SHA1(f34b352c03fe25002aecba897c619c9d7ad19f61) )
+ ROM_LOAD_VROM( "epr-vrom06.33", 0x00000c, 0x400000, CRC(d1c345c6) SHA1(2c253644b99d9c8f921bc7b166c7ea78f0cfbe57) )
+
+ ROM_REGION( 0x2000000, "user4", 0 ) // Video ROMs Part 2, flash modules
+ ROM_LOAD_VROM( "epr-vrom11.34", 0x000002, 0x400000, CRC(39fe8657) SHA1(82ff3f02694d44253900daa48cfe12b4882d2424) )
+ ROM_LOAD_VROM( "epr-vrom10.35", 0x000000, 0x400000, CRC(fd18cb56) SHA1(69de424256cb388599e3e7f59eae607b1766921f) )
+ ROM_LOAD_VROM( "epr-vrom13.36", 0x000006, 0x400000, CRC(f6efe50d) SHA1(ebd41f5fe429dff74200322a7e50534f9b3ed498) )
+ ROM_LOAD_VROM( "epr-vrom12.37", 0x000004, 0x400000, CRC(6e4ac064) SHA1(5b2f13da87255e420a0ee16de0f00be316792359) )
+ ROM_LOAD_VROM( "epr-vrom15.38", 0x00000a, 0x400000, CRC(ced63c05) SHA1(b8a962a73ecf078dd6f52bd448ec023ea488e492) )
+ ROM_LOAD_VROM( "epr-vrom14.39", 0x000008, 0x400000, CRC(2bd25533) SHA1(66f23393a5e9a6f921d19503b60453ca2e1d09b8) )
+ ROM_LOAD_VROM( "epr-vrom17.40", 0x00000e, 0x400000, CRC(4f23de3e) SHA1(5a1b9589af52142cd3435c08f335997489e8f2fb) )
+ ROM_LOAD_VROM( "epr-vrom16.41", 0x00000c, 0x400000, CRC(14f9785e) SHA1(1febbd7e32e6d4850eb64c10d7462af2596ef865) )
+
+ ROM_REGION( 0x080000, "audiocpu", 0 ) // 68000 code
+ ROM_LOAD16_WORD_SWAP( "epr-srom0.21", 0x000000, 0x080000, CRC(2bb06489) SHA1(be7bbef4862fbc727a3b660790bf97b2132cb357) )
+
+ ROM_REGION16_BE( 0x800000, "samples", 0 ) // SCSP samples, flash modules
+ ROM_LOAD16_WORD_SWAP( "epr-srom1.22", 0x000000, 0x400000, CRC(0e52e2ec) SHA1(7d17781fced1a06a0dc7ca590e7bef83a70e149e) )
+ ROM_LOAD16_WORD_SWAP( "epr-srom3.24", 0x400000, 0x400000, CRC(841ed823) SHA1(450b255184b503351f17ffb3b5776634ec4f02e6) )
+
+ // prototype DSB is missing, we use ROMs from final ver
+ ROM_REGION( 0x20000, "cpu2", 0 ) /* Z80 code */
+ ROM_LOAD16_WORD_SWAP( "epr-21384.2", 0x000000, 0x20000, CRC(12fa4780) SHA1(a10ce82d81045cc49efcfba490693d06aeced3ae) )
+
+ ROM_REGION( 0x1000000, "dsb", 0 ) /* DSB samples */
+ ROM_LOAD( "mpr-21375.18", 0x000000, 0x400000, CRC(735157a9) SHA1(d1ff5dc7a6be8c8b0b6ba33fdf353c2008507afc) )
+ ROM_LOAD( "mpr-21376.20", 0x400000, 0x400000, CRC(e635f81e) SHA1(3eb4243fd275946ce0e85d074abd59b5ed31bbcd) )
+ ROM_LOAD( "mpr-21377.22", 0x800000, 0x400000, CRC(720621f8) SHA1(191bd8159010c172a82159d0ebfa56637c2a8462) )
+ ROM_LOAD( "mpr-21378.24", 0xc00000, 0x400000, CRC(1fcf715e) SHA1(9706f36e7a61d885d34a6974311a2410fe3d6760) )
+ROM_END
+
ROM_START( dirtdvls ) /* Step 2.1 - Export version, Sega game ID# is 833-13427, ROM board ID# 834-13528 DRT */
ROM_REGION64_BE( 0x8800000, "user1", 0 ) /* program + data ROMs */
// CROM
@@ -4824,7 +4953,7 @@ ROM_START( harleya ) /* Step 2.0, Sega game ID# is 833-13325, ROM board ID# 8
ROM_FILL( 0x000000, 0x1000000, 0x0000 )
ROM_END
-ROM_START( fvipers2 ) /* Step 2.0 - Japan version */
+ROM_START( fvipers2 ) /* Step 2.0 */
ROM_REGION64_BE( 0x8800000, "user1", 0 ) /* program + data ROMs */
// CROM
ROM_LOAD64_WORD_SWAP( "epr-20596a.17", 0x000006, 0x200000, CRC(969ab801) SHA1(a7a2aa71204d1c38a6a8c0605331fd859cb224f1) )
@@ -4896,6 +5025,78 @@ ROM_START( fvipers2 ) /* Step 2.0 - Japan version */
ROM_PARAMETER( ":315_5881:key", "29260e96" )
ROM_END
+ROM_START( fvipers2o ) /* Step 2.0 */
+ ROM_REGION64_BE( 0x8800000, "user1", 0 ) /* program + data ROMs */
+ // CROM
+ ROM_LOAD64_WORD_SWAP( "epr-20596.17", 0x000006, 0x200000, CRC(a311b4af) SHA1(daf88c12533c3ae5e6c63b581a6141a829b4e133) )
+ ROM_LOAD64_WORD_SWAP( "epr-20597.18", 0x000004, 0x200000, CRC(4279de19) SHA1(fd3c459f23da2acf6b3490a0275a6f5f62d80a4e) )
+ ROM_LOAD64_WORD_SWAP( "epr-20598.19", 0x000002, 0x200000, CRC(71ec5183) SHA1(4bea922e0a26115f7f0d0dbc09508ea199e8c90a) )
+ ROM_LOAD64_WORD_SWAP( "epr-20599.20", 0x000000, 0x200000, CRC(69a0009d) SHA1(036daafac65a8cc92177f70d7236ddb10669510b) )
+
+ // CROM0
+ ROM_LOAD64_WORD_SWAP( "mpr-20560.1", 0x800006, 0x400000, CRC(b0f6584d) SHA1(e776a47fae42e43189840418945d33cf23a1f5fe) )
+ ROM_LOAD64_WORD_SWAP( "mpr-20561.2", 0x800004, 0x400000, CRC(38a0f112) SHA1(6ad9ee6a9f08ef379acce2360b3e861f574101f0) )
+ ROM_LOAD64_WORD_SWAP( "mpr-20562.3", 0x800002, 0x400000, CRC(96e4942e) SHA1(2567671fe9d7e207634464d08e5789f4521ffed2) )
+ ROM_LOAD64_WORD_SWAP( "mpr-20563.4", 0x800000, 0x400000, CRC(999848ac) SHA1(55b37ea0cfa7989871f88d89d9a13df5b1ec4e92) )
+
+ // CROM1
+ ROM_LOAD64_WORD_SWAP( "mpr-20564.5", 0x1800006, 0x400000, CRC(be69fca0) SHA1(8a0c4449b5742235f8e5eaf6d168e7512ed96fa6) )
+ ROM_LOAD64_WORD_SWAP( "mpr-20565.6", 0x1800004, 0x400000, CRC(d6bbe638) SHA1(725f53b087c65d09e28ad3cec8634d5e7e63158a) )
+ ROM_LOAD64_WORD_SWAP( "mpr-20566.7", 0x1800002, 0x400000, CRC(2901883b) SHA1(f086587578e4f4931da8a18ff53adf8b3d665a09) )
+ ROM_LOAD64_WORD_SWAP( "mpr-20567.8", 0x1800000, 0x400000, CRC(80f4eba7) SHA1(ead30d57e3ca39dcd4195eeb2b4c6ee71c968769) )
+
+ // CROM2
+ ROM_LOAD64_WORD_SWAP( "mpr-20568.9", 0x2800006, 0x400000, CRC(ff23cf1c) SHA1(54b8a38c8deda1ddd0e26aa47504bfb0e2ed4b79) )
+ ROM_LOAD64_WORD_SWAP( "mpr-20569.10", 0x2800004, 0x400000, CRC(136c014f) SHA1(c11b9b93ec6189ca745e6de9697bb274f07c6b1c) )
+ ROM_LOAD64_WORD_SWAP( "mpr-20570.11", 0x2800002, 0x400000, CRC(2c0d91fc) SHA1(5ab896272da3650dbc482629ef7bdaccfa8eba54) )
+ ROM_LOAD64_WORD_SWAP( "mpr-20571.12", 0x2800000, 0x400000, CRC(40b459af) SHA1(f2bca8783a787df45d4142436245d343a1a13fa7) )
+
+ // CROM3
+ ROM_LOAD64_WORD_SWAP( "mpr-20572.13", 0x3800006, 0x400000, CRC(d4a41a0b) SHA1(2ceb45e5ff22e2539d52a960713606742e11ed18) )
+ ROM_LOAD64_WORD_SWAP( "mpr-20573.14", 0x3800004, 0x400000, CRC(e0dee793) SHA1(be80a5ca9d3cd910b15a4372883e047c2cc6b267) )
+ ROM_LOAD64_WORD_SWAP( "mpr-20574.15", 0x3800002, 0x400000, CRC(68567771) SHA1(6183f588092d079c10e002adf641520183148143) )
+ ROM_LOAD64_WORD_SWAP( "mpr-20575.16", 0x3800000, 0x400000, CRC(ebc99d8a) SHA1(66bd76738d76f42e32d3a27db4a8586dbb694f36) )
+
+ ROM_REGION( 0x2000000, "user3", 0 ) /* Video ROMs Part 1 */
+ ROM_LOAD_VROM( "mpr-20580.26", 0x000002, 0x400000, CRC(6d42775e) SHA1(9cd77ee6a317dcac67466920f59ac5cac98f67e2) )
+ ROM_LOAD_VROM( "mpr-20581.27", 0x000000, 0x400000, CRC(ac9eec04) SHA1(0d4af895bc7cc100f9618c52e989aadbc0aa6d6e) )
+ ROM_LOAD_VROM( "mpr-20582.28", 0x000006, 0x400000, CRC(b202f7bd) SHA1(6600f4bf49795c2821a2119f1251348782bcbdb2) )
+ ROM_LOAD_VROM( "mpr-20583.29", 0x000004, 0x400000, CRC(0d6d508a) SHA1(bf7e419b097b0c90ee278766a3ee527beb860e71) )
+ ROM_LOAD_VROM( "mpr-20584.30", 0x00000a, 0x400000, CRC(eccf4de6) SHA1(b5508aab6fd28f8b55aae495920382259b4c75e5) )
+ ROM_LOAD_VROM( "mpr-20585.31", 0x000008, 0x400000, CRC(b383f4e5) SHA1(4a0d02de7fc41c66862917c35b0c2026ad06dfd0) )
+ ROM_LOAD_VROM( "mpr-20586.32", 0x00000e, 0x400000, CRC(e7cd5dfb) SHA1(b33698792b3a1190712ad1c8c337f1f7fe67a1cb) )
+ ROM_LOAD_VROM( "mpr-20587.33", 0x00000c, 0x400000, CRC(e2b2abe1) SHA1(32a6253948b852eb647a28438e8928684fc57b72) )
+
+ ROM_REGION( 0x2000000, "user4", 0 ) /* Video ROMs Part 2 */
+ ROM_LOAD_VROM( "mpr-20588.34", 0x000002, 0x400000, CRC(84f4162d) SHA1(efb7c632399616052e39f21dd399eba78563d83a) )
+ ROM_LOAD_VROM( "mpr-20589.35", 0x000000, 0x400000, CRC(4e653d02) SHA1(120161ed82d882daa90b5637aa84714de7b26c95) )
+ ROM_LOAD_VROM( "mpr-20590.36", 0x000006, 0x400000, CRC(527049be) SHA1(541bba0101baacfae3de7d998a5f29da61b2b956) )
+ ROM_LOAD_VROM( "mpr-20591.37", 0x000004, 0x400000, CRC(3be20243) SHA1(83797b50f368843462dc46401940eda1a5c2acbd) )
+ ROM_LOAD_VROM( "mpr-20592.38", 0x00000a, 0x400000, CRC(d7985b28) SHA1(a7a15757802d88e8ded363bad4d1d673bfc53a76) )
+ ROM_LOAD_VROM( "mpr-20593.39", 0x000008, 0x400000, CRC(e670c4d3) SHA1(bc180de98757972b322f4f0d461a8c8d8094ac05) )
+ ROM_LOAD_VROM( "mpr-20594.40", 0x00000e, 0x400000, CRC(35578240) SHA1(7902f41d376dd3449a17fb4d907e0bd84d70272b) )
+ ROM_LOAD_VROM( "mpr-20595.41", 0x00000c, 0x400000, CRC(1d4a2cad) SHA1(0ee9eef0bb969e715a98ca1c212a02d413f36145) )
+
+ ROM_REGION( 0x080000, "audiocpu", 0 ) /* 68000 code */
+ ROM_LOAD16_WORD_SWAP( "epr-20600.21", 0x000000, 0x080000, CRC(f0e7db7e) SHA1(980c1c6d3e8534c414d8b8016531e90f77e00f90) )
+
+ /* Are these in the correct order ?? */
+ ROM_REGION16_BE( 0x1000000, "samples", 0 ) /* SCSP samples */
+ ROM_LOAD16_WORD_SWAP( "mpr-20576", 0x000000, 0x400000, CRC(1eeb540b) SHA1(f8de2ff302757aad38b61e2093e3783857d5d0fb) ) /* IC22 ?? */
+ ROM_LOAD16_WORD_SWAP( "mpr-20578", 0x400000, 0x400000, CRC(d222f2d4) SHA1(f6128f8267e91242d7fc3d85beb2cd35124dd018) ) /* IC24 ?? */
+ ROM_LOAD16_WORD_SWAP( "mpr-20577", 0x800000, 0x400000, CRC(3b236187) SHA1(0ba1513e0652f6686b306a4f600a565570b1ebcc) ) /* IC23 ?? */
+ ROM_LOAD16_WORD_SWAP( "mpr-20579", 0xc00000, 0x400000, CRC(08788436) SHA1(6c9af2cf65e803882d6f4c0d57eb9e95cdeb5818) ) /* IC25 ?? */
+
+ ROM_REGION( 0x20000, "cpu2", 0 ) /* Z80 code */
+ ROM_FILL( 0x000000, 0x20000, 0x0000 )
+
+ ROM_REGION( 0x1000000, "dsb", 0 ) /* DSB samples */
+ ROM_FILL( 0x000000, 0x1000000, 0x0000 )
+
+ // ???? 317-0235-COM Model 3
+ ROM_PARAMETER( ":315_5881:key", "29260e96" )
+ROM_END
+
ROM_START( spikeout ) /* Step 2.1, Sega game ID# is 833-13592, ROM board ID# 834-13593 SPK */
ROM_REGION64_BE( 0x8800000, "user1", 0 ) /* program + data ROMs */
// CROM
@@ -5947,7 +6148,15 @@ void model3_state::init_swtrilga()
//uint32_t *rom = (uint32_t*)memregion("user1")->base();
init_model3_20();
- //rom[(0xf6dd0^4)/4] = 0x60000000;
+ //rom[(0xf6dd0^4)/4] = 0x60000000; // skip force feedback check
+}
+
+void model3_state::init_swtrilgp()
+{
+ uint32_t *rom = (uint32_t*)memregion("user1")->base();
+ init_model3_20();
+
+ rom[(0x87db8^4)/4] = 0x60000000; // skip force feedback check
}
void model3_state::init_von2()
@@ -6095,8 +6304,10 @@ GAME( 1998, srally2, 0, model3_20, scud, model3_state, init_sra
GAME( 1998, srally2x, 0, model3_20, scud, model3_state, init_srally2, ROT0, "Sega", "Sega Rally 2 DX", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND )
GAME( 1998, von2, 0, model3_20_5881, von2, model3_state, init_von2, ROT0, "Sega", "Virtual On 2: Oratorio Tangram (Revision B)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND )
GAME( 1998, von2a, von2, model3_20_5881, von2, model3_state, init_von2, ROT0, "Sega", "Virtual On 2: Oratorio Tangram (Revision A)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND )
+GAME( 1998, von2o, von2, model3_20_5881, von2, model3_state, init_von2, ROT0, "Sega", "Virtual On 2: Oratorio Tangram", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND )
GAME( 1998, von254g, von2, model3_20_5881, von2, model3_state, init_von2, ROT0, "Sega", "Virtual On 2: Oratorio Tangram (ver 5.4g)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND )
-GAME( 1998, fvipers2, 0, model3_20_5881, model3, model3_state, init_vs299, ROT0, "Sega", "Fighting Vipers 2 (Japan, Revision A)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND )
+GAME( 1998, fvipers2, 0, model3_20_5881, model3, model3_state, init_vs299, ROT0, "Sega", "Fighting Vipers 2 (Revision A)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND )
+GAME( 1998, fvipers2o,fvipers2,model3_20_5881, model3, model3_state, init_vs299, ROT0, "Sega", "Fighting Vipers 2", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND )
GAME( 1998, vs298, 0, model3_20_5881, model3, model3_state, init_vs298, ROT0, "Sega", "Virtua Striker 2 '98 (Step 2.0)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND )
GAME( 1998, vs2v991, 0, model3_20_5881, model3, model3_state, init_vs299, ROT0, "Sega", "Virtua Striker 2 '99.1 (Revision B)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND )
GAME( 1998, vs299b, vs2v991, model3_20_5881, model3, model3_state, init_vs299, ROT0, "Sega", "Virtua Striker 2 '99 (Revision B)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND )
@@ -6111,6 +6322,7 @@ GAME( 1998, dirtdvlsa, dirtdvls, model3_21_5881, scud, model3_state, init_di
GAME( 1998, dirtdvlsj, dirtdvls, model3_21_5881, scud, model3_state, init_dirtdvls, ROT0, "Sega", "Dirt Devils (Japan, Revision A)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND )
GAME( 1998, swtrilgy, 0, model3_21_5881, swtrilgy, model3_state, init_swtrilgy, ROT0, "Sega / LucasArts", "Star Wars Trilogy Arcade (Revision A)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND )
GAME( 1998, swtrilgya, swtrilgy, model3_21_5881, swtrilgy, model3_state, init_swtrilga, ROT0, "Sega / LucasArts", "Star Wars Trilogy Arcade", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND )
+GAME( 1998, swtrilgyp, swtrilgy, model3_21, swtrilgy, model3_state, init_swtrilgp, ROT0, "Sega / LucasArts", "Star Wars Trilogy Arcade (location test, 16.09.98)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND )
GAME( 1998, spikeout, 0, model3_21_5881, model3, model3_state, init_spikeout, ROT0, "Sega", "Spikeout (Revision C)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND )
GAME( 1999, spikeofe, 0, model3_21_5881, model3, model3_state, init_spikeofe, ROT0, "Sega", "Spikeout Final Edition", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND )
GAME( 1998, magtruck, 0, model3_21_5881, eca, model3_state, init_magtruck, ROT0, "Sega", "Magical Truck Adventure (Japan)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_IMPERFECT_SOUND )
diff --git a/src/mame/drivers/mpc3000.cpp b/src/mame/drivers/mpc3000.cpp
index fee0ca9f1aa..32522bfce2d 100644
--- a/src/mame/drivers/mpc3000.cpp
+++ b/src/mame/drivers/mpc3000.cpp
@@ -61,7 +61,7 @@ MPCs on other hardware:
***************************************************************************/
#include "emu.h"
-#include "cpu/nec/v53.h"
+#include "cpu/nec/v5x.h"
#include "sound/l7a1045_l6028_dsp_a.h"
#include "video/hd61830.h"
#include "bus/midi/midi.h"
@@ -90,7 +90,7 @@ public:
void init_mpc3000();
private:
- required_device<v53_base_device> m_maincpu;
+ required_device<v53a_device> m_maincpu;
required_device<hd61830_device> m_lcdc;
required_device<l7a1045_sound_device> m_dsp;
required_device<midi_port_device> m_mdout;
@@ -126,7 +126,7 @@ WRITE16_MEMBER(mpc3000_state::dsp_0008_hack_w)
{
// this is related to the DSP's DMA capability. The DSP
// connects to the V53's DMA3 channel on both the MPCs and HNG64.
- m_maincpu->dreq3_w(data&0x1);
+ m_maincpu->dreq_w<3>(data&0x1);
m_dsp->l7a1045_sound_w(space,8/2,data,mem_mask);
}
@@ -170,18 +170,13 @@ PALETTE_INIT_MEMBER(mpc3000_state, mpc3000)
void mpc3000_state::mpc3000(machine_config &config)
{
- // V53A isn't devcb3 compliant yet.
- //V53A(config, m_maincpu, 16_MHz_XTAL);
- //m_maincpu->set_addrmap(AS_PROGRAM, &mpc3000_state::mpc3000_map);
- //m_maincpu->set_addrmap(AS_IO, &mpc3000_state::mpc3000_io_map);
- device_t *device = nullptr;
- MCFG_DEVICE_ADD("maincpu", V53A, 16_MHz_XTAL)
- MCFG_DEVICE_PROGRAM_MAP(mpc3000_map)
- MCFG_DEVICE_IO_MAP(mpc3000_io_map)
- MCFG_V53_DMAU_OUT_HREQ_CB(WRITELINE("maincpu", v53_base_device, hack_w))
- MCFG_V53_DMAU_IN_MEMR_CB(READ8(*this, mpc3000_state, dma_memr_cb))
- MCFG_V53_DMAU_IN_IOR_3_CB(WRITE8("dsp", l7a1045_sound_device, dma_r_cb))
- MCFG_V53_DMAU_OUT_IOW_3_CB(WRITE8("dsp", l7a1045_sound_device, dma_w_cb))
+ V53A(config, m_maincpu, 16_MHz_XTAL);
+ m_maincpu->set_addrmap(AS_PROGRAM, &mpc3000_state::mpc3000_map);
+ m_maincpu->set_addrmap(AS_IO, &mpc3000_state::mpc3000_io_map);
+ m_maincpu->out_hreq_cb().set(m_maincpu, FUNC(v53a_device::hack_w));
+ m_maincpu->in_memr_cb().set(FUNC(mpc3000_state::dma_memr_cb));
+ m_maincpu->in_ior_cb<3>().set(m_dsp, FUNC(l7a1045_sound_device::dma_r_cb));
+ m_maincpu->out_iow_cb<3>().set(m_dsp, FUNC(l7a1045_sound_device::dma_w_cb));
hc259_device &loledlatch(HC259(config, "loledlatch"));
loledlatch.q_out_cb<0>().set_output("led0").invert(); // Edit Loop
@@ -203,6 +198,7 @@ void mpc3000_state::mpc3000(machine_config &config)
hiledlatch.q_out_cb<6>().set_output("led14").invert(); // 16 Levels
hiledlatch.q_out_cb<7>().set_output("led15").invert(); // After
+ device_t *device = nullptr;
MCFG_SCREEN_ADD("screen", LCD)
MCFG_SCREEN_REFRESH_RATE(80)
MCFG_SCREEN_UPDATE_DEVICE("lcdc", hd61830_device, screen_update)
diff --git a/src/mame/drivers/mrflea.cpp b/src/mame/drivers/mrflea.cpp
index 5678a2bc898..dbc3ba46330 100644
--- a/src/mame/drivers/mrflea.cpp
+++ b/src/mame/drivers/mrflea.cpp
@@ -278,11 +278,11 @@ MACHINE_CONFIG_START(mrflea_state::mrflea)
i8255_device &subppi(I8255(config, "subppi", 0));
subppi.in_pa_callback().set("mainppi", FUNC(i8255_device::pa_r));
subppi.out_pc_callback().set("mainppi", FUNC(i8255_device::pc6_w)).bit(5); // IBFA -> ACKA
- subppi.out_pc_callback().append("pic", FUNC(pic8259_device::ir0_w)).bit(3); // INTRA
+ subppi.out_pc_callback().append(m_pic, FUNC(pic8259_device::ir0_w)).bit(3); // INTRA
subppi.out_pc_callback().append("mainppi", FUNC(i8255_device::pc2_w)).bit(1); // OBFB -> STBB
- MCFG_DEVICE_ADD("pic", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE("subcpu", 0))
+ PIC8259(config, m_pic, 0);
+ m_pic->out_int_callback().set_inputline(m_subcpu, 0);
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
diff --git a/src/mame/drivers/ms0515.cpp b/src/mame/drivers/ms0515.cpp
index e583f0839c8..ee0c2878ea7 100644
--- a/src/mame/drivers/ms0515.cpp
+++ b/src/mame/drivers/ms0515.cpp
@@ -576,17 +576,16 @@ MACHINE_CONFIG_START(ms0515_state::ms0515)
MCFG_DEVICE_ADD("keyboard_clock", CLOCK, 4960*16)
MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(*this, ms0515_state, write_keyboard_clock))
- MCFG_DEVICE_ADD("pit8253", PIT8253, 0)
- MCFG_PIT8253_CLK0(XTAL(2'000'000))
-// MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, ms0515_state, write_keyboard_clock))
- MCFG_PIT8253_CLK1(XTAL(2'000'000))
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, ms0515_state, write_line_clock))
- MCFG_PIT8253_CLK2(XTAL(2'000'000))
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, ms0515_state, pit8253_out2_changed))
+ PIT8253(config, m_pit8253, 0);
+ m_pit8253->set_clk<0>(XTAL(2'000'000));
+// m_pit8253->out_handler<0>().set(FUNC(ms0515_state::write_keyboard_clock));
+ m_pit8253->set_clk<1>(XTAL(2'000'000));
+ m_pit8253->out_handler<0>().set(FUNC(ms0515_state::write_line_clock));
+ m_pit8253->set_clk<2>(XTAL(2'000'000));
+ m_pit8253->out_handler<2>().set(FUNC(ms0515_state::pit8253_out2_changed));
SPEAKER(config, "mono").front_center();
- MCFG_DEVICE_ADD("speaker", SPEAKER_SOUND)
- MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.45)
+ SPEAKER_SOUND(config, m_speaker).add_route(ALL_OUTPUTS, "mono", 0.45);
/* internal ram */
RAM(config, RAM_TAG).set_default_size("128K");
diff --git a/src/mame/drivers/ms6102.cpp b/src/mame/drivers/ms6102.cpp
index 622a52318f1..173205a0dc0 100644
--- a/src/mame/drivers/ms6102.cpp
+++ b/src/mame/drivers/ms6102.cpp
@@ -314,7 +314,7 @@ MACHINE_CONFIG_START(ms6102_state::ms6102)
I8214(config, m_pic, XTAL(18'432'000) / 9);
m_pic->int_wr_callback().set(FUNC(ms6102_state::irq_w));
- MCFG_DEVICE_ADD("earom", KR1601RR1, 0)
+ KR1601RR1(config, m_earom, 0);
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
@@ -359,11 +359,11 @@ MACHINE_CONFIG_START(ms6102_state::ms6102)
RS232_PORT(config, m_rs232, default_rs232_devices, "null_modem");
m_rs232->rxd_handler().set(m_i8251, FUNC(i8251_device::write_rxd));
- MCFG_DEVICE_ADD("pit8253", PIT8253, 0)
- MCFG_PIT8253_CLK0(XTAL(16'400'000) / 9)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE("i8251", i8251_device, write_txc))
- MCFG_PIT8253_CLK1(XTAL(16'400'000) / 9)
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE("i8251", i8251_device, write_rxc))
+ pit8253_device &pit8253(PIT8253(config, "pit8253", 0));
+ pit8253.set_clk<0>(XTAL(16'400'000) / 9);
+ pit8253.out_handler<0>().set(m_i8251, FUNC(i8251_device::write_txc));
+ pit8253.set_clk<1>(XTAL(16'400'000) / 9);
+ pit8253.out_handler<1>().set(m_i8251, FUNC(i8251_device::write_rxc));
MACHINE_CONFIG_END
ROM_START( ms6102 )
diff --git a/src/mame/drivers/multi16.cpp b/src/mame/drivers/multi16.cpp
index c066134da29..0bfa6f56bc1 100644
--- a/src/mame/drivers/multi16.cpp
+++ b/src/mame/drivers/multi16.cpp
@@ -140,10 +140,10 @@ void multi16_state::machine_reset()
MACHINE_CONFIG_START(multi16_state::multi16)
/* basic machine hardware */
- MCFG_DEVICE_ADD("maincpu", I8086, 8000000)
- MCFG_DEVICE_PROGRAM_MAP(multi16_map)
- MCFG_DEVICE_IO_MAP(multi16_io)
- MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE("pic8259", pic8259_device, inta_cb)
+ I8086(config, m_maincpu, 8000000);
+ m_maincpu->set_addrmap(AS_PROGRAM, &multi16_state::multi16_map);
+ m_maincpu->set_addrmap(AS_IO, &multi16_state::multi16_io);
+ m_maincpu->set_irq_acknowledge_callback("pic8259", FUNC(pic8259_device::inta_cb));
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
@@ -161,8 +161,8 @@ MACHINE_CONFIG_START(multi16_state::multi16)
MCFG_MC6845_SHOW_BORDER_AREA(false)
MCFG_MC6845_CHAR_WIDTH(8)
- MCFG_DEVICE_ADD("pic8259", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE("maincpu", 0))
+ PIC8259(config, m_pic, 0);
+ m_pic->out_int_callback().set_inputline(m_maincpu, 0);
MACHINE_CONFIG_END
/* ROM definition */
diff --git a/src/mame/drivers/multi8.cpp b/src/mame/drivers/multi8.cpp
index 5d78a6e795e..716086febab 100644
--- a/src/mame/drivers/multi8.cpp
+++ b/src/mame/drivers/multi8.cpp
@@ -608,9 +608,9 @@ MACHINE_CONFIG_START(multi8_state::multi8)
uart_clock.signal_handler().set("uart", FUNC(i8251_device::write_txc));
uart_clock.signal_handler().append("uart", FUNC(i8251_device::write_rxc));
- MCFG_DEVICE_ADD("uart", I8251, 0) // for cassette
- MCFG_DEVICE_ADD("pit", PIT8253, 0)
- MCFG_DEVICE_ADD("pic", PIC8259, 0)
+ I8251(config, "uart", 0); // for cassette
+ PIT8253(config, "pit", 0);
+ PIC8259(config, "pic", 0);
//UPD765A(config, "fdc", false, true);
//MCFG_FLOPPY_DRIVE_ADD("fdc:0", multi8_floppies, "525hd", floppy_image_device::default_floppy_formats)
diff --git a/src/mame/drivers/myb3k.cpp b/src/mame/drivers/myb3k.cpp
index bf2e81f6bcb..b4901092a02 100644
--- a/src/mame/drivers/myb3k.cpp
+++ b/src/mame/drivers/myb3k.cpp
@@ -932,17 +932,17 @@ static void stepone_isa_cards(device_slot_interface &device)
MACHINE_CONFIG_START(myb3k_state::myb3k)
/* basic machine hardware */
- MCFG_DEVICE_ADD("maincpu", I8088, XTAL(14'318'181) / 3) /* 14.3182 main crystal divided by three through a 8284A */
- MCFG_DEVICE_PROGRAM_MAP(myb3k_map)
- MCFG_DEVICE_IO_MAP(myb3k_io)
- MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE("pic", pic8259_device, inta_cb)
+ I8088(config, m_maincpu, XTAL(14'318'181) / 3); /* 14.3182 main crystal divided by three through a 8284A */
+ m_maincpu->set_addrmap(AS_PROGRAM, &myb3k_state::myb3k_map);
+ m_maincpu->set_addrmap(AS_IO, &myb3k_state::myb3k_io);
+ m_maincpu->set_irq_acknowledge_callback("pic", FUNC(pic8259_device::inta_cb));
/* RAM options */
RAM(config, RAM_TAG).set_default_size("256K").set_extra_options("128K, 256K");
/* Interrupt controller */
- MCFG_DEVICE_ADD("pic", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(WRITELINE(*this, myb3k_state, pic_int_w))
+ PIC8259(config, m_pic8259, 0);
+ m_pic8259->out_int_callback().set(FUNC(myb3k_state::pic_int_w));
/* Parallel port */
I8255A(config, m_ppi8255);
@@ -970,13 +970,13 @@ MACHINE_CONFIG_START(myb3k_state::myb3k)
m_dma8257->out_dack_cb<3>().set(FUNC(myb3k_state::dack3_w));
/* Timer */
- MCFG_DEVICE_ADD("pit", PIT8253, 0)
- MCFG_PIT8253_CLK0(XTAL(14'318'181) / 12.0) /* TIMINT straight into IRQ0 */
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE("pic", pic8259_device, ir0_w))
- MCFG_PIT8253_CLK1(XTAL(14'318'181) / 12.0) /* speaker if port c bit 5 is low */
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(*this, myb3k_state, pit_out1_changed))
- // MCFG_PIT8253_CLK2(XTAL(14'318'181) / 12.0) /* ANDed with port c bit 6 but marked as "not use"*/
- // MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, myb3k_state, pit_out2_changed))
+ PIT8253(config, m_pit8253, 0);
+ m_pit8253->set_clk<0>(XTAL(14'318'181) / 12.0); /* TIMINT straight into IRQ0 */
+ m_pit8253->out_handler<0>().set(m_pic8259, FUNC(pic8259_device::ir0_w));
+ m_pit8253->set_clk<1>(XTAL(14'318'181) / 12.0); /* speaker if port c bit 5 is low */
+ m_pit8253->out_handler<1>().set(FUNC(myb3k_state::pit_out1_changed));
+ // m_pit8253->set_clk<2>(XTAL(14'318'181) / 12.0); /* ANDed with port c bit 6 but marked as "not use"*/
+ // m_pit8253->out_handler<2>().set(FUNC(myb3k_state::pit_out2_changed));
/* Video controller */
MCFG_MC6845_ADD("crtc", H46505, "screen", XTAL(14'318'181) / 16) /* Main crystal divided by 16 through a 74163 4 bit counter */
@@ -987,11 +987,11 @@ MACHINE_CONFIG_START(myb3k_state::myb3k)
/* ISA8+ Expansion bus */
MCFG_DEVICE_ADD("isa", ISA8, 0)
MCFG_ISA8_CPU("maincpu")
- MCFG_ISA_OUT_IRQ2_CB(WRITELINE("pic", pic8259_device, ir2_w))
- MCFG_ISA_OUT_IRQ3_CB(WRITELINE("pic", pic8259_device, ir3_w))
- MCFG_ISA_OUT_IRQ4_CB(WRITELINE("pic", pic8259_device, ir4_w))
+ MCFG_ISA_OUT_IRQ2_CB(WRITELINE(m_pic8259, pic8259_device, ir2_w))
+ MCFG_ISA_OUT_IRQ3_CB(WRITELINE(m_pic8259, pic8259_device, ir3_w))
+ MCFG_ISA_OUT_IRQ4_CB(WRITELINE(m_pic8259, pic8259_device, ir4_w))
MCFG_ISA_OUT_IRQ5_CB(WRITELINE(*this, myb3k_state, isa_irq5_w)) // Jumper J4 selectable
- MCFG_ISA_OUT_IRQ6_CB(WRITELINE("pic", pic8259_device, ir6_w))
+ MCFG_ISA_OUT_IRQ6_CB(WRITELINE(m_pic8259, pic8259_device, ir6_w))
MCFG_ISA_OUT_IRQ7_CB(WRITELINE(*this, myb3k_state, isa_irq7_w)) // Jumper J5 selectable
//MCFG_ISA_OUT_DRQ0_CB(WRITELINE("dma", i8257_device, dreq0_w)) // Part of ISA16 but not ISA8 standard but implemented on ISA8 B8 (SRDY) on this motherboard
MCFG_ISA_OUT_DRQ1_CB(WRITELINE("dma", i8257_device, dreq1_w))
diff --git a/src/mame/drivers/mz2000.cpp b/src/mame/drivers/mz2000.cpp
index a3c5a4336cc..0b4fa35810c 100644
--- a/src/mame/drivers/mz2000.cpp
+++ b/src/mame/drivers/mz2000.cpp
@@ -895,10 +895,10 @@ MACHINE_CONFIG_START(mz2000_state::mz2000)
pio.in_pb_callback().set(FUNC(mz2000_state::mz2000_pio1_portb_r));
/* TODO: clocks aren't known */
- MCFG_DEVICE_ADD("pit", PIT8253, 0)
- MCFG_PIT8253_CLK0(31250)
- MCFG_PIT8253_CLK1(31250) /* needed by "Art Magic" to boot */
- MCFG_PIT8253_CLK2(31250)
+ PIT8253(config, m_pit8253, 0);
+ m_pit8253->set_clk<0>(31250);
+ m_pit8253->set_clk<1>(31250); /* needed by "Art Magic" to boot */
+ m_pit8253->set_clk<2>(31250);
MB8877(config, m_mb8877a, 1_MHz_XTAL);
diff --git a/src/mame/drivers/mz2500.cpp b/src/mame/drivers/mz2500.cpp
index 78abc032239..a1851236ed8 100644
--- a/src/mame/drivers/mz2500.cpp
+++ b/src/mame/drivers/mz2500.cpp
@@ -1824,13 +1824,13 @@ MACHINE_CONFIG_START(mz2500_state::mz2500)
RP5C15(config, m_rtc, 32.768_kHz_XTAL);
m_rtc->alarm().set(FUNC(mz2500_state::mz2500_rtc_alarm_irq));
- MCFG_DEVICE_ADD("pit", PIT8253, 0)
- MCFG_PIT8253_CLK0(31250)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, mz2500_state, pit8253_clk0_irq))
+ PIT8253(config, m_pit, 0);
+ m_pit->set_clk<0>(31250);
+ m_pit->out_handler<0>().set(FUNC(mz2500_state::pit8253_clk0_irq));
// TODO: is this really right?
- MCFG_PIT8253_CLK1(0)
- MCFG_PIT8253_CLK2(16) //CH2, used by Super MZ demo / The Black Onyx and a few others (TODO: timing of this)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE("pit", pit8253_device, write_clk1))
+ m_pit->set_clk<1>(0);
+ m_pit->set_clk<2>(16); //CH2, used by Super MZ demo / The Black Onyx and a few others (TODO: timing of this)
+ m_pit->out_handler<2>().set(m_pit, FUNC(pit8253_device::write_clk1));
MB8877(config, m_fdc, 1_MHz_XTAL);
diff --git a/src/mame/drivers/mz700.cpp b/src/mame/drivers/mz700.cpp
index 603c11e7395..490b89a7e88 100644
--- a/src/mame/drivers/mz700.cpp
+++ b/src/mame/drivers/mz700.cpp
@@ -401,13 +401,13 @@ MACHINE_CONFIG_START(mz_state::mz700)
MCFG_TIMER_DRIVER_ADD_PERIODIC("other", mz_state, ne556_other_callback, attotime::from_hz(34.5))
/* devices */
- MCFG_DEVICE_ADD("pit8253", PIT8253, 0)
- MCFG_PIT8253_CLK0(XTAL(17'734'470)/20)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, mz_state, pit_out0_changed))
- MCFG_PIT8253_CLK1(15611.0)
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE("pit8253", pit8253_device, write_clk2))
- MCFG_PIT8253_CLK2(0)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, mz_state, pit_irq_2))
+ PIT8253(config, m_pit, 0);
+ m_pit->set_clk<0>(XTAL(17'734'470)/20);
+ m_pit->out_handler<0>().set(FUNC(mz_state::pit_out0_changed));
+ m_pit->set_clk<1>(15611.0);
+ m_pit->out_handler<1>().set(m_pit, FUNC(pit8253_device::write_clk2));
+ m_pit->set_clk<2>(0);
+ m_pit->out_handler<2>().set(FUNC(mz_state::pit_irq_2));
I8255(config, m_ppi);
m_ppi->out_pa_callback().set(FUNC(mz_state::pio_port_a_w));
@@ -453,8 +453,7 @@ MACHINE_CONFIG_START(mz_state::mz800)
MCFG_SOFTWARE_LIST_ADD("cass_list","mz800_cass")
/* devices */
- MCFG_DEVICE_MODIFY("pit8253")
- MCFG_PIT8253_CLK0(XTAL(17'734'470)/16)
+ m_pit->set_clk<0>(XTAL(17'734'470)/16);
z80pio_device& pio(Z80PIO(config, "z80pio", XTAL(17'734'470)/5));
pio.out_int_callback().set(FUNC(mz_state::mz800_z80pio_irq));
diff --git a/src/mame/drivers/mz80.cpp b/src/mame/drivers/mz80.cpp
index 301af9c970e..dec43e3b58c 100644
--- a/src/mame/drivers/mz80.cpp
+++ b/src/mame/drivers/mz80.cpp
@@ -309,13 +309,13 @@ MACHINE_CONFIG_START(mz80_state::mz80k)
m_ppi->in_pc_callback().set(FUNC(mz80_state::mz80k_8255_portc_r));
m_ppi->out_pc_callback().set(FUNC(mz80_state::mz80k_8255_portc_w));
- MCFG_DEVICE_ADD("pit8253", PIT8253, 0)
- MCFG_PIT8253_CLK0(XTAL(8'000'000)/4)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, mz80_state, pit_out0_changed))
- MCFG_PIT8253_CLK1(XTAL(8'000'000)/256)
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE("pit8253", pit8253_device, write_clk2))
- MCFG_PIT8253_CLK2(0)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, mz80_state, pit_out2_changed))
+ PIT8253(config, m_pit, 0);
+ m_pit->set_clk<0>(XTAL(8'000'000)/4);
+ m_pit->out_handler<0>().set(FUNC(mz80_state::pit_out0_changed));
+ m_pit->set_clk<1>(XTAL(8'000'000)/256);
+ m_pit->out_handler<1>().set(m_pit, FUNC(pit8253_device::write_clk2));
+ m_pit->set_clk<2>(0);
+ m_pit->out_handler<2>().set(FUNC(mz80_state::pit_out2_changed));
MCFG_TIMER_DRIVER_ADD_PERIODIC("tempo", mz80_state, ne555_tempo_callback, attotime::from_hz(34))
MCFG_CASSETTE_ADD( "cassette" )
diff --git a/src/mame/drivers/namcos22.cpp b/src/mame/drivers/namcos22.cpp
index 57316ed70cd..d0ed4ed556f 100644
--- a/src/mame/drivers/namcos22.cpp
+++ b/src/mame/drivers/namcos22.cpp
@@ -1683,6 +1683,9 @@ READ16_MEMBER(namcos22_state::namcos22_keycus_r)
break;
}
+ if (machine().side_effects_disabled())
+ return 0;
+
// pick a random number, but don't pick the same twice in a row
u16 old_rng = m_keycus_rng;
do
@@ -1708,7 +1711,10 @@ WRITE16_MEMBER(namcos22_state::namcos22_keycus_w)
READ16_MEMBER(namcos22_state::namcos22_portbit_r)
{
u16 ret = m_portbits[offset] & 1;
- m_portbits[offset] = m_portbits[offset] >> 1 | 0x8000;
+
+ if (!machine().side_effects_disabled())
+ m_portbits[offset] = m_portbits[offset] >> 1 | 0x8000;
+
return ret;
}
@@ -2087,7 +2093,8 @@ READ16_MEMBER(namcos22_state::namcos22_dspram16_r)
break;
case 2:
- m_dspram16_latch = value >> 16;
+ if (!machine().side_effects_disabled())
+ m_dspram16_latch = value >> 16;
value &= 0xffff;
break;
@@ -2789,6 +2796,8 @@ void namcos22_state::iomcu_s22_io(address_map &map)
Tokyo Wars:
1 = start button lamp
+ 4 = handle solenoid
+ 6 = seat motor
other: ?
*/
@@ -3122,27 +3131,38 @@ static INPUT_PORTS_START( ridgera )
/* 1 3 5 When the cabinet is set to Deluxe, the stick shift is basically
|-|-| an 8-way joystick that locks into place.
2 4 6 Standard (default) setup uses a racing shifter like in Ace Driver. */
- PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_NAME("Shift Down")
- PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_NAME("Shift Up")
- PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_NAME("Shift Left") // not used in Standard Cabinet
- PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT) PORT_NAME("Shift Right") // not used in Standard Cabinet
- PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME("Clutch Pedal") // not used in Standard Cabinet
+ PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_NAME("Shift Down")
+ PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_NAME("Shift Up")
+ PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_NAME("Shift Left") // not used in Standard Cabinet
+ PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_NAME("Shift Right") // "
+ PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_NAME("Clutch Pedal") // "
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_CONFNAME( 0x0100, 0x0000, DEF_STR( Cabinet ) ) // @ JAMMA pins
+ PORT_CONFNAME( 0x0100, 0x0000, DEF_STR( Cabinet ) )
PORT_CONFSETTING( 0x0000, DEF_STR( Standard ) )
PORT_CONFSETTING( 0x0100, "Deluxe" )
PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_COIN2 )
- PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_SERVICE3 ) // also service mode?
+ PORT_SERVICE( 0x0400, IP_ACTIVE_LOW )
PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_SERVICE1 )
PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_START("ADC.0")
+ PORT_BIT( 0xff, 0x80, IPT_PADDLE ) PORT_MINMAX(0x20, 0xe0) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_NAME("Steering Wheel")
+
+ PORT_START("ADC.1")
+ PORT_BIT( 0xff, 0x00, IPT_PEDAL ) PORT_MINMAX(0x00, 0xd0) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_NAME("Gas Pedal")
+
+ PORT_START("ADC.2")
+ PORT_BIT( 0xff, 0x00, IPT_PEDAL2 ) PORT_MINMAX(0x00, 0xc0) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_NAME("Brake Pedal")
+
PORT_START("DSW")
- PORT_SERVICE_DIPLOC( 0x0001, IP_ACTIVE_LOW, "SW2:1")
+ PORT_DIPNAME( 0x0001, 0x0001, "Test Mode" ) PORT_DIPLOCATION("SW2:1")
+ PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
+ PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW2:2" )
PORT_DIPUNKNOWN_DIPLOC( 0x0004, 0x0004, "SW2:3" )
PORT_DIPUNKNOWN_DIPLOC( 0x0008, 0x0008, "SW2:4" )
@@ -3158,15 +3178,6 @@ static INPUT_PORTS_START( ridgera )
PORT_DIPUNKNOWN_DIPLOC( 0x2000, 0x2000, "SW3:6" )
PORT_DIPUNKNOWN_DIPLOC( 0x4000, 0x4000, "SW3:7" )
PORT_DIPUNKNOWN_DIPLOC( 0x8000, 0x8000, "SW3:8" )
-
- PORT_START("ADC.0")
- PORT_BIT( 0xff, 0x80, IPT_PADDLE ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_NAME("Steering Wheel")
-
- PORT_START("ADC.1")
- PORT_BIT( 0xff, 0x00, IPT_PEDAL ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_NAME("Gas Pedal")
-
- PORT_START("ADC.2")
- PORT_BIT( 0xff, 0x00, IPT_PEDAL2 ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_NAME("Brake Pedal")
INPUT_PORTS_END
static INPUT_PORTS_START( ridgeracf )
@@ -3177,14 +3188,17 @@ static INPUT_PORTS_START( ridgeracf )
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON5 ) PORT_NAME("AT Switch")
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_BUTTON6 ) PORT_NAME("MT Switch")
PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_SERVICE2 )
- PORT_SERVICE( 0x0400, IP_ACTIVE_LOW )
// DIP3-1 to DIP3-3 are for setting up the viewing angle (game used one board per screen?)
// Some of the other dipswitches are for debugging, like with Ridge Racer 2.
PORT_MODIFY("DSW")
- PORT_DIPUNKNOWN_DIPLOC( 0x0001, 0x0000, "SW2:1" ) // always on?
- PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0000, "SW2:2" ) // always on?
- PORT_DIPNAME( 0x8000, 0x8000, "Test Mode" ) PORT_DIPLOCATION("SW3:8")
+ PORT_DIPNAME( 0x0001, 0x0000, "Unknown" ) PORT_DIPLOCATION("SW2:1") // always on?
+ PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
+ PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
+ PORT_DIPNAME( 0x0002, 0x0000, "Unknown" ) PORT_DIPLOCATION("SW2:2") // always on?
+ PORT_DIPSETTING( 0x0002, DEF_STR( Off ) )
+ PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
+ PORT_DIPNAME( 0x8000, 0x8000, "Test Mode 2" ) PORT_DIPLOCATION("SW3:8")
PORT_DIPSETTING( 0x8000, DEF_STR( Off ) )
PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
INPUT_PORTS_END
@@ -3193,7 +3207,7 @@ static INPUT_PORTS_START( ridgera2 )
PORT_INCLUDE( ridgera )
PORT_MODIFY("INPUTS")
- PORT_CONFNAME( 0x2100, 0x2000, DEF_STR( Cabinet ) ) // @ JAMMA pins
+ PORT_CONFNAME( 0x2100, 0x2000, DEF_STR( Cabinet ) )
PORT_CONFSETTING( 0x0000, "50 Inch" )
PORT_CONFSETTING( 0x0100, "Twin" )
PORT_CONFSETTING( 0x2000, DEF_STR( Standard ) )
@@ -3207,7 +3221,7 @@ static INPUT_PORTS_START( ridgera2 )
3-7 : debug polygons
*/
PORT_MODIFY("DSW")
- PORT_DIPNAME( 0x8000, 0x8000, "Test Mode" ) PORT_DIPLOCATION("SW3:8")
+ PORT_DIPNAME( 0x8000, 0x8000, "Test Mode 2" ) PORT_DIPLOCATION("SW3:8")
PORT_DIPSETTING( 0x8000, DEF_STR( Off ) )
PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
INPUT_PORTS_END
@@ -3217,8 +3231,7 @@ static INPUT_PORTS_START( raveracw )
PORT_MODIFY("INPUTS")
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_NAME("View Change")
-
- PORT_CONFNAME( 0x2100, 0x2000, DEF_STR( Cabinet ) ) // @ JAMMA pins
+ PORT_CONFNAME( 0x2100, 0x2000, DEF_STR( Cabinet ) )
PORT_CONFSETTING( 0x0000, "50 Inch" )
PORT_CONFSETTING( 0x0100, "Twin" )
PORT_CONFSETTING( 0x2000, DEF_STR( Standard ) )
@@ -3228,8 +3241,8 @@ INPUT_PORTS_END
static INPUT_PORTS_START( cybrcomm )
PORT_START("INPUTS")
- PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("Gun Trigger") // placed on both sticks
- PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("Missile Button") // placed on both sticks
+ PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("Gun Trigger") // placed on both sticks
+ PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_NAME("Missile Button") // placed on both sticks
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_UNKNOWN )
@@ -3245,6 +3258,21 @@ static INPUT_PORTS_START( cybrcomm )
PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ // The ranges here are based on the test mode which displays +-224
+ // The eeprom is calibrated using these settings. If the SUBCPU handling changes then these might end up needing to change again too.
+ // Default key arrangement is based on dual-joystick 'Tank' arrangement found in Assault and CyberSled
+ PORT_START("ADC.0") // right joystick: vertical
+ PORT_BIT( 0xff, 0x7f, IPT_AD_STICK_Y ) PORT_MINMAX(0x47, 0xb7) PORT_CODE_DEC(KEYCODE_I) PORT_CODE_INC(KEYCODE_K) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(2)
+
+ PORT_START("ADC.1") // left joystick: vertical
+ PORT_BIT( 0xff, 0x7f, IPT_AD_STICK_Y ) PORT_MINMAX(0x47, 0xb7) PORT_CODE_DEC(KEYCODE_E) PORT_CODE_INC(KEYCODE_D) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1)
+
+ PORT_START("ADC.2") // right joystick: horizontal
+ PORT_BIT( 0xff, 0x7f, IPT_AD_STICK_X ) PORT_MINMAX(0x47, 0xb7) PORT_CODE_DEC(KEYCODE_J) PORT_CODE_INC(KEYCODE_L) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(2)
+
+ PORT_START("ADC.3") // left joystick: horizontal
+ PORT_BIT( 0xff, 0x7f, IPT_AD_STICK_X ) PORT_MINMAX(0x47, 0xb7) PORT_CODE_DEC(KEYCODE_S) PORT_CODE_INC(KEYCODE_F) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1)
+
PORT_START("DSW")
PORT_DIPUNKNOWN_DIPLOC( 0x0001, 0x0001, "SW2:1" )
PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW2:2" )
@@ -3262,26 +3290,11 @@ static INPUT_PORTS_START( cybrcomm )
PORT_DIPUNKNOWN_DIPLOC( 0x2000, 0x2000, "SW3:6" )
PORT_DIPUNKNOWN_DIPLOC( 0x4000, 0x4000, "SW3:7" )
PORT_DIPUNKNOWN_DIPLOC( 0x8000, 0x8000, "SW3:8" )
-
- // The ranges here are based on the test mode which displays +-224
- // The eeprom is calibrated using these settings. If the SUBCPU handling changes then these might end up needing to change again too.
- // Default key arrangement is based on dual-joystick 'Tank' arrangement found in Assault and CyberSled
- PORT_START("ADC.0") // right joystick: vertical
- PORT_BIT( 0xff, 0x7f, IPT_AD_STICK_Y ) PORT_MINMAX(0x47, 0xb7) PORT_CODE_DEC(KEYCODE_I) PORT_CODE_INC(KEYCODE_K) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(2)
-
- PORT_START("ADC.1") // left joystick: vertical
- PORT_BIT( 0xff, 0x7f, IPT_AD_STICK_Y ) PORT_MINMAX(0x47, 0xb7) PORT_CODE_DEC(KEYCODE_E) PORT_CODE_INC(KEYCODE_D) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1)
-
- PORT_START("ADC.2") // right joystick: horizontal
- PORT_BIT( 0xff, 0x7f, IPT_AD_STICK_X ) PORT_MINMAX(0x47, 0xb7) PORT_CODE_DEC(KEYCODE_J) PORT_CODE_INC(KEYCODE_L) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(2)
-
- PORT_START("ADC.3") // left joystick: horizontal
- PORT_BIT( 0xff, 0x7f, IPT_AD_STICK_X ) PORT_MINMAX(0x47, 0xb7) PORT_CODE_DEC(KEYCODE_S) PORT_CODE_INC(KEYCODE_F) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1)
INPUT_PORTS_END
static INPUT_PORTS_START( acedrvr )
PORT_START("INPUTS")
- PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_NAME("Shift Down")
+ PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_NAME("Shift Down")
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_NAME("Shift Up")
PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_UNKNOWN )
@@ -3291,28 +3304,21 @@ static INPUT_PORTS_START( acedrvr )
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_COIN2 )
- PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_SERVICE( 0x0400, IP_ACTIVE_LOW )
PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_SERVICE1 )
PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_NAME("Motion-Stop")
- PORT_START("CUSTOM.0")
- PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2) PORT_NAME("Dev Service Enter") // also "REC" start
- PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2) PORT_NAME("Dev Service Exit") // also "REC" stop
- PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_UNKNOWN ) // enters free camera view while in attract mode
- PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_UNKNOWN ) // resets game?
- PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2) PORT_NAME("Dev Service Up")
- PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2) PORT_NAME("Dev Service Down")
- PORT_BIT( 0xff30, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_START("ADC.0")
+ PORT_BIT( 0xff, 0x80, IPT_PADDLE ) PORT_MINMAX(0x20, 0xe0) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_NAME("Steering Wheel")
- PORT_START("CUSTOM.1")
- PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_UNKNOWN ) // pauses game?
- PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_BIT( 0xfff0, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_START("ADC.1")
+ PORT_BIT( 0xff, 0x00, IPT_PEDAL ) PORT_MINMAX(0x00, 0x90) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_NAME("Gas Pedal")
+
+ PORT_START("ADC.2")
+ PORT_BIT( 0xff, 0x00, IPT_PEDAL2 ) PORT_MINMAX(0x00, 0x48) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_NAME("Brake Pedal")
PORT_START("DSW")
PORT_DIPUNKNOWN_DIPLOC( 0x0001, 0x0001, "SW2:1" )
@@ -3332,31 +3338,44 @@ static INPUT_PORTS_START( acedrvr )
PORT_DIPNAME( 0x4000, 0x4000, "Test Mode?" ) PORT_DIPLOCATION("SW3:7")
PORT_DIPSETTING( 0x4000, DEF_STR( Off ) )
PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
- PORT_DIPNAME( 0x8000, 0x8000, "Test Mode?" ) PORT_DIPLOCATION("SW3:8")
+ PORT_DIPNAME( 0x8000, 0x8000, "Test Mode?" ) PORT_DIPLOCATION("SW3:8") // enter test mode if SW3:7 is on
PORT_DIPSETTING( 0x8000, DEF_STR( Off ) )
PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
- PORT_START("ADC.0")
- PORT_BIT( 0xff, 0x80, IPT_PADDLE ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_NAME("Steering Wheel")
+ PORT_START("DEV")
+ PORT_CONFNAME( 0x01, 0x00, "Enable Dev Inputs" )
+ PORT_CONFSETTING( 0x00, DEF_STR( No ) )
+ PORT_CONFSETTING( 0x01, DEF_STR( Yes ) )
- PORT_START("ADC.1")
- PORT_BIT( 0xff, 0x00, IPT_PEDAL ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_NAME("Gas Pedal")
+ PORT_START("CUSTOM.0")
+ PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_CONDITION("DEV", 0x01, EQUALS, 0x01) PORT_PLAYER(2) PORT_NAME("Dev Service Enter") // also "REC" start
+ PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_CONDITION("DEV", 0x01, EQUALS, 0x01) PORT_PLAYER(2) PORT_NAME("Dev Service Exit") // also "REC" stop
+ PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_CONDITION("DEV", 0x01, EQUALS, 0x01) PORT_PLAYER(2) PORT_NAME("Dev Unknown 1") // enters free camera view while in attract mode
+ PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_CONDITION("DEV", 0x01, EQUALS, 0x01) PORT_PLAYER(2) PORT_NAME("Dev Unknown 2") // resets game?
+ PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_CONDITION("DEV", 0x01, EQUALS, 0x01) PORT_PLAYER(2) PORT_NAME("Dev Service Left")
+ PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_CONDITION("DEV", 0x01, EQUALS, 0x01) PORT_PLAYER(2) PORT_NAME("Dev Service Right")
+ PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_CONDITION("DEV", 0x01, EQUALS, 0x01) PORT_PLAYER(2) PORT_NAME("Dev Service Up")
+ PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_CONDITION("DEV", 0x01, EQUALS, 0x01) PORT_PLAYER(2) PORT_NAME("Dev Service Down")
+ PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNKNOWN ) PORT_CONDITION("DEV", 0x01, EQUALS, 0x01)
+ PORT_BIT( 0xffff, IP_ACTIVE_LOW, IPT_UNUSED ) PORT_CONDITION("DEV", 0x01, EQUALS, 0x00)
- PORT_START("ADC.2")
- PORT_BIT( 0xff, 0x00, IPT_PEDAL2 ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_NAME("Brake Pedal")
+ PORT_START("CUSTOM.1")
+ PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_UNKNOWN ) PORT_CONDITION("DEV", 0x01, EQUALS, 0x01)
+ PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_UNKNOWN ) PORT_CONDITION("DEV", 0x01, EQUALS, 0x01)
+ PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_UNKNOWN ) PORT_CONDITION("DEV", 0x01, EQUALS, 0x01) // pauses game?
+ PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_UNKNOWN ) PORT_CONDITION("DEV", 0x01, EQUALS, 0x01)
+ PORT_BIT( 0xfff0, IP_ACTIVE_LOW, IPT_UNKNOWN ) PORT_CONDITION("DEV", 0x01, EQUALS, 0x01)
+ PORT_BIT( 0xffff, IP_ACTIVE_LOW, IPT_UNUSED ) PORT_CONDITION("DEV", 0x01, EQUALS, 0x00)
INPUT_PORTS_END
static INPUT_PORTS_START( victlap )
PORT_INCLUDE( acedrvr )
PORT_MODIFY("CUSTOM.0")
- PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2) PORT_NAME("Dev Service Exit")
- PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_UNKNOWN ) // win race and reset game?
- PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_UNKNOWN )
- PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2) PORT_NAME("Dev Service Up")
- PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2) PORT_NAME("Dev Service Down")
- PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2) PORT_NAME("Dev Service Enter")
- PORT_BIT( 0xfe0e, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_CONDITION("DEV", 0x01, EQUALS, 0x01) PORT_PLAYER(2) PORT_NAME("Dev Service Exit")
+ PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_CONDITION("DEV", 0x01, EQUALS, 0x01) PORT_PLAYER(2) PORT_NAME("Dev Service Enter")
+ PORT_BIT( 0xfe0e, IP_ACTIVE_LOW, IPT_UNKNOWN ) PORT_CONDITION("DEV", 0x01, EQUALS, 0x01)
+ PORT_BIT( 0xffff, IP_ACTIVE_LOW, IPT_UNUSED ) PORT_CONDITION("DEV", 0x01, EQUALS, 0x00)
INPUT_PORTS_END
/*********************************************************************************************/
@@ -3367,17 +3386,6 @@ CUSTOM_INPUT_MEMBER(namcos22_state::alpine_motor_read)
}
static INPUT_PORTS_START( alpiner )
- PORT_START("DSW")
- PORT_DIPUNKNOWN_DIPLOC( 0x0001, 0x0001, "SW4:1" )
- PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW4:2" )
- PORT_DIPUNKNOWN_DIPLOC( 0x0004, 0x0004, "SW4:3" )
- PORT_DIPUNKNOWN_DIPLOC( 0x0008, 0x0008, "SW4:4" )
- PORT_DIPUNKNOWN_DIPLOC( 0x0010, 0x0010, "SW4:5" )
- PORT_DIPUNKNOWN_DIPLOC( 0x0020, 0x0020, "SW4:6" )
- PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW4:7" )
- PORT_DIPUNKNOWN_DIPLOC( 0x0080, 0x0080, "SW4:8" )
- PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
-
PORT_START("INPUTS")
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_UNKNOWN )
@@ -3395,9 +3403,7 @@ static INPUT_PORTS_START( alpiner )
PORT_START("ADC.1")
PORT_BIT( 0x3ff, 0x200, IPT_AD_STICK_X ) PORT_MINMAX(0x080, 0x380) PORT_SENSITIVITY(100) PORT_KEYDELTA(16) PORT_PLAYER(2) PORT_NAME("Steps Edge")
-INPUT_PORTS_END
-static INPUT_PORTS_START( airco22 )
PORT_START("DSW")
PORT_DIPUNKNOWN_DIPLOC( 0x0001, 0x0001, "SW4:1" )
PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW4:2" )
@@ -3408,7 +3414,9 @@ static INPUT_PORTS_START( airco22 )
PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW4:7" )
PORT_DIPUNKNOWN_DIPLOC( 0x0080, 0x0080, "SW4:8" )
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
+INPUT_PORTS_END
+static INPUT_PORTS_START( airco22 )
PORT_START("INPUTS")
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_UNKNOWN )
@@ -3427,14 +3435,10 @@ static INPUT_PORTS_START( airco22 )
PORT_BIT( 0x3ff, 0x200, IPT_AD_STICK_Y ) PORT_MINMAX(0x100, 0x300) PORT_SENSITIVITY(100) PORT_KEYDELTA(12)
PORT_START("ADC.2") // throttle stick auto-centers
- PORT_BIT( 0x3ff, 0x200, IPT_AD_STICK_Z ) PORT_MINMAX(0x100, 0x300) PORT_SENSITIVITY(100) PORT_KEYDELTA(12) PORT_NAME("Throttle Stick")
-INPUT_PORTS_END
+ PORT_BIT( 0x3ff, 0x200, IPT_AD_STICK_Y ) PORT_MINMAX(0x100, 0x300) PORT_SENSITIVITY(100) PORT_KEYDELTA(12) PORT_PLAYER(2) PORT_NAME("Throttle Stick")
-static INPUT_PORTS_START( cybrcycc )
PORT_START("DSW")
- PORT_DIPNAME( 0x0001, 0x0001, "Test Mode?" ) PORT_DIPLOCATION("SW4:1")
- PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
- PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
+ PORT_DIPUNKNOWN_DIPLOC( 0x0001, 0x0001, "SW4:1" )
PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW4:2" )
PORT_DIPUNKNOWN_DIPLOC( 0x0004, 0x0004, "SW4:3" )
PORT_DIPUNKNOWN_DIPLOC( 0x0008, 0x0008, "SW4:4" )
@@ -3443,7 +3447,9 @@ static INPUT_PORTS_START( cybrcycc )
PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW4:7" )
PORT_DIPUNKNOWN_DIPLOC( 0x0080, 0x0080, "SW4:8" )
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
+INPUT_PORTS_END
+static INPUT_PORTS_START( cybrcycc )
PORT_START("INPUTS")
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_UNKNOWN )
@@ -3463,11 +3469,11 @@ static INPUT_PORTS_START( cybrcycc )
PORT_START("ADC.2")
PORT_BIT( 0x3ff, 0x000, IPT_PEDAL2 ) PORT_MINMAX(0x000, 0x100) PORT_SENSITIVITY(100) PORT_KEYDELTA(40) PORT_NAME("Brake Pedal")
-INPUT_PORTS_END
-static INPUT_PORTS_START( dirtdash )
PORT_START("DSW")
- PORT_DIPUNKNOWN_DIPLOC( 0x0001, 0x0001, "SW4:1" )
+ PORT_DIPNAME( 0x0001, 0x0001, "Test Mode" ) PORT_DIPLOCATION("SW4:1")
+ PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
+ PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW4:2" )
PORT_DIPUNKNOWN_DIPLOC( 0x0004, 0x0004, "SW4:3" )
PORT_DIPUNKNOWN_DIPLOC( 0x0008, 0x0008, "SW4:4" )
@@ -3476,7 +3482,9 @@ static INPUT_PORTS_START( dirtdash )
PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW4:7" )
PORT_DIPUNKNOWN_DIPLOC( 0x0080, 0x0080, "SW4:8" )
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
+INPUT_PORTS_END
+static INPUT_PORTS_START( dirtdash )
PORT_START("INPUTS")
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_UNKNOWN )
@@ -3486,7 +3494,11 @@ static INPUT_PORTS_START( dirtdash )
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_NAME("Shift Up")
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_NAME("Shift Down")
PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_NAME("Motion-Stop")
- PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_CONFNAME( 0x0200, 0x0000, DEF_STR( Cabinet ) )
+ PORT_CONFSETTING( 0x0000, DEF_STR( Standard ) )
+ PORT_CONFSETTING( 0x0200, "Deluxe" ) // car suspension valves
+ PORT_BIT( 0xfc00, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("ADC.0")
PORT_BIT( 0x3ff, 0x200, IPT_PADDLE ) PORT_MINMAX(0x001, 0x3ff) PORT_SENSITIVITY(100) PORT_KEYDELTA(12) PORT_NAME("Steering Wheel")
@@ -3496,13 +3508,9 @@ static INPUT_PORTS_START( dirtdash )
PORT_START("ADC.2")
PORT_BIT( 0x3ff, 0x000, IPT_PEDAL2 ) PORT_MINMAX(0x000, 0x100) PORT_SENSITIVITY(100) PORT_KEYDELTA(40) PORT_NAME("Brake Pedal")
-INPUT_PORTS_END
-static INPUT_PORTS_START( tokyowar )
PORT_START("DSW")
- PORT_DIPNAME( 0x0001, 0x0001, "Test Mode?" ) PORT_DIPLOCATION("SW4:1")
- PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
- PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
+ PORT_DIPUNKNOWN_DIPLOC( 0x0001, 0x0001, "SW4:1" )
PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW4:2" )
PORT_DIPUNKNOWN_DIPLOC( 0x0004, 0x0004, "SW4:3" )
PORT_DIPUNKNOWN_DIPLOC( 0x0008, 0x0008, "SW4:4" )
@@ -3511,7 +3519,9 @@ static INPUT_PORTS_START( tokyowar )
PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW4:7" )
PORT_DIPUNKNOWN_DIPLOC( 0x0080, 0x0080, "SW4:8" )
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
+INPUT_PORTS_END
+static INPUT_PORTS_START( tokyowar )
PORT_START("INPUTS")
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_UNKNOWN )
@@ -3520,7 +3530,9 @@ static INPUT_PORTS_START( tokyowar )
PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_START1 ) // also view-change function
PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON5 ) PORT_NAME("Right Trigger")
PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_NAME("Left Trigger")
- PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_UNKNOWN )
+ PORT_CONFNAME( 0x0080, 0x0080, DEF_STR( Cabinet ) )
+ PORT_CONFSETTING( 0x0080, DEF_STR( Standard ) )
+ PORT_CONFSETTING( 0x0000, "Deluxe" ) // cannon recoil motors
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNKNOWN )
PORT_START("ADC.0")
@@ -3531,11 +3543,9 @@ static INPUT_PORTS_START( tokyowar )
PORT_START("ADC.3")
PORT_BIT( 0x3ff, 0x000, IPT_PEDAL2 ) PORT_MINMAX(0x000, 0x100) PORT_SENSITIVITY(100) PORT_KEYDELTA(20) PORT_NAME("Brake Pedal")
-INPUT_PORTS_END
-static INPUT_PORTS_START( aquajet )
PORT_START("DSW")
- PORT_DIPNAME( 0x0001, 0x0001, "Test Mode?" ) PORT_DIPLOCATION("SW4:1")
+ PORT_DIPNAME( 0x0001, 0x0001, "Test Mode" ) PORT_DIPLOCATION("SW4:1")
PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW4:2" )
@@ -3546,7 +3556,9 @@ static INPUT_PORTS_START( aquajet )
PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW4:7" )
PORT_DIPUNKNOWN_DIPLOC( 0x0080, 0x0080, "SW4:8" )
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
+INPUT_PORTS_END
+static INPUT_PORTS_START( aquajet )
PORT_START("INPUTS")
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_UNKNOWN )
@@ -3566,11 +3578,9 @@ static INPUT_PORTS_START( aquajet )
PORT_START("ADC.2")
PORT_BIT( 0x3ff, 0x1fc, IPT_AD_STICK_Y ) PORT_MINMAX(0x000, 0x3f8) PORT_SENSITIVITY(100) PORT_KEYDELTA(40) PORT_REVERSE
-INPUT_PORTS_END
-static INPUT_PORTS_START( adillor )
PORT_START("DSW")
- PORT_DIPNAME( 0x0001, 0x0001, "Test Mode?" ) PORT_DIPLOCATION("SW4:1")
+ PORT_DIPNAME( 0x0001, 0x0001, "Test Mode" ) PORT_DIPLOCATION("SW4:1")
PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW4:2" )
@@ -3581,16 +3591,9 @@ static INPUT_PORTS_START( adillor )
PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW4:7" )
PORT_DIPUNKNOWN_DIPLOC( 0x0080, 0x0080, "SW4:8" )
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
+INPUT_PORTS_END
- PORT_START("CUSTOM.0")
- PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2) PORT_NAME("Dev Service Enter")
- PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2) PORT_NAME("Dev Service Exit")
- PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2) PORT_NAME("Dev Service Left")
- PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2) PORT_NAME("Dev Service Right") // when in normal testmode, press this to enter the extra testmode
- PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2) PORT_NAME("Dev Service Up")
- PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2) PORT_NAME("Dev Service Down")
- PORT_BIT( 0xffc0, IP_ACTIVE_LOW, IPT_UNKNOWN )
-
+static INPUT_PORTS_START( adillor )
PORT_START("INPUTS")
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_UNKNOWN )
@@ -3608,11 +3611,11 @@ static INPUT_PORTS_START( adillor )
PORT_START("TRACKY")
PORT_BIT( 0xff, 0x80, IPT_AD_STICK_Y ) PORT_MINMAX(0x01, 0xff) PORT_SENSITIVITY(100) PORT_KEYDELTA(8) PORT_NAME("Trackball Y")
-INPUT_PORTS_END
-static INPUT_PORTS_START( propcycl )
PORT_START("DSW")
- PORT_DIPUNKNOWN_DIPLOC( 0x0001, 0x0001, "SW4:1" )
+ PORT_DIPNAME( 0x0001, 0x0001, "Test Mode" ) PORT_DIPLOCATION("SW4:1")
+ PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
+ PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW4:2" )
PORT_DIPUNKNOWN_DIPLOC( 0x0004, 0x0004, "SW4:3" )
PORT_DIPUNKNOWN_DIPLOC( 0x0008, 0x0008, "SW4:4" )
@@ -3622,6 +3625,23 @@ static INPUT_PORTS_START( propcycl )
PORT_DIPUNKNOWN_DIPLOC( 0x0080, 0x0080, "SW4:8" )
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
+ PORT_START("DEV")
+ PORT_CONFNAME( 0x01, 0x00, "Enable Dev Inputs" )
+ PORT_CONFSETTING( 0x00, DEF_STR( No ) )
+ PORT_CONFSETTING( 0x01, DEF_STR( Yes ) )
+
+ PORT_START("CUSTOM.0")
+ PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_CONDITION("DEV", 0x01, EQUALS, 0x01) PORT_PLAYER(2) PORT_NAME("Dev Service Enter")
+ PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_CONDITION("DEV", 0x01, EQUALS, 0x01) PORT_PLAYER(2) PORT_NAME("Dev Service Exit")
+ PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_CONDITION("DEV", 0x01, EQUALS, 0x01) PORT_PLAYER(2) PORT_NAME("Dev Service Left")
+ PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_CONDITION("DEV", 0x01, EQUALS, 0x01) PORT_PLAYER(2) PORT_NAME("Dev Service Right") // when in normal testmode, press this to enter the extra testmode
+ PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_CONDITION("DEV", 0x01, EQUALS, 0x01) PORT_PLAYER(2) PORT_NAME("Dev Service Up")
+ PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_CONDITION("DEV", 0x01, EQUALS, 0x01) PORT_PLAYER(2) PORT_NAME("Dev Service Down")
+ PORT_BIT( 0xffc0, IP_ACTIVE_LOW, IPT_UNKNOWN ) PORT_CONDITION("DEV", 0x01, EQUALS, 0x01)
+ PORT_BIT( 0xffff, IP_ACTIVE_LOW, IPT_UNUSED ) PORT_CONDITION("DEV", 0x01, EQUALS, 0x00)
+INPUT_PORTS_END
+
+static INPUT_PORTS_START( propcycl )
PORT_START("INPUTS")
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_UNKNOWN )
@@ -3642,9 +3662,7 @@ static INPUT_PORTS_START( propcycl )
PORT_START("PEDAL")
PORT_BIT( 0x7f, 0x00, IPT_PEDAL ) PORT_SENSITIVITY(100) PORT_KEYDELTA(10)
-INPUT_PORTS_END
-static INPUT_PORTS_START( timecris )
PORT_START("DSW")
PORT_DIPUNKNOWN_DIPLOC( 0x0001, 0x0001, "SW4:1" )
PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW4:2" )
@@ -3653,9 +3671,11 @@ static INPUT_PORTS_START( timecris )
PORT_DIPUNKNOWN_DIPLOC( 0x0010, 0x0010, "SW4:5" )
PORT_DIPUNKNOWN_DIPLOC( 0x0020, 0x0020, "SW4:6" )
PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW4:7" )
- PORT_SERVICE_DIPLOC( 0x0080, IP_ACTIVE_LOW, "SW4:8")
+ PORT_DIPUNKNOWN_DIPLOC( 0x0080, 0x0080, "SW4:8" )
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
+INPUT_PORTS_END
+static INPUT_PORTS_START( timecris )
PORT_START("INPUTS")
PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_UNKNOWN )
@@ -3672,6 +3692,19 @@ static INPUT_PORTS_START( timecris )
PORT_START( "LIGHTY" ) // tuned for CRT - can't shoot below the statusbar?
PORT_BIT( 0xffff, 43+241/2, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, 1.0, 0.0, 0) PORT_MINMAX(43, 43+241) PORT_SENSITIVITY(64) PORT_KEYDELTA(4)
+
+ PORT_START("DSW")
+ PORT_DIPUNKNOWN_DIPLOC( 0x0001, 0x0001, "SW4:1" )
+ PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW4:2" )
+ PORT_DIPUNKNOWN_DIPLOC( 0x0004, 0x0004, "SW4:3" )
+ PORT_DIPUNKNOWN_DIPLOC( 0x0008, 0x0008, "SW4:4" )
+ PORT_DIPUNKNOWN_DIPLOC( 0x0010, 0x0010, "SW4:5" )
+ PORT_DIPUNKNOWN_DIPLOC( 0x0020, 0x0020, "SW4:6" )
+ PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW4:7" )
+ PORT_DIPNAME( 0x0080, 0x0080, "Test Mode" ) PORT_DIPLOCATION("SW4:8")
+ PORT_DIPSETTING( 0x0080, DEF_STR( Off ) )
+ PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
+ PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
INPUT_PORTS_END
@@ -5788,7 +5821,7 @@ void namcos22_state::init_dirtdash()
/* YEAR, NAME, PARENT, MACHINE, INPUT, CLASS, INIT, MNTR, COMPANY, FULLNAME, FLAGS */
// System22 games
-GAME( 1993, ridgerac, 0, namcos22, ridgera, namcos22_state, init_ridgeraj, ROT0, "Namco", "Ridge Racer (Rev. RR3, World)", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_GRAPHICS ) // 1994-01-17
+GAME( 1993, ridgerac, 0, namcos22, ridgera, namcos22_state, init_ridgeraj, ROT0, "Namco", "Ridge Racer (Rev. RR3, World)", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_GRAPHICS ) // 1994-01-17, RR3 means USA?
GAME( 1993, ridgerac3, ridgerac, namcos22, ridgera, namcos22_state, init_ridgeraj, ROT0, "Namco", "Ridge Racer (Rev. RR2 Ver.B, World, 3-screen?)", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_GRAPHICS ) // 1993-10-28, no indication that this really is a 3-screen version.
GAME( 1993, ridgeracb, ridgerac, namcos22, ridgera, namcos22_state, init_ridgeraj, ROT0, "Namco", "Ridge Racer (Rev. RR2, World)", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_GRAPHICS ) // 1993-10-07
GAME( 1993, ridgeracj, ridgerac, namcos22, ridgera, namcos22_state, init_ridgeraj, ROT0, "Namco", "Ridge Racer (Rev. RR1, Japan)", MACHINE_SUPPORTS_SAVE | MACHINE_IMPERFECT_GRAPHICS ) // 1993-10-07
diff --git a/src/mame/drivers/ngen.cpp b/src/mame/drivers/ngen.cpp
index 20c207bc365..9c92197f184 100644
--- a/src/mame/drivers/ngen.cpp
+++ b/src/mame/drivers/ngen.cpp
@@ -94,10 +94,10 @@ public:
m_pit(*this,"pit"),
m_hdc(*this,"hdc"),
m_fdc(*this,"fdc"),
- m_disk_rom(*this,"disk"),
- m_fd0(*this,"fdc:0"),
m_fdc_timer(*this,"fdc_timer"),
m_hdc_timer(*this,"hdc_timer"),
+ m_disk_rom(*this,"disk"),
+ m_fd0(*this,"fdc:0"),
m_hd_buffer(*this,"hd_buffer_ram")
{
}
@@ -150,6 +150,8 @@ protected:
required_device<pit8254_device> m_pit;
optional_device<wd2010_device> m_hdc;
optional_device<wd2797_device> m_fdc;
+ optional_device<pit8253_device> m_fdc_timer;
+ optional_device<pit8253_device> m_hdc_timer;
private:
DECLARE_WRITE16_MEMBER(cpu_peripheral_cb);
@@ -182,8 +184,6 @@ private:
memory_array m_vram;
memory_array m_fontram;
optional_device<floppy_connector> m_fd0;
- optional_device<pit8253_device> m_fdc_timer;
- optional_device<pit8253_device> m_hdc_timer;
optional_shared_ptr<uint8_t> m_hd_buffer;
void set_dma_channel(int channel, int state);
@@ -1015,13 +1015,14 @@ MACHINE_CONFIG_START(ngen_state::ngen)
m_fdc->intrq_wr_callback().set(FUNC(ngen_state::fdc_irq_w));
m_fdc->drq_wr_callback().set(m_maincpu, FUNC(i80186_cpu_device::drq1_w));
m_fdc->set_force_ready(true);
- MCFG_DEVICE_ADD("fdc_timer", PIT8253, 0)
- MCFG_PIT8253_CLK0(0)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(m_pic,pic8259_device,ir5_w)) // clocked on FDC data register access
- MCFG_PIT8253_CLK1(20_MHz_XTAL / 20)
-// MCFG_PIT8253_OUT1_HANDLER(WRITELINE(m_pic,pic8259_device,ir5_w)) // 1MHz
- MCFG_PIT8253_CLK2(20_MHz_XTAL / 20)
-// MCFG_PIT8253_OUT2_HANDLER(WRITELINE(m_pic,pic8259_device,ir5_w))
+
+ PIT8253(config, m_fdc_timer, 0);
+ m_fdc_timer->set_clk<0>(0);
+ m_fdc_timer->out_handler<0>().set(m_pic, FUNC(pic8259_device::ir5_w)); // clocked on FDC data register access
+ m_fdc_timer->set_clk<1>(20_MHz_XTAL / 20);
+// m_fdc_timer->out_handler<1>().set(m_pic, FUNC(pic8259_device::ir5_w)); // 1MHz
+ m_fdc_timer->set_clk<2>(20_MHz_XTAL / 20);
+// m_fdc_timer->out_handler<2>().set(m_pic, FUNC(pic8259_device::ir5_w));
// TODO: WD1010 HDC (not implemented), use WD2010 for now
WD2010(config, m_hdc, 20_MHz_XTAL / 4);
@@ -1034,8 +1035,9 @@ MACHINE_CONFIG_START(ngen_state::ngen)
m_hdc->in_tk000_callback().set_constant(1);
m_hdc->in_sc_callback().set_constant(1);
- MCFG_DEVICE_ADD("hdc_timer", PIT8253, 0)
- MCFG_PIT8253_CLK2(20_MHz_XTAL / 10) // 2MHz
+ PIT8253(config, m_hdc_timer, 0);
+ m_hdc_timer->set_clk<2>(20_MHz_XTAL / 10); // 2MHz
+
MCFG_FLOPPY_DRIVE_ADD("fdc:0", ngen_floppies, "525qd", floppy_image_device::default_floppy_formats)
MCFG_HARDDISK_ADD("hard0")
@@ -1127,13 +1129,14 @@ MACHINE_CONFIG_START(ngen386_state::ngen386)
m_fdc->intrq_wr_callback().set(FUNC(ngen386_state::fdc_irq_w));
//m_fdc->drq_wr_callback().set(m_i386cpu, FUNC(i80186_cpu_device_device::drq1_w));
m_fdc->set_force_ready(true);
- MCFG_DEVICE_ADD("fdc_timer", PIT8253, 0)
- MCFG_PIT8253_CLK0(0)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE("pic",pic8259_device,ir5_w)) // clocked on FDC data register access
- MCFG_PIT8253_CLK1(20_MHz_XTAL / 20)
-// MCFG_PIT8253_OUT1_HANDLER(WRITELINE("pic",pic8259_device,ir5_w)) // 1MHz
- MCFG_PIT8253_CLK2(20_MHz_XTAL / 20)
-// MCFG_PIT8253_OUT2_HANDLER(WRITELINE("pic",pic8259_device,ir5_w))
+
+ PIT8253(config, m_fdc_timer, 0);
+ m_fdc_timer->set_clk<0>(0);
+ m_fdc_timer->out_handler<0>().set(m_pic, FUNC(pic8259_device::ir5_w)); // clocked on FDC data register access
+ m_fdc_timer->set_clk<1>(20_MHz_XTAL / 20);
+// m_fdc_timer->out_handler<1>().set(m_pic, FUNC(pic8259_device::ir5_w)); // 1MHz
+ m_fdc_timer->set_clk<2>(20_MHz_XTAL / 20);
+// m_fdc_timer->out_handler<2>().set(m_pic, FUNC(pic8259_device::ir5_w));
// TODO: WD1010 HDC (not implemented), use WD2010 for now
WD2010(config, m_hdc, 20_MHz_XTAL / 4);
@@ -1146,8 +1149,9 @@ MACHINE_CONFIG_START(ngen386_state::ngen386)
m_hdc->in_tk000_callback().set_constant(1);
m_hdc->in_sc_callback().set_constant(1);
- MCFG_DEVICE_ADD("hdc_timer", PIT8253, 0)
- MCFG_PIT8253_CLK2(20_MHz_XTAL / 10) // 2MHz
+ PIT8253(config, m_hdc_timer, 0);
+ m_hdc_timer->set_clk<2>(20_MHz_XTAL / 10); // 2MHz
+
MCFG_FLOPPY_DRIVE_ADD("fdc:0", ngen_floppies, "525qd", floppy_image_device::default_floppy_formats)
MCFG_HARDDISK_ADD("hard0")
MACHINE_CONFIG_END
diff --git a/src/mame/drivers/notetaker.cpp b/src/mame/drivers/notetaker.cpp
index c4e8177361f..b35cad7af75 100644
--- a/src/mame/drivers/notetaker.cpp
+++ b/src/mame/drivers/notetaker.cpp
@@ -800,24 +800,23 @@ INPUT_PORTS_END
MACHINE_CONFIG_START(notetaker_state::notetakr)
/* basic machine hardware */
/* IO CPU: 8086@8MHz */
- MCFG_DEVICE_ADD("iop_cpu", I8086, 24_MHz_XTAL / 3) /* iD8086-2 @ E4A; 24Mhz crystal divided down to 8Mhz by i8284 clock generator */
- MCFG_DEVICE_PROGRAM_MAP(iop_mem)
- MCFG_DEVICE_IO_MAP(iop_io)
- MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE("iop_pic8259", pic8259_device, inta_cb)
+ I8086(config, m_iop_cpu, 24_MHz_XTAL / 3); /* iD8086-2 @ E4A; 24Mhz crystal divided down to 8Mhz by i8284 clock generator */
+ m_iop_cpu->set_addrmap(AS_PROGRAM, &notetaker_state::iop_mem);
+ m_iop_cpu->set_addrmap(AS_IO, &notetaker_state::iop_io);
+ m_iop_cpu->set_irq_acknowledge_callback("iop_pic8259", FUNC(pic8259_device::inta_cb));
- MCFG_DEVICE_ADD("iop_pic8259", PIC8259, 0) // iP8259A-2 @ E6
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE("iop_cpu", 0))
+ PIC8259(config, m_iop_pic, 0); // iP8259A-2 @ E6
+ m_iop_pic->out_int_callback().set_inputline(m_iop_cpu, 0);
/* Emulator CPU: 8086@5MHz */
- MCFG_DEVICE_ADD("ep_cpu", I8086, 15_MHz_XTAL / 3)
- MCFG_DEVICE_DISABLE() // TODO: implement the cpu control bits so this doesn't execute garbage/zeroes before its firmware gets loaded
- MCFG_DEVICE_PROGRAM_MAP(ep_mem)
- MCFG_DEVICE_IO_MAP(ep_io)
- MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE("ep_pic8259", pic8259_device, inta_cb)
-
- MCFG_DEVICE_ADD("ep_pic8259", PIC8259, 0) // iP8259A-2 @ E6
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE("ep_cpu", 0))
+ I8086(config, m_ep_cpu, 15_MHz_XTAL / 3);
+ m_ep_cpu->set_disable(); // TODO: implement the cpu control bits so this doesn't execute garbage/zeroes before its firmware gets loaded
+ m_ep_cpu->set_addrmap(AS_PROGRAM, &notetaker_state::ep_mem);
+ m_ep_cpu->set_addrmap(AS_IO, &notetaker_state::ep_io);
+ m_ep_cpu->set_irq_acknowledge_callback("ep_pic8259", FUNC(pic8259_device::inta_cb));
+ PIC8259(config, m_ep_pic, 0); // iP8259A-2 @ E6
+ m_ep_pic->out_int_callback().set_inputline(m_ep_cpu, 0);
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
@@ -843,18 +842,18 @@ MACHINE_CONFIG_START(notetaker_state::notetakr)
// TODO: for now, we just hack it to the latter setting from start; this should be handled correctly in iop_reset();
m_crtc->set_char_width(8); //(8 pixels per column/halfword, 16 pixels per fullword)
// TODO: below is HACKED to trigger the odd/even int ir4 instead of vblank int ir7 since ir4 is required for anything to be drawn to screen! hence with the hack this interrupt triggers twice as often as it should
- m_crtc->vsyn_callback().set("iop_pic8259", FUNC(pic8259_device::ir4_w)); // note this triggers interrupts on both the iop (ir7) and emulatorcpu (ir4)
+ m_crtc->vsyn_callback().set(m_iop_pic, FUNC(pic8259_device::ir4_w)); // note this triggers interrupts on both the iop (ir7) and emulatorcpu (ir4)
m_crtc->set_screen("screen");
AY31015(config, m_kbduart); // HD6402, == AY-3-1015D
m_kbduart->set_rx_clock(960_kHz_XTAL); // hard-wired to 960KHz xtal #f11 (60000 baud, 16 clocks per baud)
m_kbduart->set_tx_clock(960_kHz_XTAL); // hard-wired to 960KHz xtal #f11 (60000 baud, 16 clocks per baud)
- m_kbduart->write_dav_callback().set("iop_pic8259", FUNC(pic8259_device::ir6_w)); // DataRecvd = KbdInt
+ m_kbduart->write_dav_callback().set(m_iop_pic, FUNC(pic8259_device::ir6_w)); // DataRecvd = KbdInt
AY31015(config, m_eiauart); // HD6402, == AY-3-1015D
m_eiauart->set_rx_clock(((960_kHz_XTAL/10)/4)/5); // hard-wired through an mc14568b divider set to divide by 4, the result set to divide by 5; this resulting 4800hz signal being 300 baud (16 clocks per baud)
m_eiauart->set_tx_clock(((960_kHz_XTAL/10)/4)/5); // hard-wired through an mc14568b divider set to divide by 4, the result set to divide by 5; this resulting 4800hz signal being 300 baud (16 clocks per baud)
- m_eiauart->write_dav_callback().set("iop_pic8259", FUNC(pic8259_device::ir3_w)); // EIADataReady = EIAInt
+ m_eiauart->write_dav_callback().set(m_iop_pic, FUNC(pic8259_device::ir3_w)); // EIADataReady = EIAInt
/* Floppy */
FD1791(config, m_fdc, (((24_MHz_XTAL/3)/2)/2)); // 2mhz, from 24mhz ip clock divided by 6 via 8284, an additional 2 by LS161 at #e1 on display/floppy board
diff --git a/src/mame/drivers/octopus.cpp b/src/mame/drivers/octopus.cpp
index 536dc880d30..ce0d1e97811 100644
--- a/src/mame/drivers/octopus.cpp
+++ b/src/mame/drivers/octopus.cpp
@@ -980,13 +980,13 @@ MACHINE_CONFIG_START(octopus_state::octopus)
MCFG_FLOPPY_DRIVE_ADD("fdc:1", octopus_floppies, "525dd", floppy_image_device::default_floppy_formats)
MCFG_SOFTWARE_LIST_ADD("fd_list","octopus")
- MCFG_DEVICE_ADD("pit", PIT8253, 0)
- MCFG_PIT8253_CLK0(4.9152_MHz_XTAL / 2) // DART channel A
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, octopus_state,serial_clock_w)) // being able to write both Rx and Tx clocks at one time would be nice
- MCFG_PIT8253_CLK1(4.9152_MHz_XTAL / 2) // DART channel B
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(m_serial,z80sio_device,rxtxcb_w))
- MCFG_PIT8253_CLK2(4.9152_MHz_XTAL / 2) // speaker frequency
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, octopus_state,spk_freq_w))
+ PIT8253(config, m_pit, 0);
+ m_pit->set_clk<0>(4.9152_MHz_XTAL / 2); // DART channel A
+ m_pit->out_handler<0>().set(FUNC(octopus_state::serial_clock_w)); // being able to write both Rx and Tx clocks at one time would be nice
+ m_pit->set_clk<1>(4.9152_MHz_XTAL / 2); // DART channel B
+ m_pit->out_handler<1>().set(m_serial, FUNC(z80sio_device::rxtxcb_w));
+ m_pit->set_clk<2>(4.9152_MHz_XTAL / 2); // speaker frequency
+ m_pit->out_handler<2>().set(FUNC(octopus_state::spk_freq_w));
SPEAKER(config, "mono").front_center();
MCFG_DEVICE_ADD("speaker", SPEAKER_SOUND)
diff --git a/src/mame/drivers/okean240.cpp b/src/mame/drivers/okean240.cpp
index 6629ceac625..ca108352322 100644
--- a/src/mame/drivers/okean240.cpp
+++ b/src/mame/drivers/okean240.cpp
@@ -563,8 +563,7 @@ MACHINE_CONFIG_START(okean240_state::okean240a)
m_ppikbd->in_pb_callback().set(FUNC(okean240_state::okean240a_port41_r));
m_ppikbd->in_pc_callback().set(FUNC(okean240_state::okean240a_port42_r));
- MCFG_DEVICE_MODIFY("pit")
- MCFG_PIT8253_CLK1(1536000) // artificial rate
+ subdevice<pit8253_device>("pit")->set_clk<1>(1536000); // artificial rate
MACHINE_CONFIG_END
MACHINE_CONFIG_START(okean240_state::okean240)
@@ -574,8 +573,7 @@ MACHINE_CONFIG_START(okean240_state::okean240)
MCFG_DEVICE_ADD("gfxdecode", GFXDECODE, "palette", gfx_okean240)
MCFG_DEVICE_REMOVE("uart")
MCFG_DEVICE_REMOVE("rs232")
- MCFG_DEVICE_MODIFY("pit")
- MCFG_PIT8253_OUT1_HANDLER(NOOP)
+ subdevice<pit8253_device>("pit")->out_handler<1>().set_nop();
MCFG_DEVICE_ADD("keyboard", GENERIC_KEYBOARD, 0)
MCFG_GENERIC_KEYBOARD_CB(PUT(okean240_state, kbd_put))
MACHINE_CONFIG_END
diff --git a/src/mame/drivers/olyboss.cpp b/src/mame/drivers/olyboss.cpp
index f1bdbc88b33..f164741811d 100644
--- a/src/mame/drivers/olyboss.cpp
+++ b/src/mame/drivers/olyboss.cpp
@@ -511,8 +511,8 @@ MACHINE_CONFIG_START( olyboss_state::bossb85 )
/* devices */
- MCFG_DEVICE_ADD("pic", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE("maincpu", 0))
+ PIC8259(config, m_pic, 0);
+ m_pic->out_int_callback().set_inputline(m_maincpu, 0);
UPD765A(config, m_fdc, true, true);
m_fdc->intrq_wr_callback().set_inputline(m_maincpu, I8085_RST65_LINE);
diff --git a/src/mame/drivers/pbaction.cpp b/src/mame/drivers/pbaction.cpp
index 889b803c16a..257dd69ee14 100644
--- a/src/mame/drivers/pbaction.cpp
+++ b/src/mame/drivers/pbaction.cpp
@@ -31,7 +31,36 @@ e800 command for the sound CPU
Notes:
-- pbactio2 has a ROM for a third Z80, not emulated, function unknown
+- pbactiont (Tecfri) has a ROM on a small subboard with two Z80, not hooked up:
+
+ 2-pin conn 12-pin conn
+____||________||||||||||||____________________
+| || _______________ |
+| |Z8430A PS | |
+| |______________| |
+| _____________ |
+| |TMM2016BP-10| |
+| |____________| |
+| __________ _______________ |
+| |74HCT273 | |ROM17 D27128D | |
+| |______________| |
+| _________ __________________ |
+| |74LS139| |MK3880N-4 Z80 CPU| |
+| |_________________| |
+| _________ __________________ |
+| |74HCT259 |MK3880N-4 Z80 CPU| |
+| |_________________| |
+| _________ _________ |
+| |74LS00P | |74LS32P | |
+| |
+|____________________________TECFRI S.A.______|
+
+This subboard controls a vertical board panel with three 7-seg displays (like on a real pinball),
+one for player 1 (7 digits), another for player 2 (7 digits) and the third for game scores (with
+three goups: two digits - one digit - two digits).
+
+One of the Z80s on this board is the main game Z80, the other is for the Pinball cabinet
+
Stephh's notes (based on the game Z80 code and some tests) :
@@ -72,12 +101,13 @@ Stephh's notes (based on the game Z80 code and some tests) :
#include "machine/segacrpt_device.h"
#include "screen.h"
#include "speaker.h"
+#include "pbactiont.lh"
WRITE8_MEMBER(pbaction_state::pbaction_sh_command_w)
{
m_soundlatch->write(space, offset, data);
- machine().scheduler().synchronize(timer_expired_delegate(FUNC(pbaction_state::sound_trigger), this));
+ m_soundcommand_timer->adjust(attotime::zero, 0);
}
TIMER_CALLBACK_MEMBER(pbaction_state::sound_trigger)
@@ -140,7 +170,7 @@ void pbaction_state::pbaction_sound_map(address_map &map)
map(0xffff, 0xffff).w(FUNC(pbaction_state::sound_irq_ack_w));
}
-void pbaction_state::pbaction2_sound_map(address_map &map)
+void pbaction_state::pbaction_alt_sound_map(address_map &map)
{
map(0x0000, 0x1fff).rom();
map(0x4000, 0x47ff).ram();
@@ -152,10 +182,110 @@ void pbaction_state::pbaction_sound_io_map(address_map &map)
map.global_mask(0xff);
map(0x00, 0x03).rw(m_ctc, FUNC(z80ctc_device::read), FUNC(z80ctc_device::write));
map(0x10, 0x11).w("ay1", FUNC(ay8910_device::address_data_w));
+ map(0x12, 0x13).nopw(); // unknown
map(0x20, 0x21).w("ay2", FUNC(ay8910_device::address_data_w));
map(0x30, 0x31).w("ay3", FUNC(ay8910_device::address_data_w));
}
+WRITE8_MEMBER(pbaction_tecfri_state::pbaction_tecfri_sub8000_w)
+{
+ m_outlatch = (data & 0x01)>>0;
+
+}
+
+WRITE8_MEMBER(pbaction_tecfri_state::pbaction_tecfri_sub8001_w)
+{
+ // writes 01 , 00 to clock after writing data to 8000
+ if (data & 0x01)
+ {
+ m_outdata = (m_outdata << 1) | m_outlatch;
+ }
+}
+
+WRITE8_MEMBER(pbaction_tecfri_state::pbaction_tecfri_sub8008_w)
+{
+ if (data != 0x00)
+ {
+ int base = 0;
+
+ switch (data)
+ {
+ case 0x01: base = 6; break;
+ case 0x02: base = 5; break;
+ case 0x04: base = 4; break;
+ case 0x08: base = 3; break;
+ case 0x10: base = 2; break;
+ case 0x20: base = 1; break;
+ case 0x40: base = 0; break;
+
+ default: break;
+ }
+
+ m_digits[base + 0] = (~m_outdata >> 0) & 0xff;
+ m_digits[base + 7] = (~m_outdata >> 8) & 0xff;
+ m_digits[base + 14] = (~m_outdata >> 16) & 0xff;
+
+ }
+ else
+ {
+ m_outdata = 0;
+ }
+}
+
+WRITE8_MEMBER(pbaction_tecfri_state::pbaction_tecfri_subtomain_w)
+{
+ //m_subtomainlatch->write(space, offset, data); // where does this go if it can't go to maincpu?
+}
+
+READ8_MEMBER(pbaction_tecfri_state::pbaction_tecfri_maintosub_r)
+{
+ return m_maintosublatch->read(space, offset);
+}
+
+READ8_MEMBER(pbaction_tecfri_state::subcpu_r)
+{
+ return 0x00; // other values stop the flippers from working? are there different inputs from the custom cabinet in here somehow?
+// return m_subtomainlatch->read(space, offset);
+}
+
+WRITE8_MEMBER(pbaction_tecfri_state::subcpu_w)
+{
+ m_maintosublatch->write(space, offset, data);
+ m_subcommand_timer->adjust(attotime::zero, 0);
+}
+
+void pbaction_tecfri_state::pbaction_tecfri_sub_map(address_map &map)
+{
+ map(0x0000, 0x03ff).rom();
+ map(0x4000, 0x47ff).ram();
+
+ map(0x8000, 0x8000).w(FUNC(pbaction_tecfri_state::pbaction_tecfri_sub8000_w));
+ map(0x8001, 0x8001).w(FUNC(pbaction_tecfri_state::pbaction_tecfri_sub8001_w));
+ //map(0x8002, 0x8007).nopw(); // startup only
+ map(0x8008, 0x8008).w(FUNC(pbaction_tecfri_state::pbaction_tecfri_sub8008_w));
+
+ map(0x8010, 0x8010).r(FUNC(pbaction_tecfri_state::pbaction_tecfri_maintosub_r));
+ map(0x8018, 0x8018).w(FUNC(pbaction_tecfri_state::pbaction_tecfri_subtomain_w));
+}
+
+void pbaction_tecfri_state::pbaction_tecfri_sub_io_map(address_map &map)
+{
+ map.global_mask(0xff);
+ map(0x00, 0x03).rw(m_ctc2, FUNC(z80ctc_device::read), FUNC(z80ctc_device::write));
+}
+
+void pbaction_tecfri_state::pbaction_tecfri_main_io_map(address_map &map)
+{
+ map.global_mask(0xff);
+ map(0x00, 0x00).rw(FUNC(pbaction_tecfri_state::subcpu_r), FUNC(pbaction_tecfri_state::subcpu_w));
+}
+
+TIMER_CALLBACK_MEMBER(pbaction_tecfri_state::sub_trigger)
+{
+ m_ctc2->trg1(0);
+ m_ctc2->trg1(1);
+}
+
static INPUT_PORTS_START( pbaction )
PORT_START("P1")
@@ -236,8 +366,6 @@ static INPUT_PORTS_START( pbaction )
PORT_DIPSETTING( 0xc0, DEF_STR( Hardest ) )
INPUT_PORTS_END
-
-
static const gfx_layout charlayout1 =
{
8,8,
@@ -291,6 +419,7 @@ GFXDECODE_END
void pbaction_state::machine_start()
{
+ m_soundcommand_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(pbaction_state::sound_trigger), this));
save_item(NAME(m_nmi_mask));
save_item(NAME(m_scroll));
}
@@ -363,22 +492,52 @@ MACHINE_CONFIG_START(pbaction_state::pbaction)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.25)
MACHINE_CONFIG_END
-MACHINE_CONFIG_START(pbaction_state::pbaction2)
+MACHINE_CONFIG_START(pbaction_state::pbactionx)
pbaction(config);
- m_audiocpu->set_addrmap(AS_PROGRAM, &pbaction_state::pbaction2_sound_map);
- m_audiocpu->irqack_cb().set(FUNC(pbaction_state::sound_irq_clear));
-MACHINE_CONFIG_END
-
-MACHINE_CONFIG_START(pbaction_state::pbactionx)
- pbaction2(config);
MCFG_DEVICE_REPLACE("maincpu", SEGA_315_5128, 4_MHz_XTAL)
MCFG_DEVICE_PROGRAM_MAP(pbaction_map)
MCFG_DEVICE_OPCODES_MAP(decrypted_opcodes_map)
MCFG_SEGACRPT_SET_DECRYPTED_TAG(":decrypted_opcodes")
+
+ m_audiocpu->set_addrmap(AS_PROGRAM, &pbaction_state::pbaction_alt_sound_map);
+ m_audiocpu->irqack_cb().set(FUNC(pbaction_state::sound_irq_clear));
MACHINE_CONFIG_END
+static const z80_daisy_config daisy_chain2[] =
+{
+ { "ctc2" },
+ { nullptr }
+};
+
+void pbaction_tecfri_state::machine_start()
+{
+ pbaction_state::machine_start();
+
+ m_subcommand_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(pbaction_tecfri_state::sub_trigger), this));
+ m_digits.resolve();
+}
+
+MACHINE_CONFIG_START(pbaction_tecfri_state::pbactiont)
+ pbaction(config);
+
+ MCFG_DEVICE_MODIFY("maincpu")
+ MCFG_DEVICE_IO_MAP(pbaction_tecfri_main_io_map)
+
+ Z80(config, m_subcpu, 4_MHz_XTAL);
+ m_subcpu->set_addrmap(AS_PROGRAM, &pbaction_tecfri_state::pbaction_tecfri_sub_map);
+ m_subcpu->set_addrmap(AS_IO, &pbaction_tecfri_state::pbaction_tecfri_sub_io_map);
+ m_subcpu->set_daisy_config(daisy_chain2);
+ MCFG_GENERIC_LATCH_8_ADD("maintosublatch")
+ //MCFG_GENERIC_LATCH_8_ADD("subtomainlatch")
+
+ Z80CTC(config, m_ctc2, 12_MHz_XTAL/4);
+ m_ctc2->intr_callback().set_inputline(m_subcpu, 0);
+
+ m_audiocpu->set_addrmap(AS_PROGRAM, &pbaction_state::pbaction_alt_sound_map);
+ m_audiocpu->irqack_cb().set(FUNC(pbaction_state::sound_irq_clear));
+MACHINE_CONFIG_END
/***************************************************************************
@@ -412,37 +571,7 @@ ROM_START( pbaction )
ROM_LOAD( "b-f7.bin", 0x04000, 0x2000, CRC(af6e9817) SHA1(56f47d25761b3850c49a3a81b5ea35f12bd77b14) )
ROM_END
-
ROM_START( pbaction2 )
- ROM_REGION( 0x10000, "maincpu", 0 )
- ROM_LOAD( "pba16.bin", 0x0000, 0x4000, CRC(4a239ebd) SHA1(74e6da0485ac78093b4f09953fa3accb14bc3e43) )
- ROM_LOAD( "pba15.bin", 0x4000, 0x4000, CRC(3afef03a) SHA1(dec714415d2fd00c9021171a48f6c94b40888ae8) )
- ROM_LOAD( "pba14.bin", 0x8000, 0x2000, CRC(c0a98c8a) SHA1(442f37af31db13fd98602dd7f9eeae5529da0f44) )
-
- ROM_REGION( 0x10000, "audiocpu", 0 ) /* 64k for sound board */
- ROM_LOAD( "pba1.bin", 0x0000, 0x2000, CRC(8b69b933) SHA1(eb0762579d52ed9f5b1a002ffe7e517c59650e22) )
-
- ROM_REGION( 0x10000, "cpu2", 0 ) /* 64k for a third Z80 (not emulated) */
- ROM_LOAD( "pba17.bin", 0x0000, 0x4000, CRC(2734ae60) SHA1(4edcdfac1611c49c4f890609efbe8352b8161f8e) )
-
- ROM_REGION( 0x06000, "fgchars", 0 )
- ROM_LOAD( "a-s6.bin", 0x00000, 0x2000, CRC(9a74a8e1) SHA1(bd27439b91f41db3fd7eedb44e828d61b793bda0) )
- ROM_LOAD( "a-s7.bin", 0x02000, 0x2000, CRC(5ca6ad3c) SHA1(7c8eff087f18cc2ff0572ea45e681a3a1ec94fad) )
- ROM_LOAD( "a-s8.bin", 0x04000, 0x2000, CRC(9f00b757) SHA1(74b6d926b8f456c8d0101f0232c5d3662423b396) )
-
- ROM_REGION( 0x10000, "bgchars", 0 )
- ROM_LOAD( "a-j5.bin", 0x00000, 0x4000, CRC(21efe866) SHA1(0c0a05a26d793ba98b0f421d464ff4b1d301ff9e) )
- ROM_LOAD( "a-j6.bin", 0x04000, 0x4000, CRC(7f984c80) SHA1(18795ecbcd2da94f1cfcce5559d652388d1b8bc0) )
- ROM_LOAD( "a-j7.bin", 0x08000, 0x4000, CRC(df69e51b) SHA1(52ab15c63332f0fa98884fa9adc8d35b93c939c4) )
- ROM_LOAD( "a-j8.bin", 0x0c000, 0x4000, CRC(0094cb8b) SHA1(58f48d24903b797e8451bf231f9e8df621685d9f) )
-
- ROM_REGION( 0x06000, "sprites", 0 )
- ROM_LOAD( "b-c7.bin", 0x00000, 0x2000, CRC(d1795ef5) SHA1(69ad8e419e340d2f548468ed7838102789b978da) )
- ROM_LOAD( "b-d7.bin", 0x02000, 0x2000, CRC(f28df203) SHA1(060f70ed6386c808303a488c97691257681bd8f3) )
- ROM_LOAD( "b-f7.bin", 0x04000, 0x2000, CRC(af6e9817) SHA1(56f47d25761b3850c49a3a81b5ea35f12bd77b14) )
-ROM_END
-
-ROM_START( pbaction3 )
ROM_REGION( 0xc000, "maincpu", 0 )
ROM_LOAD( "14.bin", 0x0000, 0x4000, CRC(f17a62eb) SHA1(8dabfc0ad127c154c0293a65df32d52d57dd9755) )
ROM_LOAD( "12.bin", 0x4000, 0x4000, CRC(ec3c64c6) SHA1(6130b80606d717f95e219316c2d3fa0a1980ea1d) )
@@ -468,7 +597,7 @@ ROM_START( pbaction3 )
ROM_LOAD( "b-f7.bin", 0x04000, 0x2000, CRC(af6e9817) SHA1(56f47d25761b3850c49a3a81b5ea35f12bd77b14) )
ROM_END
-ROM_START( pbaction4 )
+ROM_START( pbaction3 )
ROM_REGION( 0xc000, "maincpu", 0 )
ROM_LOAD( "pinball_09.bin", 0x0000, 0x4000, CRC(c8e81ece) SHA1(04eafbd79263225f6c6fb5f04951b54179144f17) )
ROM_IGNORE(0x4000)
@@ -498,7 +627,7 @@ ROM_START( pbaction4 )
ROM_LOAD( "pinball_12.bin", 0x04000, 0x2000, CRC(af6e9817) SHA1(56f47d25761b3850c49a3a81b5ea35f12bd77b14) )
ROM_END
-ROM_START( pbaction5 )
+ROM_START( pbaction4 )
ROM_REGION( 0xc000, "maincpu", 0 )
ROM_LOAD( "p16.bin", 0x0000, 0x4000, CRC(ad20b360) SHA1(91e3cdceb1c170580d926b2ed8359c3100f71b11) )
ROM_LOAD( "c15.bin", 0x4000, 0x4000, CRC(057acfe3) SHA1(49c184d7caea0c0e9f0d0e163f2ef42bb9aebf16) )
@@ -524,7 +653,37 @@ ROM_START( pbaction5 )
ROM_LOAD( "p13.bin", 0x04000, 0x2000, CRC(af6e9817) SHA1(56f47d25761b3850c49a3a81b5ea35f12bd77b14) )
ROM_END
-READ8_MEMBER(pbaction_state::pbactio3_prot_kludge_r)
+// PCB has Tehkan logo (6001-1A/1B) and also "Fabricado por Tecfri S.A. Made in Spain"
+ROM_START( pbactiont )
+ ROM_REGION( 0x10000, "maincpu", 0 )
+ ROM_LOAD( "pba16.bin", 0x0000, 0x4000, CRC(4a239ebd) SHA1(74e6da0485ac78093b4f09953fa3accb14bc3e43) )
+ ROM_LOAD( "pba15.bin", 0x4000, 0x4000, CRC(3afef03a) SHA1(dec714415d2fd00c9021171a48f6c94b40888ae8) )
+ ROM_LOAD( "pba14.bin", 0x8000, 0x2000, CRC(c0a98c8a) SHA1(442f37af31db13fd98602dd7f9eeae5529da0f44) )
+
+ ROM_REGION( 0x10000, "audiocpu", 0 ) /* 64k for sound board */
+ ROM_LOAD( "pba1.bin", 0x0000, 0x2000, CRC(8b69b933) SHA1(eb0762579d52ed9f5b1a002ffe7e517c59650e22) )
+
+ ROM_REGION( 0x10000, "subcpu", 0 ) /* 64k for the subboard */
+ ROM_LOAD( "pba17.bin", 0x0000, 0x4000, CRC(2734ae60) SHA1(4edcdfac1611c49c4f890609efbe8352b8161f8e) )
+
+ ROM_REGION( 0x06000, "fgchars", 0 )
+ ROM_LOAD( "a-s6.bin", 0x00000, 0x2000, CRC(9a74a8e1) SHA1(bd27439b91f41db3fd7eedb44e828d61b793bda0) )
+ ROM_LOAD( "a-s7.bin", 0x02000, 0x2000, CRC(5ca6ad3c) SHA1(7c8eff087f18cc2ff0572ea45e681a3a1ec94fad) )
+ ROM_LOAD( "a-s8.bin", 0x04000, 0x2000, CRC(9f00b757) SHA1(74b6d926b8f456c8d0101f0232c5d3662423b396) )
+
+ ROM_REGION( 0x10000, "bgchars", 0 )
+ ROM_LOAD( "a-j5.bin", 0x00000, 0x4000, CRC(21efe866) SHA1(0c0a05a26d793ba98b0f421d464ff4b1d301ff9e) )
+ ROM_LOAD( "a-j6.bin", 0x04000, 0x4000, CRC(7f984c80) SHA1(18795ecbcd2da94f1cfcce5559d652388d1b8bc0) )
+ ROM_LOAD( "a-j7.bin", 0x08000, 0x4000, CRC(df69e51b) SHA1(52ab15c63332f0fa98884fa9adc8d35b93c939c4) )
+ ROM_LOAD( "a-j8.bin", 0x0c000, 0x4000, CRC(0094cb8b) SHA1(58f48d24903b797e8451bf231f9e8df621685d9f) )
+
+ ROM_REGION( 0x06000, "sprites", 0 )
+ ROM_LOAD( "b-c7.bin", 0x00000, 0x2000, CRC(d1795ef5) SHA1(69ad8e419e340d2f548468ed7838102789b978da) )
+ ROM_LOAD( "b-d7.bin", 0x02000, 0x2000, CRC(f28df203) SHA1(060f70ed6386c808303a488c97691257681bd8f3) )
+ ROM_LOAD( "b-f7.bin", 0x04000, 0x2000, CRC(af6e9817) SHA1(56f47d25761b3850c49a3a81b5ea35f12bd77b14) )
+ROM_END
+
+READ8_MEMBER(pbaction_state::pbaction2_prot_kludge_r)
{
/* on startup, the game expect this location to NOT act as RAM */
if (m_maincpu->pc() == 0xab80)
@@ -533,7 +692,7 @@ READ8_MEMBER(pbaction_state::pbactio3_prot_kludge_r)
return m_work_ram[0];
}
-void pbaction_state::init_pbactio3()
+void pbaction_state::init_pbaction2()
{
uint8_t *rom = memregion("maincpu")->base();
@@ -544,13 +703,13 @@ void pbaction_state::init_pbactio3()
}
/* install a protection (?) workaround */
- m_maincpu->space(AS_PROGRAM).install_read_handler(0xc000, 0xc000, read8_delegate(FUNC(pbaction_state::pbactio3_prot_kludge_r),this) );
+ m_maincpu->space(AS_PROGRAM).install_read_handler(0xc000, 0xc000, read8_delegate(FUNC(pbaction_state::pbaction2_prot_kludge_r),this) );
}
// some of these are probably bootlegs
-GAME( 1985, pbaction, 0, pbaction, pbaction, pbaction_state, empty_init, ROT90, "Tehkan", "Pinball Action (set 1)", MACHINE_SUPPORTS_SAVE )
-GAME( 1985, pbaction2, pbaction, pbaction2, pbaction, pbaction_state, empty_init, ROT90, "Tehkan", "Pinball Action (set 2)", MACHINE_SUPPORTS_SAVE )
-GAME( 1985, pbaction3, pbaction, pbactionx, pbaction, pbaction_state, init_pbactio3, ROT90, "Tehkan", "Pinball Action (set 3, encrypted)", MACHINE_SUPPORTS_SAVE )
-GAME( 1985, pbaction4, pbaction, pbactionx, pbaction, pbaction_state, empty_init, ROT90, "Tehkan", "Pinball Action (set 4, encrypted)", MACHINE_SUPPORTS_SAVE )
-GAME( 1985, pbaction5, pbaction, pbactionx, pbaction, pbaction_state, empty_init, ROT90, "Tehkan", "Pinball Action (set 5, encrypted)", MACHINE_SUPPORTS_SAVE )
+GAME( 1985, pbaction, 0, pbaction, pbaction, pbaction_state, empty_init, ROT90, "Tehkan", "Pinball Action (set 1)", MACHINE_SUPPORTS_SAVE ) // possible bootleg due to not being encrypted + different sound map
+GAME( 1985, pbaction2, pbaction, pbactionx, pbaction, pbaction_state, init_pbaction2, ROT90, "Tehkan", "Pinball Action (set 2, encrypted)", MACHINE_SUPPORTS_SAVE ) // likely bootleg due to extra protection on top of usual
+GAME( 1985, pbaction3, pbaction, pbactionx, pbaction, pbaction_state, empty_init, ROT90, "Tehkan", "Pinball Action (set 3, encrypted)", MACHINE_SUPPORTS_SAVE ) // possible bootleg due to oversized ROMs
+GAME( 1985, pbaction4, pbaction, pbactionx, pbaction, pbaction_state, empty_init, ROT90, "Tehkan", "Pinball Action (set 4, encrypted)", MACHINE_SUPPORTS_SAVE ) // original?
+GAMEL(1985, pbactiont, pbaction, pbactiont, pbaction, pbaction_tecfri_state, empty_init, ROT90, "Tehkan (Tecfri license)", "Pinball Action (Tecfri license)", MACHINE_SUPPORTS_SAVE, layout_pbactiont )
diff --git a/src/mame/drivers/pc100.cpp b/src/mame/drivers/pc100.cpp
index 24cf154d520..485ec9b3913 100644
--- a/src/mame/drivers/pc100.cpp
+++ b/src/mame/drivers/pc100.cpp
@@ -339,7 +339,7 @@ WRITE8_MEMBER( pc100_state::pc100_crtc_data_w )
void pc100_state::pc100_io(address_map &map)
{
map.global_mask(0xff);
- map(0x00, 0x03).rw("pic8259", FUNC(pic8259_device::read), FUNC(pic8259_device::write)).umask16(0x00ff); // i8259
+ map(0x00, 0x03).rw(m_pic, FUNC(pic8259_device::read), FUNC(pic8259_device::write)).umask16(0x00ff); // i8259
// AM_RANGE(0x04, 0x07) i8237?
map(0x08, 0x0b).m(m_fdc, FUNC(upd765a_device::map)).umask16(0x00ff); // upd765
map(0x10, 0x17).rw("ppi8255_1", FUNC(i8255_device::read), FUNC(i8255_device::write)).umask16(0x00ff); // i8255 #1
@@ -636,11 +636,11 @@ static void pc100_floppies(device_slot_interface &device)
MACHINE_CONFIG_START(pc100_state::pc100)
/* basic machine hardware */
- MCFG_DEVICE_ADD("maincpu", I8086, MASTER_CLOCK)
- MCFG_DEVICE_PROGRAM_MAP(pc100_map)
- MCFG_DEVICE_IO_MAP(pc100_io)
- MCFG_DEVICE_VBLANK_INT_DRIVER("screen", pc100_state, pc100_vblank_irq)
- MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE("pic8259", pic8259_device, inta_cb)
+ I8086(config, m_maincpu, MASTER_CLOCK);
+ m_maincpu->set_addrmap(AS_PROGRAM, &pc100_state::pc100_map);
+ m_maincpu->set_addrmap(AS_IO, &pc100_state::pc100_io);
+ m_maincpu->set_vblank_int("screen", FUNC(pc100_state::pc100_vblank_irq));
+ m_maincpu->set_irq_acknowledge_callback("pic8259", FUNC(pic8259_device::inta_cb));
MCFG_TIMER_DRIVER_ADD_PERIODIC("600hz", pc100_state, pc100_600hz_irq, attotime::from_hz(MASTER_CLOCK/600))
MCFG_TIMER_DRIVER_ADD_PERIODIC("100hz", pc100_state, pc100_100hz_irq, attotime::from_hz(MASTER_CLOCK/100))
@@ -657,15 +657,15 @@ MACHINE_CONFIG_START(pc100_state::pc100)
ppi2.out_pb_callback().set(FUNC(pc100_state::upper_mask_w));
ppi2.out_pc_callback().set(FUNC(pc100_state::crtc_bank_w));
- MCFG_DEVICE_ADD("pic8259", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE("maincpu", 0))
- MCFG_PIC8259_IN_SP_CB(CONSTANT(0)) // ???
+ PIC8259(config, m_pic, 0);
+ m_pic->out_int_callback().set_inputline(m_maincpu, 0);
+ m_pic->in_sp_callback().set_constant(0); // ???
i8251_device &i8251(I8251(config, "uart8251", 0));
//i8251.txd_handler().set("rs232", FUNC(rs232_port_device::write_txd));
//i8251.dtr_handler().set("rs232", FUNC(rs232_port_device::write_dtr));
//i8251.rts_handler().set("rs232", FUNC(rs232_port_device::write_rts));
- i8251.rxrdy_handler().set("pic8259", FUNC(pic8259_device::ir1_w));
+ i8251.rxrdy_handler().set(m_pic, FUNC(pic8259_device::ir1_w));
UPD765A(config, m_fdc, true, true);
m_fdc->intrq_wr_callback().set(FUNC(pc100_state::irqnmi_w));
diff --git a/src/mame/drivers/pc1512.cpp b/src/mame/drivers/pc1512.cpp
index 1a7140bb8ce..4f034d7a4e1 100644
--- a/src/mame/drivers/pc1512.cpp
+++ b/src/mame/drivers/pc1512.cpp
@@ -1199,16 +1199,16 @@ MACHINE_CONFIG_START(pc1512_state::pc1512)
PIC8259(config, m_pic, 0);
m_pic->out_int_callback().set_inputline(m_maincpu, INPUT_LINE_IRQ0);
- MCFG_DEVICE_ADD(I8253_TAG, PIT8253, 0)
- MCFG_PIT8253_CLK0(28.636363_MHz_XTAL / 24)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(I8259A2_TAG, pic8259_device, ir0_w))
- MCFG_PIT8253_CLK1(28.636363_MHz_XTAL / 24)
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(*this, pc1512_state, pit1_w))
- MCFG_PIT8253_CLK2(28.636363_MHz_XTAL / 24)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, pc1512_state, pit2_w))
+ PIT8253(config, m_pit, 0);
+ m_pit->set_clk<0>(28.636363_MHz_XTAL / 24);
+ m_pit->out_handler<0>().set(m_pic, FUNC(pic8259_device::ir0_w));
+ m_pit->set_clk<1>(28.636363_MHz_XTAL / 24);
+ m_pit->out_handler<1>().set(FUNC(pc1512_state::pit1_w));
+ m_pit->set_clk<2>(28.636363_MHz_XTAL / 24);
+ m_pit->out_handler<2>().set(FUNC(pc1512_state::pit2_w));
MC146818(config, m_rtc, 32.768_kHz_XTAL);
- m_rtc->irq().set(I8259A2_TAG, FUNC(pic8259_device::ir2_w));
+ m_rtc->irq().set(m_pic, FUNC(pic8259_device::ir2_w));
MCFG_PC_FDC_XT_ADD(PC_FDC_XT_TAG)
MCFG_PC_FDC_INTRQ_CALLBACK(WRITELINE(*this, pc1512_state, fdc_int_w))
@@ -1220,7 +1220,7 @@ MACHINE_CONFIG_START(pc1512_state::pc1512)
m_uart->out_tx_callback().set(RS232_TAG, FUNC(rs232_port_device::write_txd));
m_uart->out_dtr_callback().set(RS232_TAG, FUNC(rs232_port_device::write_dtr));
m_uart->out_rts_callback().set(RS232_TAG, FUNC(rs232_port_device::write_rts));
- m_uart->out_int_callback().set(I8259A2_TAG, FUNC(pic8259_device::ir4_w));
+ m_uart->out_int_callback().set(m_pic, FUNC(pic8259_device::ir4_w));
MCFG_DEVICE_ADD(m_centronics, CENTRONICS, centronics_devices, "printer")
MCFG_CENTRONICS_ACK_HANDLER(WRITELINE(*this, pc1512_state, write_centronics_ack))
@@ -1240,12 +1240,12 @@ MACHINE_CONFIG_START(pc1512_state::pc1512)
// ISA8 bus
MCFG_DEVICE_ADD(ISA_BUS_TAG, ISA8, 0)
MCFG_ISA8_CPU(I8086_TAG)
- MCFG_ISA_OUT_IRQ2_CB(WRITELINE(I8259A2_TAG, pic8259_device, ir2_w))
- MCFG_ISA_OUT_IRQ3_CB(WRITELINE(I8259A2_TAG, pic8259_device, ir3_w))
- MCFG_ISA_OUT_IRQ4_CB(WRITELINE(I8259A2_TAG, pic8259_device, ir4_w))
- MCFG_ISA_OUT_IRQ5_CB(WRITELINE(I8259A2_TAG, pic8259_device, ir5_w))
- MCFG_ISA_OUT_IRQ6_CB(WRITELINE(I8259A2_TAG, pic8259_device, ir6_w))
- MCFG_ISA_OUT_IRQ7_CB(WRITELINE(I8259A2_TAG, pic8259_device, ir7_w))
+ MCFG_ISA_OUT_IRQ2_CB(WRITELINE(m_pic, pic8259_device, ir2_w))
+ MCFG_ISA_OUT_IRQ3_CB(WRITELINE(m_pic, pic8259_device, ir3_w))
+ MCFG_ISA_OUT_IRQ4_CB(WRITELINE(m_pic, pic8259_device, ir4_w))
+ MCFG_ISA_OUT_IRQ5_CB(WRITELINE(m_pic, pic8259_device, ir5_w))
+ MCFG_ISA_OUT_IRQ6_CB(WRITELINE(m_pic, pic8259_device, ir6_w))
+ MCFG_ISA_OUT_IRQ7_CB(WRITELINE(m_pic, pic8259_device, ir7_w))
MCFG_ISA_OUT_DRQ1_CB(WRITELINE(I8237A5_TAG, am9517a_device, dreq1_w))
MCFG_ISA_OUT_DRQ2_CB(WRITELINE(I8237A5_TAG, am9517a_device, dreq2_w))
MCFG_ISA_OUT_DRQ3_CB(WRITELINE(I8237A5_TAG, am9517a_device, dreq3_w))
@@ -1330,16 +1330,16 @@ MACHINE_CONFIG_START(pc1640_state::pc1640)
PIC8259(config, m_pic, 0);
m_pic->out_int_callback().set_inputline(m_maincpu, INPUT_LINE_IRQ0);
- MCFG_DEVICE_ADD(I8253_TAG, PIT8253, 0)
- MCFG_PIT8253_CLK0(28.636363_MHz_XTAL / 24)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(I8259A2_TAG, pic8259_device, ir0_w))
- MCFG_PIT8253_CLK1(28.636363_MHz_XTAL / 24)
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(*this, pc1512_base_state, pit1_w))
- MCFG_PIT8253_CLK2(28.636363_MHz_XTAL / 24)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, pc1512_base_state, pit2_w))
+ PIT8253(config, m_pit, 0);
+ m_pit->set_clk<0>(28.636363_MHz_XTAL / 24);
+ m_pit->out_handler<0>().set(m_pic, FUNC(pic8259_device::ir0_w));
+ m_pit->set_clk<1>(28.636363_MHz_XTAL / 24);
+ m_pit->out_handler<1>().set(FUNC(pc1512_base_state::pit1_w));
+ m_pit->set_clk<2>(28.636363_MHz_XTAL / 24);
+ m_pit->out_handler<2>().set(FUNC(pc1512_base_state::pit2_w));
MC146818(config, m_rtc, 32.768_kHz_XTAL);
- m_rtc->irq().set(I8259A2_TAG, FUNC(pic8259_device::ir2_w));
+ m_rtc->irq().set(m_pic, FUNC(pic8259_device::ir2_w));
MCFG_PC_FDC_XT_ADD(PC_FDC_XT_TAG)
MCFG_PC_FDC_INTRQ_CALLBACK(WRITELINE(*this, pc1512_base_state, fdc_int_w))
@@ -1351,7 +1351,7 @@ MACHINE_CONFIG_START(pc1640_state::pc1640)
m_uart->out_tx_callback().set(RS232_TAG, FUNC(rs232_port_device::write_txd));
m_uart->out_dtr_callback().set(RS232_TAG, FUNC(rs232_port_device::write_dtr));
m_uart->out_rts_callback().set(RS232_TAG, FUNC(rs232_port_device::write_rts));
- m_uart->out_int_callback().set(I8259A2_TAG, FUNC(pic8259_device::ir4_w));
+ m_uart->out_int_callback().set(m_pic, FUNC(pic8259_device::ir4_w));
MCFG_DEVICE_ADD(m_centronics, CENTRONICS, centronics_devices, "printer")
MCFG_CENTRONICS_ACK_HANDLER(WRITELINE(*this, pc1512_base_state, write_centronics_ack))
@@ -1371,12 +1371,12 @@ MACHINE_CONFIG_START(pc1640_state::pc1640)
// ISA8 bus
MCFG_DEVICE_ADD(ISA_BUS_TAG, ISA8, 0)
MCFG_ISA8_CPU(I8086_TAG)
- MCFG_ISA_OUT_IRQ2_CB(WRITELINE(I8259A2_TAG, pic8259_device, ir2_w))
- MCFG_ISA_OUT_IRQ3_CB(WRITELINE(I8259A2_TAG, pic8259_device, ir3_w))
- MCFG_ISA_OUT_IRQ4_CB(WRITELINE(I8259A2_TAG, pic8259_device, ir4_w))
- MCFG_ISA_OUT_IRQ5_CB(WRITELINE(I8259A2_TAG, pic8259_device, ir5_w))
- MCFG_ISA_OUT_IRQ6_CB(WRITELINE(I8259A2_TAG, pic8259_device, ir6_w))
- MCFG_ISA_OUT_IRQ7_CB(WRITELINE(I8259A2_TAG, pic8259_device, ir7_w))
+ MCFG_ISA_OUT_IRQ2_CB(WRITELINE(m_pic, pic8259_device, ir2_w))
+ MCFG_ISA_OUT_IRQ3_CB(WRITELINE(m_pic, pic8259_device, ir3_w))
+ MCFG_ISA_OUT_IRQ4_CB(WRITELINE(m_pic, pic8259_device, ir4_w))
+ MCFG_ISA_OUT_IRQ5_CB(WRITELINE(m_pic, pic8259_device, ir5_w))
+ MCFG_ISA_OUT_IRQ6_CB(WRITELINE(m_pic, pic8259_device, ir6_w))
+ MCFG_ISA_OUT_IRQ7_CB(WRITELINE(m_pic, pic8259_device, ir7_w))
MCFG_ISA_OUT_DRQ1_CB(WRITELINE(I8237A5_TAG, am9517a_device, dreq1_w))
MCFG_ISA_OUT_DRQ2_CB(WRITELINE(I8237A5_TAG, am9517a_device, dreq2_w))
MCFG_ISA_OUT_DRQ3_CB(WRITELINE(I8237A5_TAG, am9517a_device, dreq3_w))
diff --git a/src/mame/drivers/pc88va.cpp b/src/mame/drivers/pc88va.cpp
index 6753c89381d..2c2b67d2ca1 100644
--- a/src/mame/drivers/pc88va.cpp
+++ b/src/mame/drivers/pc88va.cpp
@@ -1655,11 +1655,11 @@ MACHINE_CONFIG_START(pc88va_state::pc88va)
FLOPPY_CONNECTOR(config, m_fdd[1], pc88va_floppies, "525hd", pc88va_state::floppy_formats);
MCFG_SOFTWARE_LIST_ADD("disk_list","pc88va")
- MCFG_DEVICE_ADD("pit8253", PIT8253, 0)
- MCFG_PIT8253_CLK0(8000000) /* general purpose timer 1 */
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, pc88va_state, pc88va_pit_out0_changed))
- MCFG_PIT8253_CLK1(8000000) /* BEEP frequency setting */
- MCFG_PIT8253_CLK2(8000000) /* RS232C baud rate setting */
+ pit8253_device &pit8253(PIT8253(config, "pit8253", 0));
+ pit8253.set_clk<0>(8000000); /* general purpose timer 1 */
+ pit8253.out_handler<0>().set(FUNC(pc88va_state::pc88va_pit_out0_changed));
+ pit8253.set_clk<1>(8000000); /* BEEP frequency setting */
+ pit8253.set_clk<2>(8000000); /* RS232C baud rate setting */
ADDRESS_MAP_BANK(config, "sysbank").set_map(&pc88va_state::sysbank_map).set_options(ENDIANNESS_LITTLE, 16, 18+4, 0x40000);
diff --git a/src/mame/drivers/pc9801.cpp b/src/mame/drivers/pc9801.cpp
index 640a0338eed..980d1d596a3 100644
--- a/src/mame/drivers/pc9801.cpp
+++ b/src/mame/drivers/pc9801.cpp
@@ -2485,10 +2485,9 @@ MACHINE_CONFIG_START(pc9801_state::pc9821)
MCFG_DEVICE_IO_MAP(pc9821_io)
MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE("pic8259_master", pic8259_device, inta_cb)
- MCFG_DEVICE_MODIFY("pit8253")
- MCFG_PIT8253_CLK0(MAIN_CLOCK_X2)
- MCFG_PIT8253_CLK1(MAIN_CLOCK_X2)
- MCFG_PIT8253_CLK2(MAIN_CLOCK_X2)
+ m_pit8253->set_clk<0>(MAIN_CLOCK_X2);
+ m_pit8253->set_clk<1>(MAIN_CLOCK_X2);
+ m_pit8253->set_clk<2>(MAIN_CLOCK_X2);
MCFG_MACHINE_START_OVERRIDE(pc9801_state,pc9821)
MCFG_MACHINE_RESET_OVERRIDE(pc9801_state,pc9821)
diff --git a/src/mame/drivers/pcd.cpp b/src/mame/drivers/pcd.cpp
index 9bc1ef95030..3c9104d2504 100644
--- a/src/mame/drivers/pcd.cpp
+++ b/src/mame/drivers/pcd.cpp
@@ -508,13 +508,13 @@ MACHINE_CONFIG_START(pcd_state::pcd)
MCFG_TIMER_DRIVER_ADD_PERIODIC("timer0_tick", pcd_state, timer0_tick, attotime::from_hz(16_MHz_XTAL / 24)) // adjusted to pass post
- MCFG_DEVICE_ADD(m_pic1, PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(WRITELINE("maincpu", i80186_cpu_device, int0_w))
+ PIC8259(config, m_pic1, 0);
+ m_pic1->out_int_callback().set(m_maincpu, FUNC(i80186_cpu_device::int0_w));
- MCFG_DEVICE_ADD(m_pic2, PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(WRITELINE("maincpu", i80186_cpu_device, int1_w))
+ PIC8259(config, m_pic2, 0);
+ m_pic2->out_int_callback().set(m_maincpu, FUNC(i80186_cpu_device::int1_w));
- MCFG_DEVICE_ADD("video", PCD_VIDEO, 0)
+ PCD_VIDEO(config, "video", 0);
RAM(config, RAM_TAG).set_default_size("1M");
diff --git a/src/mame/drivers/peoplepc.cpp b/src/mame/drivers/peoplepc.cpp
index 100d6df6b3b..d869d2add7d 100644
--- a/src/mame/drivers/peoplepc.cpp
+++ b/src/mame/drivers/peoplepc.cpp
@@ -244,29 +244,29 @@ DEVICE_INPUT_DEFAULTS_END
MACHINE_CONFIG_START(peoplepc_state::olypeopl)
/* basic machine hardware */
- MCFG_DEVICE_ADD("maincpu", I8086, XTAL(14'745'600)/3)
- MCFG_DEVICE_PROGRAM_MAP(peoplepc_map)
- MCFG_DEVICE_IO_MAP(peoplepc_io)
- MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE("pic8259_0", pic8259_device, inta_cb)
-
- MCFG_DEVICE_ADD("pit8253", PIT8253, 0)
- MCFG_PIT8253_CLK0(XTAL(14'745'600)/6)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, peoplepc_state, kbd_clock_tick_w))
- MCFG_PIT8253_CLK1(XTAL(14'745'600)/6)
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(*this, peoplepc_state, tty_clock_tick_w))
- MCFG_PIT8253_CLK2(XTAL(14'745'600)/6)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE("pic8259_0", pic8259_device, ir0_w))
-
- MCFG_DEVICE_ADD("pic8259_0", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE("maincpu", 0))
- MCFG_PIC8259_IN_SP_CB(CONSTANT(1))
- MCFG_PIC8259_CASCADE_ACK_CB(READ8(*this, peoplepc_state, get_slave_ack))
-
- MCFG_DEVICE_ADD("pic8259_1", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(WRITELINE("pic8259_0", pic8259_device, ir7_w))
- MCFG_PIC8259_IN_SP_CB(CONSTANT(0))
-
- MCFG_DEVICE_ADD("ppi8255", I8255, 0)
+ I8086(config, m_maincpu, XTAL(14'745'600)/3);
+ m_maincpu->set_addrmap(AS_PROGRAM, &peoplepc_state::peoplepc_map);
+ m_maincpu->set_addrmap(AS_IO, &peoplepc_state::peoplepc_io);
+ m_maincpu->set_irq_acknowledge_callback("pic8259_0", FUNC(pic8259_device::inta_cb));
+
+ pit8253_device &pit8253(PIT8253(config, "pit8253", 0));
+ pit8253.set_clk<0>(XTAL(14'745'600)/6);
+ pit8253.out_handler<0>().set(FUNC(peoplepc_state::kbd_clock_tick_w));
+ pit8253.set_clk<1>(XTAL(14'745'600)/6);
+ pit8253.out_handler<1>().set(FUNC(peoplepc_state::tty_clock_tick_w));
+ pit8253.set_clk<2>(XTAL(14'745'600)/6);
+ pit8253.out_handler<2>().set("pic8259_0", FUNC(pic8259_device::ir0_w));
+
+ pic8259_device &pic8259_0(PIC8259(config, "pic8259_0", 0));
+ pic8259_0.out_int_callback().set_inputline(m_maincpu, 0);
+ pic8259_0.in_sp_callback().set_constant(1);
+ pic8259_0.read_slave_ack_callback().set(FUNC(peoplepc_state::get_slave_ack));
+
+ PIC8259(config, m_pic_1, 0);
+ m_pic_1->out_int_callback().set("pic8259_0", FUNC(pic8259_device::ir7_w));
+ m_pic_1->in_sp_callback().set_constant(0);
+
+ I8255(config, "ppi8255");
MCFG_SCREEN_ADD_MONOCHROME("screen", RASTER, rgb_t::green())
MCFG_SCREEN_RAW_PARAMS(XTAL(22'000'000),640,0,640,475,0,475)
diff --git a/src/mame/drivers/pg685.cpp b/src/mame/drivers/pg685.cpp
index 177fadb2ca4..ce2c1294daa 100644
--- a/src/mame/drivers/pg685.cpp
+++ b/src/mame/drivers/pg685.cpp
@@ -185,7 +185,7 @@ void pg685_state::pg685_mem(address_map &map)
{
map.unmap_value_high();
pg675_mem(map);
- map(0xf9f34, 0xf9f37).rw("bppit", FUNC(pit8253_device::read), FUNC(pit8253_device::write));
+ map(0xf9f34, 0xf9f37).rw(m_bppit, FUNC(pit8253_device::read), FUNC(pit8253_device::write));
map(0xf9f38, 0xf9f3b).rw("bpuart", FUNC(mc2661_device::read), FUNC(mc2661_device::write));
map(0xf9f3c, 0xf9f3d).rw("bppic", FUNC(pic8259_device::read), FUNC(pic8259_device::write));
map(0xf9f3e, 0xf9f3e).w(FUNC(pg685_state::f9f3e_w));
@@ -211,7 +211,7 @@ void pg685_state::pg685oua12_mem(address_map &map)
map(0xf9f30, 0xf9f31).rw("moduart", FUNC(i8251_device::read), FUNC(i8251_device::write));
map(0xf9f32, 0xf9f32).w(FUNC(pg685_state::f9f32_w));
map(0xf9f33, 0xf9f33).r(FUNC(pg685_state::f9f33_r));
- map(0xf9f34, 0xf9f37).rw("bppit", FUNC(pit8253_device::read), FUNC(pit8253_device::write));
+ map(0xf9f34, 0xf9f37).rw(m_bppit, FUNC(pit8253_device::read), FUNC(pit8253_device::write));
map(0xf9f38, 0xf9f3b).rw("bpuart", FUNC(mc2661_device::read), FUNC(mc2661_device::write));
map(0xf9f3c, 0xf9f3d).rw("bppic", FUNC(pic8259_device::read), FUNC(pic8259_device::write));
map(0xf9f3e, 0xf9f3e).w(FUNC(pg685_state::f9f3e_w));
@@ -395,30 +395,31 @@ MC6845_UPDATE_ROW( pg685_state::crtc_update_row_oua12 )
// MACHINE DRIVERS
//**************************************************************************
-MACHINE_CONFIG_START(pg685_state::pg685_backplane)
- MCFG_DEVICE_ADD("bppit", PIT8253, 0)
- MCFG_PIT8253_CLK0(XTAL(12'288'000) / 10) // same input clock as for PC16-11?
- MCFG_PIT8253_CLK1(XTAL(12'288'000) / 10)
- MCFG_PIT8253_CLK2(XTAL(12'288'000) / 10)
+void pg685_state::pg685_backplane(machine_config &config)
+{
+ PIT8253(config, m_bppit, 0);
+ m_bppit->set_clk<0>(XTAL(12'288'000) / 10); // same input clock as for PC16-11?
+ m_bppit->set_clk<1>(XTAL(12'288'000) / 10);
+ m_bppit->set_clk<2>(XTAL(12'288'000) / 10);
- MCFG_DEVICE_ADD("bppic", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(NOOP) // configured in single 8086 mode?
+ pic8259_device &bppic(PIC8259(config, "bppic", 0));
+ bppic.out_int_callback().set_nop(); // configured in single 8086 mode?
- MCFG_DEVICE_ADD("bpuart", MC2661, 4915200)
-MACHINE_CONFIG_END
+ MC2661(config, "bpuart", 4915200);
+}
-MACHINE_CONFIG_START(pg685_state::pg685_module)
+void pg685_state::pg685_module(machine_config &config)
+{
FD1797(config, m_fdc, XTAL(4'000'000) / 2); // divider guessed
m_fdc->intrq_wr_callback().set("mainpic", FUNC(pic8259_device::ir4_w));
- MCFG_DEVICE_ADD("modppi1", I8255, 0)
- MCFG_DEVICE_ADD("modppi2", I8255, 0)
+ I8255(config, "modppi1", 0);
+ I8255(config, "modppi2", 0);
- MCFG_DEVICE_ADD("moduart", I8251, XTAL(4'000'000) / 2) // divider guessed
+ I8251(config, "moduart", XTAL(4'000'000) / 2); // divider guessed
- MCFG_DEVICE_ADD("rtc", MM58167, XTAL(32'768))
-
-MACHINE_CONFIG_END
+ MM58167(config, "rtc", XTAL(32'768));
+}
MACHINE_CONFIG_START(pg685_state::pg675)
// main cpu
@@ -426,9 +427,9 @@ MACHINE_CONFIG_START(pg685_state::pg675)
MCFG_DEVICE_PROGRAM_MAP(pg675_mem)
MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE("mainpic", pic8259_device, inta_cb)
- MCFG_DEVICE_ADD("mainpic", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE("maincpu", 0))
- MCFG_PIC8259_IN_SP_CB(CONSTANT(1))
+ pic8259_device &mainpic(PIC8259(config, "mainpic", 0));
+ mainpic.out_int_callback().set_inputline(m_maincpu, 0);
+ mainpic.in_sp_callback().set_constant(1);
// i/o cpu
@@ -475,9 +476,9 @@ MACHINE_CONFIG_START(pg685_state::pg685)
MCFG_DEVICE_PROGRAM_MAP(pg685_mem)
MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE("mainpic", pic8259_device, inta_cb)
- MCFG_DEVICE_ADD("mainpic", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE("maincpu", 0))
- MCFG_PIC8259_IN_SP_CB(CONSTANT(1))
+ pic8259_device &mainpic(PIC8259(config, "mainpic", 0));
+ mainpic.out_int_callback().set_inputline(m_maincpu, 0);
+ mainpic.in_sp_callback().set_constant(1);
// i/o cpu
@@ -526,9 +527,9 @@ MACHINE_CONFIG_START(pg685_state::pg685oua12)
MCFG_DEVICE_PROGRAM_MAP(pg685oua12_mem)
MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE("mainpic", pic8259_device, inta_cb)
- MCFG_DEVICE_ADD("mainpic", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE("maincpu", 0))
- MCFG_PIC8259_IN_SP_CB(CONSTANT(1))
+ pic8259_device &mainpic(PIC8259(config, "mainpic", 0));
+ mainpic.out_int_callback().set_inputline(m_maincpu, 0);
+ mainpic.in_sp_callback().set_constant(1);
// i/o cpu
diff --git a/src/mame/drivers/pk8020.cpp b/src/mame/drivers/pk8020.cpp
index df4816d16db..4e36c2ba67b 100644
--- a/src/mame/drivers/pk8020.cpp
+++ b/src/mame/drivers/pk8020.cpp
@@ -222,21 +222,21 @@ MACHINE_CONFIG_START(pk8020_state::pk8020)
I8255(config, m_ppi8255_3);
- MCFG_DEVICE_ADD("pit8253", PIT8253, 0)
- MCFG_PIT8253_CLK0(20_MHz_XTAL / 10)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, pk8020_state,pk8020_pit_out0))
- MCFG_PIT8253_CLK1(20_MHz_XTAL / 10)
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(*this, pk8020_state,pk8020_pit_out1))
- MCFG_PIT8253_CLK2((20_MHz_XTAL / 8) / 164)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE("pic8259", pic8259_device, ir5_w))
+ PIT8253(config, m_pit8253, 0);
+ m_pit8253->set_clk<0>(20_MHz_XTAL / 10);
+ m_pit8253->out_handler<0>().set(FUNC(pk8020_state::pk8020_pit_out0));
+ m_pit8253->set_clk<1>(20_MHz_XTAL / 10);
+ m_pit8253->out_handler<1>().set(FUNC(pk8020_state::pk8020_pit_out1));
+ m_pit8253->set_clk<2>((20_MHz_XTAL / 8) / 164);
+ m_pit8253->out_handler<2>().set(m_pic8259, FUNC(pic8259_device::ir5_w));
- MCFG_DEVICE_ADD("pic8259", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE("maincpu", 0))
+ PIC8259(config, m_pic8259, 0);
+ m_pic8259->out_int_callback().set_inputline(m_maincpu, 0);
I8251(config, m_rs232, 0);
m_rs232->txd_handler().set("rs232", FUNC(rs232_port_device::write_txd));
- m_rs232->rxrdy_handler().set("pic8259", FUNC(pic8259_device::ir1_w));
- m_rs232->txrdy_handler().set("pic8259", FUNC(pic8259_device::ir2_w));
+ m_rs232->rxrdy_handler().set(m_pic8259, FUNC(pic8259_device::ir1_w));
+ m_rs232->txrdy_handler().set(m_pic8259, FUNC(pic8259_device::ir2_w));
rs232_port_device &rs232(RS232_PORT(config, "rs232", default_rs232_devices, nullptr));
rs232.rxd_handler().set(m_rs232, FUNC(i8251_device::write_rxd));
diff --git a/src/mame/drivers/poisk1.cpp b/src/mame/drivers/poisk1.cpp
index 9b2894fad13..41d0b79c702 100644
--- a/src/mame/drivers/poisk1.cpp
+++ b/src/mame/drivers/poisk1.cpp
@@ -647,24 +647,24 @@ INPUT_PORTS_END
MACHINE_CONFIG_START(p1_state::poisk1)
/* basic machine hardware */
- MCFG_DEVICE_ADD("maincpu", I8088, 5000000)
- MCFG_DEVICE_PROGRAM_MAP(poisk1_map)
- MCFG_DEVICE_IO_MAP(poisk1_io)
- MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE("pic8259", pic8259_device, inta_cb)
+ I8088(config, m_maincpu, 5000000);
+ m_maincpu->set_addrmap(AS_PROGRAM, &p1_state::poisk1_map);
+ m_maincpu->set_addrmap(AS_IO, &p1_state::poisk1_io);
+ m_maincpu->set_irq_acknowledge_callback("pic8259", FUNC(pic8259_device::inta_cb));
MCFG_MACHINE_START_OVERRIDE( p1_state, poisk1 )
MCFG_MACHINE_RESET_OVERRIDE( p1_state, poisk1 )
- MCFG_DEVICE_ADD( "pit8253", PIT8253 ,0)
- MCFG_PIT8253_CLK0(XTAL(15'000'000)/12) /* heartbeat IRQ */
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE("pic8259", pic8259_device, ir0_w))
- MCFG_PIT8253_CLK1(XTAL(15'000'000)/12) /* keyboard poll -- XXX edge or level triggered? */
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE("pic8259", pic8259_device, ir6_w))
- MCFG_PIT8253_CLK2(XTAL(15'000'000)/12) /* pio port c pin 4, and speaker polling enough */
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, p1_state, p1_pit8253_out2_changed))
+ PIT8253(config, m_pit8253, 0);
+ m_pit8253->set_clk<0>(XTAL(15'000'000)/12); /* heartbeat IRQ */
+ m_pit8253->out_handler<0>().set(m_pic8259, FUNC(pic8259_device::ir0_w));
+ m_pit8253->set_clk<1>(XTAL(15'000'000)/12); /* keyboard poll -- XXX edge or level triggered? */
+ m_pit8253->out_handler<1>().set(m_pic8259, FUNC(pic8259_device::ir6_w));
+ m_pit8253->set_clk<2>(XTAL(15'000'000)/12); /* pio port c pin 4, and speaker polling enough */
+ m_pit8253->out_handler<2>().set(FUNC(p1_state::p1_pit8253_out2_changed));
- MCFG_DEVICE_ADD("pic8259", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE("maincpu", 0))
+ PIC8259(config, m_pic8259, 0);
+ m_pic8259->out_int_callback().set_inputline(m_maincpu, 0);
I8255A(config, m_ppi8255n1);
m_ppi8255n1->in_pa_callback().set(FUNC(p1_state::p1_ppi_porta_r)); /*60H*/
@@ -680,11 +680,11 @@ MACHINE_CONFIG_START(p1_state::poisk1)
MCFG_DEVICE_ADD("isa", ISA8, 0)
MCFG_ISA8_CPU("maincpu")
- MCFG_ISA_OUT_IRQ2_CB(WRITELINE("pic8259", pic8259_device, ir2_w))
- MCFG_ISA_OUT_IRQ3_CB(WRITELINE("pic8259", pic8259_device, ir3_w))
- MCFG_ISA_OUT_IRQ4_CB(WRITELINE("pic8259", pic8259_device, ir4_w))
- MCFG_ISA_OUT_IRQ5_CB(WRITELINE("pic8259", pic8259_device, ir5_w))
- MCFG_ISA_OUT_IRQ7_CB(WRITELINE("pic8259", pic8259_device, ir7_w))
+ MCFG_ISA_OUT_IRQ2_CB(WRITELINE(m_pic8259, pic8259_device, ir2_w))
+ MCFG_ISA_OUT_IRQ3_CB(WRITELINE(m_pic8259, pic8259_device, ir3_w))
+ MCFG_ISA_OUT_IRQ4_CB(WRITELINE(m_pic8259, pic8259_device, ir4_w))
+ MCFG_ISA_OUT_IRQ5_CB(WRITELINE(m_pic8259, pic8259_device, ir5_w))
+ MCFG_ISA_OUT_IRQ7_CB(WRITELINE(m_pic8259, pic8259_device, ir7_w))
MCFG_DEVICE_ADD("isa1", ISA8_SLOT, 0, "isa", p1_isa8_cards, "fdc", false) // FIXME: determine ISA bus clock
MCFG_DEVICE_ADD("isa2", ISA8_SLOT, 0, "isa", p1_isa8_cards, nullptr, false)
MCFG_DEVICE_ADD("isa3", ISA8_SLOT, 0, "isa", p1_isa8_cards, nullptr, false)
diff --git a/src/mame/drivers/pp01.cpp b/src/mame/drivers/pp01.cpp
index 3263cf7f740..e1fa74061ff 100644
--- a/src/mame/drivers/pp01.cpp
+++ b/src/mame/drivers/pp01.cpp
@@ -226,13 +226,13 @@ MACHINE_CONFIG_START(pp01_state::pp01)
MCFG_DEVICE_ADD("uart", I8251, 0)
// when rts and dtr are both high, the uart is being used for cassette operations
- MCFG_DEVICE_ADD("pit8253", PIT8253, 0)
- MCFG_PIT8253_CLK0(0)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, pp01_state,pp01_pit_out0))
- MCFG_PIT8253_CLK1(2000000)
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(*this, pp01_state,pp01_pit_out1))
- MCFG_PIT8253_CLK2(2000000)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE("pit8253", pit8253_device, write_clk0))
+ PIT8253(config, m_pit, 0);
+ m_pit->set_clk<0>(0);
+ m_pit->out_handler<0>().set(FUNC(pp01_state::pp01_pit_out0));
+ m_pit->set_clk<1>(2000000);
+ m_pit->out_handler<1>().set(FUNC(pp01_state::pp01_pit_out1));
+ m_pit->set_clk<2>(2000000);
+ m_pit->out_handler<2>().set(m_pit, FUNC(pit8253_device::write_clk0));
i8255_device &ppi(I8255A(config, "ppi8255"));
ppi.in_pa_callback().set(FUNC(pp01_state::pp01_8255_porta_r));
diff --git a/src/mame/drivers/prehisle.cpp b/src/mame/drivers/prehisle.cpp
index a19243527f2..70a19165cef 100644
--- a/src/mame/drivers/prehisle.cpp
+++ b/src/mame/drivers/prehisle.cpp
@@ -304,7 +304,7 @@ ROM_START( prehislek )
ROM_LOAD( "gt1.1", 0x000000, 0x10000, CRC(80a4c093) SHA1(abe59e43259eb80b504bd5541f58cd0e5eb998ab) )
ROM_REGION( 0x008000, "chars", 0 )
- ROM_LOAD( "gt15.b15", 0x000000, 0x08000, BAD_DUMP CRC(ac652412) SHA1(916c04c3a8a7bfb961313ab73c0a27d7f5e48de1) ) // not dumped, missing korean text
+ ROM_LOAD( "gt15k.b15", 0x000000, 0x08000, CRC(4cad1451) SHA1(5c81240e94f5a38af874b2ec7c65cb0f55d2ba8c) )
ROM_REGION( 0x040000, "bgtiles", 0 )
ROM_LOAD( "pi8914.b14", 0x000000, 0x40000, CRC(207d6187) SHA1(505dfd1424b894e7b898f91b89f021ddde433c48) )
diff --git a/src/mame/drivers/prophet600.cpp b/src/mame/drivers/prophet600.cpp
index 6c67d59fca7..d4b8201f856 100644
--- a/src/mame/drivers/prophet600.cpp
+++ b/src/mame/drivers/prophet600.cpp
@@ -278,12 +278,12 @@ MACHINE_CONFIG_START(prophet600_state::prophet600)
config.set_default_layout(layout_prophet600);
- MCFG_DEVICE_ADD(PIT_TAG, PIT8253, XTAL(8'000'000)/4)
- MCFG_PIT8253_CLK0(XTAL(8'000'000)/4)
- MCFG_PIT8253_CLK1(XTAL(8'000'000)/4)
- MCFG_PIT8253_CLK2(XTAL(8'000'000)/4)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, prophet600_state, pit_ch0_tick_w))
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, prophet600_state, pit_ch2_tick_w))
+ pit8253_device &pit8253(PIT8253(config, PIT_TAG, XTAL(8'000'000)/4));
+ pit8253.set_clk<0>(XTAL(8'000'000)/4);
+ pit8253.set_clk<1>(XTAL(8'000'000)/4);
+ pit8253.set_clk<2>(XTAL(8'000'000)/4);
+ pit8253.out_handler<0>().set(FUNC(prophet600_state::pit_ch0_tick_w));
+ pit8253.out_handler<2>().set(FUNC(prophet600_state::pit_ch2_tick_w));
ACIA6850(config, m_acia, 0);
m_acia->txd_handler().set("mdout", FUNC(midi_port_device::write_txd));
diff --git a/src/mame/drivers/pwrview.cpp b/src/mame/drivers/pwrview.cpp
index 4a8cb3ebe54..25d2b355d06 100644
--- a/src/mame/drivers/pwrview.cpp
+++ b/src/mame/drivers/pwrview.cpp
@@ -413,10 +413,10 @@ MACHINE_CONFIG_START(pwrview_state::pwrview)
MCFG_SCREEN_RAW_PARAMS(XTAL(64'000'000)/8, 480, 0, 384, 1040, 0, 960) // clock unknown
MCFG_SCREEN_UPDATE_DEVICE("crtc", hd6845_device, screen_update)
- MCFG_DEVICE_ADD("pit", PIT8253, 0)
- MCFG_PIT8253_CLK0(XTAL(16'000'000)/16) // clocks unknown, fix above when found
- MCFG_PIT8253_CLK1(XTAL(16'000'000)/16)
- MCFG_PIT8253_CLK2(XTAL(16'000'000)/16)
+ PIT8253(config, m_pit, 0);
+ m_pit->set_clk<0>(XTAL(16'000'000)/16); // clocks unknown, fix above when found
+ m_pit->set_clk<1>(XTAL(16'000'000)/16);
+ m_pit->set_clk<2>(XTAL(16'000'000)/16);
// floppy disk controller
UPD765A(config, "fdc", true, true); // Rockwell R7675P
@@ -425,7 +425,7 @@ MACHINE_CONFIG_START(pwrview_state::pwrview)
MCFG_FLOPPY_DRIVE_ADD("fdc:0", pwrview_floppies, "525dd", floppy_image_device::default_floppy_formats)
MCFG_FLOPPY_DRIVE_ADD("fdc:1", pwrview_floppies, "525dd", floppy_image_device::default_floppy_formats)
- MCFG_DEVICE_ADD("uart", I8251, 0)
+ I8251(config, "uart", 0);
Z80SIO2(config, "sio", 4000000);
diff --git a/src/mame/drivers/ql.cpp b/src/mame/drivers/ql.cpp
index 34df45d79e5..23d168c30fe 100644
--- a/src/mame/drivers/ql.cpp
+++ b/src/mame/drivers/ql.cpp
@@ -900,7 +900,7 @@ void ql_state::machine_reset()
MACHINE_CONFIG_START(ql_state::ql)
// basic machine hardware
- MCFG_DEVICE_ADD(M68008_TAG, M68008, X1/2)
+ MCFG_DEVICE_ADD(m_maincpu, M68008, X1/2)
MCFG_DEVICE_PROGRAM_MAP(ql_mem)
MCFG_DEVICE_ADD(I8749_TAG, I8749, X4)
@@ -925,27 +925,26 @@ MACHINE_CONFIG_START(ql_state::ql)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.25)
// devices
- MCFG_DEVICE_ADD(ZX8301_TAG, ZX8301, X1, M68008_TAG)
- MCFG_ZX8301_VSYNC_CALLBACK(WRITELINE(ZX8302_TAG, zx8302_device, vsync_w))
-
- MCFG_VIDEO_SET_SCREEN(SCREEN_TAG)
-
- MCFG_DEVICE_ADD(ZX8302_TAG, ZX8302, X1)
- MCFG_ZX8302_RTC_CLOCK(X2)
- MCFG_ZX8302_OUT_IPL1L_CB(INPUTLINE(M68008_TAG, M68K_IRQ_2))
- MCFG_ZX8302_OUT_BAUDX4_CB(WRITELINE(*this, ql_state, ql_baudx4_w))
- MCFG_ZX8302_OUT_COMDATA_CB(WRITELINE(*this, ql_state, ql_comdata_w))
+ ZX8301(config, m_zx8301, X1, m_maincpu);
+ m_zx8301->vsync_wr_callback().set(m_zx8302, FUNC(zx8302_device::vsync_w));
+ m_zx8301->set_screen(SCREEN_TAG);
+
+ ZX8302(config, m_zx8302, X1);
+ m_zx8302->set_rtc_clock(X2);
+ m_zx8302->out_ipl1l_callback().set_inputline(m_maincpu, M68K_IRQ_2);
+ m_zx8302->out_baudx4_callback().set(FUNC(ql_state::ql_baudx4_w));
+ m_zx8302->out_comdata_callback().set(FUNC(ql_state::ql_comdata_w));
// TXD1
- MCFG_ZX8302_OUT_TXD2_CB(WRITELINE(RS232_B_TAG, rs232_port_device, write_txd))
+ m_zx8302->out_txd2_callback().set(RS232_B_TAG, FUNC(rs232_port_device::write_txd));
// NETOUT
- MCFG_ZX8302_OUT_MDSELCK_CB(WRITELINE(*this, ql_state, zx8302_mdselck_w))
- MCFG_ZX8302_OUT_MDSELD_CB(WRITELINE(MDV_1, microdrive_image_device, comms_in_w))
- MCFG_ZX8302_OUT_MDRDW_CB(WRITELINE(*this, ql_state, zx8302_mdrdw_w))
- MCFG_ZX8302_OUT_ERASE_CB(WRITELINE(*this, ql_state, zx8302_erase_w))
- MCFG_ZX8302_OUT_RAW1_CB(WRITELINE(*this, ql_state, zx8302_raw1_w))
- MCFG_ZX8302_IN_RAW1_CB(READLINE(*this, ql_state, zx8302_raw1_r))
- MCFG_ZX8302_OUT_RAW2_CB(WRITELINE(*this, ql_state, zx8302_raw2_w))
- MCFG_ZX8302_IN_RAW2_CB(READLINE(*this, ql_state, zx8302_raw2_r))
+ m_zx8302->out_mdselck_callback().set(FUNC(ql_state::zx8302_mdselck_w));
+ m_zx8302->out_mdseld_callback().set(m_mdv1, FUNC(microdrive_image_device::comms_in_w));
+ m_zx8302->out_mdrdw_callback().set(FUNC(ql_state::zx8302_mdrdw_w));
+ m_zx8302->out_erase_callback().set(FUNC(ql_state::zx8302_erase_w));
+ m_zx8302->out_raw1_callback().set(FUNC(ql_state::zx8302_raw1_w));
+ m_zx8302->in_raw1_callback().set(FUNC(ql_state::zx8302_raw1_r));
+ m_zx8302->out_raw2_callback().set(FUNC(ql_state::zx8302_raw2_w));
+ m_zx8302->in_raw2_callback().set(FUNC(ql_state::zx8302_raw2_r));
MCFG_MICRODRIVE_ADD(MDV_1)
MCFG_MICRODRIVE_COMMS_OUT_CALLBACK(WRITELINE(MDV_2, microdrive_image_device, comms_in_w))
diff --git a/src/mame/drivers/rc759.cpp b/src/mame/drivers/rc759.cpp
index 33a1c85d5a1..d188eb3fd24 100644
--- a/src/mame/drivers/rc759.cpp
+++ b/src/mame/drivers/rc759.cpp
@@ -540,8 +540,8 @@ MACHINE_CONFIG_START(rc759_state::rc759)
MCFG_80186_TMROUT1_HANDLER(WRITELINE(*this, rc759_state, i186_timer1_w))
// interrupt controller
- MCFG_DEVICE_ADD("pic", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(WRITELINE("maincpu", i80186_cpu_device, int0_w))
+ PIC8259(config, m_pic, 0);
+ m_pic->out_int_callback().set(m_maincpu, FUNC(i80186_cpu_device::int0_w));
// nvram
NVRAM(config, "nvram").set_custom_handler(FUNC(rc759_state::nvram_init));
@@ -554,7 +554,7 @@ MACHINE_CONFIG_START(rc759_state::rc759)
// rtc
MCFG_DEVICE_ADD("rtc", MM58167, 32.768_kHz_XTAL)
- MCFG_MM58167_IRQ_CALLBACK(WRITELINE("pic", pic8259_device, ir3_w))
+ MCFG_MM58167_IRQ_CALLBACK(WRITELINE(m_pic, pic8259_device, ir3_w))
// video
MCFG_SCREEN_ADD("screen", RASTER)
@@ -564,7 +564,7 @@ MACHINE_CONFIG_START(rc759_state::rc759)
MCFG_I82730_ADD("txt", "maincpu", 1250000)
MCFG_VIDEO_SET_SCREEN("screen")
MCFG_I82730_UPDATE_ROW_CB(rc759_state, txt_update_row)
- MCFG_I82730_SINT_HANDLER(WRITELINE("pic", pic8259_device, ir4_w))
+ MCFG_I82730_SINT_HANDLER(WRITELINE(m_pic, pic8259_device, ir4_w))
// keyboard
MCFG_DEVICE_ADD("keyb", GENERIC_KEYBOARD, 0)
diff --git a/src/mame/drivers/sacstate.cpp b/src/mame/drivers/sacstate.cpp
index 9dbd5828b98..78fbaa66432 100644
--- a/src/mame/drivers/sacstate.cpp
+++ b/src/mame/drivers/sacstate.cpp
@@ -106,7 +106,6 @@ void sacstate_state::sacstate_mem(address_map &map)
void sacstate_state::sacstate_io(address_map &map)
{
map.unmap_value_high();
- map.global_mask(0xff);
map(0x00, 0x00).r(FUNC(sacstate_state::port00_r));
map(0x01, 0x01).r(FUNC(sacstate_state::port01_r));
map(0x04, 0x04).r(FUNC(sacstate_state::port04_r));
diff --git a/src/mame/drivers/sage2.cpp b/src/mame/drivers/sage2.cpp
index 2beb04fe575..5e425f0f941 100644
--- a/src/mame/drivers/sage2.cpp
+++ b/src/mame/drivers/sage2.cpp
@@ -414,8 +414,8 @@ MACHINE_CONFIG_START(sage2_state::sage2)
MCFG_DEVICE_PROGRAM_MAP(sage2_mem)
// devices
- MCFG_DEVICE_ADD(I8259_TAG, PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE(M68000_TAG, M68K_IRQ_1))
+ PIC8259(config, m_pic, 0);
+ m_pic->out_int_callback().set_inputline(m_maincpu, M68K_IRQ_1);
i8255_device &ppi0(I8255A(config, I8255A_0_TAG));
ppi0.in_pa_callback().set_ioport("J7");
@@ -427,28 +427,28 @@ MACHINE_CONFIG_START(sage2_state::sage2)
ppi1.in_pb_callback().set(FUNC(sage2_state::ppi1_pb_r));
ppi1.out_pc_callback().set(FUNC(sage2_state::ppi1_pc_w));
- MCFG_DEVICE_ADD(I8253_0_TAG, PIT8253, 0)
- MCFG_PIT8253_CLK0(0) // from U75 OUT0
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(I8259_TAG, pic8259_device, ir6_w))
- MCFG_PIT8253_CLK1(XTAL(16'000'000)/2/125)
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(I8253_0_TAG, pit8253_device, write_clk2))
- MCFG_PIT8253_CLK2(0) // from OUT2
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(I8259_TAG, pic8259_device, ir0_w))
-
- MCFG_DEVICE_ADD(I8253_1_TAG, PIT8253, 0)
- MCFG_PIT8253_CLK0(XTAL(16'000'000)/2/125)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(I8253_0_TAG, pit8253_device, write_clk0))
- MCFG_PIT8253_CLK1(XTAL(16'000'000)/2/13)
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(*this, sage2_state, br1_w))
- MCFG_PIT8253_CLK2(XTAL(16'000'000)/2/13)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, sage2_state, br2_w))
+ pit8253_device &i8253_0(PIT8253(config, I8253_0_TAG, 0));
+ i8253_0.set_clk<0>(0); // from U75 OUT0
+ i8253_0.out_handler<0>().set(m_pic, FUNC(pic8259_device::ir6_w));
+ i8253_0.set_clk<1>(XTAL(16'000'000)/2/125);
+ i8253_0.out_handler<1>().set(I8253_0_TAG, FUNC(pit8253_device::write_clk2));
+ i8253_0.set_clk<2>(0); // from OUT2
+ i8253_0.out_handler<2>().set(m_pic, FUNC(pic8259_device::ir0_w));
+
+ pit8253_device &i8253_1(PIT8253(config, I8253_1_TAG, 0));
+ i8253_1.set_clk<0>(XTAL(16'000'000)/2/125);
+ i8253_1.out_handler<0>().set(I8253_0_TAG, FUNC(pit8253_device::write_clk0));
+ i8253_1.set_clk<1>(XTAL(16'000'000)/2/13);
+ i8253_1.out_handler<1>().set(FUNC(sage2_state::br1_w));
+ i8253_1.set_clk<2>(XTAL(16'000'000)/2/13);
+ i8253_1.out_handler<2>().set(FUNC(sage2_state::br2_w));
I8251(config, m_usart0, 0);
m_usart0->txd_handler().set(RS232_A_TAG, FUNC(rs232_port_device::write_txd));
m_usart0->dtr_handler().set(RS232_A_TAG, FUNC(rs232_port_device::write_dtr));
m_usart0->rts_handler().set(RS232_A_TAG, FUNC(rs232_port_device::write_rts));
m_usart0->rxrdy_handler().set_inputline(M68000_TAG, M68K_IRQ_5);
- m_usart0->txrdy_handler().set(I8259_TAG, FUNC(pic8259_device::ir2_w));
+ m_usart0->txrdy_handler().set(m_pic, FUNC(pic8259_device::ir2_w));
rs232_port_device &rs232a(RS232_PORT(config, RS232_A_TAG, default_rs232_devices, "terminal"));
rs232a.rxd_handler().set(m_usart0, FUNC(i8251_device::write_rxd));
@@ -460,8 +460,8 @@ MACHINE_CONFIG_START(sage2_state::sage2)
m_usart1->txd_handler().set(RS232_B_TAG, FUNC(rs232_port_device::write_txd));
m_usart1->dtr_handler().set(RS232_B_TAG, FUNC(rs232_port_device::write_dtr));
m_usart1->rts_handler().set(RS232_B_TAG, FUNC(rs232_port_device::write_rts));
- m_usart1->rxrdy_handler().set(I8259_TAG, FUNC(pic8259_device::ir1_w));
- m_usart1->txrdy_handler().set(I8259_TAG, FUNC(pic8259_device::ir3_w));
+ m_usart1->rxrdy_handler().set(m_pic, FUNC(pic8259_device::ir1_w));
+ m_usart1->txrdy_handler().set(m_pic, FUNC(pic8259_device::ir3_w));
rs232_port_device &rs232b(RS232_PORT(config, RS232_B_TAG, default_rs232_devices, nullptr));
rs232b.rxd_handler().set(m_usart1, FUNC(i8251_device::write_rxd));
diff --git a/src/mame/drivers/segacoin.cpp b/src/mame/drivers/segacoin.cpp
index 6f26d1569ea..3418ee08f27 100644
--- a/src/mame/drivers/segacoin.cpp
+++ b/src/mame/drivers/segacoin.cpp
@@ -124,39 +124,39 @@ INPUT_PORTS_END
***************************************************************************/
-MACHINE_CONFIG_START(segacoin_state::westdrm)
-
+void segacoin_state::westdrm(machine_config &config)
+{
/* basic machine hardware */
- MCFG_DEVICE_ADD("maincpu", Z80, 8000000) // clock frequency unknown
- MCFG_DEVICE_PROGRAM_MAP(main_map)
- MCFG_DEVICE_IO_MAP(main_portmap)
+ Z80(config, m_maincpu, 8000000); // clock frequency unknown
+ m_maincpu->set_addrmap(AS_PROGRAM, &segacoin_state::main_map);
+ m_maincpu->set_addrmap(AS_IO, &segacoin_state::main_portmap);
- MCFG_DEVICE_ADD("pit", PIT8253, 0)
- MCFG_PIT8253_CLK2(1000000) // clock frequency unknown
+ pit8253_device &pit(PIT8253(config, "pit", 0));
+ pit.set_clk<2>(1000000); // clock frequency unknown
- MCFG_DEVICE_ADD("io", SEGA_315_5338A, 0)
+ SEGA_315_5338A(config, "io", 0);
- MCFG_DEVICE_ADD("audiocpu", Z80, 8000000) // clock frequency unknown
- MCFG_DEVICE_PROGRAM_MAP(sound_map)
- MCFG_DEVICE_IO_MAP(sound_portmap)
+ Z80(config, m_audiocpu, 8000000); // clock frequency unknown
+ m_audiocpu->set_addrmap(AS_PROGRAM, &segacoin_state::sound_map);
+ m_audiocpu->set_addrmap(AS_IO, &segacoin_state::sound_portmap);
/* no video! */
/* sound hardware */
SPEAKER(config, "mono").front_center();
- MCFG_DEVICE_ADD("ym0", YM3438, 8000000) // clock frequency unknown
- MCFG_SOUND_ROUTE(0, "mono", 0.40)
- MCFG_SOUND_ROUTE(1, "mono", 0.40)
+ ym3438_device &ym0(YM3438(config, "ym0", 8000000)); // clock frequency unknown
+ ym0.add_route(0, "mono", 0.40);
+ ym0.add_route(1, "mono", 0.40);
- MCFG_DEVICE_ADD("ym1", YM3438, 8000000) // clock frequency unknown
- MCFG_SOUND_ROUTE(0, "mono", 0.40)
- MCFG_SOUND_ROUTE(1, "mono", 0.40)
+ ym3438_device &ym1(YM3438(config, "ym1", 8000000)); // clock frequency unknown
+ ym1.add_route(0, "mono", 0.40);
+ ym1.add_route(1, "mono", 0.40);
- MCFG_DEVICE_ADD("ym2", YM3438, 8000000) // clock frequency unknown
- MCFG_SOUND_ROUTE(0, "mono", 0.40)
- MCFG_SOUND_ROUTE(1, "mono", 0.40)
-MACHINE_CONFIG_END
+ ym3438_device &ym2(YM3438(config, "ym2", 8000000)); // clock frequency unknown
+ ym2.add_route(0, "mono", 0.40);
+ ym2.add_route(1, "mono", 0.40);
+}
diff --git a/src/mame/drivers/segas16b.cpp b/src/mame/drivers/segas16b.cpp
index 8a22aa2ebf5..72ce7b81743 100644
--- a/src/mame/drivers/segas16b.cpp
+++ b/src/mame/drivers/segas16b.cpp
@@ -5022,7 +5022,7 @@ ROM_END
ROM_START( aurailjd )
ROM_REGION( 0x80000, "maincpu", 0 ) // 68000 code
ROM_LOAD16_BYTE( "bootleg_epr-13446.a7", 0x000000, 0x20000, CRC(25221510) SHA1(8c461db9438bc785c5f81e3cb3bcea9adbd2be9c) )
- ROM_LOAD16_BYTE( "bootleg_epr-13444.a5", 0x000001, 0x20000, CRC(56ba5356) SHA1(a8cf41f415776328b645a23f13999ff356284772))
+ ROM_LOAD16_BYTE( "bootleg_epr-13444.a5", 0x000001, 0x20000, CRC(56ba5356) SHA1(a8cf41f415776328b645a23f13999ff356284772) )
ROM_LOAD16_BYTE( "epr-13447.a8", 0x040000, 0x20000, CRC(70a52167) SHA1(51512d4ee1e63902375b197cf04170744b099d88) )
ROM_LOAD16_BYTE( "epr-13445.a6", 0x040001, 0x20000, CRC(28dfc3dd) SHA1(b1d6d3e31a48062a91cc9b7b6ff68bfde0a3ea1c) )
@@ -5263,7 +5263,7 @@ ROM_END
ROM_START( bulletd )
ROM_REGION( 0x30000, "maincpu", 0 ) // 68000 code
ROM_LOAD16_BYTE( "bootleg_epr-11010.a4", 0x000000, 0x08000, CRC(c4b7cb63) SHA1(c35fceab2a03f23d9690432a582064d12de950f6) )
- ROM_LOAD16_BYTE( "bootleg_epr-11007.a1", 0x000001, 0x08000, CRC(2afa84c5) SHA1(97f74ba4b9f83314c9e1f61afe7db3d7fa7a9935))
+ ROM_LOAD16_BYTE( "bootleg_epr-11007.a1", 0x000001, 0x08000, CRC(2afa84c5) SHA1(97f74ba4b9f83314c9e1f61afe7db3d7fa7a9935) )
ROM_LOAD16_BYTE( "epr-11011.a5", 0x010000, 0x08000, CRC(7f446b9f) SHA1(0b92ab100c13bdcdd0f770da5da5e19cb79afde1) )
ROM_LOAD16_BYTE( "epr-11008.a2", 0x010001, 0x08000, CRC(34824d3b) SHA1(7a3134a71ad176b8a08a919c0acb75ae1e05743b) )
ROM_LOAD16_BYTE( "epr-11012.a6", 0x020000, 0x08000, CRC(3992f159) SHA1(50686b394693ab01cbd159ae661f326c8eee50b8) )
@@ -5339,7 +5339,7 @@ ROM_END
ROM_START( cottond )
ROM_REGION( 0x80000, "maincpu", 0 ) // 68000 code
- ROM_LOAD16_BYTE( "bootleg_epr-13921a.a7", 0x000000, 0x20000, CRC(92947867) SHA1(6d5f1be45690bacac7093b442ed99c4de56d73a4))
+ ROM_LOAD16_BYTE( "bootleg_epr-13921a.a7", 0x000000, 0x20000, CRC(92947867) SHA1(6d5f1be45690bacac7093b442ed99c4de56d73a4) )
ROM_LOAD16_BYTE( "bootleg_epr-13919a.a5", 0x000001, 0x20000, CRC(30f131fb) SHA1(5b35b4691d2436e82be3079634d8f7f259e46450) )
ROM_LOAD16_BYTE( "bootleg_epr-13922a.a8", 0x040000, 0x20000, CRC(f0f75329) SHA1(e223b3b6e15ead11f93e353ddce5227f8b362d2e) )
ROM_LOAD16_BYTE( "bootleg_epr-13920a.a6", 0x040001, 0x20000, CRC(a3721aab) SHA1(bfcd8e564f06520e51c61418246ef06e4a0036d7) )
@@ -6243,9 +6243,9 @@ ROM_START( exctleag )
ROM_LOAD16_BYTE( "epr-11957.b8", 0x60000, 0x10000, CRC(218f835b) SHA1(bfef3ec45665a5921c095da34701528d4d4e0e3a) )
ROM_REGION( 0x50000, "soundcpu", 0 ) // sound CPU
- ROM_LOAD( "epr-11945.a7", 0x00000, 0x8000, CRC(c2a83012) SHA1(b3de8af803497438aa3e110a9c608ac290f7d1e8) )
- ROM_LOAD( "epr-11140.a8", 0x10000, 0x8000, CRC(b297371b) SHA1(4e787aa9ee2aeab4da30237644421df407b684a5) )
- ROM_LOAD( "epr-11141.a9", 0x20000, 0x8000, CRC(19756aa6) SHA1(81597e17b848f6a41f5fb117296e7508297815e4) )
+ ROM_LOAD( "epr-11945.a7", 0x00000, 0x8000, CRC(c2a83012) SHA1(b3de8af803497438aa3e110a9c608ac290f7d1e8) )
+ ROM_LOAD( "epr-11140.a8", 0x10000, 0x8000, CRC(b297371b) SHA1(4e787aa9ee2aeab4da30237644421df407b684a5) )
+ ROM_LOAD( "epr-11141.a9", 0x20000, 0x8000, CRC(19756aa6) SHA1(81597e17b848f6a41f5fb117296e7508297815e4) )
ROM_LOAD( "epr-11142.a10", 0x30000, 0x8000, CRC(25d26c66) SHA1(2485afb859f84a9cc90b2091e9ae4eef263f42b3) )
ROM_LOAD( "epr-11143.a11", 0x40000, 0x8000, CRC(848b7b77) SHA1(8903a39f8f0ffb4ce32117d33282876196516c30) )
ROM_END
@@ -6253,7 +6253,7 @@ ROM_END
ROM_START( exctleagd )
ROM_REGION( 0x60000, "maincpu", 0 ) // 68000 code
- ROM_LOAD16_BYTE( "bootleg_epr-11939.a4", 0x00000, 0x10000, CRC(42db9082) SHA1(3ac03ad9dc9b5554b0e4ded4520f957e7dc4bf6e))
+ ROM_LOAD16_BYTE( "bootleg_epr-11939.a4", 0x00000, 0x10000, CRC(42db9082) SHA1(3ac03ad9dc9b5554b0e4ded4520f957e7dc4bf6e) )
ROM_LOAD16_BYTE( "bootleg_epr-11936.a1", 0x00001, 0x10000, CRC(8a0c126c) SHA1(8770ab22b06829ad3441c54cdc3211991fe6299b) )
ROM_LOAD16_BYTE( "bootleg_epr-11940.a5", 0x20000, 0x10000, CRC(e490bb47) SHA1(cc6c05b86149f2fa180c67d351df06571b48f3c8) )
ROM_LOAD16_BYTE( "bootleg_epr-11937.a2", 0x20001, 0x10000, CRC(f1c07e10) SHA1(844da4f2cf5b084e833a834dd70e584d69f15d33) )
@@ -6276,9 +6276,9 @@ ROM_START( exctleagd )
ROM_LOAD16_BYTE( "epr-11957.b8", 0x60000, 0x10000, CRC(218f835b) SHA1(bfef3ec45665a5921c095da34701528d4d4e0e3a) )
ROM_REGION( 0x50000, "soundcpu", 0 ) // sound CPU
- ROM_LOAD( "epr-11945.a7", 0x00000, 0x8000, CRC(c2a83012) SHA1(b3de8af803497438aa3e110a9c608ac290f7d1e8) )
- ROM_LOAD( "epr-11140.a8", 0x10000, 0x8000, CRC(b297371b) SHA1(4e787aa9ee2aeab4da30237644421df407b684a5) )
- ROM_LOAD( "epr-11141.a9", 0x20000, 0x8000, CRC(19756aa6) SHA1(81597e17b848f6a41f5fb117296e7508297815e4) )
+ ROM_LOAD( "epr-11945.a7", 0x00000, 0x8000, CRC(c2a83012) SHA1(b3de8af803497438aa3e110a9c608ac290f7d1e8) )
+ ROM_LOAD( "epr-11140.a8", 0x10000, 0x8000, CRC(b297371b) SHA1(4e787aa9ee2aeab4da30237644421df407b684a5) )
+ ROM_LOAD( "epr-11141.a9", 0x20000, 0x8000, CRC(19756aa6) SHA1(81597e17b848f6a41f5fb117296e7508297815e4) )
ROM_LOAD( "epr-11142.a10", 0x30000, 0x8000, CRC(25d26c66) SHA1(2485afb859f84a9cc90b2091e9ae4eef263f42b3) )
ROM_LOAD( "epr-11143.a11", 0x40000, 0x8000, CRC(848b7b77) SHA1(8903a39f8f0ffb4ce32117d33282876196516c30) )
ROM_END
@@ -6340,7 +6340,7 @@ ROM_END
ROM_START( fpointd )
ROM_REGION( 0x20000, "maincpu", 0 ) // 68000 code
ROM_LOAD16_BYTE( "bootleg_epr-12599b.a4", 0x000000, 0x10000, CRC(f5102d28) SHA1(5353e66a3c510ea394025162abe9a04c6122b19b) )
- ROM_LOAD16_BYTE( "bootleg_epr-12598b.a1", 0x000001, 0x10000, CRC(5335558c) SHA1(508cd878cb9653c0169532002b5e4ee0a7de98b9))
+ ROM_LOAD16_BYTE( "bootleg_epr-12598b.a1", 0x000001, 0x10000, CRC(5335558c) SHA1(508cd878cb9653c0169532002b5e4ee0a7de98b9) )
ROM_REGION( 0x30000, "gfx1", 0 ) // tiles
ROM_LOAD( "opr-12593.a14", 0x00000, 0x10000, CRC(cc0582d8) SHA1(92c7d125a6dcb9c5e6e7bd92a5bf3008385ed487) )
@@ -7351,7 +7351,7 @@ ROM_START( cencourt )
ROM_LOAD16_BYTE( "a1_478b.a1", 0x000001, 0x10000, CRC(37beb770) SHA1(694a7f7977226997e06a198b311b355505e45b0b) )
ROM_REGION( 0x30000, "gfx1", 0 ) // tiles
- ROM_LOAD( "epr-b-9.b9", 0x00000, 0x10000, CRC(9a55cd88) SHA1(4a6cf4aa5dde8d50148381aee8c141c98bb86fe8) )
+ ROM_LOAD( "epr-b-9.b9", 0x00000, 0x10000, CRC(9a55cd88) SHA1(4a6cf4aa5dde8d50148381aee8c141c98bb86fe8) )
ROM_LOAD( "epr-b-10.b10", 0x10000, 0x10000, CRC(fc13ca35) SHA1(3dc9d7c7f28d5605c6ce93243c79f63839aec8f4) )
ROM_LOAD( "epr-b-11.b11", 0x20000, 0x10000, CRC(1503c203) SHA1(95e9634bdcfd8027c1b0a47fa87736180ec39b08) )
@@ -7755,6 +7755,10 @@ ROM_END
// Shinobi, Sega System 16B
// CPU: 68000
// ROM Board type: 171-5521
+// Following baord numbers are NOT verified:
+// Main board: 837-6500-01 ??
+// Game Number: 833-6496-01 SHINOBI ??
+// ROM board: 834-6499-01 ??
//
ROM_START( shinobi5 )
ROM_REGION( 0x40000, "maincpu", 0 ) // 68000 code
@@ -7762,27 +7766,28 @@ ROM_START( shinobi5 )
ROM_LOAD16_BYTE( "epr-11359.a5", 0x00001, 0x20000, CRC(0f0306e1) SHA1(eebe7c88e5f665d1d0920fb9b545e20b05be9b52) )
ROM_REGION( 0x60000, "gfx1", 0 ) // tiles
- ROM_LOAD( "epr-11363.a14", 0x00000, 0x20000, CRC(40914168) SHA1(cf0508e8c852c24ec3d2fc4a4013aec631d2271f) )
- ROM_LOAD( "epr-11364.a15", 0x20000, 0x20000, CRC(e63649a4) SHA1(042dded1ff964889571f63d2642b2b21b75f9763) )
- ROM_LOAD( "epr-11365.a16", 0x40000, 0x20000, CRC(1ef55d20) SHA1(314590881a2f18339b7b9c16010e408aa0164e04) )
+ ROM_LOAD( "mpr-11363.a14", 0x00000, 0x20000, CRC(40914168) SHA1(cf0508e8c852c24ec3d2fc4a4013aec631d2271f) ) // 28 pin Fujitsu MB831000 MASK roms
+ ROM_LOAD( "mpr-11364.a15", 0x20000, 0x20000, CRC(e63649a4) SHA1(042dded1ff964889571f63d2642b2b21b75f9763) )
+ ROM_LOAD( "mpr-11365.a16", 0x40000, 0x20000, CRC(1ef55d20) SHA1(314590881a2f18339b7b9c16010e408aa0164e04) )
ROM_REGION16_BE( 0x80000, "sprites", 0 ) // sprites
- ROM_LOAD16_BYTE( "epr-11366.b1", 0x00001, 0x20000, CRC(319ede73) SHA1(c48ba4694ff677f30cc1ced3a3ad11c0feb1122d) )
- ROM_LOAD16_BYTE( "epr-11368.b5", 0x00000, 0x20000, CRC(0377d7ce) SHA1(14f9674c142b78bf8b458beccfef93cc3e722c03) )
- ROM_LOAD16_BYTE( "epr-11367.b2", 0x40001, 0x20000, CRC(1d06c5c7) SHA1(3a44f5a2058b96f212930c2e838eda1ce1036818) )
- ROM_LOAD16_BYTE( "epr-11369.b6", 0x40000, 0x20000, CRC(d751d2a2) SHA1(3659948beacfc8dde5c50775859aa3fed537f768) )
+ ROM_LOAD16_BYTE( "mpr-11366.b1", 0x00001, 0x20000, CRC(319ede73) SHA1(c48ba4694ff677f30cc1ced3a3ad11c0feb1122d) ) // 28 pin Fujitsu MB831000 MASK roms
+ ROM_LOAD16_BYTE( "mpr-11368.b5", 0x00000, 0x20000, CRC(0377d7ce) SHA1(14f9674c142b78bf8b458beccfef93cc3e722c03) )
+ ROM_LOAD16_BYTE( "mpr-11367.b2", 0x40001, 0x20000, CRC(1d06c5c7) SHA1(3a44f5a2058b96f212930c2e838eda1ce1036818) )
+ ROM_LOAD16_BYTE( "mpr-11369.b6", 0x40000, 0x20000, CRC(d751d2a2) SHA1(3659948beacfc8dde5c50775859aa3fed537f768) )
ROM_REGION( 0x50000, "soundcpu", 0 ) // sound CPU
ROM_LOAD( "epr-11361.a10", 0x00000, 0x08000, CRC(1f47ebcb) SHA1(32837f3f1dd5ff309d1d955c1a738c444b248d3d) )
- ROM_LOAD( "epr-11362.a11", 0x10000, 0x20000, CRC(256af749) SHA1(041bd007ea7708c6d69f07865828b9bd17a139f5) )
+ ROM_LOAD( "mpr-11362.a11", 0x10000, 0x20000, CRC(256af749) SHA1(041bd007ea7708c6d69f07865828b9bd17a139f5) ) // 28 pin Fujitsu MB831000 MASK rom
ROM_END
//*************************************************************************************************************************
// Shinobi, Sega System 16B
// CPU: 68000 + MC8123B (317-0054)
// ROM Board type: 171-5521
-// Game Nunmber: 834-6496-04
-// ROM board: 834-6499-03
+// Main board: 837-6500-02
+// Game Number: 833-6496-03 SHINOBI
+// ROM board: 834-6499-03
//
ROM_START( shinobi4 )
ROM_REGION( 0x40000, "maincpu", 0 ) // 68000 code
@@ -7790,19 +7795,19 @@ ROM_START( shinobi4 )
ROM_LOAD16_BYTE( "epr-11359.a5", 0x00001, 0x20000, CRC(0f0306e1) SHA1(eebe7c88e5f665d1d0920fb9b545e20b05be9b52) )
ROM_REGION( 0x60000, "gfx1", 0 ) // tiles
- ROM_LOAD( "epr-11363.a14", 0x00000, 0x20000, CRC(40914168) SHA1(cf0508e8c852c24ec3d2fc4a4013aec631d2271f) )
- ROM_LOAD( "epr-11364.a15", 0x20000, 0x20000, CRC(e63649a4) SHA1(042dded1ff964889571f63d2642b2b21b75f9763) )
- ROM_LOAD( "epr-11365.a16", 0x40000, 0x20000, CRC(1ef55d20) SHA1(314590881a2f18339b7b9c16010e408aa0164e04) )
+ ROM_LOAD( "mpr-11363.a14", 0x00000, 0x20000, CRC(40914168) SHA1(cf0508e8c852c24ec3d2fc4a4013aec631d2271f) ) // 28 pin Fujitsu MB831000 MASK roms
+ ROM_LOAD( "mpr-11364.a15", 0x20000, 0x20000, CRC(e63649a4) SHA1(042dded1ff964889571f63d2642b2b21b75f9763) )
+ ROM_LOAD( "mpr-11365.a16", 0x40000, 0x20000, CRC(1ef55d20) SHA1(314590881a2f18339b7b9c16010e408aa0164e04) )
ROM_REGION16_BE( 0x80000, "sprites", 0 ) // sprites
- ROM_LOAD16_BYTE( "epr-11366.b1", 0x00001, 0x20000, CRC(319ede73) SHA1(c48ba4694ff677f30cc1ced3a3ad11c0feb1122d) )
- ROM_LOAD16_BYTE( "epr-11368.b5", 0x00000, 0x20000, CRC(0377d7ce) SHA1(14f9674c142b78bf8b458beccfef93cc3e722c03) )
- ROM_LOAD16_BYTE( "epr-11367.b2", 0x40001, 0x20000, CRC(1d06c5c7) SHA1(3a44f5a2058b96f212930c2e838eda1ce1036818) )
- ROM_LOAD16_BYTE( "epr-11369.b6", 0x40000, 0x20000, CRC(d751d2a2) SHA1(3659948beacfc8dde5c50775859aa3fed537f768) )
+ ROM_LOAD16_BYTE( "mpr-11366.b1", 0x00001, 0x20000, CRC(319ede73) SHA1(c48ba4694ff677f30cc1ced3a3ad11c0feb1122d) ) // 28 pin Fujitsu MB831000 MASK roms
+ ROM_LOAD16_BYTE( "mpr-11368.b5", 0x00000, 0x20000, CRC(0377d7ce) SHA1(14f9674c142b78bf8b458beccfef93cc3e722c03) )
+ ROM_LOAD16_BYTE( "mpr-11367.b2", 0x40001, 0x20000, CRC(1d06c5c7) SHA1(3a44f5a2058b96f212930c2e838eda1ce1036818) )
+ ROM_LOAD16_BYTE( "mpr-11369.b6", 0x40000, 0x20000, CRC(d751d2a2) SHA1(3659948beacfc8dde5c50775859aa3fed537f768) )
ROM_REGION( 0x50000, "soundcpu", 0 ) // sound CPU
ROM_LOAD( "epr-11377.a10", 0x00000, 0x08000, CRC(0fb6af34) SHA1(ae9da18bd2db317ed96c5f642f90cc1eba60ba99) ) // MC8123B (317-0054) encrypted version of epr-11361.a10 above
- ROM_LOAD( "epr-11362.a11", 0x10000, 0x20000, CRC(256af749) SHA1(041bd007ea7708c6d69f07865828b9bd17a139f5) )
+ ROM_LOAD( "mpr-11362.a11", 0x10000, 0x20000, CRC(256af749) SHA1(041bd007ea7708c6d69f07865828b9bd17a139f5) ) // 28 pin Fujitsu MB831000 MASK rom
ROM_REGION( 0x2000, "soundcpu:key", 0 ) // MC8123 key
ROM_LOAD( "317-0054.key", 0x0000, 0x2000, CRC(39fd4535) SHA1(93bbb139d2d5acc6a1e338d92077e79a5e880b2e) )
@@ -7812,8 +7817,9 @@ ROM_END
// Shinobi, Sega System 16B
// CPU: 68000 + MC8123B (317-0054)
// ROM Board type: 171-5358
-// Game Nunmber: 834-6496-04
-// ROM board: 834-6499-02
+// Main board: 837-6500-02
+// Game Number: 833-6496-04 SHINOBI
+// ROM board: 834-6499-04
//
ROM_START( shinobi3 )
ROM_REGION( 0x40000, "maincpu", 0 ) // 68000 code
@@ -7850,7 +7856,9 @@ ROM_END
// Shinobi, Sega System 16B
// CPU: FD1094 (317-0049)
// ROM Board type: 171-5358
-// ROM board: 834-6499
+// Main board: 837-6500
+// Game Number: 833-6496 SHINOBI
+// ROM board: 834-6499
//
ROM_START( shinobi2 )
ROM_REGION( 0x40000, "maincpu", 0 ) // 68000 code
@@ -8065,7 +8073,7 @@ ROM_START( suprleag )
ROM_LOAD( "317-0045.key", 0x0000, 0x2000, CRC(0594cc2e) SHA1(8aec3fffd00cbfd50d7cfb92e4748e2653fbb504) )
ROM_REGION( 0x30000, "gfx1", 0 ) // tiles
- ROM_LOAD( "epr-11136.b9", 0x00000, 0x10000, CRC(c3860ce4) SHA1(af7618f3b5a0e8d6374877c7815ba69fff218a45) )
+ ROM_LOAD( "epr-11136.b9", 0x00000, 0x10000, CRC(c3860ce4) SHA1(af7618f3b5a0e8d6374877c7815ba69fff218a45) )
ROM_LOAD( "epr-11137.b10", 0x10000, 0x10000, CRC(92d96187) SHA1(45138795992b9842d5b0c86a96b300445bf12060) )
ROM_LOAD( "epr-11138.b11", 0x20000, 0x10000, CRC(c01dc773) SHA1(b27da906186e1272cdd6f8d5e5a979f6623255ac) )
@@ -8080,9 +8088,9 @@ ROM_START( suprleag )
ROM_LOAD16_BYTE( "epr-11151.b8", 0x60000, 0x10000, CRC(9de95169) SHA1(1a2801ecd9dece3dae7ceab3b793d5005caa4614) )
ROM_REGION( 0x50000, "soundcpu", 0 ) // sound CPU
- ROM_LOAD( "epr-11139.a7", 0x00000, 0x08000, CRC(9cbd99da) SHA1(55960b68b23a4f89ec810e1d31f22ba60cda0cfe) )
- ROM_LOAD( "epr-11140.a8", 0x10000, 0x08000, CRC(b297371b) SHA1(4e787aa9ee2aeab4da30237644421df407b684a5) )
- ROM_LOAD( "epr-11141.a9", 0x20000, 0x08000, CRC(19756aa6) SHA1(81597e17b848f6a41f5fb117296e7508297815e4) )
+ ROM_LOAD( "epr-11139.a7", 0x00000, 0x08000, CRC(9cbd99da) SHA1(55960b68b23a4f89ec810e1d31f22ba60cda0cfe) )
+ ROM_LOAD( "epr-11140.a8", 0x10000, 0x08000, CRC(b297371b) SHA1(4e787aa9ee2aeab4da30237644421df407b684a5) )
+ ROM_LOAD( "epr-11141.a9", 0x20000, 0x08000, CRC(19756aa6) SHA1(81597e17b848f6a41f5fb117296e7508297815e4) )
ROM_LOAD( "epr-11142.a10", 0x30000, 0x08000, CRC(25d26c66) SHA1(2485afb859f84a9cc90b2091e9ae4eef263f42b3) )
ROM_LOAD( "epr-11143.a11", 0x40000, 0x08000, CRC(848b7b77) SHA1(8903a39f8f0ffb4ce32117d33282876196516c30) )
ROM_END
@@ -8110,8 +8118,8 @@ ROM_START( tetris2 )
ROM_LOAD( "epr-12167.b11", 0x20000, 0x10000, CRC(2495fd4e) SHA1(2db94ead9223a67238a97e724668076fc43e5534) )
ROM_REGION16_BE( 0x020000, "sprites", 0 ) // sprites
- ROM_LOAD16_BYTE( "epr-12194.b1", 0x00001, 0x10000, CRC(2fb38880) SHA1(0e1b601bbda78d1887951c1f7e752531c281bc83) ) // 28 pin Fujitsu MB831000 MASK rom
- ROM_LOAD16_BYTE( "epr-12195.b5", 0x00000, 0x10000, CRC(d6a02cba) SHA1(d80000f92e754e89c6ca7b7273feab448fc9a061) ) // 28 pin Fujitsu MB831000 MASK rom
+ ROM_LOAD16_BYTE( "mpr-12194.b1", 0x00001, 0x10000, CRC(2fb38880) SHA1(0e1b601bbda78d1887951c1f7e752531c281bc83) ) // 28 pin Fujitsu MB831000 MASK rom
+ ROM_LOAD16_BYTE( "mpr-12195.b5", 0x00000, 0x10000, CRC(d6a02cba) SHA1(d80000f92e754e89c6ca7b7273feab448fc9a061) ) // 28 pin Fujitsu MB831000 MASK rom
ROM_REGION( 0x10000, "soundcpu", 0 ) // sound CPU
ROM_LOAD( "epr-12168.a7", 0x0000, 0x8000, CRC(bd9ba01b) SHA1(fafa7dc36cc057a50ae4cdf7a35f3594292336f4) )
@@ -8128,8 +8136,8 @@ ROM_START( tetris2d )
ROM_LOAD( "epr-12167.b11", 0x20000, 0x10000, CRC(2495fd4e) SHA1(2db94ead9223a67238a97e724668076fc43e5534) )
ROM_REGION16_BE( 0x020000, "sprites", 0 ) // sprites
- ROM_LOAD16_BYTE( "epr-12194.b1", 0x00001, 0x10000, CRC(2fb38880) SHA1(0e1b601bbda78d1887951c1f7e752531c281bc83) ) // 28 pin Fujitsu MB831000 MASK rom
- ROM_LOAD16_BYTE( "epr-12195.b5", 0x00000, 0x10000, CRC(d6a02cba) SHA1(d80000f92e754e89c6ca7b7273feab448fc9a061) ) // 28 pin Fujitsu MB831000 MASK rom
+ ROM_LOAD16_BYTE( "mpr-12194.b1", 0x00001, 0x10000, CRC(2fb38880) SHA1(0e1b601bbda78d1887951c1f7e752531c281bc83) ) // 28 pin Fujitsu MB831000 MASK rom
+ ROM_LOAD16_BYTE( "mpr-12195.b5", 0x00000, 0x10000, CRC(d6a02cba) SHA1(d80000f92e754e89c6ca7b7273feab448fc9a061) ) // 28 pin Fujitsu MB831000 MASK rom
ROM_REGION( 0x10000, "soundcpu", 0 ) // sound CPU
ROM_LOAD( "epr-12168.a7", 0x0000, 0x8000, CRC(bd9ba01b) SHA1(fafa7dc36cc057a50ae4cdf7a35f3594292336f4) )
@@ -8419,7 +8427,7 @@ ROM_END
// Wonder Boy III, Sega System 16B
// CPU: FD1094 (317-0087)
// ROM Board type: 171-5704
-// Sega ID# for Game Nunmber: 833-6851-01 MONSTER LAIR
+// Sega ID# for Game Number: 833-6851-01 MONSTER LAIR
// Sega ID# for ROM board: 834-6854-01
//
ROM_START( wb34 )
@@ -8508,7 +8516,7 @@ ROM_END
ROM_START( wb33d )
ROM_REGION( 0x40000, "maincpu", 0 ) // 68000 code
ROM_LOAD16_BYTE( "bootleg_epr-12137.a7", 0x000000, 0x20000, CRC(18a898af) SHA1(4614fab9f27bdfefc0c402edbac454c517b78c2f) )
- ROM_LOAD16_BYTE( "bootleg_epr-12136.a5", 0x000001, 0x20000, CRC(e3d21248) SHA1(6d146a0c9a5b1f8cb0d2770b2c272fafe58360c0))
+ ROM_LOAD16_BYTE( "bootleg_epr-12136.a5", 0x000001, 0x20000, CRC(e3d21248) SHA1(6d146a0c9a5b1f8cb0d2770b2c272fafe58360c0) )
ROM_REGION( 0x30000, "gfx1", 0 ) // tiles
ROM_LOAD( "epr-12124.a14", 0x00000, 0x10000, CRC(dacefb6f) SHA1(789a5a99ad9419aee9da5397bcea34452ea8b4b3) )
diff --git a/src/mame/drivers/segasp.cpp b/src/mame/drivers/segasp.cpp
index d6b730e29c3..19579541bc7 100644
--- a/src/mame/drivers/segasp.cpp
+++ b/src/mame/drivers/segasp.cpp
@@ -38,7 +38,9 @@ todo: make this actually readable, we don't support unicode source files
Title PCB ID REV CFID Dumped Region PIC MAIN BD Serial
Battle Police ???-????? no ???-????-???? AAFE-xxxxxxxxxxx
Beetle DASH!! ???-????? no ???-????-???? AAFE-xxxxxxxxxxx
-Bingo Galaxy 834-14788 no ???-????-???? AAFE-01E10924916, AAFE-01D67304905, Medal
+Bingo Galaxy (main) 834-14788 C ROM JP 253-5508-0513J AAFE-01A37754716, AAFE-01E10924916, AAFE-01D67304905, Medal
+Bingo Galaxy (satellite) 837-14481 C ROM JP not used AAFE-01A36474716, Medal
+Bingo Galaxy (satellite) 837-14789 F* ROM JP not used AAFE-xxxxxxxxxxx, game is same as above
Bingo Parade ???-????? no ???-????-???? AAFE-xxxxxxxxxxx, Medal
Brick People / Block People 834-14881 ROM ANY 253-5508-0558 AAFE-01F67905202, AAFE-01F68275202
Dinosaur King 834-14493-01 D ROM US 253-5508-0408 AAFE-01D1132xxxx, AAFE-01D15924816
@@ -68,8 +70,10 @@ Tetris Giant / Tetris Dekaris Ver.2.000 834-14970 G ROM ANY
Thomas: The Tank Engine ???-????? no ???-????-???? AAFE-xxxxxxxxxxx
REV PCB IC6s Flash AU1500
+C 171-8278C 315-6370 8x 128Mbit AMD
D 171-8278D 315-6370 8x 128Mbit AMD
F 171-8278F 315-6416 8x 512Mbit AMD
+F* 171-8278F 315-6416 2x 512Mbit RMI
G 171-8278G 315-6416 2x 512Mbit RMI
*/
@@ -331,13 +335,17 @@ void segasp_state::init_segasp()
ROM_REGION16_BE( 0x80, "main_eeprom", 0 ) \
ROM_LOAD16_WORD( "mb_serial.ic57", 0x0000, 0x0080, CRC(e1e3c009) SHA1(66bc636c527389c3338f631d78c788b4bd4e93be) )
-// net_firm_119.ic72 - Network/Media Board firmware VER 1.19(VxWorks), 1st half contain original 1.10 version
-// fpr-24407.ic72 - version 1.25
+// net_firm_119.ic72 - Network/Media Board firmware VER 1.19(VxWorks), 1st half contain original 1.10 version
+// fpr-24208a.ic72 - version 1.23, 1st half - 1.10
+// fpr-24407_123.ic72 - version 1.23, 1st half - 1.20
+// fpr-24407.ic72 - version 1.25, 1st half - 1.20
#define SEGASP_NETFIRM \
ROM_REGION( 0x200000, "netcpu", 0) \
ROM_LOAD( "net_eeprom.ic74s", 0x00000000, 0x200, CRC(77cc5a6c) SHA1(cbfba546256b70bce6c6fd0030d7e2e410a25526) ) \
ROM_LOAD( "net_firm_119.ic72", 0x00000000, 0x200000, CRC(a738ea1c) SHA1(d25187a973a7e166e70334f964363adf2be87257) ) \
- ROM_LOAD( "fpr-24407.ic72", 0x00000000, 0x200000, CRC(a738ea1c) SHA1(fbcc3d119b47a6da4d194e3fe4a98126c7049edf) )
+ ROM_LOAD( "fpr-24208a.ic72", 0x00000000, 0x200000, CRC(a738ea1c) SHA1(3c32ddfb3c40be66b9fb2ba35fbfd5b534bb3da0) ) \
+ ROM_LOAD( "fpr-24407.ic72", 0x00000000, 0x200000, CRC(a738ea1c) SHA1(fbcc3d119b47a6da4d194e3fe4a98126c7049edf) ) \
+ ROM_LOAD( "fpr-24407_123.ic72",0x00000000, 0x200000, CRC(a738ea1c) SHA1(3f5a2fb03bbb1bd9af9fe32ad76a224c97aa9b7a) )
// keep M4 board code happy for now
#define SEGASP_MISC \
@@ -391,6 +399,43 @@ ROM_START( brickppl )
ROM_LOAD( "317-0558-com.ic15", 0, 0x800, BAD_DUMP CRC(7592d004) SHA1(632373d807f54953d68c95a9f874ed3e8011f085) )
ROM_END
+ROM_START( bingogal )
+ SEGASP_BIOS
+ SEGASP_JP
+ SEGASP_MISC
+
+ ROM_REGION( 0x08000000, "rom_board", ROMREGION_ERASE)
+ ROM_LOAD( "ic62", 0x00000000, 0x01000000, CRC(c07d9870) SHA1(5d40c14c398c11908f05ef1fd274aa3818409fc6) )
+ ROM_LOAD( "ic63", 0x01000000, 0x01000000, CRC(5d85e6c0) SHA1(c09e843399fa4855ea149564480adbdf02dcc182) )
+ ROM_LOAD( "ic64", 0x02000000, 0x01000000, CRC(73134f52) SHA1(63e32fbbd15bb527d9b840dcc92bb9dd86483ae3) )
+ ROM_LOAD( "ic65", 0x03000000, 0x01000000, CRC(1e4ae511) SHA1(55b4f9dc86f7da8db9e4875a6ee120228be42591) )
+ ROM_LOAD( "ic66s", 0x04000000, 0x01000000, CRC(810d5dfc) SHA1(6998a622d0a4be27ba6d1fcfb2a89586f269b59e) )
+ ROM_LOAD( "ic67s", 0x05000000, 0x01000000, CRC(92014e31) SHA1(6a5cf75da4c81dc55386996b6e62bbb4594591e8) )
+ ROM_LOAD( "ic68s", 0x06000000, 0x01000000, CRC(0640172c) SHA1(44ccf6919922a1ce8ffd49ad3306c68b15193a71) )
+ ROM_LOAD( "ic69s", 0x07000000, 0x01000000, CRC(ca26fbf9) SHA1(fe131e23109d4ff2b79ce53b79c22009b2078c85) )
+
+ ROM_PARAMETER( ":rom_board:id", "5502" ) // actually 8x 128Mbit FlashROMs
+
+ ROM_REGION( 0x800, "pic_readout", 0 )
+ ROM_LOAD( "317-0513-jpn.ic15", 0, 0x800, BAD_DUMP CRC(778dc297) SHA1(a920ab31ea670cc5056c40baea3b832b7868bfe7) )
+ROM_END
+
+// Also was dumped 837-14789 PCB, which uses 2x 512Mbit Flash ROMs. Game contents is the same as joined IC 62-64 dumps below.
+ROM_START( bingogals )
+ SEGASP_BIOS
+ SEGASP_JP
+ SEGASP_MISC
+
+ ROM_REGION( 0x08000000, "rom_board", ROMREGION_ERASE)
+ ROM_LOAD( "ic62", 0x00000000, 0x01000000, CRC(880eb905) SHA1(7afdb154329d49c85b10316d62aef4934e9a5479) )
+ ROM_LOAD( "ic63", 0x01000000, 0x01000000, CRC(41dab407) SHA1(d4582e6d8a0e67e6bfebcb336a4c8392f7cdba39) )
+ ROM_LOAD( "ic64", 0x02000000, 0x01000000, CRC(97dfb2ab) SHA1(97f95643145717b199cf79020d5e81bf913a96a7) )
+
+ ROM_PARAMETER( ":rom_board:id", "5502" ) // actually 8x 128Mbit FlashROMs
+
+ ROM_REGION( 0x800, "pic_readout", ROMREGION_ERASEFF) // not populated
+ROM_END
+
ROM_START( dinoking )
SEGASP_BIOS
SEGASP_US
@@ -566,6 +611,8 @@ ROM_END
GAME( 2004, segasp, 0, segasp, segasp, segasp_state, init_segasp, ROT0, "Sega", "Sega System SP (Spider) BIOS", GAME_FLAGS | MACHINE_IS_BIOS_ROOT )
// These use ROMs
+GAME( 2009, bingogal,segasp, segasp, segasp, segasp_state, init_segasp, ROT0, "Sega", "Bingo Galaxy (main)", GAME_FLAGS ) // 28.05.2009
+GAME( 2009, bingogals,bingogal, segasp, segasp, segasp_state, init_segasp, ROT0, "Sega", "Bingo Galaxy (satellite)", GAME_FLAGS ) // 28.05.2009
GAME( 2009, brickppl,segasp, segasp, segasp, segasp_state, init_segasp, ROT0, "Sega", "Brick People / Block PeePoo (Ver 1.002)", GAME_FLAGS )
GAME( 2005, dinoking,segasp, segasp, segasp, segasp_state, init_segasp, ROT0, "Sega", "Dinosaur King (USA)", GAME_FLAGS )
GAME( 2006, lovebery,segasp, segasp, segasp, segasp_state, init_segasp, ROT0, "Sega", "Love And Berry - 1st-2nd Collection (Export, Ver 2.000)", GAME_FLAGS )
diff --git a/src/mame/drivers/segaufo.cpp b/src/mame/drivers/segaufo.cpp
index 5b3a66a9085..078d778842c 100644
--- a/src/mame/drivers/segaufo.cpp
+++ b/src/mame/drivers/segaufo.cpp
@@ -806,13 +806,13 @@ MACHINE_CONFIG_START(ufo_state::newufo)
m_io2->out_pf_callback().set(FUNC(ufo_state::crane_xyz_w));
m_io2->out_pg_callback().set(FUNC(ufo_state::ufo_lamps_w));
- MCFG_DEVICE_ADD("pit", PIT8254, XTAL(16'000'000)/2) // uPD71054C, configuration is unknown
- MCFG_PIT8253_CLK0(XTAL(16'000'000)/2/256)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, ufo_state, pit_out0))
- MCFG_PIT8253_CLK1(XTAL(16'000'000)/2/256)
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(*this, ufo_state, pit_out1))
- MCFG_PIT8253_CLK2(XTAL(16'000'000)/2/256)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, ufo_state, pit_out2))
+ pit8254_device &pit(PIT8254(config, "pit", XTAL(16'000'000)/2)); // uPD71054C, configuration is unknown
+ pit.set_clk<0>(XTAL(16'000'000)/2/256);
+ pit.out_handler<0>().set(FUNC(ufo_state::pit_out0));
+ pit.set_clk<1>(XTAL(16'000'000)/2/256);
+ pit.out_handler<1>().set(FUNC(ufo_state::pit_out1));
+ pit.set_clk<2>(XTAL(16'000'000)/2/256);
+ pit.out_handler<2>().set(FUNC(ufo_state::pit_out2));
/* no video! */
diff --git a/src/mame/drivers/seta.cpp b/src/mame/drivers/seta.cpp
index 8777d9b3f41..9edde5eb618 100644
--- a/src/mame/drivers/seta.cpp
+++ b/src/mame/drivers/seta.cpp
@@ -8870,9 +8870,9 @@ MACHINE_CONFIG_START(seta_state::kamenrid)
MCFG_DEVICE_VBLANK_INT_DRIVER("screen", seta_state, irq2_line_assert)
WATCHDOG_TIMER(config, "watchdog");
- MCFG_DEVICE_ADD("pit", PIT8254, 0) // uPD71054C
- MCFG_PIT8253_CLK0(16000000/2/8)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, seta_state, pit_out0))
+ pit8254_device &pit(PIT8254(config, "pit", 0)); // uPD71054C
+ pit.set_clk<0>(16000000/2/8);
+ pit.out_handler<0>().set(FUNC(seta_state::pit_out0));
MCFG_DEVICE_ADD("spritegen", SETA001_SPRITE, 0)
MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
@@ -9044,9 +9044,9 @@ MACHINE_CONFIG_START(seta_state::madshark)
MCFG_DEVICE_PROGRAM_MAP(madshark_map)
MCFG_DEVICE_VBLANK_INT_DRIVER("screen", seta_state, irq2_line_assert)
- MCFG_DEVICE_ADD("pit", PIT8254, 0) // uPD71054C
- MCFG_PIT8253_CLK0(16000000/2/8)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, seta_state, pit_out0))
+ pit8254_device &pit(PIT8254(config, "pit", 0)); // uPD71054C
+ pit.set_clk<0>(16000000/2/8);
+ pit.out_handler<0>().set(FUNC(seta_state::pit_out0));
MCFG_DEVICE_ADD("spritegen", SETA001_SPRITE, 0)
MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
@@ -9096,9 +9096,9 @@ MACHINE_CONFIG_START(seta_state::magspeed)
MCFG_MACHINE_START_OVERRIDE(seta_state, magspeed)
- MCFG_DEVICE_ADD("pit", PIT8254, 0) // uPD71054C
- MCFG_PIT8253_CLK0(16000000/2/8)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, seta_state, pit_out0))
+ pit8254_device &pit(PIT8254(config, "pit", 0)); // uPD71054C
+ pit.set_clk<0>(16000000/2/8);
+ pit.out_handler<0>().set(FUNC(seta_state::pit_out0));
MCFG_DEVICE_ADD("spritegen", SETA001_SPRITE, 0)
MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
@@ -9139,9 +9139,9 @@ MACHINE_CONFIG_START(seta_state::msgundam)
MCFG_DEVICE_PROGRAM_MAP(msgundam_map)
MCFG_DEVICE_VBLANK_INT_DRIVER("screen", seta_state, irq2_line_assert)
- MCFG_DEVICE_ADD("pit", PIT8254, 0) // uPD71054C
- MCFG_PIT8253_CLK0(16000000/2/8)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, seta_state, pit_out0))
+ pit8254_device &pit(PIT8254(config, "pit", 0)); // uPD71054C
+ pit.set_clk<0>(16000000/2/8);
+ pit.out_handler<0>().set(FUNC(seta_state::pit_out0));
MCFG_DEVICE_ADD("spritegen", SETA001_SPRITE, 0)
MCFG_SETA001_SPRITE_GFXDECODE("gfxdecode")
diff --git a/src/mame/drivers/sm7238.cpp b/src/mame/drivers/sm7238.cpp
index 38170e09129..f7add03ba11 100644
--- a/src/mame/drivers/sm7238.cpp
+++ b/src/mame/drivers/sm7238.cpp
@@ -373,31 +373,31 @@ MACHINE_CONFIG_START(sm7238_state::sm7238)
MCFG_SCREEN_ADD("screen", RASTER)
MCFG_SCREEN_RAW_PARAMS(20.625_MHz_XTAL, KSM_TOTAL_HORZ, 0, KSM_DISP_HORZ, KSM_TOTAL_VERT, 0, KSM_DISP_VERT);
MCFG_SCREEN_UPDATE_DRIVER(sm7238_state, screen_update)
- MCFG_SCREEN_VBLANK_CALLBACK(WRITELINE("pic8259", pic8259_device, ir2_w))
+ MCFG_SCREEN_VBLANK_CALLBACK(WRITELINE(m_pic8259, pic8259_device, ir2_w))
MCFG_SCREEN_PALETTE("palette")
MCFG_PALETTE_ADD("palette", 3)
MCFG_PALETTE_INIT_OWNER(sm7238_state, sm7238)
MCFG_DEVICE_ADD("gfxdecode", GFXDECODE, "palette", gfx_sm7238)
- MCFG_DEVICE_ADD("pic8259", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE("maincpu", 0))
+ PIC8259(config, m_pic8259, 0);
+ m_pic8259->out_int_callback().set_inputline(m_maincpu, 0);
- MCFG_DEVICE_ADD("t_hblank", PIT8253, 0)
- MCFG_PIT8253_CLK1(16.384_MHz_XTAL/9) // XXX workaround -- keyboard is slower and doesn't sync otherwise
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(*this, sm7238_state, write_keyboard_clock))
+ PIT8253(config, m_t_hblank, 0);
+ m_t_hblank->set_clk<1>(16.384_MHz_XTAL/9); // XXX workaround -- keyboard is slower and doesn't sync otherwise
+ m_t_hblank->out_handler<1>().set(FUNC(sm7238_state::write_keyboard_clock));
- MCFG_DEVICE_ADD("t_vblank", PIT8253, 0)
- MCFG_PIT8253_CLK2(16.5888_MHz_XTAL/9)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, sm7238_state, write_printer_clock))
+ PIT8253(config, m_t_vblank, 0);
+ m_t_vblank->set_clk<2>(16.5888_MHz_XTAL/9);
+ m_t_vblank->out_handler<2>().set(FUNC(sm7238_state::write_printer_clock));
- MCFG_DEVICE_ADD("t_color", PIT8253, 0)
+ PIT8253(config, m_t_color, 0);
- MCFG_DEVICE_ADD("t_iface", PIT8253, 0)
- MCFG_PIT8253_CLK1(16.5888_MHz_XTAL/9)
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE("i8251line", i8251_device, write_txc))
- MCFG_PIT8253_CLK2(16.5888_MHz_XTAL/9)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE("i8251line", i8251_device, write_rxc))
+ PIT8253(config, m_t_iface, 0);
+ m_t_iface->set_clk<1>(16.5888_MHz_XTAL/9);
+ m_t_iface->out_handler<1>().set(m_i8251line, FUNC(i8251_device::write_txc));
+ m_t_iface->set_clk<2>(16.5888_MHz_XTAL/9);
+ m_t_iface->out_handler<2>().set(m_i8251line, FUNC(i8251_device::write_rxc));
// serial connection to host
I8251(config, m_i8251line, 0);
diff --git a/src/mame/drivers/snk.cpp b/src/mame/drivers/snk.cpp
index c30141723be..c4e21a84818 100644
--- a/src/mame/drivers/snk.cpp
+++ b/src/mame/drivers/snk.cpp
@@ -2644,6 +2644,11 @@ static INPUT_PORTS_START( ikarijpb )
// this is accomplished by hooking the joystick input to the rotary input, plus
// of course the code is patched to handle that.
+ // According to a SNK 40th Anniversary Collection screenshot, this bootleg
+ // came from Korea:
+ // "The idea for Guevara's use of tanks with a human torso poking out of the top
+ // came from a poorly-programmed Korean bootleg of Ikari."
+
PORT_MODIFY("IN1")
PORT_BIT( 0x21, 0x01, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
PORT_BIT( 0x42, 0x02, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
diff --git a/src/mame/drivers/special.cpp b/src/mame/drivers/special.cpp
index dced843e63e..677f90c8703 100644
--- a/src/mame/drivers/special.cpp
+++ b/src/mame/drivers/special.cpp
@@ -453,13 +453,13 @@ MACHINE_CONFIG_START(special_state::specimx)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "speaker", 1.0)
/* Devices */
- MCFG_DEVICE_ADD( "pit8253", PIT8253, 0)
- MCFG_PIT8253_CLK0(2000000)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE("custom", specimx_sound_device, set_input_ch0))
- MCFG_PIT8253_CLK1(2000000)
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE("custom", specimx_sound_device, set_input_ch1))
- MCFG_PIT8253_CLK2(2000000)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE("custom", specimx_sound_device, set_input_ch2))
+ PIT8253(config, m_pit, 0);
+ m_pit->set_clk<0>(2000000);
+ m_pit->out_handler<0>().set("custom", FUNC(specimx_sound_device::set_input_ch0));
+ m_pit->set_clk<1>(2000000);
+ m_pit->out_handler<1>().set("custom", FUNC(specimx_sound_device::set_input_ch1));
+ m_pit->set_clk<2>(2000000);
+ m_pit->out_handler<2>().set("custom", FUNC(specimx_sound_device::set_input_ch2));
m_ppi->in_pa_callback().set(FUNC(special_state::specialist_8255_porta_r));
m_ppi->out_pa_callback().set(FUNC(special_state::specialist_8255_porta_w));
diff --git a/src/mame/drivers/supbtime.cpp b/src/mame/drivers/supbtime.cpp
index 8ebc21e8bc1..b51ab746c59 100644
--- a/src/mame/drivers/supbtime.cpp
+++ b/src/mame/drivers/supbtime.cpp
@@ -356,19 +356,19 @@ MACHINE_CONFIG_START(supbtime_state::supbtime)
MCFG_PALETTE_ADD("palette", 1024)
MCFG_PALETTE_FORMAT(xxxxBBBBGGGGRRRR)
- MCFG_DEVICE_ADD("tilegen", DECO16IC, 0)
- MCFG_DECO16IC_SPLIT(0)
- MCFG_DECO16IC_PF1_SIZE(DECO_64x32)
- MCFG_DECO16IC_PF2_SIZE(DECO_64x32)
- MCFG_DECO16IC_PF1_TRANS_MASK(0x0f)
- MCFG_DECO16IC_PF2_TRANS_MASK(0x0f)
- MCFG_DECO16IC_PF1_COL_BANK(0x00)
- MCFG_DECO16IC_PF2_COL_BANK(0x10)
- MCFG_DECO16IC_PF1_COL_MASK(0x0f)
- MCFG_DECO16IC_PF2_COL_MASK(0x0f)
- MCFG_DECO16IC_PF12_8X8_BANK(0)
- MCFG_DECO16IC_PF12_16X16_BANK(1)
- MCFG_DECO16IC_GFXDECODE("gfxdecode")
+ DECO16IC(config, m_deco_tilegen, 0);
+ m_deco_tilegen->set_split(0);
+ m_deco_tilegen->set_pf1_size(DECO_64x32);
+ m_deco_tilegen->set_pf2_size(DECO_64x32);
+ m_deco_tilegen->set_pf1_trans_mask(0x0f);
+ m_deco_tilegen->set_pf2_trans_mask(0x0f);
+ m_deco_tilegen->set_pf1_col_bank(0x00);
+ m_deco_tilegen->set_pf2_col_bank(0x10);
+ m_deco_tilegen->set_pf1_col_mask(0x0f);
+ m_deco_tilegen->set_pf2_col_mask(0x0f);
+ m_deco_tilegen->set_pf12_8x8_bank(0);
+ m_deco_tilegen->set_pf12_16x16_bank(1);
+ m_deco_tilegen->set_gfxdecode_tag("gfxdecode");
MCFG_DEVICE_ADD("spritegen", DECO_SPRITE, 0)
MCFG_DECO_SPRITE_GFX_REGION(2)
@@ -393,6 +393,9 @@ MACHINE_CONFIG_START(supbtime_state::chinatwn)
supbtime(config);
MCFG_DEVICE_MODIFY("maincpu")
MCFG_DEVICE_PROGRAM_MAP(chinatwn_map)
+
+ MCFG_SCREEN_MODIFY("screen")
+ MCFG_SCREEN_UPDATE_DRIVER(supbtime_state, screen_update_chinatwn)
MACHINE_CONFIG_END
MACHINE_CONFIG_START(supbtime_state::tumblep)
@@ -436,8 +439,7 @@ ROM_START( supbtime )
ROM_LOAD("tg5.j1", 0x514, 0x104, CRC(21d02af7) SHA1(4b221a478cb3381e9551de770df7c491c5e59c90)) // PAL16L8
ROM_END
-// is this actually a good dump?, there are no backgrounds ingame!
-ROM_START( supbtimea )
+ROM_START( supbtimea ) // this set has no backgrounds ingame for most stages, but has been verifeid as good on multiple PCBs, design choice
ROM_REGION( 0x40000, "maincpu", 0 )
ROM_LOAD16_BYTE("3.11f", 0x00000, 0x20000, CRC(98b5f263) SHA1(ee4b0d2fcdc95aba0e78d066bd6c4d553a902848))
ROM_LOAD16_BYTE("4.12f", 0x00001, 0x20000, CRC(937e68b9) SHA1(4779e150518b9014c2154f33d38767c6a7447334))
diff --git a/src/mame/drivers/tandy2k.cpp b/src/mame/drivers/tandy2k.cpp
index 7aa830a52b3..8ff8ebd00f3 100644
--- a/src/mame/drivers/tandy2k.cpp
+++ b/src/mame/drivers/tandy2k.cpp
@@ -837,19 +837,19 @@ MACHINE_CONFIG_START(tandy2k_state::tandy2k)
// TODO pin 15 external transmit clock
// TODO pin 17 external receiver clock
- MCFG_DEVICE_ADD(I8253_TAG, PIT8253, 0)
- MCFG_PIT8253_CLK0(16_MHz_XTAL / 16)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, tandy2k_state, outspkr_w))
- MCFG_PIT8253_CLK1(16_MHz_XTAL / 8)
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(*this, tandy2k_state, intbrclk_w))
- //MCFG_PIT8253_CLK2(16_MHz_XTAL / 8)
- //MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, tandy2k_state, rfrqpulse_w))
-
- MCFG_DEVICE_ADD(I8259A_0_TAG, PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(WRITELINE(I80186_TAG, i80186_cpu_device, int0_w))
-
- MCFG_DEVICE_ADD(I8259A_1_TAG, PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(WRITELINE(I80186_TAG, i80186_cpu_device, int1_w))
+ PIT8253(config, m_pit, 0);
+ m_pit->set_clk<0>(16_MHz_XTAL / 16);
+ m_pit->out_handler<0>().set(FUNC(tandy2k_state::outspkr_w));
+ m_pit->set_clk<1>(16_MHz_XTAL / 8);
+ m_pit->out_handler<1>().set(FUNC(tandy2k_state::intbrclk_w));
+ //m_pit->set_clk<2>(16_MHz_XTAL / 8);
+ //m_pit->out_handler<2>().set(FUNC(tandy2k_state::rfrqpulse_w));
+
+ PIC8259(config, m_pic0, 0);
+ m_pic0->out_int_callback().set(m_maincpu, FUNC(i80186_cpu_device::int0_w));
+
+ PIC8259(config, m_pic1, 0);
+ m_pic1->out_int_callback().set(m_maincpu, FUNC(i80186_cpu_device::int1_w));
I8272A(config, m_fdc, true);
m_fdc->set_select_lines_connected(true);
diff --git a/src/mame/drivers/tdv2324.cpp b/src/mame/drivers/tdv2324.cpp
index 55004c681f9..3864743ee6b 100644
--- a/src/mame/drivers/tdv2324.cpp
+++ b/src/mame/drivers/tdv2324.cpp
@@ -289,11 +289,11 @@ MACHINE_CONFIG_START(tdv2324_state::tdv2324)
TMS9927(config, m_tms, 25.39836_MHz_XTAL / 8).set_char_width(8);
// devices
- MCFG_DEVICE_ADD(P8259A_TAG, PIC8259, 0)
+ PIC8259(config, m_pic, 0);
- MCFG_DEVICE_ADD(P8253_5_0_TAG, PIT8253, 0)
+ PIT8253(config, m_pit0, 0);
- MCFG_DEVICE_ADD(P8253_5_1_TAG, PIT8253, 0)
+ PIT8253(config, m_pit1, 0);
Z80SIO2(config, MK3887N4_TAG, 8000000/2);
diff --git a/src/mame/drivers/tiamc1.cpp b/src/mame/drivers/tiamc1.cpp
index 20dcb203f5e..46cf544749b 100644
--- a/src/mame/drivers/tiamc1.cpp
+++ b/src/mame/drivers/tiamc1.cpp
@@ -372,10 +372,10 @@ MACHINE_CONFIG_START(tiamc1_state::kot)
MCFG_DEVICE_ADD("speaker", SPEAKER_SOUND)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
- MCFG_DEVICE_ADD("pit8253", PIT8253, 0)
- MCFG_PIT8253_CLK0(PIXEL_CLOCK / 4)
- MCFG_PIT8253_CLK2(SND_CLOCK) // guess
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, tiamc1_state, pit8253_2_w))
+ pit8253_device &pit8253(PIT8253(config, "pit8253", 0));
+ pit8253.set_clk<0>(PIXEL_CLOCK / 4);
+ pit8253.set_clk<2>(SND_CLOCK); // guess
+ pit8253.out_handler<2>().set(FUNC(tiamc1_state::pit8253_2_w));
MACHINE_CONFIG_END
diff --git a/src/mame/drivers/tsispch.cpp b/src/mame/drivers/tsispch.cpp
index a6fe540acc3..468b4971d8f 100644
--- a/src/mame/drivers/tsispch.cpp
+++ b/src/mame/drivers/tsispch.cpp
@@ -372,10 +372,10 @@ INPUT_PORTS_END
MACHINE_CONFIG_START(tsispch_state::prose2k)
/* basic machine hardware */
/* There are two crystals on the board: a 24MHz xtal at Y2 and a 16MHz xtal at Y1 */
- MCFG_DEVICE_ADD("maincpu", I8086, 8000000) /* VERIFIED clock, unknown divider */
- MCFG_DEVICE_PROGRAM_MAP(i8086_mem)
- MCFG_DEVICE_IO_MAP(i8086_io)
- MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE("pic8259", pic8259_device, inta_cb)
+ I8086(config, m_maincpu, 8000000); /* VERIFIED clock, unknown divider */
+ m_maincpu->set_addrmap(AS_PROGRAM, &tsispch_state::i8086_mem);
+ m_maincpu->set_addrmap(AS_IO, &tsispch_state::i8086_io);
+ m_maincpu->set_irq_acknowledge_callback("pic8259", FUNC(pic8259_device::inta_cb));
/* TODO: the UPD7720 has a 10KHz clock to its INT pin */
/* TODO: the UPD7720 has a 2MHz clock to its SCK pin */
@@ -387,8 +387,8 @@ MACHINE_CONFIG_START(tsispch_state::prose2k)
MCFG_NECDSP_OUT_P1_CB(WRITELINE(*this, tsispch_state, dsp_to_8086_p1_w))
/* PIC 8259 */
- MCFG_DEVICE_ADD("pic8259", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE("maincpu", 0))
+ PIC8259(config, m_pic, 0);
+ m_pic->out_int_callback().set_inputline(m_maincpu, 0);
/* uarts */
i8251_device &u15(I8251(config, "i8251a_u15", 0));
diff --git a/src/mame/drivers/unistar.cpp b/src/mame/drivers/unistar.cpp
index bca0b614de4..5f75c99aa0c 100644
--- a/src/mame/drivers/unistar.cpp
+++ b/src/mame/drivers/unistar.cpp
@@ -66,8 +66,7 @@ void unistar_state::unistar_mem(address_map &map)
void unistar_state::unistar_io(address_map &map)
{
- //ADDRESS_MAP_UNMAP_HIGH
- map.global_mask(0xff);
+ //map.unmap_value_high();
map(0x00, 0x0f).rw("dmac", FUNC(am9517a_device::read), FUNC(am9517a_device::write));
map(0x84, 0x84).portr("CONFIG");
map(0x8c, 0x8d).rw("stc", FUNC(am9513_device::read8), FUNC(am9513_device::write8));
diff --git a/src/mame/drivers/vector06.cpp b/src/mame/drivers/vector06.cpp
index 31a70bfdd08..2c3a529ea90 100644
--- a/src/mame/drivers/vector06.cpp
+++ b/src/mame/drivers/vector06.cpp
@@ -217,13 +217,13 @@ MACHINE_CONFIG_START(vector06_state::vector06)
MCFG_DEVICE_ADD("speaker", SPEAKER_SOUND)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
- MCFG_DEVICE_ADD("pit8253", PIT8253, 0)
- MCFG_PIT8253_CLK0(1500000)
- MCFG_PIT8253_CLK1(1500000)
- MCFG_PIT8253_CLK2(1500000)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, vector06_state, speaker_w))
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(*this, vector06_state, speaker_w))
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, vector06_state, speaker_w))
+ PIT8253(config, m_pit8253, 0);
+ m_pit8253->set_clk<0>(1500000);
+ m_pit8253->set_clk<1>(1500000);
+ m_pit8253->set_clk<2>(1500000);
+ m_pit8253->out_handler<0>().set(FUNC(vector06_state::speaker_w));
+ m_pit8253->out_handler<1>().set(FUNC(vector06_state::speaker_w));
+ m_pit8253->out_handler<2>().set(FUNC(vector06_state::speaker_w));
// optional
MCFG_DEVICE_ADD("aysnd", AY8910, 1773400)
diff --git a/src/mame/drivers/vertigo.cpp b/src/mame/drivers/vertigo.cpp
index e86dd8999bc..1dd61368b7a 100644
--- a/src/mame/drivers/vertigo.cpp
+++ b/src/mame/drivers/vertigo.cpp
@@ -127,18 +127,18 @@ MACHINE_CONFIG_START(vertigo_state::vertigo)
MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
- MCFG_DEVICE_ADD("pit", PIT8254, 0)
- MCFG_PIT8253_CLK0(24_MHz_XTAL / 100)
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, vertigo_state, v_irq4_w))
- MCFG_PIT8253_CLK1(24_MHz_XTAL / 100)
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(*this, vertigo_state, v_irq3_w))
- MCFG_PIT8253_CLK2(24_MHz_XTAL / 100)
+ pit8254_device &pit(PIT8254(config, "pit", 0));
+ pit.set_clk<0>(24_MHz_XTAL / 100);
+ pit.out_handler<0>().set(FUNC(vertigo_state::v_irq4_w));
+ pit.set_clk<1>(24_MHz_XTAL / 100);
+ pit.out_handler<1>().set(FUNC(vertigo_state::v_irq3_w));
+ pit.set_clk<2>(24_MHz_XTAL / 100);
TTL74148(config, m_ttl74148, 0);
m_ttl74148->out_cb().set(FUNC(vertigo_state::update_irq));
/* motor controller */
- MCFG_DEVICE_ADD("motorcpu", M68705P3, 24_MHz_XTAL / 6)
+ M68705P3(config, "motorcpu", 24_MHz_XTAL / 6);
NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0);
diff --git a/src/mame/drivers/wacky_gator.cpp b/src/mame/drivers/wacky_gator.cpp
index 158aa458af8..9b5939616f9 100644
--- a/src/mame/drivers/wacky_gator.cpp
+++ b/src/mame/drivers/wacky_gator.cpp
@@ -36,8 +36,7 @@ public:
driver_device(mconfig, type, tag),
m_maincpu(*this, "maincpu"),
m_msm(*this, "msm"),
- m_pit8253_0(*this, "pit8253_0"),
- m_pit8253_1(*this, "pit8253_1"),
+ m_pit8253(*this, "pit8253%u", 0U),
m_ticket(*this, "ticket"),
m_samples(*this, "oki"),
m_alligator(*this, "alligator%u", 0U),
@@ -78,8 +77,7 @@ private:
required_device<cpu_device> m_maincpu;
required_device<msm5205_device> m_msm;
- required_device<pit8253_device> m_pit8253_0;
- required_device<pit8253_device> m_pit8253_1;
+ required_device_array<pit8253_device, 2> m_pit8253;
required_device<ticket_dispenser_device> m_ticket;
required_memory_region m_samples;
output_finder<5> m_alligator;
@@ -126,11 +124,11 @@ WRITE8_MEMBER(wackygtr_state::sample_ctrl_w)
WRITE8_MEMBER(wackygtr_state::alligators_ctrl1_w)
{
- m_pit8253_0->write_gate0(BIT(data, 0));
- m_pit8253_0->write_gate1(BIT(data, 1));
- m_pit8253_0->write_gate2(BIT(data, 2));
- m_pit8253_1->write_gate1(BIT(data, 3));
- m_pit8253_1->write_gate2(BIT(data, 4));
+ m_pit8253[0]->write_gate0(BIT(data, 0));
+ m_pit8253[0]->write_gate1(BIT(data, 1));
+ m_pit8253[0]->write_gate2(BIT(data, 2));
+ m_pit8253[1]->write_gate1(BIT(data, 3));
+ m_pit8253[1]->write_gate2(BIT(data, 4));
machine().bookkeeping().coin_lockout_w(0, data & 0x40 ? 0 : 1);
}
@@ -272,8 +270,8 @@ void wackygtr_state::program_map(address_map &map)
map(0x1000, 0x1001).w("ymsnd", FUNC(ym2413_device::write));
- map(0x2000, 0x2003).rw(m_pit8253_0, FUNC(pit8253_device::read), FUNC(pit8253_device::write));
- map(0x3000, 0x3003).rw(m_pit8253_1, FUNC(pit8253_device::read), FUNC(pit8253_device::write));
+ map(0x2000, 0x2003).rw(m_pit8253[0], FUNC(pit8253_device::read), FUNC(pit8253_device::write));
+ map(0x3000, 0x3003).rw(m_pit8253[1], FUNC(pit8253_device::read), FUNC(pit8253_device::write));
map(0x4000, 0x4003).rw("i8255_0", FUNC(i8255_device::read), FUNC(i8255_device::write));
map(0x5000, 0x5003).rw("i8255_1", FUNC(i8255_device::read), FUNC(i8255_device::write));
@@ -319,21 +317,21 @@ MACHINE_CONFIG_START(wackygtr_state::wackygtr)
ppi2.in_pb_callback().set_ioport("IN1");
ppi2.in_pc_callback().set_ioport("IN2");
- MCFG_DEVICE_ADD("pit8253_0", PIT8253, 0)
- MCFG_PIT8253_CLK0(XTAL(3'579'545)/16) // this is a guess
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, wackygtr_state, alligator_ck<0>))
- MCFG_PIT8253_CLK1(XTAL(3'579'545)/16) // this is a guess
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(*this, wackygtr_state, alligator_ck<1>))
- MCFG_PIT8253_CLK2(XTAL(3'579'545)/16) // this is a guess
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, wackygtr_state, alligator_ck<2>))
-
- MCFG_DEVICE_ADD("pit8253_1", PIT8253, 0)
- MCFG_PIT8253_CLK0(XTAL(3'579'545)/16) // this is a guess
- MCFG_PIT8253_OUT0_HANDLER(INPUTLINE("maincpu", M6809_FIRQ_LINE))
- MCFG_PIT8253_CLK1(XTAL(3'579'545)/16) // this is a guess
- MCFG_PIT8253_OUT1_HANDLER(WRITELINE(*this, wackygtr_state, alligator_ck<3>))
- MCFG_PIT8253_CLK2(XTAL(3'579'545)/16) // this is a guess
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, wackygtr_state, alligator_ck<4>))
+ PIT8253(config, m_pit8253[0], 0);
+ m_pit8253[0]->set_clk<0>(XTAL(3'579'545)/16); // this is a guess
+ m_pit8253[0]->out_handler<0>().set(FUNC(wackygtr_state::alligator_ck<0>));
+ m_pit8253[0]->set_clk<1>(XTAL(3'579'545)/16); // this is a guess
+ m_pit8253[0]->out_handler<1>().set(FUNC(wackygtr_state::alligator_ck<1>));
+ m_pit8253[0]->set_clk<2>(XTAL(3'579'545)/16); // this is a guess
+ m_pit8253[0]->out_handler<2>().set(FUNC(wackygtr_state::alligator_ck<2>));
+
+ PIT8253(config, m_pit8253[1], 0);
+ m_pit8253[1]->set_clk<0>(XTAL(3'579'545)/16); // this is a guess
+ m_pit8253[1]->out_handler<0>().set_inputline(m_maincpu, M6809_FIRQ_LINE);
+ m_pit8253[1]->set_clk<1>(XTAL(3'579'545)/16); // this is a guess
+ m_pit8253[1]->out_handler<1>().set(FUNC(wackygtr_state::alligator_ck<3>));
+ m_pit8253[1]->set_clk<2>(XTAL(3'579'545)/16); // this is a guess
+ m_pit8253[1]->out_handler<2>().set(FUNC(wackygtr_state::alligator_ck<4>));
MCFG_TICKET_DISPENSER_ADD("ticket", attotime::from_msec(200), TICKET_MOTOR_ACTIVE_HIGH, TICKET_STATUS_ACTIVE_HIGH)
MACHINE_CONFIG_END
diff --git a/src/mame/drivers/williams.cpp b/src/mame/drivers/williams.cpp
index 73e3e4fe971..2ba3b356a38 100644
--- a/src/mame/drivers/williams.cpp
+++ b/src/mame/drivers/williams.cpp
@@ -2121,32 +2121,32 @@ ROM_END
// The dumps of ROMs 1, 2, 3 were bad, but the dumper observed that using the defenderb ROMs the emulation behaves identically to the PCB.
// A redump is definitely needed:
-// 1.bin [1/2] wb01.bin [1/2] IDENTICAL
-// 2.bin [1/2] defeng02.bin [1/2] IDENTICAL
-// 1.bin [2/2] wb01.bin [1/2] IDENTICAL
-// 2.bin [2/2] defeng02.bin [1/2] IDENTICAL
-// 3ojo.bin [2/2] wb03.bin [1/2] IDENTICAL
-// 3ojo.bin [1/2] defend.11 2.197266%
+// 002-1.ic1 [1/2] wb01.bin [1/2] IDENTICAL
+// 002-2.ic2 [1/2] defeng02.bin [1/2] IDENTICAL
+// 002-1.ic1 [2/2] wb01.bin [1/2] IDENTICAL
+// 002-2.ic2 [2/2] defeng02.bin [1/2] IDENTICAL
+// 002-3.ic3 [2/2] wb03.bin [1/2] IDENTICAL
+// 002-3.ic3 [1/2] defend.11 2.197266%
// For now we use the defenderb ones.
// PCBs: FAMARESA 590-001, 590-002, 590-003, 590-004
ROM_START( attackf )
ROM_REGION( 0x19000, "maincpu", 0 )
- ROM_LOAD( "1.bin", 0x0d000, 0x1000, BAD_DUMP CRC(0ee1019d) SHA1(a76247e825b8267abfd195c12f96348fe10d4cbc) )
- ROM_LOAD( "2.bin", 0x0e000, 0x1000, BAD_DUMP CRC(d184ab6b) SHA1(ed61a95b04f6162aedba8a72bc46005b77283955) )
- ROM_LOAD( "3ojo.bin", 0x0f000, 0x1000, BAD_DUMP CRC(a732d649) SHA1(b681882c02c5870ad613edc77255969a5f796422) )
- ROM_LOAD( "9.bin", 0x10000, 0x0800, CRC(f57caa62) SHA1(c8c91b96fd3bc98eddcc1503159050dae5755001) )
- ROM_LOAD( "12.bin", 0x10800, 0x0800, CRC(eb73d8a1) SHA1(f26007839a9eff6c7f77768da150fa26b8c96643) )
- ROM_LOAD( "8.bin", 0x11000, 0x0800, CRC(17f7abde) SHA1(6959ed471687174a3fdc3f980ca7bd993b23d54f) )
- ROM_LOAD( "11.bin", 0x11800, 0x0800, CRC(5ca4e860) SHA1(031188c009b8fca92703a0cc0c2bb44976212ae9) )
- ROM_LOAD( "7.bin", 0x12000, 0x0800, CRC(545c3326) SHA1(98199df5206c261061b0108c68ab9128fa0779eb) )
- ROM_LOAD( "10.bin", 0x12800, 0x0800, CRC(3940d731) SHA1(c867efa48e3ed6a6c3ddcd519aba1fe0a1712400) )
- ROM_LOAD( "6.bin", 0x16000, 0x0800, CRC(3af34c05) SHA1(71f3ced06a373fa4805c856bd9fc97760787a920) )
+ ROM_LOAD( "002-1.ic1", 0x0d000, 0x1000, BAD_DUMP CRC(0ee1019d) SHA1(a76247e825b8267abfd195c12f96348fe10d4cbc) )
+ ROM_LOAD( "002-2.ic2", 0x0e000, 0x1000, BAD_DUMP CRC(d184ab6b) SHA1(ed61a95b04f6162aedba8a72bc46005b77283955) )
+ ROM_LOAD( "002-3.ic3", 0x0f000, 0x1000, BAD_DUMP CRC(a732d649) SHA1(b681882c02c5870ad613edc77255969a5f796422) )
+ ROM_LOAD( "002-9.ic12", 0x10000, 0x0800, CRC(f57caa62) SHA1(c8c91b96fd3bc98eddcc1503159050dae5755001) )
+ ROM_LOAD( "002-12.ic9", 0x10800, 0x0800, CRC(eb73d8a1) SHA1(f26007839a9eff6c7f77768da150fa26b8c96643) )
+ ROM_LOAD( "002-8.ic11", 0x11000, 0x0800, CRC(17f7abde) SHA1(6959ed471687174a3fdc3f980ca7bd993b23d54f) )
+ ROM_LOAD( "002-11.ic8", 0x11800, 0x0800, CRC(5ca4e860) SHA1(031188c009b8fca92703a0cc0c2bb44976212ae9) )
+ ROM_LOAD( "002-7.ic10", 0x12000, 0x0800, CRC(545c3326) SHA1(98199df5206c261061b0108c68ab9128fa0779eb) )
+ ROM_LOAD( "002-10.ic7", 0x12800, 0x0800, CRC(3940d731) SHA1(c867efa48e3ed6a6c3ddcd519aba1fe0a1712400) )
+ ROM_LOAD( "002-6.ic6", 0x16000, 0x0800, CRC(3af34c05) SHA1(71f3ced06a373fa4805c856bd9fc97760787a920) )
ROM_REGION( 0x10000, "soundcpu", 0 )
- ROM_LOAD( "13.bin", 0xf800, 0x0800, CRC(fefd5b48) SHA1(ceb0d18483f0691978c604db94417e6941ad7ff2) )
+ ROM_LOAD( "003-13.ic12", 0xf800, 0x0800, CRC(fefd5b48) SHA1(ceb0d18483f0691978c604db94417e6941ad7ff2) )
ROM_REGION( 0x0200, "proms", 0 )
- ROM_LOAD( "decoder.1", 0x0000, 0x0200, CRC(8dd98da5) SHA1(da979604f7a2aa8b5a6d4a5debd2e80f77569e35) ) // not dumped from this PCB, believed to match
+ ROM_LOAD( "001-14.g1", 0x0000, 0x0200, BAD_DUMP CRC(8dd98da5) SHA1(da979604f7a2aa8b5a6d4a5debd2e80f77569e35) ) // not dumped from this PCB, believed to match
ROM_END
ROM_START( galwars2 ) // 2 board stack: CPU and ROM boards
@@ -3336,8 +3336,8 @@ GAME( 1980, zero2, defender, defender, defender, williams_state, init
GAME( 1980, defcmnd, defender, defender, defender, williams_state, init_defender, ROT0, "bootleg", "Defense Command (Defender bootleg)", MACHINE_SUPPORTS_SAVE )
GAME( 1981, defence, defender, defender, defender, williams_state, init_defender, ROT0, "bootleg (Outer Limits)", "Defence Command (Defender bootleg)", MACHINE_SUPPORTS_SAVE )
GAME( 1981, startrkd, defender, defender, defender, williams_state, init_defender, ROT0, "bootleg", "Star Trek (Defender bootleg)", MACHINE_SUPPORTS_SAVE )
-GAME( 1980, attackf, defender, defender, defender, williams_state, init_defender, ROT0, "bootleg (Famare SA)", "Attack (Defender bootleg)", MACHINE_SUPPORTS_SAVE )
-GAME( 1981, galwars2, defender, defender, defender, williams_state, init_defender, ROT0, "bootleg (Sonic)", "Galaxy Wars II (Defender bootleg)", MACHINE_SUPPORTS_SAVE ) // Sega Sonic - Sega Sa, only displays Sonic on title screen
+GAME( 1980, attackf, defender, defender, defender, williams_state, init_defender, ROT0, "bootleg (FAMARE S.A.)", "Attack (Defender bootleg)", MACHINE_SUPPORTS_SAVE )
+GAME( 1981, galwars2, defender, defender, defender, williams_state, init_defender, ROT0, "bootleg (Sonic)", "Galaxy Wars II (Defender bootleg)", MACHINE_SUPPORTS_SAVE ) // Sega Sonic - Sega S.A., only displays Sonic on title screen
GAME( 1980, mayday, 0, defender, mayday, williams_state, init_mayday, ROT0, "Hoei", "Mayday (set 1)", MACHINE_SUPPORTS_SAVE | MACHINE_UNEMULATED_PROTECTION ) // \ original by Hoei, which one of these 3 sets is bootleg/licensed/original is unknown
GAME( 1980, maydaya, mayday, defender, mayday, williams_state, init_mayday, ROT0, "Hoei", "Mayday (set 2)", MACHINE_SUPPORTS_SAVE | MACHINE_UNEMULATED_PROTECTION ) // > these games have an unemulated protection chip of some sort which is hacked around in /machine/williams.cpp "mayday_protection_r" function
diff --git a/src/mame/drivers/wswan.cpp b/src/mame/drivers/wswan.cpp
index a16a42503f9..abd46b66060 100644
--- a/src/mame/drivers/wswan.cpp
+++ b/src/mame/drivers/wswan.cpp
@@ -193,12 +193,12 @@ MACHINE_CONFIG_END
ROM_START( wswan )
ROM_REGION( 0x100000, "maincpu", ROMREGION_ERASEFF )
-// ROM_LOAD_OPTIONAL( "ws_bios.bin", 0x0000, 0x0001, NO_DUMP )
+// ROM_LOAD( "ws_bios.bin", 0x0000, 0x0001, NO_DUMP )
ROM_END
ROM_START( wscolor )
ROM_REGION( 0x100000, "maincpu", ROMREGION_ERASEFF )
-// ROM_LOAD_OPTIONAL( "wsc_bios.bin", 0x0000, 0x0001, NO_DUMP )
+// ROM_LOAD( "wsc_bios.bin", 0x0000, 0x0001, NO_DUMP )
ROM_END
// YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME
diff --git a/src/mame/drivers/xavix.cpp b/src/mame/drivers/xavix.cpp
index 8c3b047954d..40e4cea5d18 100644
--- a/src/mame/drivers/xavix.cpp
+++ b/src/mame/drivers/xavix.cpp
@@ -417,9 +417,9 @@ void xavix_state::xavix_lowbus_map(address_map &map)
//map(7b82, 7b83)
// Timer control
- map(0x7c00, 0x7c00).w(FUNC(xavix_state::timer_control_w));
+ map(0x7c00, 0x7c00).rw(FUNC(xavix_state::timer_status_r), FUNC(xavix_state::timer_control_w));
map(0x7c01, 0x7c01).rw(FUNC(xavix_state::timer_baseval_r), FUNC(xavix_state::timer_baseval_w)); // r/w tested
- map(0x7c02, 0x7c02).w(FUNC(xavix_state::timer_freq_w));
+ map(0x7c02, 0x7c02).rw(FUNC(xavix_state::timer_freq_r), FUNC(xavix_state::timer_freq_w));
// Barrel Shifter registers
// map(0x7ff0, 0x7ff1)
@@ -540,7 +540,7 @@ static INPUT_PORTS_START( rad_mtrk )
PORT_MODIFY("IN1")
PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_NAME("Horn")
- PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_SERVICE1 ) // some kind of 'power off' (fades screen to black, jumps to an infinite loop) maybe low battery condition or just the power button?
+ PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_POWER_OFF ) PORT_NAME("Power Switch") // pressing this will turn the game off.
INPUT_PORTS_END
static INPUT_PORTS_START( rad_mtrkp )
@@ -612,6 +612,14 @@ static INPUT_PORTS_START( rad_bass )
INPUT_PORTS_END
+static INPUT_PORTS_START( ekara )
+ PORT_INCLUDE(xavix)
+
+ PORT_MODIFY("IN1")
+ PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_POWER_OFF ) PORT_NAME("Power Switch") // pressing this will turn the game off.
+
+INPUT_PORTS_END
+
static INPUT_PORTS_START( rad_bassp )
PORT_INCLUDE(rad_bass)
@@ -638,6 +646,24 @@ static INPUT_PORTS_START( rad_snowp )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_CUSTOM )
INPUT_PORTS_END
+static INPUT_PORTS_START( rad_ping )
+ PORT_INCLUDE(xavix)
+
+ PORT_MODIFY("IN0")
+ PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_NAME("Select?")
+ PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_NAME("Pause?")
+ PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP )
+ PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN )
+ PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_SERVICE ) // resets? not a real button?
+
+ PORT_MODIFY("IN1") // are these for the 2nd player?
+ //PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_NAME("Pause?")
+ //PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP )
+ //PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN )
+ //PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_SERVICE ) // resets? not a real button?
+ PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_POWER_OFF ) PORT_NAME("Power Switch") // pressing this will turn the game off.
+INPUT_PORTS_END
+
static INPUT_PORTS_START( namcons2 )
PORT_INCLUDE(xavix)
@@ -695,8 +721,13 @@ CUSTOM_INPUT_MEMBER( xavix_state::rad_rh_in1_08_r )
static INPUT_PORTS_START( rad_rh )
PORT_INCLUDE(xavix)
+ PORT_MODIFY("IN0") // hold Button1+2 when resetting for a version number
+ PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_BUTTON1 )
+ PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON2 )
+
PORT_MODIFY("IN1")
PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_CUSTOM ) PORT_CUSTOM_MEMBER(DEVICE_SELF, xavix_state,rad_rh_in1_08_r, (void *)0)
+ PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_POWER_OFF ) PORT_NAME("Power Switch") // pressing this will turn the game off.
INPUT_PORTS_END
/* correct, 4bpp gfxs */
@@ -837,6 +868,39 @@ MACHINE_CONFIG_START(xavix_state::xavix2000_i2c_24c02)
I2CMEM(config, "i2cmem", 0).set_page_size(16).set_data_size(0x100); // 24C02
MACHINE_CONFIG_END
+
+
+DEVICE_IMAGE_LOAD_MEMBER( xavix_ekara_state, ekara_cart )
+{
+ uint32_t size = m_cart->common_get_size("rom");
+ std::vector<uint8_t> temp;
+ temp.resize(size);
+ m_cart->rom_alloc(size, GENERIC_ROM8_WIDTH, ENDIANNESS_LITTLE);
+ m_cart->common_load_rom(&temp[0], size, "rom");
+
+ memcpy(memregion("bios")->base(), &temp[0], size);
+
+ return image_init_result::PASS;
+}
+
+
+MACHINE_CONFIG_START(xavix_ekara_state::xavix_ekara)
+ xavix(config);
+
+ MCFG_GENERIC_CARTSLOT_ADD("cartslot", generic_plain_slot, "ekara_cart")
+ MCFG_GENERIC_EXTENSIONS("bin")
+ MCFG_GENERIC_WIDTH(GENERIC_ROM8_WIDTH)
+ MCFG_GENERIC_LOAD(xavix_ekara_state, ekara_cart)
+
+ /* software lists */
+ MCFG_SOFTWARE_LIST_ADD("cart_list","ekara")
+
+MACHINE_CONFIG_END
+
+
+
+
+
void xavix_state::init_xavix()
{
m_rgnlen = memregion("bios")->bytes();
@@ -956,34 +1020,12 @@ ROM_END
it etc.
*/
-#define EKARA_BASE_ROM \
- ROM_LOAD( "ekara.bin", 0x600000, 0x100000, CRC(9b27c4a2) SHA1(d75dda7434933135d2f7e353840a9384e9a0d586) )
-
-
-ROM_START( eka_base )
+ROM_START( ekara )
ROM_REGION( 0x800000, "bios", ROMREGION_ERASE00 )
- EKARA_BASE_ROM
+ ROM_LOAD( "ekara.bin", 0x600000, 0x100000, CRC(9b27c4a2) SHA1(d75dda7434933135d2f7e353840a9384e9a0d586) )
ROM_RELOAD(0x000000, 0x100000)
ROM_END
-ROM_START( eka_strt )
- ROM_REGION( 0x800000, "bios", ROMREGION_ERASE00 )
- EKARA_BASE_ROM
- ROM_LOAD( "ekarastartcart.bin", 0x000000, 0x080000, CRC(8c12c0c2) SHA1(8cc1b098894af25a4bfccada884125b66f5fe8b2) )
-ROM_END
-
-ROM_START( eka_vol1 )
- ROM_REGION( 0x800000, "bios", ROMREGION_ERASE00 )
- EKARA_BASE_ROM
- ROM_LOAD( "ekaravol1.bin", 0x000000, 0x100000, CRC(29df4aea) SHA1(b95835aaf8630b61b47e5da0968cd4a1dd3bc517) )
-ROM_END
-
-ROM_START( eka_vol2 )
- ROM_REGION( 0x800000, "bios", ROMREGION_ERASE00 )
- EKARA_BASE_ROM
- ROM_LOAD( "ekaravol2.bin", 0x000000, 0x100000, CRC(6c66772e) SHA1(e1e719df1e51caaafd9b3af187059334f7abbba3) )
-ROM_END
-
ROM_START( has_wamg )
ROM_REGION( 0x400000, "bios", ROMREGION_ERASE00 )
ROM_LOAD( "minigolf.bin", 0x000000, 0x400000, CRC(35cee2ad) SHA1(c7344e8ba336bc329638485ea571cd731ebf7649) )
@@ -991,51 +1033,45 @@ ROM_END
/* Standalone TV Games */
-CONS( 2006, taitons1, 0, 0, xavix_i2c_24lc04, namcons2, xavix_state, init_xavix, "Bandai / SSD Company LTD / Taito", "Let's! TV Play Classic - Taito Nostalgia 1", MACHINE_IS_SKELETON )
+CONS( 2006, taitons1, 0, 0, xavix_i2c_24lc04, namcons2, xavix_state, init_xavix, "Bandai / SSD Company LTD / Taito", "Let's! TV Play Classic - Taito Nostalgia 1", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND )
-CONS( 2006, taitons2, 0, 0, xavix_i2c_24lc04, namcons2, xavix_state, init_xavix, "Bandai / SSD Company LTD / Taito", "Let's! TV Play Classic - Taito Nostalgia 2", MACHINE_IS_SKELETON )
+CONS( 2006, taitons2, 0, 0, xavix_i2c_24lc04, namcons2, xavix_state, init_xavix, "Bandai / SSD Company LTD / Taito", "Let's! TV Play Classic - Taito Nostalgia 2", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND )
-CONS( 2006, namcons1, 0, 0, xavix_i2c_24lc04, namcons2, xavix_state, init_xavix, "Bandai / SSD Company LTD / Namco", "Let's! TV Play Classic - Namco Nostalgia 1", MACHINE_IS_SKELETON )
+CONS( 2006, namcons1, 0, 0, xavix_i2c_24lc04, namcons2, xavix_state, init_xavix, "Bandai / SSD Company LTD / Namco", "Let's! TV Play Classic - Namco Nostalgia 1", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND )
-CONS( 2006, namcons2, 0, 0, xavix_i2c_24lc04, namcons2, xavix_state, init_xavix, "Bandai / SSD Company LTD / Namco", "Let's! TV Play Classic - Namco Nostalgia 2", MACHINE_IS_SKELETON )
+CONS( 2006, namcons2, 0, 0, xavix_i2c_24lc04, namcons2, xavix_state, init_xavix, "Bandai / SSD Company LTD / Namco", "Let's! TV Play Classic - Namco Nostalgia 2", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND )
-CONS( 2000, rad_ping, 0, 0, xavix, xavix, xavix_state, init_xavix, "Radica / SSD Company LTD / Simmer Technology", "Play TV Ping Pong", MACHINE_IS_SKELETON ) // "Simmer Technology" is also known as "Hummer Technology Co., Ltd"
+CONS( 2000, rad_ping, 0, 0, xavix, rad_ping, xavix_state, init_xavix, "Radica / SSD Company LTD / Simmer Technology", "Play TV Ping Pong", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND ) // "Simmer Technology" is also known as "Hummer Technology Co., Ltd"
-CONS( 2003, rad_mtrk, 0, 0, xavix, rad_mtrk, xavix_state, init_xavix, "Radica / SSD Company LTD", "Play TV Monster Truck (NTSC)", MACHINE_IS_SKELETON )
-CONS( 2003, rad_mtrkp, rad_mtrk, 0, xavixp, rad_mtrkp,xavix_state, init_xavix, "Radica / SSD Company LTD", "ConnecTV Monster Truck (PAL)", MACHINE_IS_SKELETON )
+CONS( 2003, rad_mtrk, 0, 0, xavix, rad_mtrk, xavix_state, init_xavix, "Radica / SSD Company LTD", "Play TV Monster Truck (NTSC)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND )
+CONS( 2003, rad_mtrkp, rad_mtrk, 0, xavixp, rad_mtrkp,xavix_state, init_xavix, "Radica / SSD Company LTD", "ConnecTV Monster Truck (PAL)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND )
-CONS( 200?, rad_box, 0, 0, xavix, rad_box, xavix_state, init_xavix, "Radica / SSD Company LTD", "Play TV Boxing (NTSC)", MACHINE_IS_SKELETON)
-CONS( 200?, rad_boxp, rad_box, 0, xavixp, rad_boxp, xavix_state, init_xavix, "Radica / SSD Company LTD", "ConnecTV Boxing (PAL)", MACHINE_IS_SKELETON)
+CONS( 200?, rad_box, 0, 0, xavix, rad_box, xavix_state, init_xavix, "Radica / SSD Company LTD", "Play TV Boxin' (NTSC)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND)
+CONS( 200?, rad_boxp, rad_box, 0, xavixp, rad_boxp, xavix_state, init_xavix, "Radica / SSD Company LTD", "ConnecTV Boxin' (PAL)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND)
-CONS( 200?, rad_crdn, 0, 0, xavix, rad_crdn, xavix_state, init_xavix, "Radica / SSD Company LTD", "Play TV Card Night (NTSC)", MACHINE_IS_SKELETON)
-CONS( 200?, rad_crdnp, rad_crdn, 0, xavixp, rad_crdnp,xavix_state, init_xavix, "Radica / SSD Company LTD", "ConnecTV Card Night (PAL)", MACHINE_IS_SKELETON)
+CONS( 200?, rad_crdn, 0, 0, xavix, rad_crdn, xavix_state, init_xavix, "Radica / SSD Company LTD", "Play TV Card Night (NTSC)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND)
+CONS( 200?, rad_crdnp, rad_crdn, 0, xavixp, rad_crdnp,xavix_state, init_xavix, "Radica / SSD Company LTD", "ConnecTV Card Night (PAL)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND)
-CONS( 2002, rad_bb2, 0, 0, xavix, rad_bb2, xavix_state, init_xavix, "Radica / SSD Company LTD", "Play TV Baseball 2", MACHINE_IS_SKELETON ) // contains string "Radica RBB2 V1.0"
+CONS( 2002, rad_bb2, 0, 0, xavix, rad_bb2, xavix_state, init_xavix, "Radica / SSD Company LTD", "Play TV Baseball 2", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND ) // contains string "Radica RBB2 V1.0"
-CONS( 2001, rad_bass, 0, 0, xavix, rad_bass, xavix_state, init_xavix, "Radica / SSD Company LTD", "Play TV Bass Fishin' (NTSC)", MACHINE_IS_SKELETON)
-CONS( 2001, rad_bassp, rad_bass, 0, xavixp, rad_bassp,xavix_state, init_xavix, "Radica / SSD Company LTD", "ConnecTV Bass Fishin' (PAL)", MACHINE_IS_SKELETON)
+CONS( 2001, rad_bass, 0, 0, xavix, rad_bass, xavix_state, init_xavix, "Radica / SSD Company LTD", "Play TV Bass Fishin' (NTSC)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND)
+CONS( 2001, rad_bassp, rad_bass, 0, xavixp, rad_bassp,xavix_state, init_xavix, "Radica / SSD Company LTD", "ConnecTV Bass Fishin' (PAL)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND)
// there is another 'Snowboarder' with a white coloured board, it appears to be a newer game closer to 'SSX Snowboarder' but without the SSX license.
-CONS( 2001, rad_snow, 0, 0, xavix, rad_snow, xavix_state, init_xavix, "Radica / SSD Company LTD", "Play TV Snowboarder (Blue) (NTSC)", MACHINE_IS_SKELETON)
-CONS( 2001, rad_snowp, rad_snow, 0, xavixp, rad_snowp,xavix_state, init_xavix, "Radica / SSD Company LTD", "ConnecTV Snowboarder (Blue) (PAL)", MACHINE_IS_SKELETON)
-
-CONS( 2003, rad_madf, 0, 0, xavix, xavix, xavix_state, init_xavix, "Radica / SSD Company LTD", "EA Sports Madden Football (NTSC)", MACHINE_IS_SKELETON) // no Play TV branding, USA only release?
-
-CONS( 200?, rad_fb, 0, 0, xavix, xavix, xavix_state, init_xavix, "Radica / SSD Company LTD", "Play TV Football (NTSC)", MACHINE_IS_SKELETON) // USA only release? doesn't change logo for PAL
-
-CONS( 200?, rad_rh, 0, 0, xavix, rad_rh, xavix_state, init_xavix, "Radioa / Fisher-Price / SSD Company LTD", "Play TV Rescue Heroes", MACHINE_IS_SKELETON)
+CONS( 2001, rad_snow, 0, 0, xavix, rad_snow, xavix_state, init_xavix, "Radica / SSD Company LTD", "Play TV Snowboarder (Blue) (NTSC)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND)
+CONS( 2001, rad_snowp, rad_snow, 0, xavixp, rad_snowp,xavix_state, init_xavix, "Radica / SSD Company LTD", "ConnecTV Snowboarder (Blue) (PAL)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND)
-CONS( 200?, epo_efdx, 0, 0, xavix_i2c_24c08, xavix, xavix_state, init_xavix, "Epoch / SSD Company LTD", "Excite Fishing DX (Japan)", MACHINE_IS_SKELETON)
+CONS( 2003, rad_madf, 0, 0, xavix, xavix, xavix_state, init_xavix, "Radica / SSD Company LTD", "EA Sports Madden Football (NTSC)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND) // no Play TV branding, USA only release?
-CONS( 200?, has_wamg, 0, 0, xavix, xavix, xavix_state, init_xavix, "Hasbro / Milton Bradley / SSD Company LTD", "TV Wild Adventure Mini Golf", MACHINE_IS_SKELETON)
+CONS( 200?, rad_fb, 0, 0, xavix, xavix, xavix_state, init_xavix, "Radica / SSD Company LTD", "Play TV Football (NTSC)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND) // USA only release? doesn't change logo for PAL
-CONS( 200?, eka_base, 0, 0, xavix, xavix, xavix_state, init_xavix, "Takara / Hasbro / SSD Company LTD", "e-kara (US?)", MACHINE_IS_SKELETON|MACHINE_IS_BIOS_ROOT)
+CONS( 200?, rad_rh, 0, 0, xavix, rad_rh, xavix_state, init_xavix, "Radioa / Fisher-Price / SSD Company LTD", "Play TV Rescue Heroes", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND)
-CONS( 200?, eka_strt, eka_base, 0, xavix, xavix, xavix_state, init_xavix, "Takara / Hasbro / SSD Company LTD", "e-kara Starter (US?)", MACHINE_IS_SKELETON)
+CONS( 200?, epo_efdx, 0, 0, xavix_i2c_24c08, xavix, xavix_state, init_xavix, "Epoch / SSD Company LTD", "Excite Fishing DX (Japan)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND)
-CONS( 200?, eka_vol1, eka_base, 0, xavix, xavix, xavix_state, init_xavix, "Takara / Hasbro / SSD Company LTD", "e-kara Volume 1 (US?)", MACHINE_IS_SKELETON) // insert calls it 'HIT MIX Vol 1'
+CONS( 200?, has_wamg, 0, 0, xavix, xavix, xavix_state, init_xavix, "Hasbro / Milton Bradley / SSD Company LTD", "TV Wild Adventure Mini Golf", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND)
-CONS( 200?, eka_vol2, eka_base, 0, xavix, xavix , xavix_state, init_xavix, "Takara / Hasbro / SSD Company LTD", "e-kara Volume 2 (US?)", MACHINE_IS_SKELETON) // insert calls it 'HIT MIX Vol 2'
+CONS( 200?, ekara, 0, 0, xavix_ekara, ekara, xavix_ekara_state, init_xavix, "Takara / Hasbro / SSD Company LTD", "e-kara (US?)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND|MACHINE_IS_BIOS_ROOT)
/* The 'XaviXPORT' isn't a real console, more of a TV adapter, all the actual hardware (CPU including video hw, sound hw) is in the cartridges and controllers
and can vary between games, see notes at top of driver.
@@ -1070,9 +1106,9 @@ ROM_START( drgqst )
ROM_END
-CONS( 2004, xavtenni, 0, 0, xavix2000_i2c_24c04, xavix, xavix_state, init_xavix, "SSD Company LTD", "XaviX Tennis (XaviXPORT)", MACHINE_IS_SKELETON )
+CONS( 2004, xavtenni, 0, 0, xavix2000_i2c_24c04, xavix, xavix_state, init_xavix, "SSD Company LTD", "XaviX Tennis (XaviXPORT)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND )
-CONS( 2005, ttv_sw, 0, 0, xavix2000_i2c_24c02, xavix, xavix_state, init_xavix, "Tiger / SSD Company LTD", "Star Wars Saga Edition - Lightsaber Battle Game", MACHINE_IS_SKELETON )
-CONS( 2005, ttv_lotr, 0, 0, xavix2000_i2c_24c02, xavix, xavix_state, init_xavix, "Tiger / SSD Company LTD", "Lord Of The Rings - Warrior of Middle-Earth", MACHINE_IS_SKELETON )
-CONS( 2005, ttv_mx, 0, 0, xavix2000_i2c_24c04, ttv_mx, xavix_state, init_xavix, "Tiger / SSD Company LTD", "MX Dirt Rebel", MACHINE_IS_SKELETON )
-CONS( 2003, drgqst, 0, 0, xavix2000_i2c_24c02, xavix, xavix_state, init_xavix, "Square Enix / SSD Company LTD", "Kenshin Dragon Quest: Yomigaerishi Densetsu no Ken", MACHINE_IS_SKELETON )
+CONS( 2005, ttv_sw, 0, 0, xavix2000_i2c_24c02, xavix, xavix_state, init_xavix, "Tiger / SSD Company LTD", "Star Wars Saga Edition - Lightsaber Battle Game", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND )
+CONS( 2005, ttv_lotr, 0, 0, xavix2000_i2c_24c02, xavix, xavix_state, init_xavix, "Tiger / SSD Company LTD", "Lord Of The Rings - Warrior of Middle-Earth", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND )
+CONS( 2005, ttv_mx, 0, 0, xavix2000_i2c_24c04, ttv_mx, xavix_state, init_xavix, "Tiger / SSD Company LTD", "MX Dirt Rebel", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND )
+CONS( 2003, drgqst, 0, 0, xavix2000_i2c_24c02, xavix, xavix_state, init_xavix, "Square Enix / SSD Company LTD", "Kenshin Dragon Quest: Yomigaerishi Densetsu no Ken", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NO_SOUND )
diff --git a/src/mame/drivers/z100.cpp b/src/mame/drivers/z100.cpp
index f502eb087b6..c3c0a558449 100644
--- a/src/mame/drivers/z100.cpp
+++ b/src/mame/drivers/z100.cpp
@@ -438,7 +438,7 @@ INPUT_CHANGED_MEMBER(z100_state::key_stroke)
{
/* TODO: table */
m_keyb_press = (uint8_t)(uintptr_t)(param) & 0xff;
- //pic8259_ir6_w(m_picm, 1);
+ //m_picm->ir6_w(1);
m_keyb_status = 1;
}
@@ -676,10 +676,10 @@ static void z100_floppies(device_slot_interface &device)
MACHINE_CONFIG_START(z100_state::z100)
/* basic machine hardware */
- MCFG_DEVICE_ADD("maincpu", I8088, 14.318181_MHz_XTAL / 3)
- MCFG_DEVICE_PROGRAM_MAP(z100_mem)
- MCFG_DEVICE_IO_MAP(z100_io)
- MCFG_DEVICE_IRQ_ACKNOWLEDGE_DEVICE("pic8259_master", pic8259_device, inta_cb)
+ I8088(config, m_maincpu, 14.318181_MHz_XTAL / 3);
+ m_maincpu->set_addrmap(AS_PROGRAM, &z100_state::z100_mem);
+ m_maincpu->set_addrmap(AS_IO, &z100_state::z100_io);
+ m_maincpu->set_irq_acknowledge_callback("pic8259_master", FUNC(pic8259_device::inta_cb));
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
@@ -697,14 +697,14 @@ MACHINE_CONFIG_START(z100_state::z100)
MCFG_MC6845_SHOW_BORDER_AREA(false)
MCFG_MC6845_CHAR_WIDTH(8)
- MCFG_DEVICE_ADD("pic8259_master", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(INPUTLINE("maincpu", 0))
- MCFG_PIC8259_IN_SP_CB(CONSTANT(1))
- MCFG_PIC8259_CASCADE_ACK_CB(READ8(*this, z100_state, get_slave_ack))
+ PIC8259(config, m_picm, 0);
+ m_picm->out_int_callback().set_inputline(m_maincpu, 0);
+ m_picm->in_sp_callback().set_constant(1);
+ m_picm->read_slave_ack_callback().set(FUNC(z100_state::get_slave_ack));
- MCFG_DEVICE_ADD("pic8259_slave", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(WRITELINE("pic8259_master", pic8259_device, ir3_w))
- MCFG_PIC8259_IN_SP_CB(CONSTANT(0))
+ PIC8259(config, m_pics, 0);
+ m_pics->out_int_callback().set(m_picm, FUNC(pic8259_device::ir3_w));
+ m_pics->in_sp_callback().set_constant(0);
PIA6821(config, m_pia0, 0);
m_pia0->writepa_handler().set(FUNC(z100_state::video_pia_A_w));
diff --git a/src/mame/includes/combatsc.h b/src/mame/includes/combatsc.h
index ae90faaa309..a20e21756e4 100644
--- a/src/mame/includes/combatsc.h
+++ b/src/mame/includes/combatsc.h
@@ -5,6 +5,10 @@
Combat School
*************************************************************************/
+#ifndef MAME_INCLUDES_COMBATSC_H
+#define MAME_INCLUDES_COMBATSC_H
+
+#pragma once
#include "machine/gen_latch.h"
#include "sound/upd7759.h"
@@ -16,8 +20,8 @@
class combatsc_state : public driver_device
{
public:
- combatsc_state(const machine_config &mconfig, device_type type, const char *tag)
- : driver_device(mconfig, type, tag),
+ combatsc_state(const machine_config &mconfig, device_type type, const char *tag) :
+ driver_device(mconfig, type, tag),
m_maincpu(*this, "maincpu"),
m_audiocpu(*this, "audiocpu"),
m_k007121_1(*this, "k007121_1"),
@@ -122,3 +126,5 @@ public:
void combatscb_map(address_map &map);
void combatscb_sound_map(address_map &map);
};
+
+#endif // MAME_INCLUDES_COMBATSC_H
diff --git a/src/mame/includes/fantland.h b/src/mame/includes/fantland.h
index e60e730d9cf..3ffd2bd4750 100644
--- a/src/mame/includes/fantland.h
+++ b/src/mame/includes/fantland.h
@@ -1,5 +1,9 @@
// license:BSD-3-Clause
// copyright-holders:Luca Elia
+#ifndef MAME_INCLUDES_FANTLAND_H
+#define MAME_INCLUDES_FANTLAND_H
+
+#pragma once
#include "machine/gen_latch.h"
#include "sound/msm5205.h"
@@ -9,42 +13,27 @@
class fantland_state : public driver_device
{
public:
- fantland_state(const machine_config &mconfig, device_type type, const char *tag)
- : driver_device(mconfig, type, tag),
+ fantland_state(const machine_config &mconfig, device_type type, const char *tag) :
+ driver_device(mconfig, type, tag),
m_maincpu(*this, "maincpu"),
m_audiocpu(*this, "audiocpu"),
m_gfxdecode(*this, "gfxdecode"),
m_screen(*this, "screen"),
m_palette(*this, "palette"),
m_soundlatch(*this, "soundlatch"),
- m_msm1(*this, "msm1"),
- m_msm2(*this, "msm2"),
- m_msm3(*this, "msm3"),
- m_msm4(*this, "msm4"),
m_spriteram(*this, "spriteram", 0),
- m_spriteram2(*this, "spriteram2", 0) { }
+ m_spriteram2(*this, "spriteram2", 0)
+ { }
void fantland(machine_config &config);
void wheelrun(machine_config &config);
- void borntofi(machine_config &config);
void galaxygn(machine_config &config);
DECLARE_CUSTOM_INPUT_MEMBER(wheelrun_wheel_r);
-private:
- /* memory pointers */
-// uint8_t * m_spriteram; // currently directly used in a 16bit map...
-// uint8_t * m_spriteram_2; // currently directly used in a 16bit map...
-
+protected:
/* misc */
- uint8_t m_nmi_enable;
- int m_old_x[2];
- int m_old_y[2];
- int m_old_f[2];
- uint8_t m_input_ret[2];
- int m_adpcm_playing[4];
- int m_adpcm_addr[2][4];
- int m_adpcm_nibble[4];
+ uint8_t m_nmi_enable;
/* devices */
required_device<cpu_device> m_maincpu;
@@ -53,42 +42,26 @@ private:
required_device<screen_device> m_screen;
required_device<palette_device> m_palette;
required_device<generic_latch_8_device> m_soundlatch;
- optional_device<msm5205_device> m_msm1;
- optional_device<msm5205_device> m_msm2;
- optional_device<msm5205_device> m_msm3;
- optional_device<msm5205_device> m_msm4;
- optional_shared_ptr<uint8_t> m_spriteram;
- optional_shared_ptr<uint8_t> m_spriteram2;
+ /* memory pointers */
+ required_shared_ptr<uint8_t> m_spriteram;
+ required_shared_ptr<uint8_t> m_spriteram2;
+
+ DECLARE_WRITE8_MEMBER(nmi_enable_w);
+ DECLARE_WRITE8_MEMBER(soundlatch_w);
+ virtual void machine_start() override;
+ virtual void machine_reset() override;
+ uint32_t screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
+ DECLARE_WRITE_LINE_MEMBER(vblank_irq);
+ void draw_sprites(bitmap_ind16 &bitmap,const rectangle &cliprect);
+
+private:
+ DECLARE_READ8_MEMBER(spriteram_r);
+ DECLARE_READ8_MEMBER(spriteram2_r);
+ DECLARE_WRITE8_MEMBER(spriteram_w);
+ DECLARE_WRITE8_MEMBER(spriteram2_w);
DECLARE_WRITE_LINE_MEMBER(galaxygn_sound_irq);
- DECLARE_WRITE8_MEMBER(fantland_nmi_enable_w);
- DECLARE_WRITE16_MEMBER(fantland_nmi_enable_16_w);
- DECLARE_WRITE8_MEMBER(fantland_soundlatch_w);
- DECLARE_WRITE16_MEMBER(fantland_soundlatch_16_w);
- DECLARE_READ16_MEMBER(spriteram_16_r);
- DECLARE_READ16_MEMBER(spriteram2_16_r);
- DECLARE_WRITE16_MEMBER(spriteram_16_w);
- DECLARE_WRITE16_MEMBER(spriteram2_16_w);
- DECLARE_WRITE8_MEMBER(borntofi_nmi_enable_w);
- DECLARE_READ8_MEMBER(borntofi_inputs_r);
- DECLARE_WRITE8_MEMBER(borntofi_msm5205_w);
- DECLARE_MACHINE_START(fantland);
- DECLARE_MACHINE_RESET(fantland);
- DECLARE_MACHINE_START(borntofi);
- DECLARE_MACHINE_RESET(borntofi);
- uint32_t screen_update_fantland(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
- DECLARE_WRITE_LINE_MEMBER(fantland_irq);
INTERRUPT_GEN_MEMBER(fantland_sound_irq);
- void draw_sprites(bitmap_ind16 &bitmap,const rectangle &cliprect);
- DECLARE_WRITE_LINE_MEMBER(borntofi_adpcm_int_0);
- DECLARE_WRITE_LINE_MEMBER(borntofi_adpcm_int_1);
- DECLARE_WRITE_LINE_MEMBER(borntofi_adpcm_int_2);
- DECLARE_WRITE_LINE_MEMBER(borntofi_adpcm_int_3);
- void borntofi_adpcm_start( msm5205_device *device, int voice );
- void borntofi_adpcm_stop( msm5205_device *device, int voice );
- void borntofi_adpcm_int( msm5205_device *device, int voice );
- void borntofi_map(address_map &map);
- void borntofi_sound_map(address_map &map);
void fantland_map(address_map &map);
void fantland_sound_iomap(address_map &map);
void fantland_sound_map(address_map &map);
@@ -97,3 +70,42 @@ private:
void wheelrun_map(address_map &map);
void wheelrun_sound_map(address_map &map);
};
+
+class borntofi_state : public fantland_state
+{
+public:
+ borntofi_state(const machine_config &mconfig, device_type type, const char *tag) :
+ fantland_state(mconfig, type, tag),
+ m_msm(*this, "msm%u", 1U),
+ m_adpcm_rom(*this, "adpcm")
+ {
+ }
+
+ void borntofi(machine_config &config);
+
+private:
+ /* misc */
+ int m_old_x[2];
+ int m_old_y[2];
+ int m_old_f[2];
+ uint8_t m_input_ret[2];
+ int m_adpcm_playing[4];
+ int m_adpcm_addr[2][4];
+ int m_adpcm_nibble[4];
+
+ /* devices */
+ required_device_array<msm5205_device, 4> m_msm;
+ required_region_ptr<uint8_t> m_adpcm_rom;
+
+ DECLARE_READ8_MEMBER(inputs_r);
+ DECLARE_WRITE8_MEMBER(msm5205_w);
+ virtual void machine_start() override;
+ virtual void machine_reset() override;
+ template<int Voice> DECLARE_WRITE_LINE_MEMBER(adpcm_int);
+ void adpcm_start(int voice);
+ void adpcm_stop(int voice);
+ void main_map(address_map &map);
+ void sound_map(address_map &map);
+};
+
+#endif // MAME_INCLUDES_FANTLAND_H
diff --git a/src/mame/includes/hng64.h b/src/mame/includes/hng64.h
index c4d6965f2f3..94a40f97eff 100644
--- a/src/mame/includes/hng64.h
+++ b/src/mame/includes/hng64.h
@@ -4,7 +4,7 @@
#include "machine/msm6242.h"
#include "machine/timer.h"
#include "cpu/mips/mips3.h"
-#include "cpu/nec/v53.h"
+#include "cpu/nec/v5x.h"
#include "sound/l7a1045_l6028_dsp_a.h"
#include "video/poly.h"
#include "cpu/tlcs870/tlcs870.h"
diff --git a/src/mame/includes/m52.h b/src/mame/includes/m52.h
index 5d77946b3f6..04cc7316a6b 100644
--- a/src/mame/includes/m52.h
+++ b/src/mame/includes/m52.h
@@ -13,12 +13,30 @@ public:
m_colorram(*this, "colorram"),
m_spriteram(*this, "spriteram"),
m_maincpu(*this, "maincpu"),
- m_gfxdecode(*this, "gfxdecode"),
+ m_sp_gfxdecode(*this, "sp_gfxdecode"),
+ m_tx_gfxdecode(*this, "tx_gfxdecode"),
+ m_bg_gfxdecode(*this, "bg_gfxdecode"),
m_screen(*this, "screen"),
- m_palette(*this, "palette") { }
+ m_sp_palette(*this, "sp_palette"),
+ m_tx_palette(*this, "tx_palette"),
+ m_bg_palette(*this, "bg_palette")
+ { }
void m52(machine_config &config);
- void alpha1v(machine_config &config);
+
+ DECLARE_WRITE8_MEMBER(m52_videoram_w);
+ DECLARE_WRITE8_MEMBER(m52_colorram_w);
+ DECLARE_READ8_MEMBER(m52_protection_r);
+
+protected:
+ virtual void video_start() override;
+ virtual DECLARE_WRITE8_MEMBER(m52_scroll_w);
+
+ /* board mod changes? */
+ int m_spritelimit;
+ bool m_do_bg_fills;
+
+ tilemap_t* m_tx_tilemap;
private:
/* memory pointers */
@@ -27,35 +45,50 @@ private:
optional_shared_ptr<uint8_t> m_spriteram;
/* video-related */
- tilemap_t* m_bg_tilemap;
uint8_t m_bg1xpos;
uint8_t m_bg1ypos;
uint8_t m_bg2xpos;
uint8_t m_bg2ypos;
uint8_t m_bgcontrol;
- DECLARE_WRITE8_MEMBER(m52_scroll_w);
- DECLARE_WRITE8_MEMBER(m52_videoram_w);
- DECLARE_WRITE8_MEMBER(m52_colorram_w);
- DECLARE_READ8_MEMBER(m52_protection_r);
DECLARE_WRITE8_MEMBER(m52_bg1ypos_w);
DECLARE_WRITE8_MEMBER(m52_bg1xpos_w);
DECLARE_WRITE8_MEMBER(m52_bg2xpos_w);
DECLARE_WRITE8_MEMBER(m52_bg2ypos_w);
DECLARE_WRITE8_MEMBER(m52_bgcontrol_w);
DECLARE_WRITE8_MEMBER(m52_flipscreen_w);
- DECLARE_WRITE8_MEMBER(alpha1v_flipscreen_w);
TILE_GET_INFO_MEMBER(get_tile_info);
virtual void machine_reset() override;
- virtual void video_start() override;
- DECLARE_PALETTE_INIT(m52);
- uint32_t screen_update_m52(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
- void draw_background(bitmap_ind16 &bitmap, const rectangle &cliprect, int xpos, int ypos, int image);
- void draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect, int initoffs);
+ void init_palette();
+ void init_sprite_palette(const int *resistances_3, const int *resistances_2, double *weights_r, double *weights_g, double *weights_b, double scale);
+ uint32_t screen_update_m52(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
+ void draw_background(bitmap_rgb32 &bitmap, const rectangle &cliprect, int xpos, int ypos, int image);
+ void draw_sprites(bitmap_rgb32 &bitmap, const rectangle &cliprect, int initoffs);
required_device<cpu_device> m_maincpu;
- required_device<gfxdecode_device> m_gfxdecode;
+ required_device<gfxdecode_device> m_sp_gfxdecode;
+ required_device<gfxdecode_device> m_tx_gfxdecode;
+ required_device<gfxdecode_device> m_bg_gfxdecode;
required_device<screen_device> m_screen;
- required_device<palette_device> m_palette;
- void alpha1v_map(address_map &map);
+ required_device<palette_device> m_sp_palette;
+ required_device<palette_device> m_tx_palette;
+ required_device<palette_device> m_bg_palette;
void main_map(address_map &map);
void main_portmap(address_map &map);
};
+
+class m52_alpha1v_state : public m52_state
+{
+public:
+ m52_alpha1v_state(const machine_config &mconfig, device_type type, const char *tag)
+ : m52_state(mconfig, type, tag)
+ { }
+
+ void alpha1v(machine_config &config);
+
+ void alpha1v_map(address_map &map);
+
+protected:
+ virtual void video_start() override;
+ virtual DECLARE_WRITE8_MEMBER(m52_scroll_w) override;
+ DECLARE_WRITE8_MEMBER(alpha1v_flipscreen_w);
+
+}; \ No newline at end of file
diff --git a/src/mame/includes/mips.h b/src/mame/includes/mips.h
index 0fb9ee547ee..d7df4116618 100644
--- a/src/mame/includes/mips.h
+++ b/src/mame/includes/mips.h
@@ -8,26 +8,32 @@
// processors and memory
#include "cpu/mips/r3000.h"
-#include "cpu/nec/v53.h"
+#include "cpu/nec/v5x.h"
#include "machine/ram.h"
// i/o devices
-#include "machine/am79c90.h"
-#include "machine/at_keybc.h"
#include "machine/mc146818.h"
-#include "machine/ncr5390.h"
-#include "machine/upd765.h"
-#include "machine/wd33c93.h"
+#include "machine/z8038.h"
+#include "machine/at_keybc.h"
#include "machine/z80scc.h"
+#include "machine/upd765.h"
+#include "machine/aic6250.h"
+#include "machine/am79c90.h"
// busses and connectors
+#include "machine/nscsi_bus.h"
+#include "machine/nscsi_cd.h"
+#include "machine/nscsi_hd.h"
+
#include "bus/pc_kbd/pc_kbdc.h"
#include "bus/pc_kbd/keyboards.h"
#include "bus/rs232/rs232.h"
-// video
+// video and audio
#include "screen.h"
#include "video/bt45x.h"
+#include "sound/spkrdev.h"
+#include "speaker.h"
#include "formats/pc_dsk.h"
@@ -36,17 +42,20 @@ class rx2030_state : public driver_device
public:
rx2030_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag)
- , m_maincpu(*this, "cpu")
+ , m_cpu(*this, "cpu")
, m_iop(*this, "iop")
, m_ram(*this, "ram")
, m_rtc(*this, "rtc")
+ , m_fio(*this, "fio")
, m_kbdc(*this, "kbdc")
, m_kbd(*this, "kbd")
, m_scc(*this, "scc")
, m_tty(*this, "tty%u", 0U)
, m_fdc(*this, "fdc")
- , m_scsi(*this, "scsi")
+ , m_scsibus(*this, "scsi")
+ , m_scsi(*this, "scsi:7:aic6250")
, m_net(*this, "net")
+ , m_buzzer(*this, "buzzer")
, m_screen(*this, "screen")
, m_ramdac(*this, "ramdac")
, m_vram(*this, "vram")
@@ -66,35 +75,55 @@ protected:
virtual void machine_reset() override;
// address maps
- void cpu_map(address_map &map);
+ void rx2030_map(address_map &map);
+ void rs2030_map(address_map &map);
+
void iop_program_map(address_map &map);
void iop_io_map(address_map &map);
+ u16 mmu_r(offs_t offset, u16 mem_mask = 0xffff);
+ void mmu_w(offs_t offset, u16 data, u16 mem_mask = 0xffff);
+
u32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
private:
+ enum iop_interface_status_mask : u8
+ {
+ FPU_ABSENT = 0x01, // clear if FPU installed
+ DBG_ABSENT = 0x02, // clear if debug board installed
+ IOP_IRQ = 0x04, // set when CPU interrupts IOP
+ VID_ABSENT = 0x10, // clear if video board installed
+ IOP_IACK = 0x40, // set when IOP acknowledges CPU interrupt
+ IOP_NERR = 0x80, // clear when IOP receives parity error
+ };
+
// processors and memory
- required_device<r2000_device> m_maincpu;
- required_device<v53_device> m_iop;
+ required_device<r3000_device_base> m_cpu;
+ required_device<v50_device> m_iop;
required_device<ram_device> m_ram;
// i/o devices
required_device<mc146818_device> m_rtc;
+ required_device<z8038_device> m_fio;
required_device<at_keyboard_controller_device> m_kbdc;
required_device<pc_kbdc_slot_device> m_kbd;
required_device<z80scc_device> m_scc;
required_device_array<rs232_port_device, 2> m_tty;
required_device<wd37c65c_device> m_fdc;
- required_device<wd33c93_device> m_scsi;
+ required_device<nscsi_bus_device> m_scsibus;
+ required_device<aic6250_device> m_scsi;
required_device<am7990_device> m_net;
+ required_device<speaker_sound_device> m_buzzer;
// optional video board
optional_device<screen_device> m_screen;
optional_device<bt458_device> m_ramdac;
- optional_device<ram_device> m_vram;
+ optional_shared_ptr<u32> m_vram;
// machine state
u16 m_mmu[32];
+
+ u8 m_iop_interface;
};
#endif // MAME_INCLUDES_MIPS_H
diff --git a/src/mame/includes/model3.h b/src/mame/includes/model3.h
index 642cf4716a7..34718b9cdd5 100644
--- a/src/mame/includes/model3.h
+++ b/src/mame/includes/model3.h
@@ -118,6 +118,7 @@ public:
void init_scud();
void init_harley();
void init_swtrilga();
+ void init_swtrilgp();
void init_vs29815();
void init_model3_10();
void init_vs215();
diff --git a/src/mame/includes/pbaction.h b/src/mame/includes/pbaction.h
index cac977d4771..58380b2278d 100644
--- a/src/mame/includes/pbaction.h
+++ b/src/mame/includes/pbaction.h
@@ -52,20 +52,21 @@ public:
required_device<z80ctc_device> m_ctc;
optional_shared_ptr<uint8_t> m_decrypted_opcodes;
+ emu_timer *m_soundcommand_timer;
uint8_t m_nmi_mask;
DECLARE_WRITE8_MEMBER(pbaction_sh_command_w);
TIMER_CALLBACK_MEMBER(sound_trigger);
DECLARE_WRITE8_MEMBER(nmi_mask_w);
DECLARE_READ8_MEMBER(sound_data_r);
DECLARE_WRITE8_MEMBER(sound_irq_ack_w);
- DECLARE_READ8_MEMBER(pbactio3_prot_kludge_r);
+ DECLARE_READ8_MEMBER(pbaction2_prot_kludge_r);
DECLARE_WRITE8_MEMBER(pbaction_videoram_w);
DECLARE_WRITE8_MEMBER(pbaction_colorram_w);
DECLARE_WRITE8_MEMBER(pbaction_videoram2_w);
DECLARE_WRITE8_MEMBER(pbaction_colorram2_w);
DECLARE_WRITE8_MEMBER(pbaction_scroll_w);
DECLARE_WRITE8_MEMBER(pbaction_flipscreen_w);
- void init_pbactio3();
+ void init_pbaction2();
TILE_GET_INFO_MEMBER(get_bg_tile_info);
TILE_GET_INFO_MEMBER(get_fg_tile_info);
virtual void machine_start() override;
@@ -77,11 +78,53 @@ public:
DECLARE_WRITE_LINE_MEMBER(sound_irq_clear);
void draw_sprites( bitmap_ind16 &bitmap, const rectangle &cliprect );
void pbaction(machine_config &config);
- void pbaction2(machine_config &config);
void pbactionx(machine_config &config);
void decrypted_opcodes_map(address_map &map);
void pbaction_map(address_map &map);
void pbaction_sound_io_map(address_map &map);
void pbaction_sound_map(address_map &map);
- void pbaction2_sound_map(address_map &map);
+ void pbaction_alt_sound_map(address_map &map);
+};
+
+class pbaction_tecfri_state : public pbaction_state
+{
+public:
+ pbaction_tecfri_state(const machine_config &mconfig, device_type type, const char *tag)
+ : pbaction_state(mconfig, type, tag),
+ m_subcpu(*this, "subcpu"),
+ m_ctc2(*this, "ctc2"),
+ m_maintosublatch(*this, "maintosublatch"),
+ //m_subtomainlatch(*this, "subtomainlatch"),
+ m_digits(*this, "digit%u", 0U) { }
+
+ void pbactiont(machine_config &config);
+
+protected:
+ virtual void machine_start() override;
+
+private:
+ void pbaction_tecfri_sub_map(address_map &map);
+ void pbaction_tecfri_sub_io_map(address_map &map);
+ void pbaction_tecfri_main_io_map(address_map &map);
+
+ TIMER_CALLBACK_MEMBER(sub_trigger);
+ emu_timer *m_subcommand_timer;
+
+ DECLARE_READ8_MEMBER(subcpu_r);
+ DECLARE_WRITE8_MEMBER(subcpu_w);
+
+ DECLARE_WRITE8_MEMBER(pbaction_tecfri_sub8000_w);
+ DECLARE_WRITE8_MEMBER(pbaction_tecfri_sub8001_w);
+ DECLARE_WRITE8_MEMBER(pbaction_tecfri_sub8008_w);
+
+ DECLARE_WRITE8_MEMBER(pbaction_tecfri_subtomain_w);
+ DECLARE_READ8_MEMBER(pbaction_tecfri_maintosub_r);
+
+ required_device<z80_device> m_subcpu;
+ required_device<z80ctc_device> m_ctc2;
+ required_device<generic_latch_8_device> m_maintosublatch;
+ //required_device<generic_latch_8_device> m_subtomainlatch;
+ output_finder<24> m_digits;
+ uint8_t m_outlatch;
+ uint32_t m_outdata;
};
diff --git a/src/mame/includes/supbtime.h b/src/mame/includes/supbtime.h
index 52665b50bb9..5887e7b35db 100644
--- a/src/mame/includes/supbtime.h
+++ b/src/mame/includes/supbtime.h
@@ -42,6 +42,8 @@ public:
private:
DECLARE_WRITE_LINE_MEMBER(vblank_w);
DECLARE_READ16_MEMBER(vblank_ack_r);
+ uint32_t screen_update_common(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect, bool use_offsets);
+ uint32_t screen_update_chinatwn(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
uint32_t screen_update_supbtime(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
uint32_t screen_update_tumblep(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
diff --git a/src/mame/includes/xavix.h b/src/mame/includes/xavix.h
index f73d3381c22..6f3a08152ff 100644
--- a/src/mame/includes/xavix.h
+++ b/src/mame/includes/xavix.h
@@ -11,6 +11,8 @@
#include "speaker.h"
#include "machine/bankdev.h"
#include "machine/i2cmem.h"
+#include "bus/generic/slot.h"
+#include "bus/generic/carts.h"
class xavix_state : public driver_device
@@ -180,10 +182,17 @@ void superxavix_lowbus_map(address_map &map);
DECLARE_WRITE8_MEMBER(sound_75fe_w);
DECLARE_WRITE8_MEMBER(sound_75ff_w);
+ DECLARE_READ8_MEMBER(timer_status_r);
DECLARE_WRITE8_MEMBER(timer_control_w);
DECLARE_READ8_MEMBER(timer_baseval_r);
DECLARE_WRITE8_MEMBER(timer_baseval_w);
+ DECLARE_READ8_MEMBER(timer_freq_r);
DECLARE_WRITE8_MEMBER(timer_freq_w);
+ uint8_t m_timer_control;
+ uint8_t m_timer_freq;
+ TIMER_CALLBACK_MEMBER(freq_timer_done);
+ emu_timer *m_freq_timer;
+
DECLARE_WRITE8_MEMBER(tmap1_regs_w);
DECLARE_WRITE8_MEMBER(tmap2_regs_w);
@@ -205,6 +214,9 @@ void superxavix_lowbus_map(address_map &map);
required_device<xavix_device> m_maincpu;
required_device<screen_device> m_screen;
+
+ void update_irqs();
+ uint8_t m_irqsource;
uint8_t m_vectorenable;
uint8_t m_nmi_vector_lo_data;
@@ -304,4 +316,20 @@ void superxavix_lowbus_map(address_map &map);
optional_device<i2cmem_device> m_i2cmem;
};
+class xavix_ekara_state : public xavix_state
+{
+public:
+ xavix_ekara_state(const machine_config &mconfig, device_type type, const char *tag)
+ : xavix_state(mconfig, type, tag),
+ m_cart(*this, "cartslot")
+ { }
+
+ void xavix_ekara(machine_config &config);
+
+protected:
+ required_device<generic_slot_device> m_cart;
+ DECLARE_DEVICE_IMAGE_LOAD_MEMBER(ekara_cart);
+ //READ8_MEMBER(cart_r) { return m_cart->read_rom(space, offset); }
+};
+
#endif // MAME_INCLUDES_XAVIX_H
diff --git a/src/mame/layout/pbactiont.lay b/src/mame/layout/pbactiont.lay
new file mode 100644
index 00000000000..cdb2c87f4a8
--- /dev/null
+++ b/src/mame/layout/pbactiont.lay
@@ -0,0 +1,194 @@
+<?xml version="1.0"?>
+<mamelayout version="2">
+
+<!-- Mini Flipper cabinet, used by Tecfri versions of Pinball Action -->
+<!-- based on Speed Ball layout, which used a similar cabinet -->
+
+<!-- define elements -->
+
+ <element name="static_black">
+ <rect>
+ <color red="0.0" green="0.0" blue="0.0" />
+ </rect>
+ </element>
+ <element name="static_red">
+ <rect>
+ <color red="0.6" green="0.2" blue="0.2" />
+ </rect>
+ </element>
+
+ <element name="digit" defstate="0">
+ <led7seg>
+ <color red="1.0" green="0.3" blue="0.0" />
+ </led7seg>
+ </element>
+
+ <element name="text_p1">
+ <text string="1 PLAYER">
+ <color red="1.0" green="1.0" blue="1.0" />
+ </text>
+ </element>
+ <element name="text_p2">
+ <text string="2 PLAYER">
+ <color red="1.0" green="1.0" blue="1.0" />
+ </text>
+ </element>
+ <element name="text_credit">
+ <text string="CREDIT">
+ <color red="1.0" green="1.0" blue="1.0" />
+ </text>
+ </element>
+ <element name="text_ball">
+ <text string="BALL">
+ <color red="1.0" green="1.0" blue="1.0" />
+ </text>
+ </element>
+ <element name="text_bonus">
+ <text string="BONUS">
+ <color red="1.0" green="1.0" blue="1.0" />
+ </text>
+ </element>
+
+ <view name="Simple LEDs">
+ <bounds left="0" right="300" top="-35" bottom="400" />
+
+ <screen index="0">
+ <bounds left="0" top="0" right="300" bottom="400" />
+ </screen>
+
+
+<!-- player 1 score -->
+
+ <bezel element="static_red">
+ <bounds left="4" top="-23" right="86" bottom="-5" />
+ </bezel>
+ <bezel element="static_black">
+ <bounds left="5" top="-22" right="85" bottom="-6" />
+ </bezel>
+
+ <bezel element="text_p1">
+ <bounds left="4" top="-34" right="86" bottom="-25" />
+ </bezel>
+
+ <bezel name="digit0" element="digit">
+ <bounds left="10" top="-20" right="20" bottom="-8" />
+ </bezel>
+ <bezel name="digit1" element="digit">
+ <bounds left="20" top="-20" right="30" bottom="-8" />
+ </bezel>
+ <bezel name="digit2" element="digit">
+ <bounds left="30" top="-20" right="40" bottom="-8" />
+ </bezel>
+ <bezel name="digit3" element="digit">
+ <bounds left="40" top="-20" right="50" bottom="-8" />
+ </bezel>
+ <bezel name="digit4" element="digit">
+ <bounds left="50" top="-20" right="60" bottom="-8" />
+ </bezel>
+ <bezel name="digit5" element="digit">
+ <bounds left="60" top="-20" right="70" bottom="-8" />
+ </bezel>
+ <bezel name="digit6" element="digit">
+ <bounds left="70" top="-20" right="80" bottom="-8" />
+ </bezel>
+
+
+<!-- credit -->
+
+ <bezel element="static_red">
+ <bounds left="104" top="-23" right="136" bottom="-5" />
+ </bezel>
+ <bezel element="static_black">
+ <bounds left="105" top="-22" right="135" bottom="-6" />
+ </bezel>
+
+ <bezel element="text_credit">
+ <bounds left="104" top="-34" right="136" bottom="-25" />
+ </bezel>
+
+ <bezel name="digit15" element="digit">
+ <bounds left="110" top="-20" right="120" bottom="-8" />
+ </bezel>
+ <bezel name="digit16" element="digit">
+ <bounds left="120" top="-20" right="130" bottom="-8" />
+ </bezel>
+
+
+<!-- ball -->
+<!-- note: digit14 (before credit) and digit17 (before ball) are left unused -->
+
+ <bezel element="static_red">
+ <bounds left="139" top="-23" right="161" bottom="-5" />
+ </bezel>
+ <bezel element="static_black">
+ <bounds left="140" top="-22" right="160" bottom="-6" />
+ </bezel>
+
+ <bezel element="text_ball">
+ <bounds left="139" top="-34" right="161" bottom="-25" />
+ </bezel>
+
+ <bezel name="digit18" element="digit">
+ <bounds left="145" top="-20" right="155" bottom="-8" />
+ </bezel>
+
+
+<!-- bonus -->
+
+ <bezel element="static_red">
+ <bounds left="164" top="-23" right="196" bottom="-5" />
+ </bezel>
+ <bezel element="static_black">
+ <bounds left="165" top="-22" right="195" bottom="-6" />
+ </bezel>
+
+ <bezel element="text_bonus">
+ <bounds left="164" top="-34" right="196" bottom="-25" />
+ </bezel>
+
+ <bezel name="digit19" element="digit">
+ <bounds left="170" top="-20" right="180" bottom="-8" />
+ </bezel>
+ <bezel name="digit20" element="digit">
+ <bounds left="180" top="-20" right="190" bottom="-8" />
+ </bezel>
+
+
+<!-- player 2 score -->
+
+ <bezel element="static_red">
+ <bounds left="214" top="-23" right="296" bottom="-5" />
+ </bezel>
+ <bezel element="static_black">
+ <bounds left="215" top="-22" right="295" bottom="-6" />
+ </bezel>
+
+ <bezel element="text_p2">
+ <bounds left="214" top="-34" right="296" bottom="-25" />
+ </bezel>
+
+ <bezel name="digit7" element="digit">
+ <bounds left="220" top="-20" right="230" bottom="-8" />
+ </bezel>
+ <bezel name="digit8" element="digit">
+ <bounds left="230" top="-20" right="240" bottom="-8" />
+ </bezel>
+ <bezel name="digit9" element="digit">
+ <bounds left="240" top="-20" right="250" bottom="-8" />
+ </bezel>
+ <bezel name="digit10" element="digit">
+ <bounds left="250" top="-20" right="260" bottom="-8" />
+ </bezel>
+ <bezel name="digit11" element="digit">
+ <bounds left="260" top="-20" right="270" bottom="-8" />
+ </bezel>
+ <bezel name="digit12" element="digit">
+ <bounds left="270" top="-20" right="280" bottom="-8" />
+ </bezel>
+ <bezel name="digit13" element="digit">
+ <bounds left="280" top="-20" right="290" bottom="-8" />
+ </bezel>
+
+ </view>
+
+</mamelayout>
diff --git a/src/mame/machine/at.cpp b/src/mame/machine/at.cpp
index 3554832896e..26d37c0b3b3 100644
--- a/src/mame/machine/at.cpp
+++ b/src/mame/machine/at.cpp
@@ -54,12 +54,12 @@ MACHINE_CONFIG_START(at_mb_device::at_softlists)
MACHINE_CONFIG_END
MACHINE_CONFIG_START(at_mb_device::device_add_mconfig)
- MCFG_DEVICE_ADD("pit8254", PIT8254, 0)
- MCFG_PIT8253_CLK0(4772720/4) /* heartbeat IRQ */
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE("pic8259_master", pic8259_device, ir0_w))
- MCFG_PIT8253_CLK1(4772720/4) /* dram refresh */
- MCFG_PIT8253_CLK2(4772720/4) /* pio port c pin 4, and speaker polling enough */
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, at_mb_device, pit8254_out2_changed))
+ PIT8254(config, m_pit8254, 0);
+ m_pit8254->set_clk<0>(4772720/4); /* heartbeat IRQ */
+ m_pit8254->out_handler<0>().set("pic8259_master", FUNC(pic8259_device::ir0_w));
+ m_pit8254->set_clk<1>(4772720/4); /* dram refresh */
+ m_pit8254->set_clk<2>(4772720/4); /* pio port c pin 4, and speaker polling enough */
+ m_pit8254->out_handler<2>().set(FUNC(at_mb_device::pit8254_out2_changed));
AM9517A(config, m_dma8237_1, 14.318181_MHz_XTAL / 3);
m_dma8237_1->out_hreq_callback().set(m_dma8237_2, FUNC(am9517a_device::dreq0_w));
@@ -151,7 +151,7 @@ void at_mb_device::map(address_map &map)
{
map(0x0000, 0x001f).rw("dma8237_1", FUNC(am9517a_device::read), FUNC(am9517a_device::write)).umask16(0xffff);
map(0x0020, 0x003f).rw("pic8259_master", FUNC(pic8259_device::read), FUNC(pic8259_device::write)).umask16(0xffff);
- map(0x0040, 0x005f).rw("pit8254", FUNC(pit8254_device::read), FUNC(pit8254_device::write)).umask16(0xffff);
+ map(0x0040, 0x005f).rw(m_pit8254, FUNC(pit8254_device::read), FUNC(pit8254_device::write)).umask16(0xffff);
map(0x0061, 0x0061).rw(FUNC(at_mb_device::portb_r), FUNC(at_mb_device::portb_w));
map(0x0060, 0x0060).rw("keybc", FUNC(at_keyboard_controller_device::data_r), FUNC(at_keyboard_controller_device::data_w));
map(0x0064, 0x0064).rw("keybc", FUNC(at_keyboard_controller_device::status_r), FUNC(at_keyboard_controller_device::command_w));
diff --git a/src/mame/machine/m24_z8000.cpp b/src/mame/machine/m24_z8000.cpp
index 4e67d664736..1a89c3d9943 100644
--- a/src/mame/machine/m24_z8000.cpp
+++ b/src/mame/machine/m24_z8000.cpp
@@ -76,15 +76,15 @@ MACHINE_CONFIG_START(m24_z8000_device::device_add_mconfig)
MCFG_DEVICE_IRQ_ACKNOWLEDGE_DRIVER(m24_z8000_device, int_cb)
MCFG_Z8000_MO(WRITELINE(*this, m24_z8000_device, mo_w))
- MCFG_DEVICE_ADD("pit8253", PIT8253, 0)
- MCFG_PIT8253_CLK0(19660000/15)
- MCFG_PIT8253_OUT0_HANDLER(NOOP) //8251
- MCFG_PIT8253_CLK1(19660000/15)
- MCFG_PIT8253_OUT1_HANDLER(NOOP)
- MCFG_PIT8253_CLK2(19660000/15)
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, m24_z8000_device, timer_irq_w))
-
- MCFG_DEVICE_ADD("i8251", I8251, 0)
+ pit8253_device &pit8253(PIT8253(config, "pit8253", 0));
+ pit8253.set_clk<0>(19660000/15); //8251
+ pit8253.out_handler<0>().set_nop();
+ pit8253.set_clk<1>(19660000/15);
+ pit8253.out_handler<1>().set_nop();
+ pit8253.set_clk<2>(19660000/15);
+ pit8253.out_handler<2>().set(FUNC(m24_z8000_device::timer_irq_w));
+
+ I8251(config, "i8251", 0);
MACHINE_CONFIG_END
const uint8_t m24_z8000_device::pmem_table[16][4] =
diff --git a/src/mame/machine/xavix.cpp b/src/mame/machine/xavix.cpp
index 91dd8c1581e..4704fd2ca5f 100644
--- a/src/mame/machine/xavix.cpp
+++ b/src/mame/machine/xavix.cpp
@@ -10,6 +10,16 @@
// general DMA to/from entire main map (not dedicated sprite DMA)
WRITE8_MEMBER(xavix_state::rom_dmatrg_w)
{
+ // 0x80 is set in the IRQ routine, presumably to ack it
+ if (data & 0x80)
+ {
+ if (m_irqsource & 0x20)
+ {
+ m_irqsource &= ~0x20;
+ update_irqs();
+ }
+ }
+
if (data & 0x01) // namcons2 writes 0x81, most of the time things write 0x01
{
LOG("%s: rom_dmatrg_w (do DMA?) %02x\n", machine().describe_context(), data);
@@ -30,6 +40,13 @@ WRITE8_MEMBER(xavix_state::rom_dmatrg_w)
uint8_t dat = m_maincpu->read_full_data_sp(m_tmpaddress);
m_maincpu->write_full_data(dest+i, dat);
}
+
+ if (data & 0x40) // or merely the absense of 0x80 being set? (ttv_lotr and drgqst are the only games needing the IRQ and both set 0x40 tho)
+ {
+ m_irqsource |= 0x20;
+ update_irqs();
+ }
+
}
else // the interrupt routine writes 0x80 to the trigger, maybe 'clear IRQ?'
{
@@ -189,8 +206,6 @@ READ8_MEMBER(xavix_state::dispctrl_6ff8_r)
WRITE8_MEMBER(xavix_state::dispctrl_6ff8_w)
{
- // I think this is something to do with IRQ ack / enable
-
// 0x80 = main IRQ ack?
// 0x40 = raster IRQ ack?
// 0x20 = main IRQ enable
@@ -198,7 +213,8 @@ WRITE8_MEMBER(xavix_state::dispctrl_6ff8_w)
if (data & 0x40)
{
- m_maincpu->set_input_line(0, CLEAR_LINE);
+ m_irqsource &= ~0x40;
+ update_irqs();
}
if (data & 0x80)
@@ -210,14 +226,27 @@ WRITE8_MEMBER(xavix_state::dispctrl_6ff8_w)
// printf("%s: dispctrl_6ff8_w %02x\n", machine().describe_context(), data);
}
+void xavix_state::update_irqs()
+{
+ if (m_irqsource != 0x00)
+ {
+ m_maincpu->set_input_line(0, ASSERT_LINE);
+ }
+ else
+ {
+ m_maincpu->set_input_line(0, CLEAR_LINE);
+ }
+}
TIMER_CALLBACK_MEMBER(xavix_state::interrupt_gen)
{
if (m_video_ctrl & 0x10)
{
//printf("callback on scanline %d %d with IRQ enabled\n", m_screen->vpos(), m_screen->hpos());
- m_maincpu->set_input_line(0, ASSERT_LINE);
m_video_ctrl |= 0x40;
+ m_irqsource |= 0x40;
+ update_irqs();
+
m_screen->update_partial(m_screen->vpos());
}
m_interrupt_timer->adjust(attotime::never, 0);
@@ -362,9 +391,48 @@ READ8_MEMBER(xavix_state::timer_baseval_r)
return m_timer_baseval;
}
+READ8_MEMBER(xavix_state::timer_status_r)
+{
+ uint8_t ret = m_timer_control;
+ LOG("%s: timer_status_r\n", machine().describe_context());
+ return ret;
+}
+
WRITE8_MEMBER(xavix_state::timer_control_w)
{
- LOG("%s: timer_control_w %02x\n", machine().describe_context(), data);
+ /* timer is actively used by
+ ttv_lotr, ttv_sw, drgqst, has_wamg, rad_rh, eka_*, epo_efdx, rad_bass, rad_bb2
+
+ gets turned on briefly during the bootup of rad_crdn, but then off again
+
+ runs during rad_fb / rad_madf, but with IRQs turned off
+
+ disabled for rad_snow, rad_ping, rad_mtrk, rad_box, *nostalgia, ttv_mx, xavtenni
+ */
+
+ //LOG("%s: timer_control_w %02x\n", machine().describe_context(), data);
+ m_timer_control = data;
+
+ if (data & 0x80) // tends to read+write address to ack interrupts, assume it's similar to other things and top bit will clear IRQ (usually gets written all the time when starting timer)
+ {
+ if (m_irqsource & 0x10)
+ {
+ m_irqsource &= ~0x10;
+ update_irqs();
+ }
+ }
+
+ // has_wamg, ttv_sw, eka_*, rad_bass set bit 0x02 too (maybe reload related?)
+
+ // rad_fb / rad_madf don't set bit 0x40 (and doesn't seem to have a valid interrupt handler for timer, so probably means it generates no IRQ?)
+ if (data & 0x01) // timer start?
+ {
+ m_freq_timer->adjust(attotime::from_usec(50000));
+ }
+ else
+ {
+ m_freq_timer->adjust(attotime::never, 0);
+ }
}
WRITE8_MEMBER(xavix_state::timer_baseval_w)
@@ -374,12 +442,57 @@ WRITE8_MEMBER(xavix_state::timer_baseval_w)
LOG("%s: timer_baseval_w %02x\n", machine().describe_context(), data);
}
+READ8_MEMBER(xavix_state::timer_freq_r)
+{
+ LOG("%s: timer_freq_r\n", machine().describe_context());
+ return m_timer_freq;
+}
+
WRITE8_MEMBER(xavix_state::timer_freq_w)
{
// 4-bit prescale
LOG("%s: timer_freq_w %02x\n", machine().describe_context(), data);
+
+ /* if master clock (MC) is XTAL(21'477'272) (NTSC master)
+
+ 0x0 = MC / 2 = 10.738636 MHz
+ 0x1 = MC / 4 = 5.369318 MHz
+ 0x2 = MC / 8 = 2.684659 MHz
+ 0x3 = MC / 16 = 1.3423295 MHz
+ 0x4 = MC / 32 = 671.16475 kHz
+ 0x5 = MC / 64 = 335.582375 kHz
+ 0x6 = MC / 128 = 167.7911875 kHz
+ 0x7 = MC / 256 = 83.89559375 kHz
+ 0x8 = MC / 512 = 41.947796875 kHz
+ 0x9 = MC / 1024 = 20.9738984375 kHz
+ 0xa = MC / 2048 = 10.48694921875 kHz
+ 0xb = MC / 4096 = 5.243474609375 kHz
+ 0xc = MC / 8192 = 2.6217373046875 kHz
+ 0xd = MC / 16384 = 1.31086865234375 kHz
+ 0xe = MC / 32768 = 655.434326171875 Hz
+ 0xf = MC / 65536 = 327.7171630859375 Hz
+ */
+ m_timer_freq = data & 0x0f;
+
+ if (data & 0xf0)
+ LOG("%s: unexpected upper bits in timer freq %02x\n", machine().describe_context(), data & 0xf0);
}
+TIMER_CALLBACK_MEMBER(xavix_state::freq_timer_done)
+{
+ if (m_timer_control & 0x40) // Timer IRQ enable?
+ {
+ m_irqsource |= 0x10;
+ m_timer_control |= 0x80;
+ update_irqs();
+ }
+
+ //logerror("freq_timer_done\n");
+ // reload
+ //m_freq_timer->adjust(attotime::from_usec(50000));
+}
+
+
READ8_MEMBER(xavix_state::mult_r)
{
@@ -463,7 +576,7 @@ READ8_MEMBER(xavix_state::irq_source_r)
*/
LOG("%s: irq_source_r\n", machine().describe_context());
- return 0x40;
+ return m_irqsource;
}
WRITE8_MEMBER(xavix_state::irq_source_w)
@@ -480,6 +593,7 @@ void xavix_state::machine_start()
std::fill_n(&m_mainram[0], 0x4000, 0xff);
m_interrupt_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(xavix_state::interrupt_gen), this));
+ m_freq_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(xavix_state::freq_timer_done), this));
}
void xavix_state::machine_reset()
@@ -534,6 +648,9 @@ void xavix_state::machine_reset()
m_io0_direction = 0x00;
m_io1_direction = 0x00;
+ m_irqsource = 0x00;
+
+ m_timer_control = 0x00;
}
typedef device_delegate<uint8_t(int which, int half)> xavix_interrupt_vector_delegate;
diff --git a/src/mame/machine/xbox.cpp b/src/mame/machine/xbox.cpp
index 83fa5549c52..6a8a55807da 100644
--- a/src/mame/machine/xbox.cpp
+++ b/src/mame/machine/xbox.cpp
@@ -941,21 +941,21 @@ MACHINE_CONFIG_START(xbox_base_state::xbox_base)
MCFG_MCPX_NV2A_GPU_CPU(m_maincpu)
MCFG_MCPX_NV2A_GPU_INTERRUPT_HANDLER(WRITELINE(*this, xbox_base_state, xbox_nv2a_interrupt_changed))
- MCFG_DEVICE_ADD("pic8259_1", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(WRITELINE(*this, xbox_base_state, xbox_pic8259_1_set_int_line))
- MCFG_PIC8259_IN_SP_CB(CONSTANT(1))
- MCFG_PIC8259_CASCADE_ACK_CB(READ8(*this, xbox_base_state, get_slave_ack))
-
- MCFG_DEVICE_ADD("pic8259_2", PIC8259, 0)
- MCFG_PIC8259_OUT_INT_CB(WRITELINE("pic8259_1", pic8259_device, ir2_w))
- MCFG_PIC8259_IN_SP_CB(CONSTANT(0))
-
- MCFG_DEVICE_ADD("pit8254", PIT8254, 0)
- MCFG_PIT8253_CLK0(1125000) /* heartbeat IRQ */
- MCFG_PIT8253_OUT0_HANDLER(WRITELINE(*this, xbox_base_state, xbox_pit8254_out0_changed))
- MCFG_PIT8253_CLK1(1125000) /* (unused) dram refresh */
- MCFG_PIT8253_CLK2(1125000) /* (unused) pio port c pin 4, and speaker polling enough */
- MCFG_PIT8253_OUT2_HANDLER(WRITELINE(*this, xbox_base_state, xbox_pit8254_out2_changed))
+ pic8259_device &pic8259_1(PIC8259(config, "pic8259_1", 0));
+ pic8259_1.out_int_callback().set(FUNC(xbox_base_state::xbox_pic8259_1_set_int_line));
+ pic8259_1.in_sp_callback().set_constant(1);
+ pic8259_1.read_slave_ack_callback().set(FUNC(xbox_base_state::get_slave_ack));
+
+ pic8259_device &pic8259_2(PIC8259(config, "pic8259_2", 0));
+ pic8259_2.out_int_callback().set("pic8259_1", FUNC(pic8259_device::ir2_w));
+ pic8259_2.in_sp_callback().set_constant(0);
+
+ pit8254_device &pit8254(PIT8254(config, "pit8254", 0));
+ pit8254.set_clk<0>(1125000); /* heartbeat IRQ */
+ pit8254.out_handler<0>().set(FUNC(xbox_base_state::xbox_pit8254_out0_changed));
+ pit8254.set_clk<1>(1125000); /* (unused) dram refresh */
+ pit8254.set_clk<2>(1125000); /* (unused) pio port c pin 4, and speaker polling enough */
+ pit8254.out_handler<2>().set(FUNC(xbox_base_state::xbox_pit8254_out2_changed));
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
diff --git a/src/mame/machine/zx8302.h b/src/mame/machine/zx8302.h
index 150a697c624..5502e2d2f64 100644
--- a/src/mame/machine/zx8302.h
+++ b/src/mame/machine/zx8302.h
@@ -38,56 +38,6 @@
///*************************************************************************
-// INTERFACE CONFIGURATION MACROS
-///*************************************************************************
-
-#define MCFG_ZX8302_RTC_CLOCK(_clk) \
- downcast<zx8302_device &>(*device).set_rtc_clock(_clk);
-
-#define MCFG_ZX8302_OUT_IPL1L_CB(_devcb) \
- downcast<zx8302_device &>(*device).set_out_ipl1l_callback(DEVCB_##_devcb);
-
-#define MCFG_ZX8302_OUT_BAUDX4_CB(_devcb) \
- downcast<zx8302_device &>(*device).set_out_baudx4_callback(DEVCB_##_devcb);
-
-#define MCFG_ZX8302_OUT_COMDATA_CB(_devcb) \
- downcast<zx8302_device &>(*device).set_out_comdata_callback(DEVCB_##_devcb);
-
-#define MCFG_ZX8302_OUT_TXD1_CB(_devcb) \
- downcast<zx8302_device &>(*device).set_out_txd1_callback(DEVCB_##_devcb);
-
-#define MCFG_ZX8302_OUT_TXD2_CB(_devcb) \
- downcast<zx8302_device &>(*device).set_out_txd2_callback(DEVCB_##_devcb);
-
-#define MCFG_ZX8302_OUT_NETOUT_CB(_devcb) \
- downcast<zx8302_device &>(*device).set_out_netout_callback(DEVCB_##_devcb);
-
-#define MCFG_ZX8302_OUT_MDSELCK_CB(_devcb) \
- downcast<zx8302_device &>(*device).set_out_mdselck_callback(DEVCB_##_devcb);
-
-#define MCFG_ZX8302_OUT_MDSELD_CB(_devcb) \
- downcast<zx8302_device &>(*device).set_out_mdseld_callback(DEVCB_##_devcb);
-
-#define MCFG_ZX8302_OUT_MDRDW_CB(_devcb) \
- downcast<zx8302_device &>(*device).set_out_mdrdw_callback(DEVCB_##_devcb);
-
-#define MCFG_ZX8302_OUT_ERASE_CB(_devcb) \
- downcast<zx8302_device &>(*device).set_out_erase_callback(DEVCB_##_devcb);
-
-#define MCFG_ZX8302_OUT_RAW1_CB(_devcb) \
- downcast<zx8302_device &>(*device).set_out_raw1_callback(DEVCB_##_devcb);
-
-#define MCFG_ZX8302_IN_RAW1_CB(_devcb) \
- downcast<zx8302_device &>(*device).set_in_raw1_callback(DEVCB_##_devcb);
-
-#define MCFG_ZX8302_OUT_RAW2_CB(_devcb) \
- downcast<zx8302_device &>(*device).set_out_raw2_callback(DEVCB_##_devcb);
-
-#define MCFG_ZX8302_IN_RAW2_CB(_devcb) \
- downcast<zx8302_device &>(*device).set_in_raw2_callback(DEVCB_##_devcb);
-
-
-///*************************************************************************
// TYPE DEFINITIONS
///*************************************************************************
@@ -102,20 +52,20 @@ public:
void set_rtc_clock(int rtc_clock) { m_rtc_clock = rtc_clock; }
void set_rtc_clock(const XTAL &rtc_clock) { set_rtc_clock(rtc_clock.value()); }
- template <class Object> devcb_base &set_out_ipl1l_callback(Object &&cb) { return m_out_ipl1l_cb.set_callback(std::forward<Object>(cb)); }
- template <class Object> devcb_base &set_out_baudx4_callback(Object &&cb) { return m_out_baudx4_cb.set_callback(std::forward<Object>(cb)); }
- template <class Object> devcb_base &set_out_comdata_callback(Object &&cb) { return m_out_comdata_cb.set_callback(std::forward<Object>(cb)); }
- template <class Object> devcb_base &set_out_txd1_callback(Object &&cb) { return m_out_txd1_cb.set_callback(std::forward<Object>(cb)); }
- template <class Object> devcb_base &set_out_txd2_callback(Object &&cb) { return m_out_txd2_cb.set_callback(std::forward<Object>(cb)); }
- template <class Object> devcb_base &set_out_netout_callback(Object &&cb) { return m_out_netout_cb.set_callback(std::forward<Object>(cb)); }
- template <class Object> devcb_base &set_out_mdselck_callback(Object &&cb) { return m_out_mdselck_cb.set_callback(std::forward<Object>(cb)); }
- template <class Object> devcb_base &set_out_mdseld_callback(Object &&cb) { return m_out_mdseld_cb.set_callback(std::forward<Object>(cb)); }
- template <class Object> devcb_base &set_out_mdrdw_callback(Object &&cb) { return m_out_mdrdw_cb.set_callback(std::forward<Object>(cb)); }
- template <class Object> devcb_base &set_out_erase_callback(Object &&cb) { return m_out_erase_cb.set_callback(std::forward<Object>(cb)); }
- template <class Object> devcb_base &set_out_raw1_callback(Object &&cb) { return m_out_raw1_cb.set_callback(std::forward<Object>(cb)); }
- template <class Object> devcb_base &set_in_raw1_callback(Object &&cb) { return m_in_raw1_cb.set_callback(std::forward<Object>(cb)); }
- template <class Object> devcb_base &set_out_raw2_callback(Object &&cb) { return m_out_raw2_cb.set_callback(std::forward<Object>(cb)); }
- template <class Object> devcb_base &set_in_raw2_callback(Object &&cb) { return m_in_raw2_cb.set_callback(std::forward<Object>(cb)); }
+ auto out_ipl1l_callback() { return m_out_ipl1l_cb.bind(); }
+ auto out_baudx4_callback() { return m_out_baudx4_cb.bind(); }
+ auto out_comdata_callback() { return m_out_comdata_cb.bind(); }
+ auto out_txd1_callback() { return m_out_txd1_cb.bind(); }
+ auto out_txd2_callback() { return m_out_txd2_cb.bind(); }
+ auto out_netout_callback() { return m_out_netout_cb.bind(); }
+ auto out_mdselck_callback() { return m_out_mdselck_cb.bind(); }
+ auto out_mdseld_callback() { return m_out_mdseld_cb.bind(); }
+ auto out_mdrdw_callback() { return m_out_mdrdw_cb.bind(); }
+ auto out_erase_callback() { return m_out_erase_cb.bind(); }
+ auto out_raw1_callback() { return m_out_raw1_cb.bind(); }
+ auto in_raw1_callback() { return m_in_raw1_cb.bind(); }
+ auto out_raw2_callback() { return m_out_raw2_cb.bind(); }
+ auto in_raw2_callback() { return m_in_raw2_cb.bind(); }
DECLARE_READ8_MEMBER( rtc_r );
DECLARE_WRITE8_MEMBER( rtc_w );
diff --git a/src/mame/mame.lst b/src/mame/mame.lst
index 5a7ee513197..c10f0cc92bd 100644
--- a/src/mame/mame.lst
+++ b/src/mame/mame.lst
@@ -21388,6 +21388,7 @@ mightyframe // Convergent
mikie // GX469 (c) 1984
mikiehs // GX469 (c) 1984
mikiej // GX469 (c) 1984
+mikiek // GX469 (c) 1984
@source:mikro80.cpp
kristall2 //
@@ -21662,7 +21663,8 @@ eca // 1999.10 Kyukyuusya Emergency Call Ambulance
ecap // 1999.12 Emergency Call Ambulance - US proto or location test
ecaj //
ecau //
-fvipers2 // 1998.04 Fighting Vipers 2
+fvipers2 // 1998.04 Fighting Vipers 2 (rev A)
+fvipers2o // 1998.?? Fighting Vipers 2
getbass //
harley // 199?.?? Harley Davidson & L.A.Riders (rev B)
harleya // 1997.12 Harley Davidson & L.A.Riders (rev A)
@@ -21681,14 +21683,16 @@ spikeofe // 1999.01 Spikeout Final Edition
spikeout // 1998.09 Spikeout
srally2 // 1998.02 Sega Rally 2 Championship
srally2x //
-swtrilgy // 1998.11 Star Wars Trilogy Arcade
-swtrilgya //
+swtrilgy // 1998.12 Star Wars Trilogy Arcade (rev A)
+swtrilgya // 1998.11 Star Wars Trilogy Arcade
+swtrilgyp // 1998.09 Star Wars Trilogy Arcade (prototype)
vf3 // 1996.09 Virtua Fighter 3
vf3a //
vf3c //
vf3tb // 1997.10 Virtua Fighter 3tb
-von2 // 1998.03 Dennou Senki Virtual-On Oratorio Tangram
-von2a // 1998.03 Dennou Senki Virtual-On Oratorio Tangram
+von2 // 1998.03 Dennou Senki Virtual-On Oratorio Tangram (rev B)
+von2a // 1998.03 Dennou Senki Virtual-On Oratorio Tangram (rev A)
+von2o // 1998.03 Dennou Senki Virtual-On Oratorio Tangram
von254g // 1999.05 Dennou Senki Virtual-On Oratorio Tangram ver.5.4
vs2 // 1997.06 Virtua Striker 2
vs215 // 1997.06 Virtua Striker 2
@@ -30900,7 +30904,7 @@ pbaction // (c) 1985 Tehkan
pbaction2 // (c) 1985 Tehkan
pbaction3 // (c) 1985 Tehkan
pbaction4 // (c) 1985 Tehkan
-pbaction5 // (c) 1985 Tehkan
+pbactiont // (c) 1985 Tehkan (Tecfri license)
@source:pc.cpp
ataripc1 // Atari PC1
@@ -34444,6 +34448,8 @@ titlefj // 1993.03 Title Fight (Japan)
titlefu // 1993.04 Title Fight (US)
@source:segasp.cpp
+bingogal // 2009.05 Bingo Galaxy (main)
+bingogals // 2009.05 Bingo Galaxy (satellite)
brickppl //
dinoki25 //
dinoking // 2005.09 Kodai Ouja Kyouryuu King / Ancient Ruler Dinosaur King
@@ -39526,10 +39532,7 @@ rad_fb //
epo_efdx //
rad_rh //
has_wamg //
-eka_base //
-eka_strt //
-eka_vol1 //
-eka_vol2 //
+ekara //
xavtenni //
ttv_sw //
ttv_lotr //
diff --git a/src/mame/video/deco16ic.cpp b/src/mame/video/deco16ic.cpp
index b7e2dca7739..9bee26d4253 100644
--- a/src/mame/video/deco16ic.cpp
+++ b/src/mame/video/deco16ic.cpp
@@ -560,7 +560,7 @@ void deco16ic_device::pf12_set_gfxbank( int small, int big )
m_pf12_8x8_gfx_bank = small;
}
-/* stoneage has broken scroll registers */
+/* stoneage has broken scroll registers, original tumble pop expects a 1 pixel offset */
void deco16ic_device::set_scrolldx( int tmap, int size, int dx, int dx_if_flipped )
{
switch (tmap)
diff --git a/src/mame/video/fantland.cpp b/src/mame/video/fantland.cpp
index 44a9a742e46..4134c196801 100644
--- a/src/mame/video/fantland.cpp
+++ b/src/mame/video/fantland.cpp
@@ -65,9 +65,8 @@
void fantland_state::draw_sprites(bitmap_ind16 &bitmap,const rectangle &cliprect)
{
- uint8_t *spriteram_2 = m_spriteram2;
- uint8_t *indx_ram = m_spriteram + 0x2000, // this ram contains indexes into offs_ram
- *offs_ram = m_spriteram + 0x2400, // this ram contains x,y offsets or indexes into spriteram_2
+ uint8_t *indx_ram = m_spriteram + 0x2000, // this ram contains indexes into offs_ram
+ *offs_ram = m_spriteram + 0x2400, // this ram contains x,y offsets or indexes into m_spriteram2
*ram = m_spriteram, // current sprite pointer in spriteram
*ram2 = indx_ram; // current sprite pointer in indx_ram
@@ -100,12 +99,12 @@ void fantland_state::draw_sprites(bitmap_ind16 &bitmap,const rectangle &cliprect
if (offs_ram[idx + 2] & 0x80)
{
- // x,y & code offset is in spriteram_2, this is its index
+ // x,y & code offset is in m_spriteram2, this is its index
idx = (((offs_ram[idx + 2] << 8) + offs_ram[idx + 3]) & 0x3fff) * 4;
- yoffs = spriteram_2[idx + 0] + (spriteram_2[idx + 1] << 8);
- xoffs = spriteram_2[idx + 2] + (spriteram_2[idx + 3] << 8);
+ yoffs = m_spriteram2[idx + 0] + (m_spriteram2[idx + 1] << 8);
+ xoffs = m_spriteram2[idx + 2] + (m_spriteram2[idx + 3] << 8);
code += (yoffs & 0x3e00) >> 9;
flipy ^= (yoffs & 0x4000) ? 1 : 0;
@@ -140,7 +139,7 @@ void fantland_state::draw_sprites(bitmap_ind16 &bitmap,const rectangle &cliprect
}
}
-uint32_t fantland_state::screen_update_fantland(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
+uint32_t fantland_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
{
bitmap.fill(0, cliprect);
draw_sprites(bitmap,cliprect);
diff --git a/src/mame/video/fmtowns.cpp b/src/mame/video/fmtowns.cpp
index 65a3e33f664..f73fa87d23a 100644
--- a/src/mame/video/fmtowns.cpp
+++ b/src/mame/video/fmtowns.cpp
@@ -511,12 +511,10 @@ READ8_MEMBER(towns_state::towns_video_5c8_r)
WRITE8_MEMBER(towns_state::towns_video_5c8_w)
{
- pic8259_device* dev = m_pic_slave;
-
switch(offset)
{
case 0x02: // 0x5ca - VSync clear?
- dev->ir3_w(0);
+ m_pic_slave->ir3_w(0);
if(IRQ_LOG) logerror("PIC: IRQ11 (VSync) set low\n");
//towns_vblank_flag = 0;
break;
@@ -1488,19 +1486,17 @@ TIMER_CALLBACK_MEMBER(towns_state::towns_sprite_done)
TIMER_CALLBACK_MEMBER(towns_state::towns_vblank_end)
{
// here we'll clear the vsync signal, I presume it goes low on it's own eventually
- device_t* dev = (device_t*)ptr;
- downcast<pic8259_device *>(dev)->ir3_w(0); // IRQ11 = VSync
+ m_pic_slave->ir3_w(0); // IRQ11 = VSync
if(IRQ_LOG) logerror("PIC: IRQ11 (VSync) set low\n");
m_video.towns_vblank_flag = 0;
}
INTERRUPT_GEN_MEMBER(towns_state::towns_vsync_irq)
{
- pic8259_device* dev = m_pic_slave;
- dev->ir3_w(1); // IRQ11 = VSync
+ m_pic_slave->ir3_w(1); // IRQ11 = VSync
if(IRQ_LOG) logerror("PIC: IRQ11 (VSync) set high\n");
m_video.towns_vblank_flag = 1;
- machine().scheduler().timer_set(m_screen->time_until_vblank_end(), timer_expired_delegate(FUNC(towns_state::towns_vblank_end),this), 0, (void*)dev);
+ machine().scheduler().timer_set(m_screen->time_until_vblank_end(), timer_expired_delegate(FUNC(towns_state::towns_vblank_end),this), 0, (void*)m_pic_slave);
if(m_video.towns_tvram_enable)
draw_text_layer();
if(m_video.towns_sprite_reg[1] & 0x80)
diff --git a/src/mame/video/m107.cpp b/src/mame/video/m107.cpp
index 2e99e03ba38..3be0b00a65b 100644
--- a/src/mame/video/m107.cpp
+++ b/src/mame/video/m107.cpp
@@ -122,9 +122,7 @@ WRITE16_MEMBER(m107_state::control_w)
void m107_state::video_start()
{
- int laynum;
-
- for (laynum = 0; laynum < 4; laynum++)
+ for (int laynum = 0; laynum < 4; laynum++)
{
pf_layer_info *layer = &m_pf_layer[laynum];
diff --git a/src/mame/video/m52.cpp b/src/mame/video/m52.cpp
index 1bb2852d418..1c5dfb92072 100644
--- a/src/mame/video/m52.cpp
+++ b/src/mame/video/m52.cpp
@@ -10,7 +10,7 @@
#include "video/resnet.h"
#include "includes/m52.h"
-#define BGHEIGHT 64
+#define BGHEIGHT 128
/*************************************
@@ -19,96 +19,99 @@
*
*************************************/
-PALETTE_INIT_MEMBER(m52_state, m52)
+void m52_state::init_palette()
{
- const uint8_t *color_prom = memregion("proms")->base();
- const uint8_t *char_pal = color_prom + 0x000;
- const uint8_t *back_pal = color_prom + 0x200;
- const uint8_t *sprite_pal = color_prom + 0x220;
- const uint8_t *sprite_table = color_prom + 0x240;
- static const int resistances_3[3] = { 1000, 470, 220 };
- static const int resistances_2[2] = { 470, 220 };
+ const int resistances_3[3] = { 1000, 470, 220 };
+ const int resistances_2[2] = { 470, 220 };
double weights_r[3], weights_g[3], weights_b[3], scale;
- int i;
/* compute palette information for characters/backgrounds */
scale = compute_resistor_weights(0, 255, -1.0,
- 3, resistances_3, weights_r, 0, 0,
- 3, resistances_3, weights_g, 0, 0,
- 2, resistances_2, weights_b, 0, 0);
+ 3, resistances_3, weights_r, 0, 0,
+ 3, resistances_3, weights_g, 0, 0,
+ 2, resistances_2, weights_b, 0, 0);
/* character palette */
- for (i = 0; i < 512; i++)
+ const uint8_t *char_pal = memregion("tx_pal")->base();
+ for (int i = 0; i < 512; i++)
{
uint8_t promval = char_pal[i];
- int r = combine_3_weights(weights_r, BIT(promval,0), BIT(promval,1), BIT(promval,2));
- int g = combine_3_weights(weights_g, BIT(promval,3), BIT(promval,4), BIT(promval,5));
- int b = combine_2_weights(weights_b, BIT(promval,6), BIT(promval,7));
+ int r = combine_3_weights(weights_r, BIT(promval, 0), BIT(promval, 1), BIT(promval, 2));
+ int g = combine_3_weights(weights_g, BIT(promval, 3), BIT(promval, 4), BIT(promval, 5));
+ int b = combine_2_weights(weights_b, BIT(promval, 6), BIT(promval, 7));
- palette.set_indirect_color(i, rgb_t(r,g,b));
+ m_tx_palette->set_pen_color(i, rgb_t(r, g, b));
}
/* background palette */
- for (i = 0; i < 32; i++)
+ const uint8_t *back_pal = memregion("bg_pal")->base();
+ for (int i = 0; i < 32; i++)
{
uint8_t promval = back_pal[i];
- int r = combine_3_weights(weights_r, BIT(promval,0), BIT(promval,1), BIT(promval,2));
- int g = combine_3_weights(weights_g, BIT(promval,3), BIT(promval,4), BIT(promval,5));
- int b = combine_2_weights(weights_b, BIT(promval,6), BIT(promval,7));
+ int r = combine_3_weights(weights_r, BIT(promval, 0), BIT(promval, 1), BIT(promval, 2));
+ int g = combine_3_weights(weights_g, BIT(promval, 3), BIT(promval, 4), BIT(promval, 5));
+ int b = combine_2_weights(weights_b, BIT(promval, 6), BIT(promval, 7));
- palette.set_indirect_color(512+i, rgb_t(r,g,b));
+ m_bg_palette->set_indirect_color(i, rgb_t(r, g, b));
}
+ /* background
+ the palette is a 32x8 PROM with many colors repeated. The address of
+ the colors to pick is as follows:
+ xbb00: mountains
+ 0xxbb: hills
+ 1xxbb: city
+
+ this seems hacky, surely all bytes in the PROM should be used, not just picking the ones that give the colours we want?
+
+ */
+ m_bg_palette->set_pen_indirect(0 * 4 + 0, 0);
+ m_bg_palette->set_pen_indirect(0 * 4 + 1, 4);
+ m_bg_palette->set_pen_indirect(0 * 4 + 2, 8);
+ m_bg_palette->set_pen_indirect(0 * 4 + 3, 12);
+ m_bg_palette->set_pen_indirect(1 * 4 + 0, 0);
+ m_bg_palette->set_pen_indirect(1 * 4 + 1, 1);
+ m_bg_palette->set_pen_indirect(1 * 4 + 2, 2);
+ m_bg_palette->set_pen_indirect(1 * 4 + 3, 3);
+ m_bg_palette->set_pen_indirect(2 * 4 + 0, 0);
+ m_bg_palette->set_pen_indirect(2 * 4 + 1, 16 + 1);
+ m_bg_palette->set_pen_indirect(2 * 4 + 2, 16 + 2);
+ m_bg_palette->set_pen_indirect(2 * 4 + 3, 16 + 3);
+
+ init_sprite_palette(resistances_3, resistances_2, weights_r, weights_g, weights_b, scale);
+}
+
+void m52_state::init_sprite_palette(const int *resistances_3, const int *resistances_2, double *weights_r, double *weights_g, double *weights_b, double scale)
+{
+ const uint8_t *sprite_pal = memregion("spr_pal")->base();
+ const uint8_t *sprite_table = memregion("spr_clut")->base();
+
/* compute palette information for sprites */
compute_resistor_weights(0, 255, scale,
- 2, resistances_2, weights_r, 470, 0,
- 3, resistances_3, weights_g, 470, 0,
- 3, resistances_3, weights_b, 470, 0);
+ 2, resistances_2, weights_r, 470, 0,
+ 3, resistances_3, weights_g, 470, 0,
+ 3, resistances_3, weights_b, 470, 0);
/* sprite palette */
- for (i = 0; i < 32; i++)
+ for (int i = 0; i < 32; i++)
{
uint8_t promval = sprite_pal[i];
- int r = combine_2_weights(weights_r, BIT(promval,6), BIT(promval,7));
- int g = combine_3_weights(weights_g, BIT(promval,3), BIT(promval,4), BIT(promval,5));
- int b = combine_3_weights(weights_b, BIT(promval,0), BIT(promval,1), BIT(promval,2));
+ int r = combine_2_weights(weights_r, BIT(promval, 6), BIT(promval, 7));
+ int g = combine_3_weights(weights_g, BIT(promval, 3), BIT(promval, 4), BIT(promval, 5));
+ int b = combine_3_weights(weights_b, BIT(promval, 0), BIT(promval, 1), BIT(promval, 2));
- palette.set_indirect_color(512 + 32 + i, rgb_t(r,g,b));
+ m_sp_palette->set_indirect_color(i, rgb_t(r, g, b));
}
- /* character lookup table */
- for (i = 0; i < 512; i++)
- palette.set_pen_indirect(i, i);
-
/* sprite lookup table */
- for (i = 0; i < 16 * 4; i++)
+ for (int i = 0; i < 256; i++)
{
- uint8_t promval = sprite_table[(i & 3) | ((i & ~3) << 1)];
- palette.set_pen_indirect(512 + i, 512 + 32 + promval);
+ uint8_t promval = sprite_table[i];
+ m_sp_palette->set_pen_indirect(i, promval);
}
-
- /* background */
- /* the palette is a 32x8 PROM with many colors repeated. The address of */
- /* the colors to pick is as follows: */
- /* xbb00: mountains */
- /* 0xxbb: hills */
- /* 1xxbb: city */
- palette.set_pen_indirect(512+16*4+0*4+0, 512);
- palette.set_pen_indirect(512+16*4+0*4+1, 512+4);
- palette.set_pen_indirect(512+16*4+0*4+2, 512+8);
- palette.set_pen_indirect(512+16*4+0*4+3, 512+12);
- palette.set_pen_indirect(512+16*4+1*4+0, 512);
- palette.set_pen_indirect(512+16*4+1*4+1, 512+1);
- palette.set_pen_indirect(512+16*4+1*4+2, 512+2);
- palette.set_pen_indirect(512+16*4+1*4+3, 512+3);
- palette.set_pen_indirect(512+16*4+2*4+0, 512);
- palette.set_pen_indirect(512+16*4+2*4+1, 512+16+1);
- palette.set_pen_indirect(512+16*4+2*4+2, 512+16+2);
- palette.set_pen_indirect(512+16*4+2*4+3, 512+16+3);
}
-
/*************************************
*
* Tilemap info callback
@@ -135,7 +138,7 @@ TILE_GET_INFO_MEMBER(m52_state::get_tile_info)
flag |= TILE_FORCE_LAYER0; /* lines 0 to 6 are opaqe? */
}
- SET_TILE_INFO_MEMBER(0, code, color & 0x3f, flag);
+ SET_TILE_INFO_MEMBER(0, code, color & 0x7f, flag);
}
@@ -148,18 +151,37 @@ TILE_GET_INFO_MEMBER(m52_state::get_tile_info)
void m52_state::video_start()
{
- m_bg_tilemap = &machine().tilemap().create(*m_gfxdecode, tilemap_get_info_delegate(FUNC(m52_state::get_tile_info),this), TILEMAP_SCAN_ROWS, 8, 8, 32, 32);
+ m_tx_tilemap = &machine().tilemap().create(*m_tx_gfxdecode, tilemap_get_info_delegate(FUNC(m52_state::get_tile_info),this), TILEMAP_SCAN_ROWS, 8, 8, 32, 32);
- m_bg_tilemap->set_transparent_pen(0);
- m_bg_tilemap->set_scrolldx(127, 127);
- m_bg_tilemap->set_scrolldy(16, 16);
- m_bg_tilemap->set_scroll_rows(4); /* only lines 192-256 scroll */
+ m_tx_tilemap->set_transparent_pen(0);
+ m_tx_tilemap->set_scrolldx(127, 127);
+ m_tx_tilemap->set_scrolldy(16, 16);
+ m_tx_tilemap->set_scroll_rows(4); /* only lines 192-256 scroll */
+
+ init_palette();
save_item(NAME(m_bg1xpos));
save_item(NAME(m_bg1ypos));
save_item(NAME(m_bg2xpos));
save_item(NAME(m_bg2ypos));
save_item(NAME(m_bgcontrol));
+
+ m_spritelimit = 0x100-4;
+ m_do_bg_fills = true;
+}
+
+void m52_alpha1v_state::video_start()
+{
+ m52_state::video_start();
+
+ // is the limit really just higher anyway or is this a board mod?
+ m_spritelimit = 0x200-4;
+ m_do_bg_fills = false; // or you get solid green areas below the stars bg image. does the doubled up tilemap ROM maybe mean double height instead?
+
+ // the scrolling orange powerups 'orbs' are a single tile in the tilemap, your ship is huge, it is unclear where the hitboxes are meant to be
+ // using the same value as mpatrol puts the collision at the very back of your ship
+ // maybe the sprite positioning is incorrect instead or this is just how the game is designed
+ //m_tx_tilemap->set_scrolldx(127+8, 127-8);
}
@@ -179,12 +201,25 @@ WRITE8_MEMBER(m52_state::m52_scroll_w)
So we set the first 3 quarters to 255 and the last to the scroll value
*/
- m_bg_tilemap->set_scrollx(0, 255);
- m_bg_tilemap->set_scrollx(1, 255);
- m_bg_tilemap->set_scrollx(2, 255);
- m_bg_tilemap->set_scrollx(3, -(data + 1));
+ m_tx_tilemap->set_scrollx(0, 255);
+ m_tx_tilemap->set_scrollx(1, 255);
+ m_tx_tilemap->set_scrollx(2, 255);
+ m_tx_tilemap->set_scrollx(3, -(data + 1));
}
+WRITE8_MEMBER(m52_alpha1v_state::m52_scroll_w)
+{
+/*
+ alpha1v must have some board mod to invert scroll register use, as it expects only the first block to remain static
+ the scrolling powerups are part of the tx layer!
+
+ TODO: check if this configuration works with Moon Patrol, maybe the schematics were read incorrectly?
+*/
+ m_tx_tilemap->set_scrollx(0, 255);
+ m_tx_tilemap->set_scrollx(1, -(data + 1));
+ m_tx_tilemap->set_scrollx(2, -(data + 1));
+ m_tx_tilemap->set_scrollx(3, -(data + 1));
+}
/*************************************
@@ -196,14 +231,14 @@ WRITE8_MEMBER(m52_state::m52_scroll_w)
WRITE8_MEMBER(m52_state::m52_videoram_w)
{
m_videoram[offset] = data;
- m_bg_tilemap->mark_tile_dirty(offset);
+ m_tx_tilemap->mark_tile_dirty(offset);
}
WRITE8_MEMBER(m52_state::m52_colorram_w)
{
m_colorram[offset] = data;
- m_bg_tilemap->mark_tile_dirty(offset);
+ m_tx_tilemap->mark_tile_dirty(offset);
}
@@ -277,7 +312,7 @@ WRITE8_MEMBER(m52_state::m52_flipscreen_w)
machine().bookkeeping().coin_counter_w(1, data & 0x20);
}
-WRITE8_MEMBER(m52_state::alpha1v_flipscreen_w)
+WRITE8_MEMBER(m52_alpha1v_state::alpha1v_flipscreen_w)
{
flip_screen_set(data & 0x01);
}
@@ -290,10 +325,11 @@ WRITE8_MEMBER(m52_state::alpha1v_flipscreen_w)
*
*************************************/
-void m52_state::draw_background(bitmap_ind16 &bitmap, const rectangle &cliprect, int xpos, int ypos, int image)
+void m52_state::draw_background(bitmap_rgb32 &bitmap, const rectangle &cliprect, int xpos, int ypos, int image)
{
rectangle rect;
const rectangle &visarea = m_screen->visible_area();
+ const pen_t *paldata = m_bg_palette->pens();
if (flip_screen())
@@ -308,7 +344,7 @@ void m52_state::draw_background(bitmap_ind16 &bitmap, const rectangle &cliprect,
ypos += 16;
- m_gfxdecode->gfx(image)->transpen(bitmap,cliprect,
+ m_bg_gfxdecode->gfx(image)->transpen(bitmap,cliprect,
0, 0,
flip_screen(),
flip_screen(),
@@ -316,28 +352,32 @@ void m52_state::draw_background(bitmap_ind16 &bitmap, const rectangle &cliprect,
ypos, 0);
- m_gfxdecode->gfx(image)->transpen(bitmap,cliprect,
+ m_bg_gfxdecode->gfx(image)->transpen(bitmap,cliprect,
0, 0,
flip_screen(),
flip_screen(),
xpos - 256,
ypos, 0);
- rect.min_x = visarea.min_x;
- rect.max_x = visarea.max_x;
-
- if (flip_screen())
+ // create a solid fill below the 64 pixel high bg images
+ if (m_do_bg_fills)
{
- rect.min_y = ypos - BGHEIGHT;
- rect.max_y = ypos - 1;
- }
- else
- {
- rect.min_y = ypos + BGHEIGHT;
- rect.max_y = ypos + 2 * BGHEIGHT - 1;
- }
+ rect.min_x = visarea.min_x;
+ rect.max_x = visarea.max_x;
- bitmap.fill(m_gfxdecode->gfx(image)->colorbase() + 3, rect);
+ if (flip_screen())
+ {
+ rect.min_y = ypos - BGHEIGHT;
+ rect.max_y = ypos - 1;
+ }
+ else
+ {
+ rect.min_y = ypos + BGHEIGHT;
+ rect.max_y = ypos + 2 * BGHEIGHT - 1;
+ }
+
+ bitmap.fill(paldata[m_bg_gfxdecode->gfx(image)->colorbase() + 3], rect);
+ }
}
@@ -348,7 +388,7 @@ void m52_state::draw_background(bitmap_ind16 &bitmap, const rectangle &cliprect,
*
*************************************/
-void m52_state::draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect, int initoffs)
+void m52_state::draw_sprites(bitmap_rgb32 &bitmap, const rectangle &cliprect, int initoffs)
{
int offs;
@@ -361,11 +401,10 @@ void m52_state::draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect, in
int flipy = m_spriteram[offs + 1] & 0x80;
int code = m_spriteram[offs + 2];
int sx = m_spriteram[offs + 3];
- rectangle clip;
/* sprites from offsets $00-$7F are processed in the upper half of the frame */
/* sprites from offsets $80-$FF are processed in the lower half of the frame */
- clip = cliprect;
+ rectangle clip = cliprect;
if (!(offs & 0x80))
clip.min_y = 0, clip.max_y = 127;
else
@@ -392,9 +431,9 @@ void m52_state::draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect, in
clip = cliprect;
#endif
- m_gfxdecode->gfx(1)->transmask(bitmap,clip,
+ m_sp_gfxdecode->gfx(0)->transmask(bitmap,clip,
code, color, flipx, flipy, sx, sy,
- m_palette->transpen_mask(*m_gfxdecode->gfx(1), color, 512 + 32));
+ m_sp_palette->transpen_mask(*m_sp_gfxdecode->gfx(0), color, 0));
}
}
@@ -406,30 +445,31 @@ void m52_state::draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect, in
*
*************************************/
-uint32_t m52_state::screen_update_m52(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
+uint32_t m52_state::screen_update_m52(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
{
int offs;
+ const pen_t *paldata = m_sp_palette->pens();
- bitmap.fill(0, cliprect);
+ bitmap.fill(paldata[0], cliprect);
if (!(m_bgcontrol & 0x20))
{
if (!(m_bgcontrol & 0x10))
- draw_background(bitmap, cliprect, m_bg2xpos, m_bg2ypos, 2); /* distant mountains */
+ draw_background(bitmap, cliprect, m_bg2xpos, m_bg2ypos, 0); /* distant mountains */
+ // only one of these be drawn at once (they share the same scroll register) (alpha1v leaves everything enabled)
if (!(m_bgcontrol & 0x02))
- draw_background(bitmap, cliprect, m_bg1xpos, m_bg1ypos, 3); /* hills */
-
- if (!(m_bgcontrol & 0x04))
- draw_background(bitmap, cliprect, m_bg1xpos, m_bg1ypos, 4); /* cityscape */
+ draw_background(bitmap, cliprect, m_bg1xpos, m_bg1ypos, 1); /* hills */
+ else if (!(m_bgcontrol & 0x04))
+ draw_background(bitmap, cliprect, m_bg1xpos, m_bg1ypos, 2); /* cityscape */
}
- m_bg_tilemap->set_flip(flip_screen() ? TILEMAP_FLIPX | TILEMAP_FLIPY : 0);
+ m_tx_tilemap->set_flip(flip_screen() ? TILEMAP_FLIPX | TILEMAP_FLIPY : 0);
- m_bg_tilemap->draw(screen, bitmap, cliprect, 0, 0);
+ m_tx_tilemap->draw(screen, bitmap, cliprect, 0, 0);
/* draw the sprites */
- for (offs = 0x3c; offs <= 0xfc; offs += 0x40)
+ for (offs = 0x3c; offs <= m_spritelimit; offs += 0x40)
draw_sprites(bitmap, cliprect, offs);
return 0;
diff --git a/src/mame/video/namco_c355spr.cpp b/src/mame/video/namco_c355spr.cpp
index c1e67d2dac1..13519e184ec 100644
--- a/src/mame/video/namco_c355spr.cpp
+++ b/src/mame/video/namco_c355spr.cpp
@@ -444,8 +444,8 @@ void namco_c355spr_device::get_sprites()
get_list(1, &m_spriteram[buffer][0x14000/2], &m_spriteram[buffer][0x10000/2]);
}
-template<class _BitmapClass>
-void namco_c355spr_device::draw_sprites(screen_device &screen, _BitmapClass &bitmap, const rectangle &cliprect, int pri)
+template<class BitmapClass>
+void namco_c355spr_device::draw_sprites(screen_device &screen, BitmapClass &bitmap, const rectangle &cliprect, int pri)
{
// int offs = spriteram16[0x18000/2]; /* end-of-sprite-list */
if (pri == 0)
diff --git a/src/mame/video/namco_c355spr.h b/src/mame/video/namco_c355spr.h
index 4856733c1af..97e618596b8 100644
--- a/src/mame/video/namco_c355spr.h
+++ b/src/mame/video/namco_c355spr.h
@@ -73,7 +73,7 @@ private:
void get_single_sprite(const uint16_t *pSource, c355_sprite *sprite_ptr);
void get_list(int no, const uint16_t *pSpriteList16, const uint16_t *pSpriteTable);
void get_sprites();
- template<class _BitmapClass> void draw_sprites(screen_device &screen, _BitmapClass &bitmap, const rectangle &cliprect, int pri);
+ template<class BitmapClass> void draw_sprites(screen_device &screen, BitmapClass &bitmap, const rectangle &cliprect, int pri);
std::unique_ptr<c355_sprite []> m_spritelist[2];
const c355_sprite *m_sprite_end[2];
@@ -94,4 +94,3 @@ private:
DECLARE_DEVICE_TYPE(NAMCO_C355SPR, namco_c355spr_device)
#endif // MAME_VIDEO_NAMCO_C355SPR_H
-
diff --git a/src/mame/video/namcos22.cpp b/src/mame/video/namcos22.cpp
index a4841e3809a..ef5a609be03 100644
--- a/src/mame/video/namcos22.cpp
+++ b/src/mame/video/namcos22.cpp
@@ -22,10 +22,6 @@ void namcos22_renderer::init()
{
memset(&m_scenenode_root, 0, sizeof(m_scenenode_root));
m_scenenode_cur = nullptr;
-
- m_clipx = 320;
- m_clipy = 240;
- m_cliprect.set(0, 639, 0, 479);
}
@@ -237,31 +233,11 @@ void namcos22_renderer::renderscanline_sprite(int32_t scanline, const extent_t &
void namcos22_renderer::poly3d_drawquad(screen_device &screen, bitmap_rgb32 &bitmap, struct namcos22_scenenode *node)
{
- namcos22_object_data &extra = object_data_alloc();
vertex_t v[4];
vertex_t clipv[6];
int clipverts;
int vertnum;
-
int direct = node->data.quad.direct;
- int flags = node->data.quad.flags;
- int color = node->data.quad.color;
- int cz_adjust = node->data.quad.cz_adjust;
-
- extra.destbase = &bitmap;
- extra.pfade_enabled = 0;
- extra.zfog_enabled = 0;
- extra.fadefactor = 0;
- extra.fogfactor = 0;
-
- extra.pens = &m_state.m_palette->pen((color & 0x7f) << 8);
- extra.primap = &screen.priority();
- extra.bn = node->data.quad.texturebank;
- extra.flags = flags;
- extra.cz_adjust = cz_adjust;
- extra.cmode = node->data.quad.cmode;
- extra.prioverchar = ((node->data.quad.cmode & 7) == 1) ? 1 : 0;
- extra.prioverchar |= m_state.m_is_ss22 ? 2 : 0;
// scene clip
float cx = 320.0f + node->data.quad.vx;
@@ -317,6 +293,26 @@ void namcos22_renderer::poly3d_drawquad(screen_device &screen, bitmap_rgb32 &bit
}
}
+ namcos22_object_data &extra = object_data_alloc();
+ int flags = node->data.quad.flags;
+ int color = node->data.quad.color;
+ int cz_adjust = node->data.quad.cz_adjust;
+
+ extra.destbase = &bitmap;
+ extra.pfade_enabled = 0;
+ extra.zfog_enabled = 0;
+ extra.fadefactor = 0;
+ extra.fogfactor = 0;
+
+ extra.pens = &m_state.m_palette->pen((color & 0x7f) << 8);
+ extra.primap = &screen.priority();
+ extra.bn = node->data.quad.texturebank;
+ extra.flags = flags;
+ extra.cz_adjust = cz_adjust;
+ extra.cmode = node->data.quad.cmode;
+ extra.prioverchar = ((node->data.quad.cmode & 7) == 1) ? 1 : 0;
+ extra.prioverchar |= m_state.m_is_ss22 ? 2 : 0;
+
if (m_state.m_is_ss22)
{
// global fade
@@ -625,10 +621,6 @@ void namcos22_renderer::render_scene(screen_device &screen, bitmap_rgb32 &bitmap
node->data.nonleaf.next[i] = nullptr;
}
- m_clipx = 320;
- m_clipy = 240;
- m_cliprect.set(0, 639, 0, 479);
-
wait("render_scene");
}
@@ -1221,10 +1213,10 @@ void namcos22_state::slavesim_handle_bb0003(const s32 *src)
m_camera_vx = (s16)(src[0x5] >> 16);
m_camera_vy = (s16)(src[0x5] & 0xffff);
m_camera_zoom = dspfloat_to_nativefloat(src[0x6]);
- m_camera_vl = dspfloat_to_nativefloat(src[0x7]) * m_camera_zoom;
- m_camera_vr = dspfloat_to_nativefloat(src[0x8]) * m_camera_zoom;
- m_camera_vu = dspfloat_to_nativefloat(src[0x9]) * m_camera_zoom;
- m_camera_vd = dspfloat_to_nativefloat(src[0xa]) * m_camera_zoom;
+ m_camera_vl = dspfloat_to_nativefloat(src[0x7]) * m_camera_zoom + 0.5f;
+ m_camera_vr = dspfloat_to_nativefloat(src[0x8]) * m_camera_zoom + 0.5f;
+ m_camera_vu = dspfloat_to_nativefloat(src[0x9]) * m_camera_zoom + 0.5f;
+ m_camera_vd = dspfloat_to_nativefloat(src[0xa]) * m_camera_zoom + 0.5f;
m_reflection = src[0x2] >> 16 & 0x30; // z too?
m_cullflip = (m_reflection == 0x10 || m_reflection == 0x20);
@@ -1893,7 +1885,10 @@ READ16_MEMBER(namcos22_state::spotram_r)
{
// read
u16 ret = m_spotram[m_spotram_address >> 1 & 0x7ff];
- m_spotram_address += 2;
+
+ if (!machine().side_effects_disabled())
+ m_spotram_address += 2;
+
return ret;
}
diff --git a/src/mame/video/supbtime.cpp b/src/mame/video/supbtime.cpp
index 797e61d1e4d..d77b7ca0a02 100644
--- a/src/mame/video/supbtime.cpp
+++ b/src/mame/video/supbtime.cpp
@@ -6,13 +6,16 @@
Video mixing
+ - are there priority registers / bits in the sprites that would allow
+ this to be collapsed further?
+
***************************************************************************/
#include "emu.h"
#include "includes/supbtime.h"
-// End sequence uses rowscroll '98 c0' on pf1 (jmp to 1d61a on supbtimej)
-uint32_t supbtime_state::screen_update_supbtime(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
+
+uint32_t supbtime_state::screen_update_common(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect, bool use_offsets)
{
address_space &space = machine().dummy_space();
uint16_t flip = m_deco_tilegen->pf_control_r(space, 0, 0xffff);
@@ -23,6 +26,23 @@ uint32_t supbtime_state::screen_update_supbtime(screen_device &screen, bitmap_in
bitmap.fill(768, cliprect);
+ if (use_offsets)
+ {
+ // chinatwn and tumblep are verified as needing a 1 pixel offset on the tilemaps to match original hardware (supbtime appears to not want them)
+ m_deco_tilegen->set_scrolldx(0, 0, 1, -1);
+ m_deco_tilegen->set_scrolldx(0, 1, 1, -1);
+ m_deco_tilegen->set_scrolldx(1, 0, 1, -1);
+ m_deco_tilegen->set_scrolldx(1, 1, 1, -1);
+ }
+
+ return 0;
+}
+
+// End sequence uses rowscroll '98 c0' on pf1 (jmp to 1d61a on supbtimej)
+uint32_t supbtime_state::screen_update_supbtime(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
+{
+ screen_update_common(screen, bitmap, cliprect, false);
+
m_deco_tilegen->tilemap_2_draw(screen, bitmap, cliprect, 0, 0);
m_sprgen->draw_sprites(bitmap, cliprect, m_spriteram, 0x400);
m_deco_tilegen->tilemap_1_draw(screen, bitmap, cliprect, 0, 0);
@@ -30,18 +50,20 @@ uint32_t supbtime_state::screen_update_supbtime(screen_device &screen, bitmap_in
return 0;
}
-// Tumblepop is one of few games to take advantage of the playfields ability
-// to switch between 8*8 tiles and 16*16 tiles.
-uint32_t supbtime_state::screen_update_tumblep(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
+uint32_t supbtime_state::screen_update_chinatwn(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
{
- address_space &space = machine().dummy_space();
- uint16_t flip = m_deco_tilegen->pf_control_r(space, 0, 0xffff);
+ screen_update_common(screen, bitmap, cliprect, true);
- flip_screen_set(BIT(flip, 7));
- m_sprgen->set_flip_screen(BIT(flip, 7));
- m_deco_tilegen->pf_update(m_pf_rowscroll[0], m_pf_rowscroll[1]);
+ m_deco_tilegen->tilemap_2_draw(screen, bitmap, cliprect, 0, 0);
+ m_sprgen->draw_sprites(bitmap, cliprect, m_spriteram, 0x400);
+ m_deco_tilegen->tilemap_1_draw(screen, bitmap, cliprect, 0, 0);
+
+ return 0;
+}
- bitmap.fill(256+512, cliprect); // not verified
+uint32_t supbtime_state::screen_update_tumblep(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
+{
+ screen_update_common(screen, bitmap, cliprect, true);
m_deco_tilegen->tilemap_2_draw(screen, bitmap, cliprect, TILEMAP_DRAW_OPAQUE, 0);
m_deco_tilegen->tilemap_1_draw(screen, bitmap, cliprect, 0, 0);
diff --git a/src/mame/video/xavix.cpp b/src/mame/video/xavix.cpp
index 4e4187ce6ca..7730560db9f 100644
--- a/src/mame/video/xavix.cpp
+++ b/src/mame/video/xavix.cpp
@@ -86,14 +86,20 @@ void xavix_state::handle_palette(screen_device &screen, bitmap_ind16 &bitmap, co
//if (h_raw > 24)
// LOG("hraw >24 (%02x)\n", h_raw);
- //if (l_raw > 17)
- // LOG("lraw >17 (%02x)\n", l_raw);
+ //if (l_raw > 24)
+ // LOG("lraw >24 (%02x)\n", l_raw);
//if (s_raw > 7)
// LOG("s_raw >5 (%02x)\n", s_raw);
- double l = (double)l_raw / 17.0f;
+ double l = (double)l_raw / 24.0f; // ekara and drgqst go up to 23 during fades, expect that to be brightest
+ l = l * (std::atan(1)*2); // does not appear to be a linear curve
+ l = std::sin(l);
+
double s = (double)s_raw / 7.0f;
+ s = s * (std::atan(1)*2); // does not appear to be a linear curve
+ s = std::sin(s);
+
double h = (double)h_raw / 24.0f; // hue values 24-31 render as transparent
double r, g, b;
@@ -603,6 +609,11 @@ void xavix_state::draw_tile_line(screen_device &screen, bitmap_ind16 &bitmap, co
if ((ypos >= cliprect.min_y && ypos <= cliprect.max_y))
{
+ // if bpp>4 then ignore unaligned palette selects bits based on bpp
+ // ttv_lotr uses 5bpp graphics (so 32 colour alignment) but sets palette 0xf (a 16 colour boundary) when it expects palette 0xe
+ if (bpp>4)
+ pal &= (0xf<<(bpp-4));
+
int bits_per_tileline = drawwidth * bpp;
// set the address here so we can increment in bits in the draw function
@@ -744,7 +755,8 @@ uint32_t xavix_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap,
dat |= (get_next_bit() << i);
}
- yposptr[x] = dat + 0x100;
+ if (x < cliprect.max_x)
+ yposptr[x] = dat + 0x100;
}
}
diff --git a/src/mame/video/zx8301.h b/src/mame/video/zx8301.h
index 1d3b64f22d8..568f3303b6b 100644
--- a/src/mame/video/zx8301.h
+++ b/src/mame/video/zx8301.h
@@ -35,17 +35,6 @@
#pragma once
-
-
-///*************************************************************************
-// INTERFACE CONFIGURATION MACROS
-///*************************************************************************
-
-#define MCFG_ZX8301_VSYNC_CALLBACK(_write) \
- downcast<zx8301_device &>(*device).set_vsync_wr_callback(DEVCB_##_write);
-
-
-
///*************************************************************************
// TYPE DEFINITIONS
///*************************************************************************
@@ -66,7 +55,7 @@ public:
zx8301_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
- template <class Object> devcb_base &set_vsync_wr_callback(Object &&cb) { return m_write_vsync.set_callback(std::forward<Object>(cb)); }
+ auto vsync_wr_callback() { return m_write_vsync.bind(); }
DECLARE_WRITE8_MEMBER( control_w );
DECLARE_READ8_MEMBER( data_r );