diff options
Diffstat (limited to '3rdparty/asmjit/tools/tablegen-x86.js')
-rw-r--r-- | 3rdparty/asmjit/tools/tablegen-x86.js | 1318 |
1 files changed, 729 insertions, 589 deletions
diff --git a/3rdparty/asmjit/tools/tablegen-x86.js b/3rdparty/asmjit/tools/tablegen-x86.js index dfd0f40b6ef..61fc7349605 100644 --- a/3rdparty/asmjit/tools/tablegen-x86.js +++ b/3rdparty/asmjit/tools/tablegen-x86.js @@ -1,25 +1,7 @@ -// AsmJit - Machine code generation for C++ +// This file is part of AsmJit project <https://asmjit.com> // -// * Official AsmJit Home Page: https://asmjit.com -// * Official Github Repository: https://github.com/asmjit/asmjit -// -// Copyright (c) 2008-2020 The AsmJit Authors -// -// This software is provided 'as-is', without any express or implied -// warranty. In no event will the authors be held liable for any damages -// arising from the use of this software. -// -// Permission is granted to anyone to use this software for any purpose, -// including commercial applications, and to alter it and redistribute it -// freely, subject to the following restrictions: -// -// 1. The origin of this software must not be misrepresented; you must not -// claim that you wrote the original software. If you use this software -// in a product, an acknowledgment in the product documentation would be -// appreciated but is not required. -// 2. Altered source versions must be plainly marked as such, and must not be -// misrepresented as being the original software. -// 3. This notice may not be removed or altered from any source distribution. +// See asmjit.h or LICENSE.md for license and copyright information +// SPDX-License-Identifier: Zlib // ============================================================================ // tablegen-x86.js @@ -69,7 +51,18 @@ const x86isa = new asmdb.x86.ISA({ ["imul", "r64, ib" , "RMI" , "REX.W 6B /r ib", "X64 OF=W SF=W ZF=U AF=U PF=U CF=W"], ["imul", "r16, iw" , "RMI" , "66 69 /r iw" , "ANY OF=W SF=W ZF=U AF=U PF=U CF=W"], ["imul", "r32, id" , "RMI" , "69 /r id" , "ANY OF=W SF=W ZF=U AF=U PF=U CF=W"], - ["imul", "r64, id" , "RMI" , "REX.W 69 /r id", "X64 OF=W SF=W ZF=U AF=U PF=U CF=W"] + ["imul", "r64, id" , "RMI" , "REX.W 69 /r id", "X64 OF=W SF=W ZF=U AF=U PF=U CF=W"], + + // Movabs (X64 only). + ["movabs", "W:r64, iq/uq" , "I" , "REX.W B8+r iq", "X64"], + ["movabs", "w:al, moff8" , "NONE", "A0" , "X64"], + ["movabs", "w:ax, moff16" , "NONE", "66 A1" , "X64"], + ["movabs", "W:eax, moff32", "NONE", "A1" , "X64"], + ["movabs", "W:rax, moff64", "NONE", "REX.W A1" , "X64"], + ["movabs", "W:moff8, al" , "NONE", "A2" , "X64"], + ["movabs", "W:moff16, ax" , "NONE", "66 A3" , "X64"], + ["movabs", "W:moff32, eax", "NONE", "A3" , "X64"], + ["movabs", "W:moff64, rax", "NONE", "REX.W A3" , "X64"] ] }); @@ -138,6 +131,25 @@ class Filter { // [tablegen.x86.GenUtils] // ============================================================================ +const VexToEvexMap = { + "vbroadcastf128": "vbroadcastf32x4", + "vbroadcasti128": "vbroadcasti32x4", + "vextractf128": "vextractf32x4", + "vextracti128": "vextracti32x4", + "vinsertf128": "vinsertf32x4", + "vinserti128": "vinserti32x4", + "vmovdqa": "vmovdqa32", + "vmovdqu": "vmovdqu32", + "vpand": "vpandd", + "vpandn": "vpandnd", + "vpor": "vpord", + "vpxor": "vpxord", + "vroundpd": "vrndscalepd", + "vroundps": "vrndscaleps", + "vroundsd": "vrndscalesd", + "vroundss": "vrndscaless" +}; + class GenUtils { static cpuArchOf(dbInsts) { var anyArch = false; @@ -158,20 +170,66 @@ class GenUtils { return ArrayUtils.sorted(dbInsts.unionCpuFeatures()); } - static flagsOf(dbInsts) { - function replace(map, a, b, c) { - if (map[a] && map[b]) { - delete map[a]; - delete map[b]; - map[c] = true; + static assignVexEvexCompatibilityFlags(f, dbInsts) { + const vexInsts = dbInsts.filter((inst) => { return inst.prefix === "VEX"; }); + const evexInsts = dbInsts.filter((inst) => { return inst.prefix === "EVEX"; }); + + function isCompatible(vexInst, evexInst) { + if (vexInst.operands.length !== evexInst.operands.length) + return false; + + for (let i = 0; i < vexInst.operands.length; i++) { + const vexOp = vexInst.operands[i]; + const evexOp = evexInst.operands[i]; + + if (vexOp.data === evexOp.data) + continue; + + if (vexOp.reg && vexOp.reg === evexOp.reg) + continue; + if (vexOp.mem && vexOp.mem === evexOp.mem) + continue; + + return false; } + return true; + } + + let compatible = 0; + for (const vexInst of vexInsts) { + for (const evexInst of evexInsts) { + if (isCompatible(vexInst, evexInst)) { + compatible++; + break; + } + } + } + + if (compatible == vexInsts.length) { + f.EvexCompat = true; + return true; } + if (evexInsts[0].operands[0].reg === "k") { + f.EvexKReg = true; + return true; + } + + if (evexInsts[0].operands.length == 2 && vexInsts[0].operands.length === 3) { + f.EvexTwoOp = true; + return true; + } + + return false; + } + + static flagsOf(dbInsts) { const f = Object.create(null); var i, j; var mib = dbInsts.length > 0 && /^(?:bndldx|bndstx)$/.test(dbInsts[0].name); - if (mib) f.Mib = true; + if (mib) + f.Mib = true; var mmx = false; var vec = false; @@ -190,7 +248,7 @@ class GenUtils { const op = operands[j]; if (op.reg === "mm") mmx = true; - else if (/^(k|xmm|ymm|zmm)$/.test(op.reg)) { + else if (/^(xmm|ymm|zmm)$/.test(op.reg)) { vec = true; } } @@ -203,13 +261,14 @@ class GenUtils { const dbInst = dbInsts[i]; const operands = dbInst.operands; - if (dbInst.attributes.Lock ) f.Lock = true; - if (dbInst.attributes.XAcquire ) f.XAcquire = true; - if (dbInst.attributes.XRelease ) f.XRelease = true; - if (dbInst.attributes.BND ) f.Rep = true; - if (dbInst.attributes.REP ) f.Rep = true; - if (dbInst.attributes.REPNE ) f.Rep = true; - if (dbInst.attributes.RepIgnored) f.RepIgnored = true; + if (dbInst.attributes.Lock ) f.Lock = true; + if (dbInst.attributes.XAcquire ) f.XAcquire = true; + if (dbInst.attributes.XRelease ) f.XRelease = true; + if (dbInst.attributes.BND ) f.Rep = true; + if (dbInst.attributes.REP ) f.Rep = true; + if (dbInst.attributes.REPNE ) f.Rep = true; + if (dbInst.attributes.RepIgnored ) f.RepIgnored = true; + if (dbInst.attributes.ImplicitZeroing) f.Avx512ImplicitZ = true; if (dbInst.fpu) { for (var j = 0; j < operands.length; j++) { @@ -221,6 +280,9 @@ class GenUtils { } } + if (dbInst.attributes.Tsib) + f.Tsib = true; + if (dbInst.vsibReg) f.Vsib = true; @@ -230,6 +292,9 @@ class GenUtils { if (dbInst.prefix === "EVEX") { f.Evex = true; + if (dbInst.extensions["AVX512_VNNI"]) + f.PreferEvex = true; + if (dbInst.kmask) f.Avx512K = true; if (dbInst.zmask) f.Avx512Z = true; @@ -239,22 +304,18 @@ class GenUtils { if (dbInst.broadcast) f["Avx512B" + String(dbInst.elementSize)] = true; if (dbInst.tupleType === "T1_4X") f.Avx512T4X = true; } + + if (VexToEvexMap[dbInst.name]) + f.EvexTransformable = true; + } + + if (f.Vex && f.Evex) { + GenUtils.assignVexEvexCompatibilityFlags(f, dbInsts) } - replace(f, "Avx512K" , "Avx512Z" , "Avx512KZ"); - replace(f, "Avx512ER" , "Avx512SAE" , "Avx512ER_SAE"); - replace(f, "Avx512KZ" , "Avx512SAE" , "Avx512KZ_SAE"); - replace(f, "Avx512KZ" , "Avx512ER_SAE", "Avx512KZ_ER_SAE"); - replace(f, "Avx512K" , "Avx512B32" , "Avx512K_B32"); - replace(f, "Avx512K" , "Avx512B64" , "Avx512K_B64"); - replace(f, "Avx512KZ" , "Avx512B32" , "Avx512KZ_B32"); - replace(f, "Avx512KZ" , "Avx512B64" , "Avx512KZ_B64"); - replace(f, "Avx512KZ_SAE" , "Avx512B32" , "Avx512KZ_SAE_B32"); - replace(f, "Avx512KZ_SAE" , "Avx512B64" , "Avx512KZ_SAE_B64"); - replace(f, "Avx512KZ_ER_SAE", "Avx512B32" , "Avx512KZ_ER_SAE_B32"); - replace(f, "Avx512KZ_ER_SAE", "Avx512B64" , "Avx512KZ_ER_SAE_B64"); - - return Object.getOwnPropertyNames(f); + const result = Object.getOwnPropertyNames(f); + result.sort(); + return result; } static eqOps(aOps, aFrom, bOps, bFrom) { @@ -279,6 +340,20 @@ class GenUtils { } } + // Prevent some instructions from having implicit memory size if that would + // make them ambiguous. There are some instructions where the ambiguity is + // okay, but some like 'push' and 'pop' where it isn't. + static canUseImplicitMemSize(name) { + switch (name) { + case "pop": + case "push": + return false; + + default: + return true; + } + } + static singleRegCase(name) { switch (name) { case "xchg" : @@ -308,6 +383,16 @@ class GenUtils { case "xorpd" : case "vxorpd" : case "xorps" : case "vxorps" : + case "kxnorb": + case "kxnord": + case "kxnorw": + case "kxnorq": + + case "kxorb": + case "kxord": + case "kxorw": + case "kxorq": + case "sub" : case "sbb" : case "psubb" : case "vpsubb" : @@ -362,12 +447,12 @@ class GenUtils { } } - static controlType(dbInsts) { + static controlFlow(dbInsts) { if (dbInsts.checkAttribute("Control", "Jump")) return "Jump"; if (dbInsts.checkAttribute("Control", "Call")) return "Call"; if (dbInsts.checkAttribute("Control", "Branch")) return "Branch"; if (dbInsts.checkAttribute("Control", "Return")) return "Return"; - return "None"; + return "Regular"; } } @@ -378,6 +463,8 @@ class GenUtils { class X86TableGen extends core.TableGen { constructor() { super("X86"); + + this.emitMissingString = ""; } // -------------------------------------------------------------------------- @@ -431,31 +518,32 @@ class X86TableGen extends core.TableGen { FAIL(`Instruction '${name}' not found in asmdb`); const flags = GenUtils.flagsOf(dbInsts); - const controlType = GenUtils.controlType(dbInsts); + const controlFlow = GenUtils.controlFlow(dbInsts); const singleRegCase = GenUtils.singleRegCase(name); this.addInst({ - id : 0, // Instruction id (numeric value). - name : name, // Instruction name. - enum : enum_, // Instruction enum without `kId` prefix. - dbInsts : dbInsts, // All dbInsts returned from asmdb query. - encoding : encoding, // Instruction encoding. - opcode0 : opcode0, // Primary opcode. - opcode1 : opcode1, // Secondary opcode. - flags : flags, - signatures : null, // Instruction signatures. - controlType : controlType, - singleRegCase : singleRegCase, - - mainOpcodeValue : -1, // Main opcode value (0.255 hex). - mainOpcodeIndex : -1, // Index to InstDB::_mainOpcodeTable. - altOpcodeIndex : -1, // Index to InstDB::_altOpcodeTable. - nameIndex : -1, // Index to InstDB::_nameData. - commonInfoIndexA : -1, - commomInfoIndexB : -1, - - signatureIndex : -1, - signatureCount : -1 + id : 0, // Instruction id (numeric value). + name : name, // Instruction name. + displayName : name, // Instruction name to display. + enum : enum_, // Instruction enum without `kId` prefix. + dbInsts : dbInsts, // All dbInsts returned from asmdb query. + encoding : encoding, // Instruction encoding. + opcode0 : opcode0, // Primary opcode. + opcode1 : opcode1, // Secondary opcode. + flags : flags, + signatures : null, // Instruction signatures. + controlFlow : controlFlow, + singleRegCase : singleRegCase, + + mainOpcodeValue : -1, // Main opcode value (0.255 hex). + mainOpcodeIndex : -1, // Index to InstDB::_mainOpcodeTable. + altOpcodeIndex : -1, // Index to InstDB::_altOpcodeTable. + nameIndex : -1, // Index to InstDB::_nameData. + commonInfoIndex : -1, + additionalInfoIndex: -1, + + signatureIndex : -1, + signatureCount : -1 }); } @@ -468,15 +556,15 @@ class X86TableGen extends core.TableGen { merge() { var s = StringUtils.format(this.insts, "", true, function(inst) { return "INST(" + - String(inst.enum ).padEnd(17) + ", " + - String(inst.encoding ).padEnd(19) + ", " + - String(inst.opcode0 ).padEnd(26) + ", " + - String(inst.opcode1 ).padEnd(26) + ", " + - String(inst.mainOpcodeIndex ).padEnd( 3) + ", " + - String(inst.altOpcodeIndex ).padEnd( 3) + ", " + - String(inst.nameIndex ).padEnd( 5) + ", " + - String(inst.commonInfoIndexA).padEnd( 3) + ", " + - String(inst.commomInfoIndexB).padEnd( 3) + ")"; + String(inst.enum ).padEnd(17) + ", " + + String(inst.encoding ).padEnd(19) + ", " + + String(inst.opcode0 ).padEnd(26) + ", " + + String(inst.opcode1 ).padEnd(26) + ", " + + String(inst.mainOpcodeIndex ).padEnd( 3) + ", " + + String(inst.altOpcodeIndex ).padEnd( 3) + ", " + + String(inst.nameIndex ).padEnd( 5) + ", " + + String(inst.commonInfoIndex ).padEnd( 3) + ", " + + String(inst.additionalInfoIndex).padEnd( 3) + ")"; }) + "\n"; this.inject("InstInfo", s, this.insts.length * 8); } @@ -509,13 +597,16 @@ class X86TableGen extends core.TableGen { String(inst.encoding ).padEnd(19) + ", " + String(inst.opcode0 ).padEnd(26) + ", " + String(inst.opcode1 ).padEnd(26) + ", " + - String("0" ).padEnd( 4) + ", " + + String("0" ).padEnd( 3) + ", " + + String("0" ).padEnd( 3) + ", " + + String("0" ).padEnd( 5) + ", " + String("0" ).padEnd( 3) + ", " + String("0" ).padEnd( 3) + "),\n"; } } }, this); console.log(out); + console.log(this.emitMissingString); } newInstFromGroup(dbInsts) { @@ -540,24 +631,83 @@ class X86TableGen extends core.TableGen { return s === "VEX" || s === "EVEX" || s === "XOP"; } + function formatEmit(dbi) { + const results = []; + const nameUp = dbi.name[0].toUpperCase() + dbi.name.substr(1); + + for (let choice = 0; choice < 2; choice++) { + let s = `ASMJIT_INST_${dbi.operands.length}x(${dbi.name}, ${nameUp}`; + for (let j = 0; j < dbi.operands.length; j++) { + s += ", "; + const op = dbi.operands[j]; + var reg = op.reg; + var mem = op.mem; + + if (op.isReg() && op.isMem()) { + if (choice == 0) mem = null; + if (choice == 1) reg = null; + } + + if (reg) { + if (reg === "xmm" || reg === "ymm" || reg === "zmm") + s += "Vec"; + else if (reg === "k") + s += "KReg"; + else if (reg === "r32" || reg === "r64" || reg === "r16" || reg === "r8") + s += "Gp"; + else + s += reg; + } + else if (mem) { + s += "Mem"; + } + else if (op.isImm()) { + s += "Imm"; + } + else { + s += "Unknown"; + } + } + s += `)`; + results.push(s); + } + + return results; + } + var dbi = dbInsts[0]; - var id = this.insts.length; - var name = dbi.name; - var enum_ = name[0].toUpperCase() + name.substr(1); + var id = this.insts.length; + var name = dbi.name; + var enum_ = name[0].toUpperCase() + name.substr(1); - var opcode = dbi.opcodeHex; - var rm = dbi.rm; - var mm = dbi.mm; - var pp = dbi.pp; + var opcode = dbi.opcodeHex; + var modR = dbi.modR; + var mm = dbi.mm; + var pp = dbi.pp; var encoding = dbi.encoding; - var isVec = isVecPrefix(dbi.prefix); - - var access = GetAccess(dbi); + var isVec = isVecPrefix(dbi.prefix); + var evexCount = 0; + + var access = GetAccess(dbi); + + var vexL = undefined; + var vexW = undefined; + var evexW = undefined; + var cdshl = "_"; + var tupleType = "_"; + + const tupleTypeToCDSHL = { + "FVM": "4", + "FV": "4", + "HVM": "3", + "HV": "3", + "QVM": "2", + "QV": "2", + "T1S": "?" + } - var vexL = undefined; - var vexW = undefined; - var evexW = undefined; + const emitMap = {}; for (var i = 0; i < dbInsts.length; i++) { dbi = dbInsts[i]; @@ -577,47 +727,66 @@ class X86TableGen extends core.TableGen { } if (dbi.prefix === "EVEX") { + evexCount++; var newEvexW = String(dbi.w === "W0" ? 0 : dbi.w === "W1" ? 1 : "_"); if (evexW !== undefined && evexW !== newEvexW) evexW = "x"; else evexW = newEvexW; + + if (dbi.tupleType) { + if (tupleType !== "_" && tupleType !== dbi.tupleType) { + console.log(`${dbi.name}: WARNING: TupleType ${tupleType} != ${dbi.tupleType}`); + } + + tupleType = dbi.tupleType; + } } - if (opcode !== dbi.opcodeHex ) { console.log(`ISSUE: Opcode ${opcode} != ${dbi.opcodeHex}`); return null; } - if (rm !== dbi.rm ) { console.log(`ISSUE: RM ${rm} != ${dbi.rm}`); return null; } - if (mm !== dbi.mm ) { console.log(`ISSUE: MM ${mm} != ${dbi.mm}`); return null; } - if (pp !== dbi.pp ) { console.log(`ISSUE: PP ${pp} != ${dbi.pp}`); return null; } - if (encoding !== dbi.encoding ) { console.log(`ISSUE: Enc ${encoding} != ${dbi.encoding}`); return null; } - if (access !== GetAccess(dbi)) { console.log(`ISSUE: Access ${access} != ${GetAccess(dbi)}`); return null; } - if (isVec != isVecPrefix(dbi.prefix)) { console.log(`ISSUE: Vex/Non-Vex mismatch`); return null; } + if (opcode !== dbi.opcodeHex ) { console.log(`${dbi.name}: ISSUE: Opcode ${opcode} != ${dbi.opcodeHex}`); return null; } + if (modR !== dbi.modR ) { console.log(`${dbi.name}: ISSUE: ModR ${modR} != ${dbi.modR}`); return null; } + if (mm !== dbi.mm ) { console.log(`${dbi.name}: ISSUE: MM ${mm} != ${dbi.mm}`); return null; } + if (pp !== dbi.pp ) { console.log(`${dbi.name}: ISSUE: PP ${pp} != ${dbi.pp}`); return null; } + if (encoding !== dbi.encoding ) { console.log(`${dbi.name}: ISSUE: Enc ${encoding} != ${dbi.encoding}`); return null; } + if (access !== GetAccess(dbi)) { console.log(`${dbi.name}: ISSUE: Access ${access} != ${GetAccess(dbi)}`); return null; } + if (isVec != isVecPrefix(dbi.prefix)) { console.log(`${dbi.name}: ISSUE: Vex/Non-Vex mismatch`); return null; } + + formatEmit(dbi).forEach((emit) => { + if (!emitMap[emit]) { + emitMap[emit] = true; + this.emitMissingString += emit + "\n"; + } + }); } + if (tupleType !== "_") + cdshl = tupleTypeToCDSHL[tupleType] || "?"; + var ppmm = pp.padEnd(2).replace(/ /g, "0") + mm.padEnd(4).replace(/ /g, "0") ; var composed = composeOpCode({ - type : isVec ? "V" : "O", + type : evexCount == dbInsts.length ? "E" : isVec ? "V" : "O", prefix: ppmm, opcode: opcode, - o : rm === "r" ? "_" : (rm ? rm : "_"), + o : modR === "r" ? "_" : (modR ? modR : "_"), l : vexL !== undefined ? vexL : "_", w : vexW !== undefined ? vexW : "_", ew : evexW !== undefined ? evexW : "_", - en : "_", - tt : "_ " + en : cdshl, + tt : dbi.modRM ? dbi.modRM + " " : tupleType.padEnd(3) }); return { - id : id, - name : name, - enum : enum_, - encoding : encoding, - opcode0 : composed, - opcode1 : "0", - nameIndex : -1, - commonInfoIndexA : -1, - commomInfoIndexB : -1 + id : id, + name : name, + enum : enum_, + encoding : encoding, + opcode0 : composed, + opcode1 : "0", + nameIndex : -1, + commonInfoIndex : -1, + additionalInfoIndex: -1 }; } @@ -663,11 +832,21 @@ class IdEnum extends core.IdEnum { var text = ""; var features = GenUtils.cpuFeaturesOf(dbInsts); + const priorityFeatures = ["AVX_VNNI"]; + if (features.length) { text += "{"; const avxFeatures = filterAVX(features, true); const otherFeatures = filterAVX(features, false); + for (const pf of priorityFeatures) { + const index = avxFeatures.indexOf(pf); + if (index != -1) { + avxFeatures.splice(index, 1); + avxFeatures.unshift(pf); + } + } + const vl = avxFeatures.indexOf("AVX512_VL"); if (vl !== -1) avxFeatures.splice(vl, 1); @@ -716,39 +895,103 @@ class AltOpcodeTable extends core.Task { const mainOpcodeTable = new IndexedArray(); const altOpcodeTable = new IndexedArray(); - mainOpcodeTable.addIndexed("O(000000,00,0,0,0,0,0,_ )"); + const cdttSimplification = { + "0" : "None", + "_" : "None", + "FV" : "ByLL", + "HV" : "ByLL", + "QV" : "ByLL", + "FVM" : "ByLL", + "T1S" : "None", + "T1F" : "None", + "T1_4X": "None", + "T2" : "None", + "T4" : "None", + "T8" : "None", + "HVM" : "ByLL", + "QVM" : "ByLL", + "OVM" : "ByLL", + "128" : "None", + "T4X" : "None" + } - function indexOpcode(opcode) { - if (opcode === "0") - return ["00", 0]; + const noOp = "O(000000,00,0,0,0,0,0,0 )"; + + mainOpcodeTable.addIndexed(noOp); - // O_FPU(__,__OP,_) - if (opcode.startsWith("O_FPU(")) { - var value = opcode.substring(11, 13); - var remaining = opcode.substring(0, 11) + "00" + opcode.substring(13); + function splitOpcodeToComponents(opcode) { + const i = opcode.indexOf("("); + const prefix = opcode.substr(0, i); + return [prefix].concat(opcode.substring(i + 1, opcode.length - 1).split(",")); + } - return [value, mainOpcodeTable.addIndexed(remaining.padEnd(26))]; + function normalizeOpcodeComponents(components) { + for (let i = 1; i < components.length; i++) { + components[i] = components[i].trim(); + // These all are zeros that only have some contextual meaning in the table, but the assembler doesn't care. + if (components[i] === "_" || components[i] === "I" || components[i] === "x") + components[i] = "0"; } - // X(______,OP,_,_,_,_,_,_ ) - if (opcode.startsWith("O_FPU(") || opcode.startsWith("O(") || opcode.startsWith("V(") || opcode.startsWith("E(")) { - var value = opcode.substring(9, 11); - var remaining = opcode.substring(0, 9) + "00" + opcode.substring(11); + // Simplify CDTT (compressed displacement TupleType). + if (components.length >= 9) { + if (components[0] === "V" || components[0] === "E") { + const cdtt = components[8]; + if (cdttSimplification[cdtt] !== undefined) + components[8] = cdttSimplification[cdtt]; + } + } + return components; + } - remaining = remaining.replace(/,[_xI],/g, ",0,"); - remaining = remaining.replace(/,[_xI],/g, ",0,"); - return [value, mainOpcodeTable.addIndexed(remaining.padEnd(26))]; + function joinOpcodeComponents(components) { + const prefix = components[0]; + const values = components.slice(1); + if (values.length >= 8) + values[7] = values[7].padEnd(4); + return prefix + "(" + values.join(",") + ")"; + } + + function indexMainOpcode(opcode) { + if (opcode === "0") + return ["00", 0]; + + var opcodeByte = ""; + const components = normalizeOpcodeComponents(splitOpcodeToComponents(opcode)); + + if (components[0] === "O_FPU") { + // Reset opcode byte, this is stored in the instruction data itself. + opcodeByte = components[2].substr(2, 2); + components[2] = components[2].substr(0, 2) + "00"; + } + else if (components[0] === "O" || components[0] === "V" || components[0] === "E") { + // Reset opcode byte, this is stored in the instruction data itself. + opcodeByte = components[2]; + components[2] = "00"; + } + else { + FAIL(`Failed to process opcode '${opcode}'`); } - FAIL(`Failed to process opcode '${opcode}'`); + const newOpcode = joinOpcodeComponents(components); + return [opcodeByte, mainOpcodeTable.addIndexed(newOpcode.padEnd(27))]; + } + + function indexAltOpcode(opcode) { + if (opcode === "0") + opcode = noOp; + else + opcode = joinOpcodeComponents(normalizeOpcodeComponents(splitOpcodeToComponents(opcode))); + return altOpcodeTable.addIndexed(opcode.padEnd(27)); } insts.map((inst) => { - const [value, index] = indexOpcode(inst.opcode0); + const [value, index] = indexMainOpcode(inst.opcode0); inst.mainOpcodeValue = value; inst.mainOpcodeIndex = index; - inst.altOpcodeIndex = altOpcodeTable.addIndexed(inst.opcode1.padEnd(26)); + inst.altOpcodeIndex = indexAltOpcode(inst.opcode1); }); + // console.log(mainOpcodeTable.length); // console.log(StringUtils.format(mainOpcodeTable, kIndent, true)); @@ -763,138 +1006,6 @@ class AltOpcodeTable extends core.Task { } // ============================================================================ -// [tablegen.x86.SseToAvxTable] -// ============================================================================ -/* -// Removed from asmjit. -class InstSseToAvxTable extends core.Task { - constructor() { - super("InstSseToAvxTable", ["IdEnum"]); - } - - run() { - const insts = this.ctx.insts; - - const dataTable = new IndexedArray(); - const indexTable = []; - - function add(data) { - return dataTable.addIndexed("{ " + `SseToAvxData::kMode${data.mode}`.padEnd(28) + ", " + String(data.delta).padEnd(4) + " }"); - } - - // This will receive a zero index, which means that no SseToAvx or AvxToSSe translation is possible. - const kInvalidIndex = add({ mode: "None", delta: 0 }); - insts.forEach((inst) => { indexTable.push(kInvalidIndex); }); - - insts.forEach((inst) => { - // If it's not `kInvalidIndex` it's an AVX instruction that shares the - // SseToAvx data. We won't touch it as it already has the index assigned. - if (indexTable[inst.id] === kInvalidIndex) { - const data = this.calcSseToAvxData(inst.dbInsts); - const index = add(data); - - indexTable[inst.id] = index; - if (data.delta !== 0) - indexTable[this.ctx.instMap["v" + inst.name].id] = index; - } - }); - - this.inject("SseToAvxIndex", - disclaimer(`static const uint8_t sseToAvxIndex[] = {\n${StringUtils.format(indexTable, kIndent, -1)}\n};\n`), - indexTable.length * 1); - - this.inject("SseToAvxTable", - disclaimer(`static const SseToAvxData sseToAvxData[] = {\n${StringUtils.format(dataTable, kIndent, true)}\n};\n`), - dataTable.length * 2); - } - - filterSseToAvx(dbInsts) { - const filtered = []; - for (var x = 0; x < dbInsts.length; x++) { - const dbInst = dbInsts[x]; - const ops = dbInst.operands; - - // SSE instruction does never share its name with AVX one. - if (/^(VEX|XOP|EVEX)$/.test(dbInst.prefix)) - return []; - - var ok = false; - for (var y = 0; y < ops.length; y++) { - // There is no AVX instruction that works with MMX regs. - if (ops[y].reg === "mm") { ok = false; break; } - if (ops[y].reg === "xmm") { ok = true; } - } - - if (ok) - filtered.push(dbInst); - } - - return filtered; - } - - calcSseToAvxData(dbInsts) { - const data = { - mode : "None", // No conversion by default. - delta: 0 // 0 if no conversion is possible. - }; - - const dbSseInsts = this.filterSseToAvx(dbInsts); - if (!dbSseInsts.length) - return data; - - const sseName = dbSseInsts[0].name; - const avxName = "v" + sseName; - - const dbAvxInsts = this.ctx.query(avxName); - if (!dbAvxInsts.length) { - DEBUG(`SseToAvx: Instruction '${sseName}' has no AVX counterpart`); - return data; - } - - if (avxName === "vblendvpd" || avxName === "vblendvps" || avxName === "vpblendvb") { - // Special cases first. - data.mode = "Blend"; - } - else { - // Common case, deduce conversion mode by checking both SSE and AVX instructions. - const map = Object.create(null); - for (var sseIndex = 0; sseIndex < dbSseInsts.length; sseIndex++) { - const sseInst = dbSseInsts[sseIndex]; - var match = false; - - for (var avxIndex = 0; avxIndex < dbAvxInsts.length; avxIndex++) { - const avxInst = dbAvxInsts[avxIndex]; - - // Select only VEX instructions. - if (avxInst.prefix !== "VEX") continue; - - // Check if the AVX version is the same. - if (GenUtils.eqOps(avxInst.operands, 0, sseInst.operands, 0)) { - map.raw = true; - match = true; - } - else if (avxInst.operands[0].data === "xmm" && GenUtils.eqOps(avxInst.operands, 1, sseInst.operands, 0)) { - map.nds = true; - match = true; - } - } - - if (!match) { - const signature = sseInst.operands.map(function(op) { return op.data; }).join(", "); - console.log(`SseToAvx: Instruction '${sseName}(${signature})' has no AVX counterpart`); - return data; - } - } - - data.mode = (map.raw && !map.nds) ? "Move" : (map.raw && map.nds) ? "MoveIfMem" : "Extend"; - } - data.delta = this.ctx.instMap[avxName].id - this.ctx.instMap[sseName].id; - return data; - } -} -*/ - -// ============================================================================ // [tablegen.x86.InstSignatureTable] // ============================================================================ @@ -902,83 +1013,32 @@ const RegOp = MapUtils.arrayToMap(["al", "ah", "ax", "eax", "rax", "cl", "r8lo", const MemOp = MapUtils.arrayToMap(["m8", "m16", "m32", "m48", "m64", "m80", "m128", "m256", "m512", "m1024"]); const cmpOp = StringUtils.makePriorityCompare([ - "r8lo", "r8hi", "r16", "r32", "r64", "xmm", "ymm", "zmm", "mm", "k", "sreg", "creg", "dreg", "st", "bnd", - "mem", "vm", "m8", "m16", "m32", "m48", "m64", "m80", "m128", "m256", "m512", "m1024", - "mib", - "vm32x", "vm32y", "vm32z", "vm64x", "vm64y", "vm64z", - "memBase", "memES", "memDS", - "i4", "u4", "i8", "u8", "i16", "u16", "i32", "u32", "i64", "u64", - "rel8", "rel32", - "implicit" + "RegGpbLo", "RegGpbHi", "RegGpw", "RegGpd", "RegGpq", "RegXmm", "RegYmm", "RegZmm", "RegMm", "RegKReg", "RegSReg", "RegCReg", "RegDReg", "RegSt", "RegBnd", "RegTmm", + "MemUnspecified", "Mem8", "Mem16", "Mem32", "Mem48", "Mem64", "Mem80", "Mem128", "Mem256", "Mem512", "Mem1024", + "Vm32x", "Vm32y", "Vm32z", "Vm64x", "Vm64y", "Vm64z", + "ImmI4", "ImmU4", "ImmI8", "ImmU8", "ImmI16", "ImmU16", "ImmI32", "ImmU32", "ImmI64", "ImmU64", + "Rel8", "Rel32", + "FlagMemBase", + "FlagMemDs", + "FlagMemEs", + "FlagMib", + "FlagTMem", + "FlagConsecutive", + "FlagImplicit" ]); -const OpToAsmJitOp = { - "implicit": "F(Implicit)", - - "r8lo" : "F(GpbLo)", - "r8hi" : "F(GpbHi)", - "r16" : "F(Gpw)", - "r32" : "F(Gpd)", - "r64" : "F(Gpq)", - "xmm" : "F(Xmm)", - "ymm" : "F(Ymm)", - "zmm" : "F(Zmm)", - "mm" : "F(Mm)", - "k" : "F(KReg)", - "sreg" : "F(SReg)", - "creg" : "F(CReg)", - "dreg" : "F(DReg)", - "st" : "F(St)", - "bnd" : "F(Bnd)", - - "mem" : "F(Mem)", - "vm" : "F(Vm)", - - "i4" : "F(I4)", - "u4" : "F(U4)", - "i8" : "F(I8)", - "u8" : "F(U8)", - "i16" : "F(I16)", - "u16" : "F(U16)", - "i32" : "F(I32)", - "u32" : "F(U32)", - "i64" : "F(I64)", - "u64" : "F(U64)", - - "rel8" : "F(Rel8)", - "rel32" : "F(Rel32)", - - "m8" : "M(M8)", - "m16" : "M(M16)", - "m32" : "M(M32)", - "m48" : "M(M48)", - "m64" : "M(M64)", - "m80" : "M(M80)", - "m128" : "M(M128)", - "m256" : "M(M256)", - "m512" : "M(M512)", - "m1024" : "M(M1024)", - "mib" : "M(Mib)", - "mAny" : "M(Any)", - "vm32x" : "M(Vm32x)", - "vm32y" : "M(Vm32y)", - "vm32z" : "M(Vm32z)", - "vm64x" : "M(Vm64x)", - "vm64y" : "M(Vm64y)", - "vm64z" : "M(Vm64z)", - - "memBase" : "M(BaseOnly)", - "memDS" : "M(Ds)", - "memES" : "M(Es)" -}; - -function StringifyArray(a, map) { +function StringifyOpArray(a, map) { var s = ""; for (var i = 0; i < a.length; i++) { const op = a[i]; - if (!hasOwn.call(map, op)) + var mapped = null; + if (typeof map === "function") + mapped = map(op); + else if (hasOwn.call(map, op)) + mapped = map[op]; + else FAIL(`UNHANDLED OPERAND '${op}'`); - s += (s ? " | " : "") + map[op]; + s += (s ? " | " : "") + mapped; } return s ? s : "0"; } @@ -1021,32 +1081,18 @@ class OSignature { const index = asmdb.x86.Utils.regIndexOf(k); if (index !== null && index !== -1) { const kind = asmdb.x86.Utils.regKindOf(k); - if (indexKind !== kind) return false; + if (indexKind !== kind) + return false; } } } // Can merge... - for (k in bf) af[k] = true; + for (k in bf) + af[k] = true; return true; } - simplify() { - const flags = this.flags; - - // 32-bit register or 16-bit memory implies also 16-bit reg. - if (flags.r32 && flags.m16) { - flags.r16 = true; - } - - // 32-bit register or 8-bit memory implies also 16-bit and 8-bit reg. - if (flags.r32 && flags.m8) { - flags.r8lo = true; - flags.r8hi = true; - flags.r16 = true; - } - } - toString() { var s = ""; var flags = this.flags; @@ -1072,132 +1118,117 @@ class OSignature { } toAsmJitOpData() { - var oFlags = this.flags; - - var mFlags = Object.create(null); - var mMemFlags = Object.create(null); - var mExtFlags = Object.create(null); - var sRegMask = 0; + var opFlags = Object.create(null); + var regMask = 0; - for (var k in oFlags) { + for (var k in this.flags) { switch (k) { - case "implicit": - case "r8lo" : - case "r8hi" : - case "r16" : - case "r32" : - case "r64" : - case "creg" : - case "dreg" : - case "sreg" : - case "bnd" : - case "st" : - case "k" : - case "mm" : - case "xmm" : - case "ymm" : - case "zmm" : mFlags[k] = true; break; - - case "m8" : - case "m16" : - case "m32" : - case "m48" : - case "m64" : - case "m80" : - case "m128" : - case "m256" : - case "m512" : - case "m1024" : mFlags.mem = true; mMemFlags[k] = true; break; - case "mib" : mFlags.mem = true; mMemFlags.mib = true; break; - case "mem" : mFlags.mem = true; mMemFlags.mAny = true; break; - - case "memBase" : mFlags.mem = true; mMemFlags.memBase = true; break; - case "memDS" : mFlags.mem = true; mMemFlags.memDS = true; break; - case "memES" : mFlags.mem = true; mMemFlags.memES = true; break; - case "memZAX" : mFlags.mem = true; sRegMask |= 1 << 0; break; - case "memZSI" : mFlags.mem = true; sRegMask |= 1 << 6; break; - case "memZDI" : mFlags.mem = true; sRegMask |= 1 << 7; break; - - case "vm32x" : mFlags.vm = true; mMemFlags.vm32x = true; break; - case "vm32y" : mFlags.vm = true; mMemFlags.vm32y = true; break; - case "vm32z" : mFlags.vm = true; mMemFlags.vm32z = true; break; - case "vm64x" : mFlags.vm = true; mMemFlags.vm64x = true; break; - case "vm64y" : mFlags.vm = true; mMemFlags.vm64y = true; break; - case "vm64z" : mFlags.vm = true; mMemFlags.vm64z = true; break; - - case "i4" : - case "u4" : - case "i8" : - case "u8" : - case "i16" : - case "u16" : - case "i32" : - case "u32" : - case "i64" : - case "u64" : mFlags[k] = true; break; - - case "rel8" : - case "rel32" : - mFlags.i32 = true; - mFlags.i64 = true; - mFlags[k] = true; - break; - - case "rel16" : - mFlags.i32 = true; - mFlags.i64 = true; - mFlags.rel32 = true; - break; - - default: { - switch (k) { - case "es" : mFlags.sreg = true; sRegMask |= 1 << 1; break; - case "cs" : mFlags.sreg = true; sRegMask |= 1 << 2; break; - case "ss" : mFlags.sreg = true; sRegMask |= 1 << 3; break; - case "ds" : mFlags.sreg = true; sRegMask |= 1 << 4; break; - case "fs" : mFlags.sreg = true; sRegMask |= 1 << 5; break; - case "gs" : mFlags.sreg = true; sRegMask |= 1 << 6; break; - case "al" : mFlags.r8lo = true; sRegMask |= 1 << 0; break; - case "ah" : mFlags.r8hi = true; sRegMask |= 1 << 0; break; - case "ax" : mFlags.r16 = true; sRegMask |= 1 << 0; break; - case "eax" : mFlags.r32 = true; sRegMask |= 1 << 0; break; - case "rax" : mFlags.r64 = true; sRegMask |= 1 << 0; break; - case "cl" : mFlags.r8lo = true; sRegMask |= 1 << 1; break; - case "ch" : mFlags.r8hi = true; sRegMask |= 1 << 1; break; - case "cx" : mFlags.r16 = true; sRegMask |= 1 << 1; break; - case "ecx" : mFlags.r32 = true; sRegMask |= 1 << 1; break; - case "rcx" : mFlags.r64 = true; sRegMask |= 1 << 1; break; - case "dl" : mFlags.r8lo = true; sRegMask |= 1 << 2; break; - case "dh" : mFlags.r8hi = true; sRegMask |= 1 << 2; break; - case "dx" : mFlags.r16 = true; sRegMask |= 1 << 2; break; - case "edx" : mFlags.r32 = true; sRegMask |= 1 << 2; break; - case "rdx" : mFlags.r64 = true; sRegMask |= 1 << 2; break; - case "bl" : mFlags.r8lo = true; sRegMask |= 1 << 3; break; - case "bh" : mFlags.r8hi = true; sRegMask |= 1 << 3; break; - case "bx" : mFlags.r16 = true; sRegMask |= 1 << 3; break; - case "ebx" : mFlags.r32 = true; sRegMask |= 1 << 3; break; - case "rbx" : mFlags.r64 = true; sRegMask |= 1 << 3; break; - case "si" : mFlags.r16 = true; sRegMask |= 1 << 6; break; - case "esi" : mFlags.r32 = true; sRegMask |= 1 << 6; break; - case "rsi" : mFlags.r64 = true; sRegMask |= 1 << 6; break; - case "di" : mFlags.r16 = true; sRegMask |= 1 << 7; break; - case "edi" : mFlags.r32 = true; sRegMask |= 1 << 7; break; - case "rdi" : mFlags.r64 = true; sRegMask |= 1 << 7; break; - case "st0" : mFlags.st = true; sRegMask |= 1 << 0; break; - case "xmm0" : mFlags.xmm = true; sRegMask |= 1 << 0; break; - case "ymm0" : mFlags.ymm = true; sRegMask |= 1 << 0; break; - default: - console.log(`UNKNOWN OPERAND '${k}'`); - } - } + case "r8lo" : opFlags.RegGpbLo = true; break; + case "r8hi" : opFlags.RegGpbHi = true; break; + case "r16" : opFlags.RegGpw = true; break; + case "r32" : opFlags.RegGpd = true; break; + case "r64" : opFlags.RegGpq = true; break; + case "creg" : opFlags.RegCReg = true; break; + case "dreg" : opFlags.RegDReg = true; break; + case "sreg" : opFlags.RegSReg = true; break; + case "bnd" : opFlags.RegBnd = true; break; + case "st" : opFlags.RegSt = true; break; + case "k" : opFlags.RegKReg = true; break; + case "mm" : opFlags.RegMm = true; break; + case "xmm" : opFlags.RegXmm = true; break; + case "ymm" : opFlags.RegYmm = true; break; + case "zmm" : opFlags.RegZmm = true; break; + case "tmm" : opFlags.RegTmm = true; break; + + case "m8" : opFlags.Mem8 = true; break; + case "m16" : opFlags.Mem16 = true; break; + case "m32" : opFlags.Mem32 = true; break; + case "m48" : opFlags.Mem48 = true; break; + case "m64" : opFlags.Mem64 = true; break; + case "m80" : opFlags.Mem80 = true; break; + case "m128" : opFlags.Mem128 = true; break; + case "m256" : opFlags.Mem256 = true; break; + case "m512" : opFlags.Mem512 = true; break; + case "m1024" : opFlags.Mem1024 = true; break; + + case "mem" : opFlags.MemUnspecified = true; break; + case "mib" : opFlags.MemUnspecified = true; opFlags.FlagMib = true; break; + case "tmem" : opFlags.MemUnspecified = true; opFlags.FlagTMem = true; break; + + case "memBase" : opFlags.FlagMemBase = true; break; + case "memDS" : opFlags.FlagMemDs = true; break; + case "memES" : opFlags.FlagMemEs = true; break; + case "memZAX" : regMask |= 1 << 0; break; + case "memZSI" : regMask |= 1 << 6; break; + case "memZDI" : regMask |= 1 << 7; break; + + case "vm32x" : opFlags.Vm32x = true; break; + case "vm32y" : opFlags.Vm32y = true; break; + case "vm32z" : opFlags.Vm32z = true; break; + case "vm64x" : opFlags.Vm64x = true; break; + case "vm64y" : opFlags.Vm64y = true; break; + case "vm64z" : opFlags.Vm64z = true; break; + + case "i4" : opFlags.ImmI4 = true; break; + case "u4" : opFlags.ImmU4 = true; break; + case "i8" : opFlags.ImmI8 = true; break; + case "u8" : opFlags.ImmU8 = true; break; + case "i16" : opFlags.ImmI16 = true; break; + case "u16" : opFlags.ImmU16 = true; break; + case "i32" : opFlags.ImmI32 = true; break; + case "u32" : opFlags.ImmU32 = true; break; + case "i64" : opFlags.ImmI64 = true; break; + case "u64" : opFlags.ImmU64 = true; break; + + case "rel8" : opFlags.ImmI32 = true; opFlags.ImmI64 = true; opFlags.Rel8 = true; break; + case "rel16" : opFlags.ImmI32 = true; opFlags.ImmI64 = true; opFlags.Rel32 = true; break; + case "rel32" : opFlags.ImmI32 = true; opFlags.ImmI64 = true; opFlags.Rel32 = true; break; + + case "es" : opFlags.RegSReg = true; regMask |= 1 << 1; break; + case "cs" : opFlags.RegSReg = true; regMask |= 1 << 2; break; + case "ss" : opFlags.RegSReg = true; regMask |= 1 << 3; break; + case "ds" : opFlags.RegSReg = true; regMask |= 1 << 4; break; + case "fs" : opFlags.RegSReg = true; regMask |= 1 << 5; break; + case "gs" : opFlags.RegSReg = true; regMask |= 1 << 6; break; + case "al" : opFlags.RegGpbLo = true; regMask |= 1 << 0; break; + case "ah" : opFlags.RegGpbHi = true; regMask |= 1 << 0; break; + case "ax" : opFlags.RegGpw = true; regMask |= 1 << 0; break; + case "eax" : opFlags.RegGpd = true; regMask |= 1 << 0; break; + case "rax" : opFlags.RegGpq = true; regMask |= 1 << 0; break; + case "cl" : opFlags.RegGpbLo = true; regMask |= 1 << 1; break; + case "ch" : opFlags.RegGpbHi = true; regMask |= 1 << 1; break; + case "cx" : opFlags.RegGpw = true; regMask |= 1 << 1; break; + case "ecx" : opFlags.RegGpd = true; regMask |= 1 << 1; break; + case "rcx" : opFlags.RegGpq = true; regMask |= 1 << 1; break; + case "dl" : opFlags.RegGpbLo = true; regMask |= 1 << 2; break; + case "dh" : opFlags.RegGpbHi = true; regMask |= 1 << 2; break; + case "dx" : opFlags.RegGpw = true; regMask |= 1 << 2; break; + case "edx" : opFlags.RegGpd = true; regMask |= 1 << 2; break; + case "rdx" : opFlags.RegGpq = true; regMask |= 1 << 2; break; + case "bl" : opFlags.RegGpbLo = true; regMask |= 1 << 3; break; + case "bh" : opFlags.RegGpbHi = true; regMask |= 1 << 3; break; + case "bx" : opFlags.RegGpw = true; regMask |= 1 << 3; break; + case "ebx" : opFlags.RegGpd = true; regMask |= 1 << 3; break; + case "rbx" : opFlags.RegGpq = true; regMask |= 1 << 3; break; + case "si" : opFlags.RegGpw = true; regMask |= 1 << 6; break; + case "esi" : opFlags.RegGpd = true; regMask |= 1 << 6; break; + case "rsi" : opFlags.RegGpq = true; regMask |= 1 << 6; break; + case "di" : opFlags.RegGpw = true; regMask |= 1 << 7; break; + case "edi" : opFlags.RegGpd = true; regMask |= 1 << 7; break; + case "rdi" : opFlags.RegGpq = true; regMask |= 1 << 7; break; + case "st0" : opFlags.RegSt = true; regMask |= 1 << 0; break; + case "xmm0" : opFlags.RegXmm = true; regMask |= 1 << 0; break; + case "ymm0" : opFlags.RegYmm = true; regMask |= 1 << 0; break; + + case "implicit": opFlags.FlagImplicit = true; break; + + default: + console.log(`UNKNOWN OPERAND '${k}'`); } } - const sFlags = StringifyArray(ArrayUtils.sorted(mFlags , cmpOp), OpToAsmJitOp); - const sMemFlags = StringifyArray(ArrayUtils.sorted(mMemFlags, cmpOp), OpToAsmJitOp); - const sExtFlags = StringifyArray(ArrayUtils.sorted(mExtFlags, cmpOp), OpToAsmJitOp); - - return `ROW(${sFlags || 0}, ${sMemFlags || 0}, ${sExtFlags || 0}, ${decToHex(sRegMask, 2)})`; + const outputFlags = StringifyOpArray(ArrayUtils.sorted(opFlags, cmpOp), function(k) { return `F(${k})`; }); + return `ROW(${outputFlags || 0}, ${decToHex(regMask, 2)})`; } } @@ -1210,11 +1241,6 @@ class ISignature extends Array { this.implicit = 0; // Number of implicit operands. } - simplify() { - for (var i = 0; i < this.length; i++) - this[i].simplify(); - } - opEquals(other) { const len = this.length; if (len !== other.length) return false; @@ -1398,7 +1424,8 @@ class SignatureArray extends Array { // Patch all instructions to accept implicit-size memory operand. for (bIndex = 0; bIndex < sameSizeSet.length; bIndex++) { const bInst = sameSizeSet[bIndex]; - if (implicit) bInst[memPos].flags.mem = true; + if (implicit) + bInst[memPos].flags.mem = true; if (!implicit) DEBUG(`${this.name}: Explicit: ${bInst}`); @@ -1406,21 +1433,21 @@ class SignatureArray extends Array { } } - simplify() { - for (var i = 0; i < this.length; i++) - this[i].simplify(); - } - compact() { - for (var i = 0; i < this.length; i++) { - var row = this[i]; - var j = i + 1; - while (j < this.length) { - if (row.mergeWith(this[j])) { - this.splice(j, 1); - continue; + var didSomething = true; + while (didSomething) { + didSomething = false; + for (var i = 0; i < this.length; i++) { + var row = this[i]; + var j = i + 1; + while (j < this.length) { + if (row.mergeWith(this[j])) { + this.splice(j, 1); + didSomething = true; + continue; + } + j++; } - j++; } } } @@ -1433,14 +1460,7 @@ class SignatureArray extends Array { class InstSignatureTable extends core.Task { constructor() { super("InstSignatureTable"); - this.maxOpRows = 0; - this.opBlackList = { - "moff8" : true, - "moff16": true, - "moff32": true, - "moff64": true - }; } run() { @@ -1458,7 +1478,7 @@ class InstSignatureTable extends core.Task { const oSignatureArr = []; // Must be first to be assigned to zero. - const oSignatureNone = "ROW(0, 0, 0, 0xFF)"; + const oSignatureNone = "ROW(0, 0xFF)"; oSignatureMap[oSignatureNone] = [0]; oSignatureArr.push(oSignatureNone); @@ -1555,21 +1575,19 @@ class InstSignatureTable extends core.Task { }); } - var s = `#define ROW(count, x86, x64, implicit, o0, o1, o2, o3, o4, o5) \\\n` + - ` { count, (x86 ? uint8_t(InstDB::kModeX86) : uint8_t(0)) | \\\n` + - ` (x64 ? uint8_t(InstDB::kModeX64) : uint8_t(0)) , \\\n` + - ` implicit, \\\n` + - ` 0, \\\n` + - ` { o0, o1, o2, o3, o4, o5 } \\\n` + + var s = `#define ROW(count, x86, x64, implicit, o0, o1, o2, o3, o4, o5) \\\n` + + ` { count, uint8_t(x86 ? uint8_t(InstDB::Mode::kX86) : uint8_t(0)) | \\\n` + + ` (x64 ? uint8_t(InstDB::Mode::kX64) : uint8_t(0)) , \\\n` + + ` implicit, \\\n` + + ` 0, \\\n` + + ` { o0, o1, o2, o3, o4, o5 } \\\n` + ` }\n` + StringUtils.makeCxxArrayWithComment(iSignatureArr, "const InstDB::InstSignature InstDB::_instSignatureTable[]") + `#undef ROW\n` + `\n` + - `#define ROW(flags, mFlags, extFlags, regId) { uint32_t(flags), uint16_t(mFlags), uint8_t(extFlags), uint8_t(regId) }\n` + - `#define F(VAL) InstDB::kOp##VAL\n` + - `#define M(VAL) InstDB::kMemOp##VAL\n` + + `#define ROW(opFlags, regId) { opFlags, uint8_t(regId) }\n` + + `#define F(VAL) uint64_t(InstDB::OpFlags::k##VAL)\n` + StringUtils.makeCxxArray(oSignatureArr, "const InstDB::OpSignature InstDB::_opSignatureTable[]") + - `#undef M\n` + `#undef F\n` + `#undef ROW\n`; this.inject("InstSignatureTable", disclaimer(s), oSignatureArr.length * 8 + iSignatureArr.length * 8); @@ -1614,17 +1632,23 @@ class InstSignatureTable extends core.Task { var imm = iop.imm; var rel = iop.rel; - // Terminate if this operand is something asmjit doesn't support - // and skip all instructions having implicit `imm` operand of `1`, - // which are handled fine by asmjit. - if (this.opBlackList[mem] === true || iop.immValue !== null) + // Skip all instructions having implicit `imm` operand of `1`. + if (iop.immValue !== null) + break; + + // Shorten the number of signatures of 'mov' instruction. + if (inst.name === "mov" && mem.startsWith("moff")) break; - if (reg === "r8") reg = "r8lo"; if (reg === "seg") reg = "sreg"; if (reg === "st(i)") reg = "st"; if (reg === "st(0)") reg = "st0"; + if (mem === "moff8") mem = "m8"; + if (mem === "moff16") mem = "m16"; + if (mem === "moff32") mem = "m32"; + if (mem === "moff64") mem = "m64"; + if (mem === "m32fp") mem = "m32"; if (mem === "m64fp") mem = "m64"; if (mem === "m80fp") mem = "m80"; @@ -1656,6 +1680,46 @@ class InstSignatureTable extends core.Task { const seg = iop.memSeg; if (seg) { + switch (inst.name) { + case "cmpsb": op.flags.m8 = true; break; + case "cmpsw": op.flags.m16 = true; break; + case "cmpsd": op.flags.m32 = true; break; + case "cmpsq": op.flags.m64 = true; break; + case "lodsb": op.flags.m8 = true; break; + case "lodsw": op.flags.m16 = true; break; + case "lodsd": op.flags.m32 = true; break; + case "lodsq": op.flags.m64 = true; break; + case "movsb": op.flags.m8 = true; break; + case "movsw": op.flags.m16 = true; break; + case "movsd": op.flags.m32 = true; break; + case "movsq": op.flags.m64 = true; break; + case "scasb": op.flags.m8 = true; break; + case "scasw": op.flags.m16 = true; break; + case "scasd": op.flags.m32 = true; break; + case "scasq": op.flags.m64 = true; break; + case "stosb": op.flags.m8 = true; break; + case "stosw": op.flags.m16 = true; break; + case "stosd": op.flags.m32 = true; break; + case "stosq": op.flags.m64 = true; break; + case "insb": op.flags.m8 = true; break; + case "insw": op.flags.m16 = true; break; + case "insd": op.flags.m32 = true; break; + case "outsb": op.flags.m8 = true; break; + case "outsw": op.flags.m16 = true; break; + case "outsd": op.flags.m32 = true; break; + case "clzero": op.flags.mem = true; op.flags.m512 = true; break; + case "enqcmd": op.flags.mem = true; op.flags.m512 = true; break; + case "enqcmds": op.flags.mem = true; op.flags.m512 = true; break; + case "movdir64b": op.flags.mem = true; op.flags.m512 = true; break; + case "maskmovq": op.flags.mem = true; op.flags.m64 = true; break; + case "maskmovdqu": op.flags.mem = true; op.flags.m128 = true; break; + case "vmaskmovdqu": op.flags.mem = true; op.flags.m128 = true; break; + case "monitor": op.flags.mem = true; break; + case "monitorx": op.flags.mem = true; break; + case "umonitor": op.flags.mem = true; break; + default: console.log(`UNKNOWN MEM IN INSTRUCTION '${inst.name}'`); break; + } + if (seg === "ds") op.flags.memDS = true; if (seg === "es") op.flags.memES = true; if (reg === "reg") { op.flags.memBase = true; } @@ -1666,13 +1730,26 @@ class InstSignatureTable extends core.Task { if (reg === "zdi") { op.flags.memBase = true; op.flags.memZDI = true; } } else if (reg) { - op.flags[reg] = true; - if (reg === "r8lo") op.flags.r8hi = true; + if (reg == "r8") { + op.flags["r8lo"] = true; + op.flags["r8hi"] = true; + } + else { + op.flags[reg] = true; + } } if (mem) { op.flags[mem] = true; - // Exception: Allow LEA to use any memory size. - if (inst.name === "lea") MapUtils.add(op.flags, MemOp); + // HACK: Allow LEA|CL*|PREFETCH* to use any memory size. + if (/^(cldemote|clwb|clflush\w*|lea|prefetch\w*)$/.test(inst.name)) { + op.flags.mem = true; + Object.assign(op.flags, MemOp); + } + + // HACK: These instructions specify explicit memory size, but it's just informational. + if (inst.name === "enqcmd" || inst.name === "enqcmds" || inst.name === "movdir64b") + op.flags.mem = true; + } if (imm) { if (iop.immSign === "any" || iop.immSign === "signed" ) op.flags["i" + imm] = true; @@ -1689,30 +1766,27 @@ class InstSignatureTable extends core.Task { } } - signatures.calcImplicitMemSize(); - signatures.simplify(); - signatures.compact(); + if (signatures.length && GenUtils.canUseImplicitMemSize(dbInsts[0].name)) + signatures.calcImplicitMemSize(); - signatures.simplify(); signatures.compact(); - return signatures; } } // ============================================================================ -// [tablegen.x86.InstCommonInfoTableB] +// [tablegen.x86.AdditionalInfoTable] // ============================================================================ -class InstCommonInfoTableB extends core.Task { +class AdditionalInfoTable extends core.Task { constructor() { - super("InstCommonInfoTableB"); + super("AdditionalInfoTable"); } run() { const insts = this.ctx.insts; - const commonTableB = new IndexedArray(); const rwInfoTable = new IndexedArray(); + const additionaInfoTable = new IndexedArray(); // If the instruction doesn't read any flags it should point to the first index. rwInfoTable.addIndexed(`{ 0, 0 }`); @@ -1728,17 +1802,17 @@ class InstCommonInfoTableB extends core.Task { const wData = w.map(function(flag) { return `FLAG(${flag})`; }).join(" | ") || "0"; const rwDataIndex = rwInfoTable.addIndexed(`{ ${rData}, ${wData} }`); - inst.commomInfoIndexB = commonTableB.addIndexed(`{ { ${features} }, ${rwDataIndex}, 0 }`); + inst.additionalInfoIndex = additionaInfoTable.addIndexed(`{ { ${features} }, ${rwDataIndex}, 0 }`); }); - var s = `#define EXT(VAL) uint32_t(Features::k##VAL)\n` + - `const InstDB::CommonInfoTableB InstDB::_commonInfoTableB[] = {\n${StringUtils.format(commonTableB, kIndent, true)}\n};\n` + + var s = `#define EXT(VAL) uint32_t(CpuFeatures::X86::k##VAL)\n` + + `const InstDB::AdditionalInfo InstDB::_additionalInfoTable[] = {\n${StringUtils.format(additionaInfoTable, kIndent, true)}\n};\n` + `#undef EXT\n` + `\n` + - `#define FLAG(VAL) uint32_t(Status::k##VAL)\n` + + `#define FLAG(VAL) uint32_t(CpuRWFlags::kX86_##VAL)\n` + `const InstDB::RWFlagsInfoTable InstDB::_rwFlagsInfoTable[] = {\n${StringUtils.format(rwInfoTable, kIndent, true)}\n};\n` + `#undef FLAG\n`; - this.inject("InstCommonInfoTableB", disclaimer(s), commonTableB.length * 8 + rwInfoTable.length * 8); + this.inject("AdditionalInfoTable", disclaimer(s), additionaInfoTable.length * 8 + rwInfoTable.length * 8); } rwFlagsOf(dbInsts) { @@ -1814,17 +1888,23 @@ class InstRWInfoTable extends core.Task { constructor() { super("InstRWInfoTable"); - this.rwInfoIndex = []; - this.rwInfoTable = new IndexedArray(); + this.rwInfoIndexA = []; + this.rwInfoIndexB = []; + this.rwInfoTableA = new IndexedArray(); + this.rwInfoTableB = new IndexedArray(); + this.rmInfoTable = new IndexedArray(); this.opInfoTable = new IndexedArray(); - const _ = null; this.rwCategoryByName = { "imul" : "Imul", "mov" : "Mov", + "movabs" : "Movabs", "movhpd" : "Movh64", "movhps" : "Movh64", + "punpcklbw" : "Punpcklxx", + "punpckldq" : "Punpcklxx", + "punpcklwd" : "Punpcklxx", "vmaskmovpd": "Vmaskmov", "vmaskmovps": "Vmaskmov", "vmovddup" : "Vmovddup", @@ -1833,37 +1913,39 @@ class InstRWInfoTable extends core.Task { "vpmaskmovd": "Vmaskmov", "vpmaskmovq": "Vmaskmov" }; + + const _ = null; this.rwCategoryByData = { Vmov1_8: [ - [{access: "W", flags: {}, fixed: -1, index: 0, width: 8}, {access: "R", flags: {}, fixed: -1, index: 0, width: 64},_,_,_,_], - [{access: "W", flags: {}, fixed: -1, index: 0, width: 16}, {access: "R", flags: {}, fixed: -1, index: 0, width:128},_,_,_,_], - [{access: "W", flags: {}, fixed: -1, index: 0, width: 32}, {access: "R", flags: {}, fixed: -1, index: 0, width:256},_,_,_,_], - [{access: "W", flags: {}, fixed: -1, index: 0, width: 64}, {access: "R", flags: {}, fixed: -1, index: 0, width:512},_,_,_,_] + [{access: "W", clc: 0, flags: {}, fixed: -1, index: 0, width: 8}, {access: "R", clc: 0, flags: {}, fixed: -1, index: 0, width: 64},_,_,_,_], + [{access: "W", clc: 0, flags: {}, fixed: -1, index: 0, width: 16}, {access: "R", clc: 0, flags: {}, fixed: -1, index: 0, width:128},_,_,_,_], + [{access: "W", clc: 0, flags: {}, fixed: -1, index: 0, width: 32}, {access: "R", clc: 0, flags: {}, fixed: -1, index: 0, width:256},_,_,_,_], + [{access: "W", clc: 0, flags: {}, fixed: -1, index: 0, width: 64}, {access: "R", clc: 0, flags: {}, fixed: -1, index: 0, width:512},_,_,_,_] ], Vmov1_4: [ - [{access: "W", flags: {}, fixed: -1, index: 0, width: 32}, {access: "R", flags: {}, fixed: -1, index: 0, width:128},_,_,_,_], - [{access: "W", flags: {}, fixed: -1, index: 0, width: 64}, {access: "R", flags: {}, fixed: -1, index: 0, width:256},_,_,_,_], - [{access: "W", flags: {}, fixed: -1, index: 0, width:128}, {access: "R", flags: {}, fixed: -1, index: 0, width:512},_,_,_,_] + [{access: "W", clc: 0, flags: {}, fixed: -1, index: 0, width: 32}, {access: "R", clc: 0, flags: {}, fixed: -1, index: 0, width:128},_,_,_,_], + [{access: "W", clc: 0, flags: {}, fixed: -1, index: 0, width: 64}, {access: "R", clc: 0, flags: {}, fixed: -1, index: 0, width:256},_,_,_,_], + [{access: "W", clc: 0, flags: {}, fixed: -1, index: 0, width:128}, {access: "R", clc: 0, flags: {}, fixed: -1, index: 0, width:512},_,_,_,_] ], Vmov1_2: [ - [{access: "W", flags: {}, fixed: -1, index: 0, width: 64}, {access: "R", flags: {}, fixed: -1, index: 0, width:128},_,_,_,_], - [{access: "W", flags: {}, fixed: -1, index: 0, width:128}, {access: "R", flags: {}, fixed: -1, index: 0, width:256},_,_,_,_], - [{access: "W", flags: {}, fixed: -1, index: 0, width:256}, {access: "R", flags: {}, fixed: -1, index: 0, width:512},_,_,_,_] + [{access: "W", clc: 0, flags: {}, fixed: -1, index: 0, width: 64}, {access: "R", clc: 0, flags: {}, fixed: -1, index: 0, width:128},_,_,_,_], + [{access: "W", clc: 0, flags: {}, fixed: -1, index: 0, width:128}, {access: "R", clc: 0, flags: {}, fixed: -1, index: 0, width:256},_,_,_,_], + [{access: "W", clc: 0, flags: {}, fixed: -1, index: 0, width:256}, {access: "R", clc: 0, flags: {}, fixed: -1, index: 0, width:512},_,_,_,_] ], Vmov2_1: [ - [{access: "W", flags: {}, fixed: -1, index: 0, width: 128}, {access: "R", flags: {}, fixed: -1, index: 0, width: 64},_,_,_,_], - [{access: "W", flags: {}, fixed: -1, index: 0, width: 256}, {access: "R", flags: {}, fixed: -1, index: 0, width:128},_,_,_,_], - [{access: "W", flags: {}, fixed: -1, index: 0, width: 512}, {access: "R", flags: {}, fixed: -1, index: 0, width:256},_,_,_,_] + [{access: "W", clc: 0, flags: {}, fixed: -1, index: 0, width: 128}, {access: "R", clc: 0, flags: {}, fixed: -1, index: 0, width: 64},_,_,_,_], + [{access: "W", clc: 0, flags: {}, fixed: -1, index: 0, width: 256}, {access: "R", clc: 0, flags: {}, fixed: -1, index: 0, width:128},_,_,_,_], + [{access: "W", clc: 0, flags: {}, fixed: -1, index: 0, width: 512}, {access: "R", clc: 0, flags: {}, fixed: -1, index: 0, width:256},_,_,_,_] ], Vmov4_1: [ - [{access: "W", flags: {}, fixed: -1, index: 0, width: 128}, {access: "R", flags: {}, fixed: -1, index: 0, width: 32},_,_,_,_], - [{access: "W", flags: {}, fixed: -1, index: 0, width: 256}, {access: "R", flags: {}, fixed: -1, index: 0, width: 64},_,_,_,_], - [{access: "W", flags: {}, fixed: -1, index: 0, width: 512}, {access: "R", flags: {}, fixed: -1, index: 0, width:128},_,_,_,_] + [{access: "W", clc: 0, flags: {}, fixed: -1, index: 0, width: 128}, {access: "R", clc: 0, flags: {}, fixed: -1, index: 0, width: 32},_,_,_,_], + [{access: "W", clc: 0, flags: {}, fixed: -1, index: 0, width: 256}, {access: "R", clc: 0, flags: {}, fixed: -1, index: 0, width: 64},_,_,_,_], + [{access: "W", clc: 0, flags: {}, fixed: -1, index: 0, width: 512}, {access: "R", clc: 0, flags: {}, fixed: -1, index: 0, width:128},_,_,_,_] ], Vmov8_1: [ - [{access: "W", flags: {}, fixed: -1, index: 0, width: 128}, {access: "R", flags: {}, fixed: -1, index: 0, width: 16},_,_,_,_], - [{access: "W", flags: {}, fixed: -1, index: 0, width: 256}, {access: "R", flags: {}, fixed: -1, index: 0, width: 32},_,_,_,_], - [{access: "W", flags: {}, fixed: -1, index: 0, width: 512}, {access: "R", flags: {}, fixed: -1, index: 0, width: 64},_,_,_,_] + [{access: "W", clc: 0, flags: {}, fixed: -1, index: 0, width: 128}, {access: "R", clc: 0, flags: {}, fixed: -1, index: 0, width: 16},_,_,_,_], + [{access: "W", clc: 0, flags: {}, fixed: -1, index: 0, width: 256}, {access: "R", clc: 0, flags: {}, fixed: -1, index: 0, width: 32},_,_,_,_], + [{access: "W", clc: 0, flags: {}, fixed: -1, index: 0, width: 512}, {access: "R", clc: 0, flags: {}, fixed: -1, index: 0, width: 64},_,_,_,_] ] }; } @@ -1883,8 +1965,9 @@ class InstRWInfoTable extends core.Task { "0x0000000000000000u", "0x0000000000000000u", "0xFF", + "0", CxxUtils.struct(0), - "0" + "OpRWFlags::kNone" ); this.rmInfoTable.addIndexed(noRmInfo); @@ -1900,8 +1983,8 @@ class InstRWInfoTable extends core.Task { const o2Insts = dbInsts.filter((inst) => { return inst.operands.length === 2; }); const oxInsts = dbInsts.filter((inst) => { return inst.operands.length !== 2; }); - const rwInfoArray = [this.rwInfo(o2Insts), this.rwInfo(oxInsts)]; - const rmInfoArray = [this.rmInfo(o2Insts), this.rmInfo(oxInsts)]; + const rwInfoArray = [this.rwInfo(inst, o2Insts), this.rwInfo(inst, oxInsts)]; + const rmInfoArray = [this.rmInfo(inst, o2Insts), this.rmInfo(inst, oxInsts)]; for (var i = 0; i < 2; i++) { const rwInfo = rwInfoArray[i]; @@ -1929,12 +2012,15 @@ class InstRWInfoTable extends core.Task { const wIndex = opAcc === "X" || opAcc === "W" ? op.index : -1; const wWidth = opAcc === "X" || opAcc === "W" ? op.width : -1; + const consecutiveLeadCount = op.clc; + const opData = CxxUtils.struct( this.byteMaskFromBitRanges([{ start: rIndex, end: rIndex + rWidth - 1 }]) + "u", this.byteMaskFromBitRanges([{ start: wIndex, end: wIndex + wWidth - 1 }]) + "u", StringUtils.decToHex(op.fixed === -1 ? 0xFF : op.fixed, 2), + String(consecutiveLeadCount), CxxUtils.struct(0), - CxxUtils.flags(flags, function(flag) { return "OpRWInfo::k" + flag; }) + CxxUtils.flags(flags, function(flag) { return "OpRWFlags::k" + flag; }, "OpRWFlags::kNone") ); rwOpsIndex.push(this.opInfoTable.addIndexed(opData)); @@ -1945,7 +2031,7 @@ class InstRWInfoTable extends core.Task { StringUtils.decToHex(rmInfo.rmIndexes, 2), String(Math.max(rmInfo.memFixed, 0)).padEnd(2), CxxUtils.flags({ "InstDB::RWInfoRm::kFlagAmbiguous": Boolean(rmInfo.memAmbiguous) }), - rmInfo.memExtension === "None" ? "0" : "Features::k" + rmInfo.memExtension + rmInfo.memExtension === "None" ? "0" : "uint32_t(CpuFeatures::X86::k" + rmInfo.memExtension + ")" ); const rwData = CxxUtils.struct( @@ -1954,21 +2040,30 @@ class InstRWInfoTable extends core.Task { CxxUtils.struct(...(rwOpsIndex.map(function(item) { return String(item).padEnd(2); }))) ); - this.rwInfoIndex.push(this.rwInfoTable.addIndexed(rwData)); + if (i == 0) + this.rwInfoIndexA.push(this.rwInfoTableA.addIndexed(rwData)); + else + this.rwInfoIndexB.push(this.rwInfoTableB.addIndexed(rwData)); } }); var s = ""; - s += "const uint8_t InstDB::rwInfoIndex[Inst::_kIdCount * 2] = {\n" + StringUtils.format(this.rwInfoIndex, kIndent, -1) + "\n};\n"; + s += "const uint8_t InstDB::rwInfoIndexA[Inst::_kIdCount] = {\n" + StringUtils.format(this.rwInfoIndexA, kIndent, -1) + "\n};\n"; + s += "\n"; + s += "const uint8_t InstDB::rwInfoIndexB[Inst::_kIdCount] = {\n" + StringUtils.format(this.rwInfoIndexB, kIndent, -1) + "\n};\n"; s += "\n"; - s += "const InstDB::RWInfo InstDB::rwInfo[] = {\n" + StringUtils.format(this.rwInfoTable, kIndent, true) + "\n};\n"; + s += "const InstDB::RWInfo InstDB::rwInfoA[] = {\n" + StringUtils.format(this.rwInfoTableA, kIndent, true) + "\n};\n"; + s += "\n"; + s += "const InstDB::RWInfo InstDB::rwInfoB[] = {\n" + StringUtils.format(this.rwInfoTableB, kIndent, true) + "\n};\n"; s += "\n"; s += "const InstDB::RWInfoOp InstDB::rwInfoOp[] = {\n" + StringUtils.format(this.opInfoTable, kIndent, true) + "\n};\n"; s += "\n"; s += "const InstDB::RWInfoRm InstDB::rwInfoRm[] = {\n" + StringUtils.format(this.rmInfoTable, kIndent, true) + "\n};\n"; - const size = this.rwInfoIndex.length + - this.rwInfoTable.length * 8 + + const size = this.rwInfoIndexA.length + + this.rwInfoIndexB.length + + this.rwInfoTableA.length * 8 + + this.rwInfoTableB.length * 8 + this.rmInfoTable.length * 4 + this.opInfoTable.length * 24; @@ -2006,7 +2101,9 @@ class InstRWInfoTable extends core.Task { // Read/Write Info // --------------- - rwInfo(dbInsts) { + rwInfo(asmInst, dbInsts) { + const self = this; + function nullOps() { return [null, null, null, null, null, null]; } @@ -2017,6 +2114,7 @@ class InstRWInfoTable extends core.Task { return { access: op.read && op.write ? "X" : op.read ? "R" : op.write ? "W" : "?", + clc: 0, flags: {}, fixed: GenUtils.fixedRegOf(op.reg), index: op.rwxIndex, @@ -2038,12 +2136,16 @@ class InstRWInfoTable extends core.Task { const opSize = op.isReg() ? op.regSize : op.memSize; var d = { access: op.read && op.write ? "X" : op.read ? "R" : op.write ? "W" : "?", + clc: 0, flags: {}, fixed: -1, index: -1, width: -1 }; + if (op.consecutiveLeadCount) + d.clc = op.consecutiveLeadCount; + if (op.isReg()) d.fixed = GenUtils.fixedRegOf(op.reg); else @@ -2052,6 +2154,12 @@ class InstRWInfoTable extends core.Task { if (op.zext) d.flags.ZExt = true; + if (op.regIndexRel) + d.flags.Consecutive = true; + + for (var k in self.rwOpFlagsForInstruction(asmInst.name, j)) + d.flags[k] = true; + if ((step === -1 || step === j) || op.rwxIndex !== 0 || op.rwxWidth !== opSize) { d.index = op.rwxIndex; d.width = op.rwxWidth; @@ -2147,10 +2255,29 @@ class InstRWInfoTable extends core.Task { return null; } + rwOpFlagsForInstruction(instName, opIndex) { + const toMap = MapUtils.arrayToMap; + + // TODO: We should be able to get this information from asmdb. + switch (instName + "@" + opIndex) { + case "cmps@0": return toMap(['MemBaseRW', 'MemBasePostModify']); + case "cmps@1": return toMap(['MemBaseRW', 'MemBasePostModify']); + case "movs@0": return toMap(['MemBaseRW', 'MemBasePostModify']); + case "movs@1": return toMap(['MemBaseRW', 'MemBasePostModify']); + case "lods@1": return toMap(['MemBaseRW', 'MemBasePostModify']); + case "stos@0": return toMap(['MemBaseRW', 'MemBasePostModify']); + case "scas@1": return toMap(['MemBaseRW', 'MemBasePostModify']); + case "bndstx@0": return toMap(['MemBaseWrite', 'MemIndexWrite']); + + default: + return {}; + } + } + // Reg/Mem Info // ------------ - rmInfo(dbInsts) { + rmInfo(asmInst, dbInsts) { const info = { category: "None", rmIndexes: this.rmReplaceableIndexes(dbInsts), @@ -2198,9 +2325,14 @@ class InstRWInfoTable extends core.Task { if (category === null) category = c; else if (category !== c) { + // Special cases. if (dbInst.name === "mov" || dbInst.name === "vmovddup") - return "None"; // Special case - return StringUtils.capitalize(dbInst.name); // Special case. + return "None"; + + if (/^(punpcklbw|punpckldq|punpcklwd)$/.test(dbInst.name)) + return "None"; + + return StringUtils.capitalize(dbInst.name); } } @@ -2381,7 +2513,7 @@ class InstCommonTable extends core.Task { "IdEnum", "NameTable", "InstSignatureTable", - "InstCommonInfoTableB", + "AdditionalInfoTable", "InstRWInfoTable" ]); } @@ -2391,25 +2523,33 @@ class InstCommonTable extends core.Task { const table = new IndexedArray(); insts.forEach((inst) => { - const flags = inst.flags.map(function(flag) { return `F(${flag})`; }).join("|") || "0"; - const singleRegCase = `SINGLE_REG(${inst.singleRegCase})`; - const controlType = `CONTROL(${inst.controlType})`; + const commonFlagsArray = inst.flags.filter((flag) => { return !flag.startsWith("Avx512"); }); + const avx512FlagsArray = inst.flags.filter((flag) => { return flag.startsWith("Avx512"); }); + + const commonFlags = commonFlagsArray.map(function(flag) { return `F(${flag })`; }).join("|") || "0"; + const avx512Flags = avx512FlagsArray.map(function(flag) { return `X(${flag.substr(6)})`; }).join("|") || "0"; + + const controlFlow = `CONTROL_FLOW(${inst.controlFlow})`; + const singleRegCase = `SAME_REG_HINT(${inst.singleRegCase})`; const row = "{ " + - String(flags ).padEnd(54) + ", " + + String(commonFlags ).padEnd(50) + ", " + + String(avx512Flags ).padEnd(30) + ", " + String(inst.signatureIndex).padEnd( 3) + ", " + String(inst.signatureCount).padEnd( 2) + ", " + - String(controlType ).padEnd(16) + ", " + - String(singleRegCase ).padEnd(16) + ", " + "0 }"; - inst.commonInfoIndexA = table.addIndexed(row); + String(controlFlow ).padEnd(16) + ", " + + String(singleRegCase ).padEnd(16) + "}"; + inst.commonInfoIndex = table.addIndexed(row); }); - var s = `#define F(VAL) InstDB::kFlag##VAL\n` + - `#define CONTROL(VAL) Inst::kControl##VAL\n` + - `#define SINGLE_REG(VAL) InstDB::kSingleReg##VAL\n` + + var s = `#define F(VAL) uint32_t(InstDB::InstFlags::k##VAL)\n` + + `#define X(VAL) uint32_t(InstDB::Avx512Flags::k##VAL)\n` + + `#define CONTROL_FLOW(VAL) uint8_t(InstControlFlow::k##VAL)\n` + + `#define SAME_REG_HINT(VAL) uint8_t(InstSameRegHint::k##VAL)\n` + `const InstDB::CommonInfo InstDB::_commonInfoTable[] = {\n${StringUtils.format(table, kIndent, true)}\n};\n` + - `#undef SINGLE_REG\n` + - `#undef CONTROL\n` + + `#undef SAME_REG_HINT\n` + + `#undef CONTROL_FLOW\n` + + `#undef X\n` + `#undef F\n`; this.inject("InstCommonTable", disclaimer(s), table.length * 8); } @@ -2424,7 +2564,7 @@ new X86TableGen() .addTask(new NameTable()) .addTask(new AltOpcodeTable()) .addTask(new InstSignatureTable()) - .addTask(new InstCommonInfoTableB()) + .addTask(new AdditionalInfoTable()) .addTask(new InstRWInfoTable()) .addTask(new InstCommonTable()) .run(); |