diff options
author | 2012-09-25 14:54:37 +0000 | |
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committer | 2012-09-25 14:54:37 +0000 | |
commit | ac17372427f22cd8838301ed7fdee3a3f0312699 (patch) | |
tree | 01d788f415820c5bd436fbe58bea4c4406715dbf /src/mess/includes/dgn_beta.h | |
parent | 69e6ff0257e9e996dbd42bb4f6cf80b11ae34310 (diff) |
Added missing DECLARE_'s. (nw)
Diffstat (limited to 'src/mess/includes/dgn_beta.h')
-rw-r--r-- | src/mess/includes/dgn_beta.h | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/src/mess/includes/dgn_beta.h b/src/mess/includes/dgn_beta.h index ab344a15986..a9cfc7250f0 100644 --- a/src/mess/includes/dgn_beta.h +++ b/src/mess/includes/dgn_beta.h @@ -144,23 +144,23 @@ public: int m_DrawInterlace; virtual void machine_start(); virtual void palette_init(); - WRITE8_MEMBER(dgnbeta_ram_b0_w); - WRITE8_MEMBER(dgnbeta_ram_b1_w); - WRITE8_MEMBER(dgnbeta_ram_b2_w); - WRITE8_MEMBER(dgnbeta_ram_b3_w); - WRITE8_MEMBER(dgnbeta_ram_b4_w); - WRITE8_MEMBER(dgnbeta_ram_b5_w); - WRITE8_MEMBER(dgnbeta_ram_b6_w); - WRITE8_MEMBER(dgnbeta_ram_b7_w); - WRITE8_MEMBER(dgnbeta_ram_b8_w); - WRITE8_MEMBER(dgnbeta_ram_b9_w); - WRITE8_MEMBER(dgnbeta_ram_bA_w); - WRITE8_MEMBER(dgnbeta_ram_bB_w); - WRITE8_MEMBER(dgnbeta_ram_bC_w); - WRITE8_MEMBER(dgnbeta_ram_bD_w); - WRITE8_MEMBER(dgnbeta_ram_bE_w); - WRITE8_MEMBER(dgnbeta_ram_bF_w); - WRITE8_MEMBER(dgnbeta_ram_bG_w); + DECLARE_WRITE8_MEMBER(dgnbeta_ram_b0_w); + DECLARE_WRITE8_MEMBER(dgnbeta_ram_b1_w); + DECLARE_WRITE8_MEMBER(dgnbeta_ram_b2_w); + DECLARE_WRITE8_MEMBER(dgnbeta_ram_b3_w); + DECLARE_WRITE8_MEMBER(dgnbeta_ram_b4_w); + DECLARE_WRITE8_MEMBER(dgnbeta_ram_b5_w); + DECLARE_WRITE8_MEMBER(dgnbeta_ram_b6_w); + DECLARE_WRITE8_MEMBER(dgnbeta_ram_b7_w); + DECLARE_WRITE8_MEMBER(dgnbeta_ram_b8_w); + DECLARE_WRITE8_MEMBER(dgnbeta_ram_b9_w); + DECLARE_WRITE8_MEMBER(dgnbeta_ram_bA_w); + DECLARE_WRITE8_MEMBER(dgnbeta_ram_bB_w); + DECLARE_WRITE8_MEMBER(dgnbeta_ram_bC_w); + DECLARE_WRITE8_MEMBER(dgnbeta_ram_bD_w); + DECLARE_WRITE8_MEMBER(dgnbeta_ram_bE_w); + DECLARE_WRITE8_MEMBER(dgnbeta_ram_bF_w); + DECLARE_WRITE8_MEMBER(dgnbeta_ram_bG_w); }; |