diff options
author | 2016-05-03 02:32:29 +0200 | |
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committer | 2016-05-03 02:35:07 +0200 | |
commit | 3acd03bd5f437d628653fecc127dd849f7512f6f (patch) | |
tree | e983c6c4c935de1059d6b0b7423daa63ec32e275 /src/lib/netlist/macro | |
parent | 6f889d51aeb4ca7d692060b08f1deec7315e816b (diff) |
Implement 7402, 7408 as macro device. (nw)
Diffstat (limited to 'src/lib/netlist/macro')
-rw-r--r-- | src/lib/netlist/macro/nlm_ttl74xx.cpp | 111 | ||||
-rw-r--r-- | src/lib/netlist/macro/nlm_ttl74xx.h | 24 |
2 files changed, 135 insertions, 0 deletions
diff --git a/src/lib/netlist/macro/nlm_ttl74xx.cpp b/src/lib/netlist/macro/nlm_ttl74xx.cpp index 7cc32c573b0..d4b1a166856 100644 --- a/src/lib/netlist/macro/nlm_ttl74xx.cpp +++ b/src/lib/netlist/macro/nlm_ttl74xx.cpp @@ -46,6 +46,44 @@ NETLIST_START(TTL_7400_DIP) NETLIST_END() /* + * DM7402: Quad 2-Input NOR Gates + * + * Y = A+B + * +---+---++---+ + * | A | B || Y | + * +===+===++===+ + * | 0 | 0 || 1 | + * | 0 | 1 || 0 | + * | 1 | 0 || 0 | + * | 1 | 1 || 0 | + * +---+---++---+ + * + * Naming conventions follow National Semiconductor datasheet + * + */ + +NETLIST_START(TTL_7402_DIP) + TTL_7402_GATE(s1) + TTL_7402_GATE(s2) + TTL_7402_GATE(s3) + TTL_7402_GATE(s4) + + DUMMY_INPUT(GND) + DUMMY_INPUT(VCC) + + DIPPINS( /* +--------------+ */ + s1.Q, /* Y1 |1 ++ 14| VCC */ VCC.I, + s1.A, /* A1 |2 13| Y4 */ s4.Q, + s1.B, /* B1 |3 12| B4 */ s4.B, + s2.Q, /* Y2 |4 7402 11| A4 */ s4.A, + s2.A, /* A2 |5 10| Y3 */ s3.Q, + s2.B, /* B2 |6 9| B3 */ s3.B, + GND.I, /* GND |7 8| A3 */ s3.A + /* +--------------+ */ + ) +NETLIST_END() + +/* * DM7404: Hex Inverting Gates * _ * Y = A @@ -84,6 +122,45 @@ NETLIST_START(TTL_7404_DIP) NETLIST_END() /* + * DM7408: Quad 2-Input AND Gates + * + * + * Y = AB + * +---+---++---+ + * | A | B || Y | + * +===+===++===+ + * | 0 | 0 || 0 | + * | 0 | 1 || 0 | + * | 1 | 0 || 0 | + * | 1 | 1 || 1 | + * +---+---++---+ + * + * Naming conventions follow National Semiconductor datasheet + * + */ + +NETLIST_START(TTL_7408_DIP) + TTL_7408_GATE(s1) + TTL_7408_GATE(s2) + TTL_7408_GATE(s3) + TTL_7408_GATE(s4) + + DUMMY_INPUT(GND) + DUMMY_INPUT(VCC) + + DIPPINS( /* +--------------+ */ + s1.A, /* A1 |1 ++ 14| VCC */ VCC.I, + s1.B, /* B1 |2 13| B4 */ s4.B, + s1.Q, /* Y1 |3 12| A4 */ s4.A, + s2.A, /* A2 |4 7400 11| Y4 */ s4.Q, + s2.B, /* B2 |5 10| B3 */ s3.B, + s2.Q, /* Y2 |6 9| A3 */ s3.A, + GND.I, /* GND |7 8| Y3 */ s3.Q + /* +--------------+ */ + ) +NETLIST_END() + +/* * DM7416: Hex Inverting Buffers with * High Voltage Open-Collector Outputs * @@ -130,6 +207,22 @@ NETLIST_START(TTL74XX_lib) TT_FAMILY("74XX") TRUTHTABLE_END() + TRUTHTABLE_START(TTL_7402_GATE, 2, 1, 0, "") + TT_HEAD("A,B|Q ") + TT_LINE("0,0|1|22") + TT_LINE("X,1|0|15") + TT_LINE("1,X|0|15") + TT_FAMILY("74XX") + TRUTHTABLE_END() + + TRUTHTABLE_START(TTL_7402_NOR, 2, 1, 0, "A,B") + TT_HEAD("A,B|Q ") + TT_LINE("0,0|1|22") + TT_LINE("X,1|0|15") + TT_LINE("1,X|0|15") + TT_FAMILY("74XX") + TRUTHTABLE_END() + TRUTHTABLE_START(TTL_7404_GATE, 1, 1, 0, "") TT_HEAD(" A | Q ") TT_LINE(" 0 | 1 |22") @@ -144,6 +237,22 @@ NETLIST_START(TTL74XX_lib) TT_FAMILY("74XX") TRUTHTABLE_END() + TRUTHTABLE_START(TTL_7408_GATE, 2, 1, 0, "") + TT_HEAD("A,B|Q ") + TT_LINE("0,X|0|15") + TT_LINE("X,0|0|15") + TT_LINE("1,1|1|22") + TT_FAMILY("74XX") + TRUTHTABLE_END() + + TRUTHTABLE_START(TTL_7408_AND, 2, 1, 0, "A,B") + TT_HEAD("A,B|Q ") + TT_LINE("0,X|0|15") + TT_LINE("X,0|0|15") + TT_LINE("1,1|1|22") + TT_FAMILY("74XX") + TRUTHTABLE_END() + TRUTHTABLE_START(TTL_7416_GATE, 1, 1, 0, "") TT_HEAD(" A | Q ") TT_LINE(" 0 | 1 |15") @@ -153,6 +262,8 @@ NETLIST_START(TTL74XX_lib) TRUTHTABLE_END() LOCAL_LIB_ENTRY(TTL_7400_DIP) + LOCAL_LIB_ENTRY(TTL_7402_DIP) LOCAL_LIB_ENTRY(TTL_7404_DIP) + LOCAL_LIB_ENTRY(TTL_7408_DIP) LOCAL_LIB_ENTRY(TTL_7416_DIP) NETLIST_END() diff --git a/src/lib/netlist/macro/nlm_ttl74xx.h b/src/lib/netlist/macro/nlm_ttl74xx.h index 36b08532644..28b207ea876 100644 --- a/src/lib/netlist/macro/nlm_ttl74xx.h +++ b/src/lib/netlist/macro/nlm_ttl74xx.h @@ -23,6 +23,18 @@ NET_REGISTER_DEV(TTL_7400_DIP, _name) +#define TTL_7402_GATE(_name) \ + NET_REGISTER_DEV(TTL_7402_GATE, _name) + +#define TTL_7402_NOR(_name, _I1, _I2) \ + NET_REGISTER_DEV(TTL_7402_NOR, _name) \ + NET_CONNECT(_name, A, _I1) \ + NET_CONNECT(_name, B, _I2) + +#define TTL_7402_DIP(_name) \ + NET_REGISTER_DEV(TTL_7402_DIP, _name) + + #define TTL_7404_GATE(_name) \ NET_REGISTER_DEV(TTL_7404_GATE, _name) @@ -34,6 +46,18 @@ NET_REGISTER_DEV(TTL_7404_DIP, _name) +#define TTL_7408_GATE(_name) \ + NET_REGISTER_DEV(TTL_7408_GATE, _name) + +#define TTL_7408_NAND(_name, _A, _B) \ + NET_REGISTER_DEV(TTL_7408_NAND, _name) \ + NET_CONNECT(_name, A, _A) \ + NET_CONNECT(_name, B, _B) + +#define TTL_7408_DIP(_name) \ + NET_REGISTER_DEV(TTL_7408_DIP, _name) + + #define TTL_7416_GATE(_name) \ NET_REGISTER_DEV(TTL_7416_GATE, _name) |