diff options
author | 2017-02-17 01:33:20 +0100 | |
---|---|---|
committer | 2017-02-17 20:10:15 +0100 | |
commit | 0716d965144f17ff909affc5c465f721feb3e625 (patch) | |
tree | ca7f62459d2e24c59e465809a9f3acdc0251bb81 /src/lib/netlist/macro | |
parent | 776d89919b9f34b8fe373cec2a8bdb60a2383614 (diff) |
Reworked truthtables a bit.
- Moved 9312 and 74279 to ttl macro library.
- Renamed TTL_9312_* to DM9312. This is more appropriate.
- Fixed a number of warnings from latest ubuntu clang-5.0.
Diffstat (limited to 'src/lib/netlist/macro')
-rw-r--r-- | src/lib/netlist/macro/nlm_ttl74xx.cpp | 149 | ||||
-rw-r--r-- | src/lib/netlist/macro/nlm_ttl74xx.h | 98 |
2 files changed, 208 insertions, 39 deletions
diff --git a/src/lib/netlist/macro/nlm_ttl74xx.cpp b/src/lib/netlist/macro/nlm_ttl74xx.cpp index 85b5570183b..6af0038daf5 100644 --- a/src/lib/netlist/macro/nlm_ttl74xx.cpp +++ b/src/lib/netlist/macro/nlm_ttl74xx.cpp @@ -577,6 +577,111 @@ static NETLIST_START(TTL_74260_DIP) ) NETLIST_END() +/* + * DM74279: Quad S-R Latch + * + * +---+---+---++---+ + * |S1 |S2 | R || Q | + * +===+===+===++===+ + * | 0 | 0 | 0 || 1 | + * | 0 | 1 | 1 || 1 | + * | 1 | 0 | 1 || 1 | + * | 1 | 1 | 0 || 0 | + * | 1 | 1 | 1 ||QP | + * +---+---+---++---+ + * + * QP: Previous Q + * + * Naming conventions follow Fairchild Semiconductor datasheet + * + */ + +#ifndef __PLIB_PREPROCESSOR__ +#define TTL_74279A(name) \ + NET_REGISTER_DEV(TTL_74279A, name) +#define TTL_74279B(name) \ + NET_REGISTER_DEV(TTL_74279B, name) +#endif + +static NETLIST_START(TTL_74279_DIP) + TTL_74279B(s1) + TTL_74279A(s2) + TTL_74279B(s3) + TTL_74279A(s4) + + DUMMY_INPUT(GND) + DUMMY_INPUT(VCC) + + DIPPINS( /* +--------------+ */ + s1.R, /* 1R |1 ++ 16| VCC */ VCC.I, + s1.S1, /* 1S1 |2 15| 4S */ s4.S, + s1.S2, /* 1S2 |3 14| 4R */ s4.R, + s1.Q, /* 1Q |4 74279 13| 4Q */ s4.Q, + s2.R, /* 2R |5 12| 3S2 */ s3.S2, + s2.S, /* 2S |6 11| 3S1 */ s3.S1, + s2.Q, /* 2Q |7 10| 3R */ s3.R, + GND.I, /* GND |8 9| 3Q */ s3.Q + /* +--------------+ */ + ) +NETLIST_END() + +/* + * DM9312: One of Eight Line Data Selectors/Multiplexers + * + * +--------------+ + * D0 |1 ++ 16| VCC + * D1 |2 15| Y + * D2 |3 14| YQ + * D3 |4 9312 13| C + * D4 |5 12| B + * D5 |6 11| A + * D6 |7 10| G Strobe + * GND |8 9| D7 + * +--------------+ + * __ + * +---+---+---+---++---+---+ + * | C | B | A | G || Y | YQ| + * +===+===+===+===++===+===+ + * | X | X | X | 1 || 0| 1 | + * | 0 | 0 | 0 | 0 || D0|D0Q| + * | 0 | 0 | 1 | 0 || D1|D1Q| + * | 0 | 1 | 0 | 0 || D2|D2Q| + * | 0 | 1 | 1 | 0 || D3|D3Q| + * | 1 | 0 | 0 | 0 || D4|D4Q| + * | 1 | 0 | 1 | 0 || D5|D5Q| + * | 1 | 1 | 0 | 0 || D6|D6Q| + * | 1 | 1 | 1 | 0 || D7|D7Q| + * +---+---+---+---++---+---+ + * + * Naming conventions follow National Semiconductor datasheet + * + */ + +#ifndef __PLIB_PREPROCESSOR__ +#define DM9312_TT(name) \ + NET_REGISTER_DEV(DM9312_TT, name) +#endif + +static NETLIST_START(DM9312_DIP) + DM9312_TT(s) + + DUMMY_INPUT(GND) + DUMMY_INPUT(VCC) + +DIPPINS( /* +--------------+ */ + s.D0, /* D0 |1 ++ 16| VCC */ VCC.I, + s.D1, /* D1 |2 15| Y */ s.Y, + s.D2, /* D2 |3 14| YQ */ s.YQ, + s.D3, /* D3 |4 9312 13| C */ s.C, + s.D4, /* D4 |5 12| B */ s.B, + s.D5, /* D5 |6 11| A */ s.A, + s.D6, /* D6 |7 10| G */ s.G, //Strobe + GND.I, /* GND |8 9| D7 */ s.D7 + /* +--------------+ */ + ) +NETLIST_END() + + NETLIST_START(TTL74XX_lib) TRUTHTABLE_START(TTL_7400_GATE, 2, 1, "") @@ -847,6 +952,48 @@ NETLIST_START(TTL74XX_lib) TT_FAMILY("74XX") TRUTHTABLE_END() + // FIXME: We need "private" devices + TRUTHTABLE_START(TTL_74279A, 3, 1, "") + TT_HEAD("S,R,_Q|Q") + TT_LINE("0,X,X|1|22") + TT_LINE("1,0,X|0|27") + TT_LINE("1,1,0|0|27") + TT_LINE("1,1,1|1|22") + TT_FAMILY("74XX") + TRUTHTABLE_END() + + TRUTHTABLE_START(TTL_74279B, 4, 1, "") + TT_HEAD("S1,S2,R,_Q|Q") + TT_LINE("0,X,X,X|1|22") + TT_LINE("X,0,X,X|1|22") + TT_LINE("1,1,0,X|0|27") + TT_LINE("1,1,1,0|0|27") + TT_LINE("1,1,1,1|1|22") + TT_FAMILY("74XX") + TRUTHTABLE_END() + + TRUTHTABLE_START(DM9312_TT, 12, 2, "+A,+B,+C,+G,+D0,+D1,+D2,+D3,+D4,+D5,+D6,+D7") + TT_HEAD(" C, B, A, G,D0,D1,D2,D3,D4,D5,D6,D7| Y,YQ") + TT_LINE(" X, X, X, 1, X, X, X, X, X, X, X, X| 0, 1|33,19") + TT_LINE(" 0, 0, 0, 0, 0, X, X, X, X, X, X, X| 0, 1|33,28") + TT_LINE(" 0, 0, 0, 0, 1, X, X, X, X, X, X, X| 1, 0|33,28") + TT_LINE(" 0, 0, 1, 0, X, 0, X, X, X, X, X, X| 0, 1|33,28") + TT_LINE(" 0, 0, 1, 0, X, 1, X, X, X, X, X, X| 1, 0|33,28") + TT_LINE(" 0, 1, 0, 0, X, X, 0, X, X, X, X, X| 0, 1|33,28") + TT_LINE(" 0, 1, 0, 0, X, X, 1, X, X, X, X, X| 1, 0|33,28") + TT_LINE(" 0, 1, 1, 0, X, X, X, 0, X, X, X, X| 0, 1|33,28") + TT_LINE(" 0, 1, 1, 0, X, X, X, 1, X, X, X, X| 1, 0|33,28") + TT_LINE(" 1, 0, 0, 0, X, X, X, X, 0, X, X, X| 0, 1|33,28") + TT_LINE(" 1, 0, 0, 0, X, X, X, X, 1, X, X, X| 1, 0|33,28") + TT_LINE(" 1, 0, 1, 0, X, X, X, X, X, 0, X, X| 0, 1|33,28") + TT_LINE(" 1, 0, 1, 0, X, X, X, X, X, 1, X, X| 1, 0|33,28") + TT_LINE(" 1, 1, 0, 0, X, X, X, X, X, X, 0, X| 0, 1|33,28") + TT_LINE(" 1, 1, 0, 0, X, X, X, X, X, X, 1, X| 1, 0|33,28") + TT_LINE(" 1, 1, 1, 0, X, X, X, X, X, X, X, 0| 0, 1|33,28") + TT_LINE(" 1, 1, 1, 0, X, X, X, X, X, X, X, 1| 1, 0|33,28") + TT_FAMILY("74XX") + TRUTHTABLE_END() + LOCAL_LIB_ENTRY(TTL_7400_DIP) LOCAL_LIB_ENTRY(TTL_7402_DIP) LOCAL_LIB_ENTRY(TTL_7404_DIP) @@ -862,4 +1009,6 @@ NETLIST_START(TTL74XX_lib) LOCAL_LIB_ENTRY(TTL_7437_DIP) LOCAL_LIB_ENTRY(TTL_7486_DIP) LOCAL_LIB_ENTRY(TTL_74260_DIP) + LOCAL_LIB_ENTRY(TTL_74279_DIP) + LOCAL_LIB_ENTRY(DM9312_DIP) NETLIST_END() diff --git a/src/lib/netlist/macro/nlm_ttl74xx.h b/src/lib/netlist/macro/nlm_ttl74xx.h index 82b6dfef20b..693c885ce66 100644 --- a/src/lib/netlist/macro/nlm_ttl74xx.h +++ b/src/lib/netlist/macro/nlm_ttl74xx.h @@ -36,7 +36,6 @@ #define TTL_7402_DIP(name) \ NET_REGISTER_DEV(TTL_7402_DIP, name) - #define TTL_7404_GATE(name) \ NET_REGISTER_DEV(TTL_7404_GATE, name) @@ -103,88 +102,88 @@ NET_CONNECT(name, C, cI3) \ NET_CONNECT(name, D, cI4) -#define TTL_7420_DIP(name) \ +#define TTL_7420_DIP(name) \ NET_REGISTER_DEV(TTL_7420_DIP, name) -#define TTL_7425_GATE(name) \ +#define TTL_7425_GATE(name) \ NET_REGISTER_DEV(TTL_7425_GATE, name) -#define TTL_7425_NOR(name, cI1, cI2, cI3, cI4) \ - NET_REGISTER_DEV(TTL_7425_NOR, name) \ - NET_CONNECT(name, A, cI1) \ - NET_CONNECT(name, B, cI2) \ - NET_CONNECT(name, C, cI3) \ +#define TTL_7425_NOR(name, cI1, cI2, cI3, cI4) \ + NET_REGISTER_DEV(TTL_7425_NOR, name) \ + NET_CONNECT(name, A, cI1) \ + NET_CONNECT(name, B, cI2) \ + NET_CONNECT(name, C, cI3) \ NET_CONNECT(name, D, cI4) -#define TTL_7425_DIP(name) \ +#define TTL_7425_DIP(name) \ NET_REGISTER_DEV(TTL_7425_DIP, name) -#define TTL_7427_GATE(name) \ +#define TTL_7427_GATE(name) \ NET_REGISTER_DEV(TTL_7427_GATE, name) -#define TTL_7427_NOR(name, cI1, cI2, cI3) \ - NET_REGISTER_DEV(TTL_7427_NOR, name) \ - NET_CONNECT(name, A, cI1) \ - NET_CONNECT(name, B, cI2) \ +#define TTL_7427_NOR(name, cI1, cI2, cI3) \ + NET_REGISTER_DEV(TTL_7427_NOR, name) \ + NET_CONNECT(name, A, cI1) \ + NET_CONNECT(name, B, cI2) \ NET_CONNECT(name, C, cI3) -#define TTL_7427_DIP(name) \ +#define TTL_7427_DIP(name) \ NET_REGISTER_DEV(TTL_7427_DIP, name) -#define TTL_7430_GATE(name) \ +#define TTL_7430_GATE(name) \ NET_REGISTER_DEV(TTL_7430_GATE, name) -#define TTL_7430_NAND(name, cI1, cI2, cI3, cI4, cI5, cI6, cI7, cI8) \ - NET_REGISTER_DEV(TTL_7430_NAND, name) \ - NET_CONNECT(name, A, cI1) \ - NET_CONNECT(name, B, cI2) \ - NET_CONNECT(name, C, cI3) \ - NET_CONNECT(name, D, cI4) \ - NET_CONNECT(name, E, cI5) \ - NET_CONNECT(name, F, cI6) \ - NET_CONNECT(name, G, cI7) \ +#define TTL_7430_NAND(name, cI1, cI2, cI3, cI4, cI5, cI6, cI7, cI8) \ + NET_REGISTER_DEV(TTL_7430_NAND, name) \ + NET_CONNECT(name, A, cI1) \ + NET_CONNECT(name, B, cI2) \ + NET_CONNECT(name, C, cI3) \ + NET_CONNECT(name, D, cI4) \ + NET_CONNECT(name, E, cI5) \ + NET_CONNECT(name, F, cI6) \ + NET_CONNECT(name, G, cI7) \ NET_CONNECT(name, H, cI8) -#define TTL_7430_DIP(name) \ +#define TTL_7430_DIP(name) \ NET_REGISTER_DEV(TTL_7430_DIP, name) -#define TTL_7432_GATE(name) \ +#define TTL_7432_GATE(name) \ NET_REGISTER_DEV(TTL_7432_OR, name) -#define TTL_7432_OR(name, cI1, cI2) \ - NET_REGISTER_DEV(TTL_7432_OR, name) \ - NET_CONNECT(name, A, cI1) \ +#define TTL_7432_OR(name, cI1, cI2) \ + NET_REGISTER_DEV(TTL_7432_OR, name) \ + NET_CONNECT(name, A, cI1) \ NET_CONNECT(name, B, cI2) -#define TTL_7432_DIP(name) \ +#define TTL_7432_DIP(name) \ NET_REGISTER_DEV(TTL_7432_DIP, name) -#define TTL_7437_GATE(name) \ +#define TTL_7437_GATE(name) \ NET_REGISTER_DEV(TTL_7437_GATE, name) -#define TTL_7437_NAND(name, cA, cB) \ +#define TTL_7437_NAND(name, cA, cB) \ NET_REGISTER_DEV(TTL_7437_NAND, name) \ NET_CONNECT(name, A, cA) \ NET_CONNECT(name, B, cB) -#define TTL_7437_DIP(name) \ +#define TTL_7437_DIP(name) \ NET_REGISTER_DEV(TTL_7437_DIP, name) -#define TTL_7486_GATE(name) \ +#define TTL_7486_GATE(name) \ NET_REGISTER_DEV(TTL_7486_GATE, name) -#define TTL_7486_XOR(name, cA, cB) \ - NET_REGISTER_DEV(TTL_7486_XOR, name) \ - NET_CONNECT(name, A, cA) \ +#define TTL_7486_XOR(name, cA, cB) \ + NET_REGISTER_DEV(TTL_7486_XOR, name) \ + NET_CONNECT(name, A, cA) \ NET_CONNECT(name, B, cB) -#define TTL_7486_DIP(name) \ +#define TTL_7486_DIP(name) \ NET_REGISTER_DEV(TTL_7486_DIP, name) @@ -202,6 +201,27 @@ #define TTL_74260_DIP(name) \ NET_REGISTER_DEV(TTL_74260_DIP, name) +#define TTL_74279_DIP(name) \ + NET_REGISTER_DEV(TTL_74279_DIP, name) + +#define DM9312(name, cA, cB, cC, cSTROBE, cD0, cD1, cD2, cD3, cD4, cD5, cD6, cD7) \ + NET_REGISTER_DEV(DM9312_TT, name) \ + NET_CONNECT(name, A, cA) \ + NET_CONNECT(name, B, cB) \ + NET_CONNECT(name, C, cC) \ + NET_CONNECT(name, G, cSTROBE) \ + NET_CONNECT(name, D0, cD0) \ + NET_CONNECT(name, D1, cD1) \ + NET_CONNECT(name, D2, cD2) \ + NET_CONNECT(name, D3, cD3) \ + NET_CONNECT(name, D4, cD4) \ + NET_CONNECT(name, D5, cD5) \ + NET_CONNECT(name, D6, cD6) \ + NET_CONNECT(name, D7, cD7) + +#define DM9312_DIP(name) \ + NET_REGISTER_DEV(DM9312_DIP, name) + #endif /* ---------------------------------------------------------------------------- |