diff options
author | 2020-05-02 18:00:32 +0200 | |
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committer | 2020-05-02 18:00:32 +0200 | |
commit | fb2839ba10e89f58d26011b46ba436b7e2bd953d (patch) | |
tree | c630b5de162d66aa455458505593cf4d8034ac30 /src/lib/netlist/examples | |
parent | 4dde812af80708b6c1df6d77c46941ca2fab9aad (diff) |
netlist: Add simple ZDIODE model. [Couriersud]
The model is driven by three additional model parameters: NBV, IBV, BV.
Example code how to define a typical 7.5V Zener diode:
ZDIODE(ZD, "D(BV=7.5 IBV=0.01 NBV=3)")
or
NET_MODEL("A1234 D(BV=7.5 IBV=0.01 NBV=3)")
ZDIODE(ZD, "A1234")
Diffstat (limited to 'src/lib/netlist/examples')
-rw-r--r-- | src/lib/netlist/examples/zdiode.cpp | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/src/lib/netlist/examples/zdiode.cpp b/src/lib/netlist/examples/zdiode.cpp new file mode 100644 index 00000000000..644f813d78c --- /dev/null +++ b/src/lib/netlist/examples/zdiode.cpp @@ -0,0 +1,45 @@ +// license:CC0 +// copyright-holders:Couriersud + +/* + * zdiode.cpp + * + */ + +//! [zdiode_example] +#include "netlist/devices/net_lib.h" + +// ./nltool -t 1 -l clk.Q -l ZD.K -v --extended src/lib/netlist/examples/zdiode.cpp +// ./plot_nl.sh clk.Q ZD.K +// clk.Q: clock output +// ZD.K: voltage at Zener + +NETLIST_START(zdiode) + + SOLVER(Solver, 48000) + PARAM(Solver.DYNAMIC_TS, 1) + PARAM(Solver.VNTOL, 1e-7) + PARAM(Solver.RELTOL, 1e-4) + + ANALOG_INPUT(V12, 12.0) + ANALOG_INPUT(V4, 4.0) + + CLOCK(clk, 100) + ZDIODE(ZD, "D(BV=7.5 IBV=0.01 NBV=3)") + RES(R, 20) + RES(Rclk, 200) + CAP(C, 1e-6) + + NET_C(V4, clk.GND) // make clock between 4 and 12 V + NET_C(V12, clk.VCC, R.1) + + NET_C(GND, ZD.A, C.2) + NET_C(clk.Q, Rclk.1) + NET_C(Rclk.2, R.2, ZD.K, C.1) + + RES(RL, 1000) + NET_C(RL.1, ZD.K) + NET_C(RL.2, GND) + +NETLIST_END() +//! [zdiode_example] |