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author Vas Crabb <vas@vastheman.com>2019-12-21 15:15:32 +1100
committer Vas Crabb <vas@vastheman.com>2019-12-21 15:15:32 +1100
commit826db8a22b2d1f173af5a9be504bf9c3acd7f5c8 (patch)
treed27419821aeea7d4422a8a2fe9b48aefe3838c9c /src/lib/netlist/examples
parent320133cf13c02f8585315edb28319c0c24069a1e (diff)
srcclean (nw)
Diffstat (limited to 'src/lib/netlist/examples')
-rw-r--r--src/lib/netlist/examples/7400_astable.c44
-rw-r--r--src/lib/netlist/examples/74123_mstable.c48
-rw-r--r--src/lib/netlist/examples/7414.cpp18
-rw-r--r--src/lib/netlist/examples/9602_mstable.c56
-rw-r--r--src/lib/netlist/examples/LM3900_test.cpp56
-rw-r--r--src/lib/netlist/examples/bjt.c50
-rw-r--r--src/lib/netlist/examples/bjt_eb.c46
-rw-r--r--src/lib/netlist/examples/bjt_eb_pnp.c34
-rw-r--r--src/lib/netlist/examples/breakout.c490
-rw-r--r--src/lib/netlist/examples/cccs.c24
-rw-r--r--src/lib/netlist/examples/cd4066.c48
-rw-r--r--src/lib/netlist/examples/cdelay.c40
-rw-r--r--src/lib/netlist/examples/cmos_inverter.cpp16
-rw-r--r--src/lib/netlist/examples/cmos_inverter_clk.cpp16
-rw-r--r--src/lib/netlist/examples/congo_bongo.c10
-rw-r--r--src/lib/netlist/examples/cs.cpp8
-rw-r--r--src/lib/netlist/examples/diode.c28
-rw-r--r--src/lib/netlist/examples/kidniki.c88
-rw-r--r--src/lib/netlist/examples/mm5837_noise.c22
-rw-r--r--src/lib/netlist/examples/msx_mixer_stage.c78
-rw-r--r--src/lib/netlist/examples/ne555_astable.c50
-rw-r--r--src/lib/netlist/examples/nmos_fet.cpp44
-rw-r--r--src/lib/netlist/examples/norton_opamp.c190
-rw-r--r--src/lib/netlist/examples/opamp.c134
-rw-r--r--src/lib/netlist/examples/opamp_amplification_curve.cpp54
-rw-r--r--src/lib/netlist/examples/rc.c30
-rw-r--r--src/lib/netlist/examples/rl.c32
-rw-r--r--src/lib/netlist/examples/sn74ls629_osc.c30
-rw-r--r--src/lib/netlist/examples/test.c146
-rw-r--r--src/lib/netlist/examples/todo.c132
-rw-r--r--src/lib/netlist/examples/vccs.c28
-rw-r--r--src/lib/netlist/examples/vccs1.c42
-rw-r--r--src/lib/netlist/examples/vs.c10
-rw-r--r--src/lib/netlist/examples/vs_cs.c26
34 files changed, 1084 insertions, 1084 deletions
diff --git a/src/lib/netlist/examples/7400_astable.c b/src/lib/netlist/examples/7400_astable.c
index 07748a0816a..d20ededb6f7 100644
--- a/src/lib/netlist/examples/7400_astable.c
+++ b/src/lib/netlist/examples/7400_astable.c
@@ -9,27 +9,27 @@
NETLIST_START(7400_astable)
- /*
- * Astable multivibrator using two 7400 gates (or inverters)
- *
- */
-
- /* Standard stuff */
-
- SOLVER(Solver, 48000)
- PARAM(Solver.ACCURACY, 1e-5)
-
- // astable NAND Multivibrator ==> f ~ 1.0 / (3 * R * C)
- RES(R1, 4700)
- CAP(C1, 0.22e-6)
- TTL_7400_NAND(n1,R1.1,R1.1)
- TTL_7400_NAND(n2,R1.2,R1.2)
- NET_C(n1.Q, R1.2)
- NET_C(n2.Q, C1.1)
- NET_C(C1.2, R1.1)
-
- LOG(logC12, C1.2)
- LOG(logn1Q, n1.Q)
- LOG(logn2Q, n2.Q)
+ /*
+ * Astable multivibrator using two 7400 gates (or inverters)
+ *
+ */
+
+ /* Standard stuff */
+
+ SOLVER(Solver, 48000)
+ PARAM(Solver.ACCURACY, 1e-5)
+
+ // astable NAND Multivibrator ==> f ~ 1.0 / (3 * R * C)
+ RES(R1, 4700)
+ CAP(C1, 0.22e-6)
+ TTL_7400_NAND(n1,R1.1,R1.1)
+ TTL_7400_NAND(n2,R1.2,R1.2)
+ NET_C(n1.Q, R1.2)
+ NET_C(n2.Q, C1.1)
+ NET_C(C1.2, R1.1)
+
+ LOG(logC12, C1.2)
+ LOG(logn1Q, n1.Q)
+ LOG(logn2Q, n2.Q)
NETLIST_END()
diff --git a/src/lib/netlist/examples/74123_mstable.c b/src/lib/netlist/examples/74123_mstable.c
index aa21f4fe215..38e3f5f2072 100644
--- a/src/lib/netlist/examples/74123_mstable.c
+++ b/src/lib/netlist/examples/74123_mstable.c
@@ -9,39 +9,39 @@
NETLIST_START(74123_mstable)
- /*
- * Monoflog
- *
- */
+ /*
+ * Monoflog
+ *
+ */
- /* Standard stuff */
+ /* Standard stuff */
- SOLVER(Solver, 48000)
+ SOLVER(Solver, 48000)
- ANALOG_INPUT(V5, 5) // 5V
+ ANALOG_INPUT(V5, 5) // 5V
- /* Wiring up the 74123 */
+ /* Wiring up the 74123 */
- CLOCK(clk, 50)
- TTL_74123(mf)
+ CLOCK(clk, 50)
+ TTL_74123(mf)
- RES(R, 10000)
- CAP(C, 1e-6)
+ RES(R, 10000)
+ CAP(C, 1e-6)
- NET_C(GND, mf.GND)
- NET_C(V5, mf.VCC)
+ NET_C(GND, mf.GND)
+ NET_C(V5, mf.VCC)
- NET_C(C.1, mf.C)
- NET_C(mf.C, GND)
- NET_C(C.2, mf.RC, R.2)
- NET_C(R.1, V5)
+ NET_C(C.1, mf.C)
+ NET_C(mf.C, GND)
+ NET_C(C.2, mf.RC, R.2)
+ NET_C(R.1, V5)
- NET_C(mf.CLRQ, V5)
- NET_C(mf.B, V5)
- NET_C(mf.A, clk.Q)
+ NET_C(mf.CLRQ, V5)
+ NET_C(mf.B, V5)
+ NET_C(mf.A, clk.Q)
- LOG(log_C, C.2)
- LOG(log_Q, mf.Q)
- LOG(log_X, clk.Q)
+ LOG(log_C, C.2)
+ LOG(log_Q, mf.Q)
+ LOG(log_X, clk.Q)
NETLIST_END()
diff --git a/src/lib/netlist/examples/7414.cpp b/src/lib/netlist/examples/7414.cpp
index 0fcfde9a7f4..e7c01ce85d3 100644
--- a/src/lib/netlist/examples/7414.cpp
+++ b/src/lib/netlist/examples/7414.cpp
@@ -9,17 +9,17 @@
NETLIST_START(7414_astable)
- /*
- * Simple oscillator with 74LS14
- *
- * ./nltool -f nl_examples/7414.cpp -l C37.1 -l U4A1.Q
- *
- */
+ /*
+ * Simple oscillator with 74LS14
+ *
+ * ./nltool -f nl_examples/7414.cpp -l C37.1 -l U4A1.Q
+ *
+ */
- /* Standard stuff */
+ /* Standard stuff */
- SOLVER(Solver, 48000)
- PARAM(Solver.ACCURACY, 1e-8)
+ SOLVER(Solver, 48000)
+ PARAM(Solver.ACCURACY, 1e-8)
TTL_74LS14_GATE(U4A1)
//TTL_7404_GATE(U4A1)
diff --git a/src/lib/netlist/examples/9602_mstable.c b/src/lib/netlist/examples/9602_mstable.c
index 8e482c8dfb3..164241886b9 100644
--- a/src/lib/netlist/examples/9602_mstable.c
+++ b/src/lib/netlist/examples/9602_mstable.c
@@ -9,45 +9,45 @@
NETLIST_START(74123_mstable)
- /*
- * Monoflog
- *
- */
+ /*
+ * Monoflog
+ *
+ */
- /* Standard stuff */
+ /* Standard stuff */
- SOLVER(Solver, 48000)
+ SOLVER(Solver, 48000)
- ANALOG_INPUT(V5, 5) // 5V
+ ANALOG_INPUT(V5, 5) // 5V
- /* Wiring up the 74123 */
+ /* Wiring up the 74123 */
- CLOCK(clk, 50)
- TTL_9602_DIP(mf)
+ CLOCK(clk, 50)
+ TTL_9602_DIP(mf)
- RES(R, 10000)
- CAP(C, 1e-6)
+ RES(R, 10000)
+ CAP(C, 1e-6)
- NET_C(GND, mf.8) //
- NET_C(V5, mf.16) //
+ NET_C(GND, mf.8) //
+ NET_C(V5, mf.16) //
- NET_C(C.1, mf.1)
- NET_C(mf.1, GND) // Test - can be removed
- NET_C(C.2, mf.2, R.2)
- NET_C(R.1, V5)
+ NET_C(C.1, mf.1)
+ NET_C(mf.1, GND) // Test - can be removed
+ NET_C(C.2, mf.2, R.2)
+ NET_C(R.1, V5)
- NET_C(mf.3, V5) // CLR
- NET_C(mf.4, GND) // B
- NET_C(mf.5, clk.Q) // A
+ NET_C(mf.3, V5) // CLR
+ NET_C(mf.4, GND) // B
+ NET_C(mf.5, clk.Q) // A
- LOG(logC, C.2)
- LOG(logQ, mf.6) //Q
- LOG(logX, clk.Q)
+ LOG(logC, C.2)
+ LOG(logQ, mf.6) //Q
+ LOG(logX, clk.Q)
- // avoid non connected inputs
+ // avoid non connected inputs
- NET_C(mf.11, V5)
- NET_C(mf.12, V5)
- NET_C(mf.13, V5)
+ NET_C(mf.11, V5)
+ NET_C(mf.12, V5)
+ NET_C(mf.13, V5)
NETLIST_END()
diff --git a/src/lib/netlist/examples/LM3900_test.cpp b/src/lib/netlist/examples/LM3900_test.cpp
index 0498b4d2f0b..32ceb066864 100644
--- a/src/lib/netlist/examples/LM3900_test.cpp
+++ b/src/lib/netlist/examples/LM3900_test.cpp
@@ -20,14 +20,14 @@
NETLIST_START(main)
- /* Standard stuff */
-
- //VARCLOCK(clk, "0.5 / pow(10, 1 + T * 4)")
- //CLOCK(clk, 1000)
- SOLVER(Solver, 48000)
- PARAM(Solver.ACCURACY, 1e-10)
- PARAM(Solver.NR_LOOPS, 300)
- PARAM(Solver.DYNAMIC_TS, 1)
+ /* Standard stuff */
+
+ //VARCLOCK(clk, "0.5 / pow(10, 1 + T * 4)")
+ //CLOCK(clk, 1000)
+ SOLVER(Solver, 48000)
+ PARAM(Solver.ACCURACY, 1e-10)
+ PARAM(Solver.NR_LOOPS, 300)
+ PARAM(Solver.DYNAMIC_TS, 1)
PARAM(Solver.DYNAMIC_MIN_TIMESTEP, 1e-7)
VS(vs, 0)
@@ -57,47 +57,47 @@ NETLIST_START(main)
PARAM(vs.R, 0.1)
ALIAS(clk, vs.1)
NET_C(vs.2, GND)
- ANALOG_INPUT(V9, 9)
- ANALOG_INPUT(V12, 12)
- ANALOG_INPUT(VM12, -12)
+ ANALOG_INPUT(V9, 9)
+ ANALOG_INPUT(V12, 12)
+ ANALOG_INPUT(VM12, -12)
- //OPAMP(op, OPAMP_TEST)
+ //OPAMP(op, OPAMP_TEST)
LM3900(op)
- NET_C(op.GND, VM12)
- NET_C(op.VCC, V12)
+ NET_C(op.GND, VM12)
+ NET_C(op.VCC, V12)
- /* Opamp B wired as inverting amplifier connected to output of first opamp */
+ /* Opamp B wired as inverting amplifier connected to output of first opamp */
- RES(R1, 50)
- RES(RP, 500000) // Set to R2 * 2 if VPlus == VCC (see datasheet)
- RES(R2, 500000)
+ RES(R1, 50)
+ RES(RP, 500000) // Set to R2 * 2 if VPlus == VCC (see datasheet)
+ RES(R2, 500000)
- NET_C(op.PLUS, RP.1)
+ NET_C(op.PLUS, RP.1)
//NET_C(RP.2, V9)
NET_C(RP.2, GND)
//NET_C(RP.2, V12)
- NET_C(op.MINUS, R2.2)
- NET_C(op.MINUS, R1.2)
+ NET_C(op.MINUS, R2.2)
+ NET_C(op.MINUS, R1.2)
CAP(C, 10e-6)
NET_C(clk, C.1)
- NET_C(C.2, R1.1)
- NET_C(op.OUT, R2.1)
+ NET_C(C.2, R1.1)
+ NET_C(op.OUT, R2.1)
CAP(CL, 10.0e-6)
- RES(RL, 2000)
- NET_C(RL.2, GND)
- NET_C(RL.1, CL.2)
+ RES(RL, 2000)
+ NET_C(RL.2, GND)
+ NET_C(RL.1, CL.2)
NET_C(CL.1, op.OUT)
AFUNC(f, 1, "A0 * 1000")
NET_C(f.A0, RL.1)
#if 1
- LOG(log_Y, R1.1)
- LOG(log_Z, f)
+ LOG(log_Y, R1.1)
+ LOG(log_Z, f)
#endif
NETLIST_END()
diff --git a/src/lib/netlist/examples/bjt.c b/src/lib/netlist/examples/bjt.c
index 7222ced4445..f28c070910a 100644
--- a/src/lib/netlist/examples/bjt.c
+++ b/src/lib/netlist/examples/bjt.c
@@ -9,38 +9,38 @@
#include "netlist/devices/net_lib.h"
NETLIST_START(bjt)
- /* Standard stuff */
+ /* Standard stuff */
- CLOCK(clk, 1000) // 1000 Hz
- SOLVER(Solver, 48000)
- ANALOG_INPUT(V5, 5)
- ANALOG_INPUT(V3, 3.5)
+ CLOCK(clk, 1000) // 1000 Hz
+ SOLVER(Solver, 48000)
+ ANALOG_INPUT(V5, 5)
+ ANALOG_INPUT(V3, 3.5)
- /* NPN - example */
+ /* NPN - example */
- QBJT_SW(Q, "BC237B")
- RES(RB, 1000)
- RES(RC, 1000)
+ QBJT_SW(Q, "BC237B")
+ RES(RB, 1000)
+ RES(RC, 1000)
- NET_C(RC.1, V5)
- NET_C(RC.2, Q.C)
- NET_C(RB.1, clk)
- NET_C(RB.2, Q.B)
- NET_C(Q.E, GND)
+ NET_C(RC.1, V5)
+ NET_C(RC.2, Q.C)
+ NET_C(RB.1, clk)
+ NET_C(RB.2, Q.B)
+ NET_C(Q.E, GND)
- /* PNP - example */
+ /* PNP - example */
- QBJT_SW(Q1, "BC556B")
- RES(RB1, 1000)
- RES(RC1, 1000)
+ QBJT_SW(Q1, "BC556B")
+ RES(RB1, 1000)
+ RES(RC1, 1000)
- NET_C(RC1.1, GND)
- NET_C(RC1.2, Q1.C)
- NET_C(RB1.1, clk)
- NET_C(RB1.2, Q1.B)
- NET_C(Q1.E, V3)
+ NET_C(RC1.1, GND)
+ NET_C(RC1.2, Q1.C)
+ NET_C(RB1.1, clk)
+ NET_C(RB1.2, Q1.B)
+ NET_C(Q1.E, V3)
- LOG(logB, Q.B)
- LOG(logC, Q.C)
+ LOG(logB, Q.B)
+ LOG(logC, Q.C)
NETLIST_END()
diff --git a/src/lib/netlist/examples/bjt_eb.c b/src/lib/netlist/examples/bjt_eb.c
index f21735c36ec..a42def2df3b 100644
--- a/src/lib/netlist/examples/bjt_eb.c
+++ b/src/lib/netlist/examples/bjt_eb.c
@@ -10,35 +10,35 @@
#include "netlist/analog/nld_twoterm.h"
NETLIST_START(bjt)
- /* Standard stuff */
+ /* Standard stuff */
- CLOCK(clk, 10000) // 10000 Hz
- SOLVER(Solver, 48000)
- PARAM(Solver.ACCURACY, 1e-6)
- PARAM(Solver.RESCHED_LOOPS, 30)
- ANALOG_INPUT(V5, 5)
- ANALOG_INPUT(V3, 3.5)
+ CLOCK(clk, 10000) // 10000 Hz
+ SOLVER(Solver, 48000)
+ PARAM(Solver.ACCURACY, 1e-6)
+ PARAM(Solver.RESCHED_LOOPS, 30)
+ ANALOG_INPUT(V5, 5)
+ ANALOG_INPUT(V3, 3.5)
- /* NPN - example */
+ /* NPN - example */
- QBJT_EB(Q, "BC237B")
- RES(RB, 1000)
- RES(RC, 1000)
+ QBJT_EB(Q, "BC237B")
+ RES(RB, 1000)
+ RES(RC, 1000)
- NET_C(RC.1, V5)
- NET_C(RC.2, Q.C)
- NET_C(RB.1, clk)
- //NET_C(RB.1, V3)
- NET_C(RB.2, Q.B)
- NET_C(Q.E, GND)
+ NET_C(RC.1, V5)
+ NET_C(RC.2, Q.C)
+ NET_C(RB.1, clk)
+ //NET_C(RB.1, V3)
+ NET_C(RB.2, Q.B)
+ NET_C(Q.E, GND)
- // put some load on Q.C
+ // put some load on Q.C
- RES(RCE, 150000)
- NET_C(RCE.1, Q.C)
- NET_C(RCE.2, GND)
+ RES(RCE, 150000)
+ NET_C(RCE.1, Q.C)
+ NET_C(RCE.2, GND)
- //LOG(logB, Q.B)
- //LOG(logC, Q.C)
+ //LOG(logB, Q.B)
+ //LOG(logC, Q.C)
NETLIST_END()
diff --git a/src/lib/netlist/examples/bjt_eb_pnp.c b/src/lib/netlist/examples/bjt_eb_pnp.c
index 10169b6bd3f..7ca43466300 100644
--- a/src/lib/netlist/examples/bjt_eb_pnp.c
+++ b/src/lib/netlist/examples/bjt_eb_pnp.c
@@ -9,27 +9,27 @@
#include "netlist/devices/net_lib.h"
NETLIST_START(bjt)
- /* Standard stuff */
+ /* Standard stuff */
- CLOCK(clk, 1000) // 1000 Hz
- SOLVER(Solver, 48000)
- ANALOG_INPUT(V5, 5)
- ANALOG_INPUT(V3, 3.5)
+ CLOCK(clk, 1000) // 1000 Hz
+ SOLVER(Solver, 48000)
+ ANALOG_INPUT(V5, 5)
+ ANALOG_INPUT(V3, 3.5)
- /* PNP - example */
+ /* PNP - example */
- QBJT_EB(Q1, "BC556B")
- RES(RB1, 1000)
- RES(RC1, 1000)
+ QBJT_EB(Q1, "BC556B")
+ RES(RB1, 1000)
+ RES(RC1, 1000)
- NET_C(RC1.1, GND)
- NET_C(RC1.2, Q1.C)
- NET_C(RB1.1, clk)
- NET_C(RB1.2, Q1.B)
- NET_C(Q1.E, V3)
+ NET_C(RC1.1, GND)
+ NET_C(RC1.2, Q1.C)
+ NET_C(RB1.1, clk)
+ NET_C(RB1.2, Q1.B)
+ NET_C(Q1.E, V3)
- LOG(logA, clk)
- LOG(logB, Q1.B)
- LOG(logC, Q1.C)
+ LOG(logA, clk)
+ LOG(logB, Q1.B)
+ LOG(logC, Q1.C)
NETLIST_END()
diff --git a/src/lib/netlist/examples/breakout.c b/src/lib/netlist/examples/breakout.c
index 591ffaf3414..c5919af5e5a 100644
--- a/src/lib/netlist/examples/breakout.c
+++ b/src/lib/netlist/examples/breakout.c
@@ -9,45 +9,45 @@
//2 555 timers
static Astable555Desc b2_555_desc(OHM(560.0), M_OHM(1.8), U_FARAD(0.1));
-static Mono555Desc c9_555_desc(OHM(47.0), U_FARAD(1.0)); // R33, C21
+static Mono555Desc c9_555_desc(OHM(47.0), U_FARAD(1.0)); // R33, C21
//check these values
//static Paddle1HorizontalDesc pad1_desc(15047.0, 47.0, &c9_555_desc);
static CapacitorDesc c32_desc(U_FARAD(0.1));
-static CapacitorDesc c36_desc(N_FARAD(1.0)); //0.001uF = 1nF
+static CapacitorDesc c36_desc(N_FARAD(1.0)); //0.001uF = 1nF
static CapacitorDesc c37_desc(P_FARAD(330.0));
static BufferDesc pad_en_buf_desc(DELAY_NS(15.0), DELAY_NS(15.0)); // Prevents 12ns glitch on PAD_EN_n signal from resetting C9. TODO: is this accurate?
#if 0
static VIDEO_DESC( breakout )
- VIDEO_RESISTANCE(1, K_OHM(0.0))
- VIDEO_RESISTANCE(2, K_OHM(3.9))
- VIDEO_RESISTANCE(3, K_OHM(3.9))
- VIDEO_RESISTANCE(4, K_OHM(3.9))
- VIDEO_RESISTANCE(5, K_OHM(3.9))
- VIDEO_RESISTANCE(6, K_OHM(3.9))
- //VIDEO_RESISTANCE(Video::HBLANK_PIN, K_OHM(0.0))
- VIDEO_ORIENTATION(ROTATE_90)
- VIDEO_CONTRAST(4.0)
-
- // Values guessed based on screenshots. TODO: Make more accurate
- // X, Y, W, H, R, G, B
- VIDEO_OVERLAY( 15.570e-6, 0.0, 1.911e-6, -1.0, 0.80, 0.15, 0.05 ) // Red Bricks
- VIDEO_OVERLAY( 17.481e-6, 0.0, 1.956e-6, -1.0, 0.95, 0.65, 0.05 ) // Amber Bricks
- VIDEO_OVERLAY( 19.437e-6, 0.0, 1.956e-6, -1.0, 0.05, 0.65, 0.25 ) // Green Bricks
- VIDEO_OVERLAY( 21.393e-6, 0.0, 1.955e-6, -1.0, 0.95, 0.95, 0.20 ) // Yellow Bricks
- VIDEO_OVERLAY( 51.345e-6, 0.0, 1.956e-6, -1.0, 0.05, 0.65, 0.95 ) // Blue Paddle
-
- // TODO: Different overlays for cocktail cabinet
+ VIDEO_RESISTANCE(1, K_OHM(0.0))
+ VIDEO_RESISTANCE(2, K_OHM(3.9))
+ VIDEO_RESISTANCE(3, K_OHM(3.9))
+ VIDEO_RESISTANCE(4, K_OHM(3.9))
+ VIDEO_RESISTANCE(5, K_OHM(3.9))
+ VIDEO_RESISTANCE(6, K_OHM(3.9))
+ //VIDEO_RESISTANCE(Video::HBLANK_PIN, K_OHM(0.0))
+ VIDEO_ORIENTATION(ROTATE_90)
+ VIDEO_CONTRAST(4.0)
+
+ // Values guessed based on screenshots. TODO: Make more accurate
+ // X, Y, W, H, R, G, B
+ VIDEO_OVERLAY( 15.570e-6, 0.0, 1.911e-6, -1.0, 0.80, 0.15, 0.05 ) // Red Bricks
+ VIDEO_OVERLAY( 17.481e-6, 0.0, 1.956e-6, -1.0, 0.95, 0.65, 0.05 ) // Amber Bricks
+ VIDEO_OVERLAY( 19.437e-6, 0.0, 1.956e-6, -1.0, 0.05, 0.65, 0.25 ) // Green Bricks
+ VIDEO_OVERLAY( 21.393e-6, 0.0, 1.955e-6, -1.0, 0.95, 0.95, 0.20 ) // Yellow Bricks
+ VIDEO_OVERLAY( 51.345e-6, 0.0, 1.956e-6, -1.0, 0.05, 0.65, 0.95 ) // Blue Paddle
+
+ // TODO: Different overlays for cocktail cabinet
VIDEO_DESC_END
static AUDIO_DESC( breakout )
- AUDIO_RESISTANCE(1, K_OHM(47.0))
- AUDIO_RESISTANCE(2, K_OHM(47.0))
- AUDIO_RESISTANCE(3, K_OHM(47.0))
- AUDIO_RESISTANCE(4, K_OHM(47.0))
- AUDIO_GAIN(3.0)
+ AUDIO_RESISTANCE(1, K_OHM(47.0))
+ AUDIO_RESISTANCE(2, K_OHM(47.0))
+ AUDIO_RESISTANCE(3, K_OHM(47.0))
+ AUDIO_RESISTANCE(4, K_OHM(47.0))
+ AUDIO_GAIN(3.0)
VIDEO_DESC_END
#endif
@@ -63,26 +63,26 @@ static Dipswitch53137Desc dipswitch1_desc("bonus_credit", "Bonus Credit", 3, "No
//static DipswitchDesc dipswitch4_desc("ball_count", "Ball Count", 0, "3", "5");
CIRCUIT_LAYOUT( breakout )
- CHIP("S1", 53137, &dipswitch1_desc)
+ CHIP("S1", 53137, &dipswitch1_desc)
CHIP("S2", DIPSWITCH, &dipswitch2_desc)
CHIP("S3", DIPSWITCH, &dipswitch3_desc)
CHIP("S4", DIPSWITCH, &dipswitch4_desc)
- SOLVER(Solver, 48000)
- PARAM(Solver.ACCURACY, 1e-7) // works and is sufficient
- //CHIP("CLOCK", CLOCK_14_318_MHZ)
- MAINCLOCK(Y1, 14318000.0)
+ SOLVER(Solver, 48000)
+ PARAM(Solver.ACCURACY, 1e-7) // works and is sufficient
+ //CHIP("CLOCK", CLOCK_14_318_MHZ)
+ MAINCLOCK(Y1, 14318000.0)
- ANALOG_INPUT(V5, 5)
+ ANALOG_INPUT(V5, 5)
#define VCC "V5", Q
#define GND "GND", Q
- //CHIP("Y1", CLOCK_14_318_MHZ) //Y1
+ //CHIP("Y1", CLOCK_14_318_MHZ) //Y1
CHIP_CAPACITOR(C32, &c32_desc)
CHIP_CAPACITOR(C36, &c36_desc)
- CHIP_CAPACITOR(C37, &c37_desc)
- CHIP("PAD_EN_BUF", BUFFER, &pad_en_buf_desc)
+ CHIP_CAPACITOR(C37, &c37_desc)
+ CHIP("PAD_EN_BUF", BUFFER, &pad_en_buf_desc)
CHIP("A3", 7474)
CHIP("A4", 7408)
@@ -91,7 +91,7 @@ CIRCUIT_LAYOUT( breakout )
CHIP_9602_Mono(A7, &a7_desc)
CHIP_9602_Mono(A8, &a8_desc)
- CHIP_555_Astable(B2, &b2_555_desc)
+ CHIP_555_Astable(B2, &b2_555_desc)
CHIP("B3", 7402)
CHIP("B4", 9316)
CHIP("B5", 74193)
@@ -107,7 +107,7 @@ CIRCUIT_LAYOUT( breakout )
CHIP("C6", 7486)
CHIP("C7", 9316)
CHIP("C8", 9316)
- CHIP_555_Mono(C9, &c9_555_desc)
+ CHIP_555_Mono(C9, &c9_555_desc)
CHIP("D2", 7432)
CHIP("D3", 7474)
@@ -116,7 +116,7 @@ CIRCUIT_LAYOUT( breakout )
CHIP("D6", 7408)
CHIP("D7", 7411)
CHIP("D8", 7400)
-// CHIP("D9", 4016) //quad bilateral switch
+// CHIP("D9", 4016) //quad bilateral switch
CHIP("E1", 7404)
CHIP("E2", 7486)
@@ -144,7 +144,7 @@ CIRCUIT_LAYOUT( breakout )
CHIP("H4", 7400)
CHIP("H5", 9312)
CHIP("H6", 9310)
- CHIP("H7", 7408) //sometimes looks like N7 on schematic
+ CHIP("H7", 7408) //sometimes looks like N7 on schematic
CHIP("H8", 7474)
CHIP("H9", 7474)
@@ -165,18 +165,18 @@ CIRCUIT_LAYOUT( breakout )
CHIP("K5", 9312)
CHIP("K6", 9310)
CHIP("K7", 7486)
- CHIP("K8", 7474) //TODO: one more than bom?
+ CHIP("K8", 7474) //TODO: one more than bom?
CHIP("K9", 74107)
CHIP("L1", 9316)
CHIP("L2", 7486)
- CHIP("L3", 82S16) //RAM
+ CHIP("L3", 82S16) //RAM
CHIP("L4", 7411)
CHIP("L5", 9312)
CHIP("L6", 9310)
CHIP("L7", 7486)
CHIP("L8", 74193)
- CHIP("L9", 7400) //TODO: 1 more chip than on bom?
+ CHIP("L9", 7400) //TODO: 1 more chip than on bom?
CHIP("M1", 9316)
CHIP("M2", 7483)
@@ -193,232 +193,232 @@ CIRCUIT_LAYOUT( breakout )
CHIP("N4", 7411)
CHIP("N5", 9312)
CHIP("N6", 9310)
- CHIP("N7", 7408) //sometimes looks like H7 on schematic
+ CHIP("N7", 7408) //sometimes looks like H7 on schematic
CHIP_9602_Mono(N8, &n8_desc)
CHIP("N9", 74192)
- //LM380 //speaker amplifier
- //LM323 //regulator
+ //LM380 //speaker amplifier
+ //LM323 //regulator
// CHIP("CREDIT_LIGHT1", LAMP)
// CHIP("CREDIT_LIGHT2", LAMP)
// CHIP("SERVE_LIGHT", LAMP)
- CHIP("PAD1", PADDLE1_HORIZONTAL_INPUT, &pad1_desc)
- PADDLE_CONNECTION("PAD1", "C9")
+ CHIP("PAD1", PADDLE1_HORIZONTAL_INPUT, &pad1_desc)
+ PADDLE_CONNECTION("PAD1", "C9")
- CHIP_LATCH(LATCH)
- CHIP("COIN1", COIN_INPUT)
+ CHIP_LATCH(LATCH)
+ CHIP("COIN1", COIN_INPUT)
- //CHIP("COIN2", COIN_INPUT)
+ //CHIP("COIN2", COIN_INPUT)
- CHIP("START", START_INPUT)
+ CHIP("START", START_INPUT)
- CHIP("SERVE", BUTTONS1_INPUT)
+ CHIP("SERVE", BUTTONS1_INPUT)
- //TODO: coin2 and start 2
+ //TODO: coin2 and start 2
- VIDEO(breakout)
- AUDIO(breakout)
+ VIDEO(breakout)
+ AUDIO(breakout)
#ifdef DEBUG
CHIP("LOG1", VCD_LOG, &vcd_log_desc)
#endif
//HSYNC and VSYNC
- #define H1_d "L1", 14
- #define H2_d "L1", 13
- #define H4_d "L1", 12
- #define H8_d "L1", 11
- #define H8_n "J2", 2
- #define H16_d "K1", 14
- #define H16_n "J2", 6
- #define H32_d "K1", 13
- #define H32_n "J2", 4
- #define H64_d "K1", 12
- #define H128_d "K1", 11
-
- #define V1_d "M1", 14
- #define V2_d "M1", 13
- #define V4_d "M1", 12
- #define V8_d "M1", 11
- #define V16_d "N1", 14
- #define V16_n "J2", 10
- #define V32_d "N1", 13
- #define V64_d "N1", 12
- #define V64I "H7", 11
- #define V64_n "M9", 10
- #define V128_d "N1", 11
-
- #define H1 "L2", 8
- #define H2 "L2", 11
- #define H4 "L2", 3
- #define H8 "L2", 6
- #define H16 "K2", 8
- #define H32 "K2", 11
- #define H64 "K2", 3
- #define H128 "K2", 6
+ #define H1_d "L1", 14
+ #define H2_d "L1", 13
+ #define H4_d "L1", 12
+ #define H8_d "L1", 11
+ #define H8_n "J2", 2
+ #define H16_d "K1", 14
+ #define H16_n "J2", 6
+ #define H32_d "K1", 13
+ #define H32_n "J2", 4
+ #define H64_d "K1", 12
+ #define H128_d "K1", 11
+
+ #define V1_d "M1", 14
+ #define V2_d "M1", 13
+ #define V4_d "M1", 12
+ #define V8_d "M1", 11
+ #define V16_d "N1", 14
+ #define V16_n "J2", 10
+ #define V32_d "N1", 13
+ #define V64_d "N1", 12
+ #define V64I "H7", 11
+ #define V64_n "M9", 10
+ #define V128_d "N1", 11
+
+ #define H1 "L2", 8
+ #define H2 "L2", 11
+ #define H4 "L2", 3
+ #define H8 "L2", 6
+ #define H16 "K2", 8
+ #define H32 "K2", 11
+ #define H64 "K2", 3
+ #define H128 "K2", 6
//#define V1
- #define V2 "M3", 3
- #define V4 "M3", 6
- #define V8 "M3", 11
- #define V16 "N3", 8
- #define V32 "N3", 3
- #define V64 "N3", 6
- #define V128 "N3", 11
-
- #define HSYNC "J1", 2
- #define HSYNC_n "J1", 3
- #define VSYNC "J1", 7
- #define VSYNC_n "J1", 6
- #define PSYNC "J1", 11
- #define PSYNC_n "J1", 10
- #define BSYNC "J1", 15
- #define BSYNC_n "J1", 14
-
- #define BALL "D7", 6
+ #define V2 "M3", 3
+ #define V4 "M3", 6
+ #define V8 "M3", 11
+ #define V16 "N3", 8
+ #define V32 "N3", 3
+ #define V64 "N3", 6
+ #define V128 "N3", 11
+
+ #define HSYNC "J1", 2
+ #define HSYNC_n "J1", 3
+ #define VSYNC "J1", 7
+ #define VSYNC_n "J1", 6
+ #define PSYNC "J1", 11
+ #define PSYNC_n "J1", 10
+ #define BSYNC "J1", 15
+ #define BSYNC_n "J1", 14
+
+ #define BALL "D7", 6
#define BALL_DISPLAY "A4", 6
- #define PLAYFIELD "H4", 3
- #define SCORE "D3", 5
- #define VERT_TRIG_n "H1", 8
+ #define PLAYFIELD "H4", 3
+ #define SCORE "D3", 5
+ #define VERT_TRIG_n "H1", 8
- #define CLOCK "H1", 11
- #define SCLOCK "K1", 15
- #define CKBH "F1", 13
+ #define CLOCK "H1", 11
+ #define SCLOCK "K1", 15
+ #define CKBH "F1", 13
- #define PAD_n "K3", 8
- #define PAD_EN_n "C2", 8
+ #define PAD_n "K3", 8
+ #define PAD_EN_n "C2", 8
//#define P VCC
#define P "V5", Q
- #define COIN "L9", 6
- #define COIN1_n "F8", 5
- #define COIN2_n "H9", 5
- #define CREDIT_1_OR_2 "L9", 3
- #define CREDIT_1_OR_2_n "F9", 8
- #define CREDIT2 "F9", 6
- #define CREDIT2_n "M8", 8
- #define CR_START1 "E8", 5
- #define CR_START1_n "E8", 6 //Schematic shows E8.6 as positive CR_START1, but this can't be right?
- #define CR_START2 "E8", 9
- #define CR_START2_n "E8", 8
- #define CSW1 "F9", 12
- #define CSW2 "F9", 2
-
- #define P2_CONDITIONAL "H1", 3
- #define P2_CONDITIONAL_dash "H7", 8
- #define PLAYER_2 "B4", 14
- #define PLAYER_2_n "M9", 8
-
- #define START_GAME "D8", 6
- #define START_GAME1_n "M9", 4
- #define START_GAME_n "M9", 6
-
- #define BG1_n "K8", 9
- #define BG1 "K8", 8
- #define BG2_n "K8", 5
- #define BG2 "K8", 6
-
- #define FREE_GAME_TONE "N7", 3
- #define BONUS_COIN "L9", 11
+ #define COIN "L9", 6
+ #define COIN1_n "F8", 5
+ #define COIN2_n "H9", 5
+ #define CREDIT_1_OR_2 "L9", 3
+ #define CREDIT_1_OR_2_n "F9", 8
+ #define CREDIT2 "F9", 6
+ #define CREDIT2_n "M8", 8
+ #define CR_START1 "E8", 5
+ #define CR_START1_n "E8", 6 //Schematic shows E8.6 as positive CR_START1, but this can't be right?
+ #define CR_START2 "E8", 9
+ #define CR_START2_n "E8", 8
+ #define CSW1 "F9", 12
+ #define CSW2 "F9", 2
+
+ #define P2_CONDITIONAL "H1", 3
+ #define P2_CONDITIONAL_dash "H7", 8
+ #define PLAYER_2 "B4", 14
+ #define PLAYER_2_n "M9", 8
+
+ #define START_GAME "D8", 6
+ #define START_GAME1_n "M9", 4
+ #define START_GAME_n "M9", 6
+
+ #define BG1_n "K8", 9
+ #define BG1 "K8", 8
+ #define BG2_n "K8", 5
+ #define BG2 "K8", 6
+
+ #define FREE_GAME_TONE "N7", 3
+ #define BONUS_COIN "L9", 11
//#define Q "E9", 6
- #define LAT_Q "E9", 6
- #define Q_n "LATCH", 3
- #define SBD_n "D2", 11
+ #define LAT_Q "E9", 6
+ #define Q_n "LATCH", 3
+ #define SBD_n "D2", 11
- #define PLAY_CP "D2", 8
- #define PLGM2_n "F7", 7
- #define VB_HIT_n "A5", 6
+ #define PLAY_CP "D2", 8
+ #define PLGM2_n "F7", 7
+ #define VB_HIT_n "A5", 6
- #define SERVE_n "SERVE", 1
- #define SERVE_WAIT "A3", 9
+ #define SERVE_n "SERVE", 1
+ #define SERVE_WAIT "A3", 9
#define SERVE_WAIT_n "A3", 8
- #define BRICK_DISPLAY "E3", 1
- #define BRICK_HIT "E6", 5
- #define BRICK_HIT_n "E6", 6
-
- //#define EGL "A4", 3
- #define EGL "C37" , 2
- #define EGL_n "C5", 2
-
- #define RAM_PLAYER1 "E7", 4
- #define A1 "H6", 14
- #define B1 "H6", 13
- #define C1 "H6", 12
- #define D1 "H6", 11
- #define E1 "J6", 14
- #define F1 "J6", 13
- #define G1 "J6", 12
- #define H01 "J6", 11
- #define I1 "K6", 14
- #define J1 "K6", 13
- #define K1 "K6", 12
- #define L1 "K6", 11
- #define A2 "N6", 14
- #define B2 "N6", 13
- #define C2 "N6", 12
- #define D2 "N6", 11
- #define E2 "M6", 14
- #define F2 "M6", 13
- #define G2 "M6", 12
- #define H02 "M6", 11 //TODO: better name for these signals
- #define I2 "L6", 14
- #define J2 "L6", 13
- #define K2 "L6", 12
- #define L2 "L6", 11
-
- #define CX0 "C6", 11
- #define CX1 "C6", 6
- #define X0 "C5", 10
- #define X1 "B6", 3
- #define X2 "C6", 3
- #define Y0 "B6", 11
- #define Y1 "B6", 6
- #define Y2 "A6", 6
- #define DN "C4", 3
- #define PC "D4", 12
- #define PD "D4", 11
- #define SU_n "D5", 8
- #define V_SLOW "C5", 8
-
- #define PLNR "E3", 4
- #define SCI_n "H4", 6
- #define SFL_n "E9", 12 //score flash
- #define TOP_n "E9", 2
-
- #define BP_HIT_n "A5", 8
- #define BTB_HIT_n "C3", 3
-
- #define SET_BRICKS "D3", 9
+ #define BRICK_DISPLAY "E3", 1
+ #define BRICK_HIT "E6", 5
+ #define BRICK_HIT_n "E6", 6
+
+ //#define EGL "A4", 3
+ #define EGL "C37" , 2
+ #define EGL_n "C5", 2
+
+ #define RAM_PLAYER1 "E7", 4
+ #define A1 "H6", 14
+ #define B1 "H6", 13
+ #define C1 "H6", 12
+ #define D1 "H6", 11
+ #define E1 "J6", 14
+ #define F1 "J6", 13
+ #define G1 "J6", 12
+ #define H01 "J6", 11
+ #define I1 "K6", 14
+ #define J1 "K6", 13
+ #define K1 "K6", 12
+ #define L1 "K6", 11
+ #define A2 "N6", 14
+ #define B2 "N6", 13
+ #define C2 "N6", 12
+ #define D2 "N6", 11
+ #define E2 "M6", 14
+ #define F2 "M6", 13
+ #define G2 "M6", 12
+ #define H02 "M6", 11 //TODO: better name for these signals
+ #define I2 "L6", 14
+ #define J2 "L6", 13
+ #define K2 "L6", 12
+ #define L2 "L6", 11
+
+ #define CX0 "C6", 11
+ #define CX1 "C6", 6
+ #define X0 "C5", 10
+ #define X1 "B6", 3
+ #define X2 "C6", 3
+ #define Y0 "B6", 11
+ #define Y1 "B6", 6
+ #define Y2 "A6", 6
+ #define DN "C4", 3
+ #define PC "D4", 12
+ #define PD "D4", 11
+ #define SU_n "D5", 8
+ #define V_SLOW "C5", 8
+
+ #define PLNR "E3", 4
+ #define SCI_n "H4", 6
+ #define SFL_n "E9", 12 //score flash
+ #define TOP_n "E9", 2
+
+ #define BP_HIT_n "A5", 8
+ #define BTB_HIT_n "C3", 3
+
+ #define SET_BRICKS "D3", 9
#define SET_BRICKS_n "D3", 8
- #define BALL_A "B4", 13
- #define BALL_B "B4", 12
- #define BALL_C "B4", 11
+ #define BALL_A "B4", 13
+ #define BALL_B "B4", 12
+ #define BALL_C "B4", 11
- #define FPD1 "F3", 10
- #define FPD1_n "F3", 9
- #define FPD2 "F3", 6
- #define FPD2_n "F3", 7
+ #define FPD1 "F3", 10
+ #define FPD1_n "F3", 9
+ #define FPD2 "F3", 6
+ #define FPD2_n "F3", 7
- #define COUNT "N7", 11
- #define COUNT_1 "N7", 8
- #define COUNT_2 "N7", 6
+ #define COUNT "N7", 11
+ #define COUNT_1 "N7", 8
+ #define COUNT_2 "N7", 6
- #define ATTRACT "E6", 8
- #define ATTRACT_n "E6", 9
+ #define ATTRACT "E6", 8
+ #define ATTRACT_n "E6", 9
- #define BRICK_SOUND "B8", 14
- #define P_HIT_SOUND "B7", 12
+ #define BRICK_SOUND "B8", 14
+ #define P_HIT_SOUND "B7", 12
#define VB_HIT_SOUND "B7", 11
- #define LH_SIDE "J3", 13
- #define RH_SIDE "H2", 3
- #define TOP_BOUND "K4", 6
+ #define LH_SIDE "J3", 13
+ #define RH_SIDE "H2", 3
+ #define TOP_BOUND "K4", 6
// CONNECTION(CREDIT_1_OR_2, "CREDIT_LIGHT1", 1)
// CONNECTION(CREDIT2, "CREDIT_LIGHT2", 1)
@@ -1065,7 +1065,7 @@ CIRCUIT_LAYOUT( breakout )
//COIN2 circuit
//CONNECTION("COIN2", 1, "F9", 1)
- CONNECTION(GND, "F9", 1) //TODO: coin2 not implemented
+ CONNECTION(GND, "F9", 1) //TODO: coin2 not implemented
CONNECTION(CSW2, "F9", 3)
CONNECTION(CSW2, "H9", 10)
@@ -1132,10 +1132,10 @@ CIRCUIT_LAYOUT( breakout )
//TODO: hows this whole latch stuff work? what about Q_n going to COIN1_n and COIN2_n
CONNECTION(CREDIT_1_OR_2_n, "D8", 13)
CONNECTION(EGL, "D8", 12)
- CONNECTION("LATCH", 1, "D8", 11) //set
- CONNECTION("LATCH", 2, COIN1_n) //reset
- //CONNECTION("LATCH", 3, COIN2_n) //set //TODO: coin2 here
- CONNECTION( "LATCH", 3, "E9", 5) //output
+ CONNECTION("LATCH", 1, "D8", 11) //set
+ CONNECTION("LATCH", 2, COIN1_n) //reset
+ //CONNECTION("LATCH", 3, COIN2_n) //set //TODO: coin2 here
+ CONNECTION( "LATCH", 3, "E9", 5) //output
CONNECTION(LAT_Q, "D6", 1)
@@ -1441,21 +1441,21 @@ CIRCUIT_LAYOUT( breakout )
#ifdef DEBUG
- // RAM access
- /*CONNECTION("LOG1", 3, H4) //A
- CONNECTION("LOG1", 4, H8) //B
- CONNECTION("LOG1", 5, H16) //C
- CONNECTION("LOG1", 6, V32) //D
- CONNECTION("LOG1", 7, V64) //E
- CONNECTION("LOG1", 8, V128) //F
- CONNECTION("LOG1", 9, V16) //G
- CONNECTION("LOG1", 10, RAM_PLAYER1) //H
- CONNECTION("LOG1", 11, H32) //I
- CONNECTION("LOG1", 12, H128) //J
- CONNECTION("LOG1", 13, "H4", 8) //K
- CONNECTION("LOG1", 14, "E1", 4) //L
- CONNECTION("LOG1", 15, "F2", 12) //M
- CONNECTION("LOG1", 16, "L3", 6)*/ //N
+ // RAM access
+ /*CONNECTION("LOG1", 3, H4) //A
+ CONNECTION("LOG1", 4, H8) //B
+ CONNECTION("LOG1", 5, H16) //C
+ CONNECTION("LOG1", 6, V32) //D
+ CONNECTION("LOG1", 7, V64) //E
+ CONNECTION("LOG1", 8, V128) //F
+ CONNECTION("LOG1", 9, V16) //G
+ CONNECTION("LOG1", 10, RAM_PLAYER1) //H
+ CONNECTION("LOG1", 11, H32) //I
+ CONNECTION("LOG1", 12, H128) //J
+ CONNECTION("LOG1", 13, "H4", 8) //K
+ CONNECTION("LOG1", 14, "E1", 4) //L
+ CONNECTION("LOG1", 15, "F2", 12) //M
+ CONNECTION("LOG1", 16, "L3", 6)*/ //N
#endif
CIRCUIT_LAYOUT_END
diff --git a/src/lib/netlist/examples/cccs.c b/src/lib/netlist/examples/cccs.c
index a1244677d20..2c7833b19f3 100644
--- a/src/lib/netlist/examples/cccs.c
+++ b/src/lib/netlist/examples/cccs.c
@@ -10,24 +10,24 @@
NETLIST_START(cccs)
- CLOCK(clk, 1000) // 1000 Hz
- SOLVER(Solver, 48000)
- PARAM(Solver.ACCURACY, 1e-12)
- PARAM(Solver.METHOD, "MAT_CR")
+ CLOCK(clk, 1000) // 1000 Hz
+ SOLVER(Solver, 48000)
+ PARAM(Solver.ACCURACY, 1e-12)
+ PARAM(Solver.METHOD, "MAT_CR")
- CCCS(VV)
- PARAM(VV.G, 1)
- PARAM(VV.RI, 1e-3)
+ CCCS(VV)
+ PARAM(VV.G, 1)
+ PARAM(VV.RI, 1e-3)
RES(R2, 1000)
RES(R1, 1000)
- NET_C(clk, VV.IP)
- NET_C(VV.IN, R1.1)
+ NET_C(clk, VV.IP)
+ NET_C(VV.IN, R1.1)
NET_C(R1.2, GND)
- NET_C(R2.1, VV.OP)
- NET_C(R2.2, GND)
- NET_C(VV.ON, GND)
+ NET_C(R2.1, VV.OP)
+ NET_C(R2.2, GND)
+ NET_C(VV.ON, GND)
/* Simple current source */
diff --git a/src/lib/netlist/examples/cd4066.c b/src/lib/netlist/examples/cd4066.c
index c77e6438c0f..1917c1909fc 100644
--- a/src/lib/netlist/examples/cd4066.c
+++ b/src/lib/netlist/examples/cd4066.c
@@ -9,38 +9,38 @@
#include "netlist/devices/net_lib.h"
NETLIST_START(cd4066)
- /* Standard stuff */
+ /* Standard stuff */
- CLOCK(clk, 1000) // 1000 Hz
- SOLVER(Solver, 48000)
+ CLOCK(clk, 1000) // 1000 Hz
+ SOLVER(Solver, 48000)
- ANALOG_INPUT(V5, 5)
+ ANALOG_INPUT(V5, 5)
- CD_4066_DIP(SW)
- RES(R1, 1000)
+ CD_4066_DIP(SW)
+ RES(R1, 1000)
- NET_C(SW.7, GND)
- NET_C(SW.14, V5)
+ NET_C(SW.7, GND)
+ NET_C(SW.14, V5)
- NET_C(SW.13, clk)
- NET_C(SW.1, V5)
+ NET_C(SW.13, clk)
+ NET_C(SW.1, V5)
- NET_C(SW.2, R1.1)
- NET_C(R1.2, GND)
+ NET_C(SW.2, R1.1)
+ NET_C(R1.2, GND)
- // ground anything else
+ // ground anything else
- NET_C(SW.3, GND)
- NET_C(SW.4, GND)
- NET_C(SW.5, GND)
- NET_C(SW.6, GND)
- NET_C(SW.8, GND)
- NET_C(SW.9, GND)
- NET_C(SW.10, GND)
- NET_C(SW.11, GND)
- NET_C(SW.12, GND)
+ NET_C(SW.3, GND)
+ NET_C(SW.4, GND)
+ NET_C(SW.5, GND)
+ NET_C(SW.6, GND)
+ NET_C(SW.8, GND)
+ NET_C(SW.9, GND)
+ NET_C(SW.10, GND)
+ NET_C(SW.11, GND)
+ NET_C(SW.12, GND)
- LOG(logB, clk)
- LOG(logC, R1.1)
+ LOG(logB, clk)
+ LOG(logC, R1.1)
NETLIST_END()
diff --git a/src/lib/netlist/examples/cdelay.c b/src/lib/netlist/examples/cdelay.c
index 5f4f8d04440..273a9fcfab7 100644
--- a/src/lib/netlist/examples/cdelay.c
+++ b/src/lib/netlist/examples/cdelay.c
@@ -9,11 +9,11 @@
NETLIST_START(perf)
- SOLVER(Solver, 48000)
- PARAM(Solver.ACCURACY, 1e-20)
- MAINCLOCK(clk, 50000000)
+ SOLVER(Solver, 48000)
+ PARAM(Solver.ACCURACY, 1e-20)
+ MAINCLOCK(clk, 50000000)
- TTL_7400_NAND(n1,clk,clk)
+ TTL_7400_NAND(n1,clk,clk)
NETLIST_END()
@@ -27,27 +27,27 @@ NETLIST_END()
NETLIST_START(cap_delay)
- /*
- * delay circuit
- *
- */
+ /*
+ * delay circuit
+ *
+ */
- /* Standard stuff */
+ /* Standard stuff */
- SOLVER(Solver, P_FREQ)
- PARAM(Solver.ACCURACY, 1e-20)
+ SOLVER(Solver, P_FREQ)
+ PARAM(Solver.ACCURACY, 1e-20)
PARAM(Solver.DYNAMIC_TS, P_DTS)
PARAM(Solver.DYNAMIC_MIN_TIMESTEP, 1e-6)
- CLOCK(clk, 5000)
+ CLOCK(clk, 5000)
- TTL_7400_NAND(n1,clk,clk)
- CAP(C, 1e-6)
- NET_C(n1.Q, C.2)
- NET_C(GND, C.1)
- TTL_7400_NAND(n2,n1.Q, n1.Q)
+ TTL_7400_NAND(n1,clk,clk)
+ CAP(C, 1e-6)
+ NET_C(n1.Q, C.2)
+ NET_C(GND, C.1)
+ TTL_7400_NAND(n2,n1.Q, n1.Q)
- LOG(logclk, clk)
- LOG(logn1Q, C.2)
- LOG(logn2Q, n1.Q)
+ LOG(logclk, clk)
+ LOG(logn1Q, C.2)
+ LOG(logn2Q, n1.Q)
NETLIST_END()
diff --git a/src/lib/netlist/examples/cmos_inverter.cpp b/src/lib/netlist/examples/cmos_inverter.cpp
index e0936bfd3bc..02ea330cb77 100644
--- a/src/lib/netlist/examples/cmos_inverter.cpp
+++ b/src/lib/netlist/examples/cmos_inverter.cpp
@@ -10,19 +10,19 @@
#include "netlist/analog/nld_twoterm.h"
NETLIST_START(cmos_inverter)
- /* Standard stuff */
+ /* Standard stuff */
- SOLVER(Solver, 48000)
- PARAM(Solver.ACCURACY, 1e-7)
+ SOLVER(Solver, 48000)
+ PARAM(Solver.ACCURACY, 1e-7)
PARAM(Solver.NR_LOOPS, 5000)
PARAM(Solver.METHOD, "MAT_CR")
- ANALOG_INPUT(V5, 5)
+ ANALOG_INPUT(V5, 5)
VS(IN, 5)
PARAM(IN.FUNC, "T 5 *")
- MOSFET(P, "PMOS(VTO=-1.0 KP=2e-3 LAMBDA=2E-2)")
- MOSFET(M, "NMOS(VTO=1.0 KP=2e-3 LAMBDA=2E-2)")
+ MOSFET(P, "PMOS(VTO=-1.0 KP=2e-3 LAMBDA=2E-2)")
+ MOSFET(M, "NMOS(VTO=1.0 KP=2e-3 LAMBDA=2E-2)")
NET_C(P.S, V5)
NET_C(P.D, M.D)
@@ -36,7 +36,7 @@ NETLIST_START(cmos_inverter)
NET_C(M.D, C.1)
NET_C(M.S, C.2)
#endif
- LOG(log_G, M.G)
- LOG(log_D, M.D)
+ LOG(log_G, M.G)
+ LOG(log_D, M.D)
NETLIST_END()
diff --git a/src/lib/netlist/examples/cmos_inverter_clk.cpp b/src/lib/netlist/examples/cmos_inverter_clk.cpp
index 8b70c46e715..32dbb25a33b 100644
--- a/src/lib/netlist/examples/cmos_inverter_clk.cpp
+++ b/src/lib/netlist/examples/cmos_inverter_clk.cpp
@@ -12,19 +12,19 @@
#define USE_CLOCK (1)
NETLIST_START(cmos_inverter_clk)
- /* Standard stuff */
+ /* Standard stuff */
//SOLVER(Solver, 480000)
SOLVER(Solver, 1e5)
//SOLVER(Solver, 100000000000)
- PARAM(Solver.ACCURACY, 1e-6 )
+ PARAM(Solver.ACCURACY, 1e-6 )
PARAM(Solver.NR_LOOPS, 500000)
PARAM(Solver.DYNAMIC_TS, 1)
PARAM(Solver.DYNAMIC_LTE, 1e-5)
PARAM(Solver.DYNAMIC_MIN_TIMESTEP, 2e-9)
- ANALOG_INPUT(V5, 5)
+ ANALOG_INPUT(V5, 5)
-// CLOCK(clk, 0.5e6)
+// CLOCK(clk, 0.5e6)
#if (USE_CLOCK)
CLOCK(V, 5000)
@@ -35,8 +35,8 @@ NETLIST_START(cmos_inverter_clk)
PARAM(V.FUNC, "T * 5e6")
#endif
- MOSFET(P, "PMOS(VTO=-0.5 GAMMA=0.5 TOX=20n)")
- MOSFET(M, "NMOS(VTO=0.5 GAMMA=0.5 TOX=20n)")
+ MOSFET(P, "PMOS(VTO=-0.5 GAMMA=0.5 TOX=20n)")
+ MOSFET(M, "NMOS(VTO=0.5 GAMMA=0.5 TOX=20n)")
RES(RG, 1)
NET_C(P.S, V5)
@@ -57,8 +57,8 @@ NETLIST_START(cmos_inverter_clk)
NET_C(M.S, C.2)
#endif
#if 1
- LOG(log_G, M.G)
- LOG(log_D, M.D)
+ LOG(log_G, M.G)
+ LOG(log_D, M.D)
LOGD(log_X, RG.1, RG.2)
#endif
NETLIST_END()
diff --git a/src/lib/netlist/examples/congo_bongo.c b/src/lib/netlist/examples/congo_bongo.c
index 3ad52e7dced..9c5db529d6c 100644
--- a/src/lib/netlist/examples/congo_bongo.c
+++ b/src/lib/netlist/examples/congo_bongo.c
@@ -10,8 +10,8 @@
/* set to 1 to use optimizations increasing performance significantly */
-#define USE_OPTMIZATIONS 1
-#define USE_FRONTIERS 1
+#define USE_OPTMIZATIONS 1
+#define USE_FRONTIERS 1
/* ----------------------------------------------------------------------------
* Library section header START
@@ -19,7 +19,7 @@
#ifndef __PLIB_PREPROCESSOR__
-#define LM358_DIP(_name) \
+#define LM358_DIP(_name) \
NET_REGISTER_DEV_X(LM358_DIP, _name)
#define G501534_DIP(_name) \
@@ -391,8 +391,8 @@ NETLIST_START(G501534_DIP)
* 12: VCC
* 4: GND
* 1: IN
- * 3: OUT
- * 13: CV
+ * 3: OUT
+ * 13: CV
* 2: RDL - connected via Capacitor to ground
*/
diff --git a/src/lib/netlist/examples/cs.cpp b/src/lib/netlist/examples/cs.cpp
index 8229c5bc032..f9b9741e0ff 100644
--- a/src/lib/netlist/examples/cs.cpp
+++ b/src/lib/netlist/examples/cs.cpp
@@ -10,14 +10,14 @@
NETLIST_START(cs)
- SOLVER(Solver, 48000)
- PARAM(Solver.ACCURACY, 1e-12)
- PARAM(Solver.METHOD, "MAT_CR")
+ SOLVER(Solver, 48000)
+ PARAM(Solver.ACCURACY, 1e-12)
+ PARAM(Solver.METHOD, "MAT_CR")
/* Positive current flows into pin 1 of the current source
* Thus we observe a negative voltage on R1.1 !
*/
- CS(CS1, 1e-3)
+ CS(CS1, 1e-3)
RES(R1, 1000)
NET_C(CS1.1, R1.1)
diff --git a/src/lib/netlist/examples/diode.c b/src/lib/netlist/examples/diode.c
index 9a2196c6f24..b628a18af4a 100644
--- a/src/lib/netlist/examples/diode.c
+++ b/src/lib/netlist/examples/diode.c
@@ -7,25 +7,25 @@
#include "netlist/devices/net_lib.h"
NETLIST_START(diode)
- /* Standard stuff */
+ /* Standard stuff */
- CLOCK(clk, 1000) // 1000 Hz
- SOLVER(Solver, 48)
- ANALOG_INPUT(V5, 5)
+ CLOCK(clk, 1000) // 1000 Hz
+ SOLVER(Solver, 48)
+ ANALOG_INPUT(V5, 5)
//DIODE(D, "1N914")
- DIODE(D, "D(IS=1e-15)")
+ DIODE(D, "D(IS=1e-15)")
- RES(R, RES_K(10))
- RES(R1, RES_K(10))
+ RES(R, RES_K(10))
+ RES(R1, RES_K(10))
- NET_C(clk, D.K)
- NET_C(D.A, R.1)
- NET_C(R.2, V5)
- NET_C(R1.2, GND)
- NET_C(R.1, R1.1)
+ NET_C(clk, D.K)
+ NET_C(D.A, R.1)
+ NET_C(R.2, V5)
+ NET_C(R1.2, GND)
+ NET_C(R.1, R1.1)
- LOG(logB, clk)
- LOG(logC, D.A)
+ LOG(logB, clk)
+ LOG(logC, D.A)
NETLIST_END()
diff --git a/src/lib/netlist/examples/kidniki.c b/src/lib/netlist/examples/kidniki.c
index edbcf5ce203..b05a3b52d9f 100644
--- a/src/lib/netlist/examples/kidniki.c
+++ b/src/lib/netlist/examples/kidniki.c
@@ -67,7 +67,7 @@ NETLIST_START(dummy)
TTL_INPUT(I_BD0, 1)
//CLOCK(I_BD0, 5)
TTL_INPUT(I_CH0, 1)
- //CLOCK(I_CH0, 5 )
+ //CLOCK(I_CH0, 5 )
//TTL_INPUT(I_OH0, 1)
CLOCK(I_OH0, 5)
TTL_INPUT(I_SOUNDIC0, 1)
@@ -351,68 +351,68 @@ NETLIST_END()
NETLIST_START(opamp)
- /* Opamp model from
- *
- * http://www.ecircuitcenter.com/Circuits/opmodel1/opmodel1.htm
- *
- * Bandwidth 1Mhz
- *
- */
+ /* Opamp model from
+ *
+ * http://www.ecircuitcenter.com/Circuits/opmodel1/opmodel1.htm
+ *
+ * Bandwidth 1Mhz
+ *
+ */
- /* Terminal definitions for calling netlists */
+ /* Terminal definitions for calling netlists */
- ALIAS(PLUS, G1.IP) // Positive input
- ALIAS(MINUS, G1.IN) // Negative input
- ALIAS(OUT, EBUF.OP) // Opamp output ...
+ ALIAS(PLUS, G1.IP) // Positive input
+ ALIAS(MINUS, G1.IN) // Negative input
+ ALIAS(OUT, EBUF.OP) // Opamp output ...
- ALIAS(GND, EBUF.ON) // GND terminal
- ALIAS(VCC, DUMMY.I) // VCC terminal
- DUMMY_INPUT(DUMMY)
+ ALIAS(GND, EBUF.ON) // GND terminal
+ ALIAS(VCC, DUMMY.I) // VCC terminal
+ DUMMY_INPUT(DUMMY)
- /* The opamp model */
+ /* The opamp model */
- VCCS(G1)
- PARAM(G1.RI, RES_K(1000))
+ VCCS(G1)
+ PARAM(G1.RI, RES_K(1000))
#if 1
- PARAM(G1.G, 100) // typical OP-AMP amplification 100 * 1000 = 100000
- RES(RP1, 1000)
- CAP(CP1, 1.59e-5) // <== change to 1.59e-3 for 10Khz bandwidth
+ PARAM(G1.G, 100) // typical OP-AMP amplification 100 * 1000 = 100000
+ RES(RP1, 1000)
+ CAP(CP1, 1.59e-5) // <== change to 1.59e-3 for 10Khz bandwidth
#else
- PARAM(G1.G, 1) // typical OP-AMP amplification 100 * 1000 = 100000
- RES(RP1, 100000)
- CAP(CP1, 1.59e-7) // <== change to 1.59e-3 for 10Khz bandwidth
+ PARAM(G1.G, 1) // typical OP-AMP amplification 100 * 1000 = 100000
+ RES(RP1, 100000)
+ CAP(CP1, 1.59e-7) // <== change to 1.59e-3 for 10Khz bandwidth
#endif
- VCVS(EBUF)
- PARAM(EBUF.RO, 50)
- PARAM(EBUF.G, 1)
+ VCVS(EBUF)
+ PARAM(EBUF.RO, 50)
+ PARAM(EBUF.G, 1)
// PARAM(EBUF.RI, 1e20)
// NET_C(EBUF.ON, GND)
- NET_C(G1.ON, GND)
- NET_C(RP1.2, GND)
- NET_C(CP1.2, GND)
- NET_C(EBUF.IN, GND)
+ NET_C(G1.ON, GND)
+ NET_C(RP1.2, GND)
+ NET_C(CP1.2, GND)
+ NET_C(EBUF.IN, GND)
- NET_C(RP1.1, G1.OP)
- NET_C(CP1.1, RP1.1)
+ NET_C(RP1.1, G1.OP)
+ NET_C(CP1.1, RP1.1)
- DIODE(DP,"1N914")
- DIODE(DN,"1N914")
+ DIODE(DP,"1N914")
+ DIODE(DN,"1N914")
- NET_C(DP.K, VCC)
+ NET_C(DP.K, VCC)
#if 1
- NET_C(DP.A, DN.K, RP1.1)
+ NET_C(DP.A, DN.K, RP1.1)
#else
- RES(RDP, 1000)
- RES(RDN, 1000)
- NET_C(RDP.1, DP.A)
- NET_C(RDN.1, DN.K)
- NET_C(RDP.2, RDN.2, RP1.1)
+ RES(RDP, 1000)
+ RES(RDN, 1000)
+ NET_C(RDP.1, DP.A)
+ NET_C(RDN.1, DN.K)
+ NET_C(RDP.2, RDN.2, RP1.1)
#endif
- NET_C(DN.A, GND)
+ NET_C(DN.A, GND)
- NET_C(EBUF.IP, RP1.1)
+ NET_C(EBUF.IP, RP1.1)
NETLIST_END()
diff --git a/src/lib/netlist/examples/mm5837_noise.c b/src/lib/netlist/examples/mm5837_noise.c
index dff1966e1eb..c5237274af0 100644
--- a/src/lib/netlist/examples/mm5837_noise.c
+++ b/src/lib/netlist/examples/mm5837_noise.c
@@ -9,24 +9,24 @@
NETLIST_START(ne555_astable)
- /*
- * Astable ne555
- *
- */
+ /*
+ * Astable ne555
+ *
+ */
- /* Standard stuff */
+ /* Standard stuff */
- SOLVER(Solver, 48000)
+ SOLVER(Solver, 48000)
- ANALOG_INPUT(V12, 12) // 5V
+ ANALOG_INPUT(V12, 12) // 5V
- /* Wiring up the ne555 */
+ /* Wiring up the ne555 */
- // astable NE555, 1.13 ms period
+ // astable NE555, 1.13 ms period
- MM5837_DIP(NOISE)
+ MM5837_DIP(NOISE)
- RES(R, 10000)
+ RES(R, 10000)
NET_C(NOISE.1, NOISE.2, R.2, GND)
NET_C(NOISE.4, V12)
diff --git a/src/lib/netlist/examples/msx_mixer_stage.c b/src/lib/netlist/examples/msx_mixer_stage.c
index 445777eb9cf..413ad271e08 100644
--- a/src/lib/netlist/examples/msx_mixer_stage.c
+++ b/src/lib/netlist/examples/msx_mixer_stage.c
@@ -9,57 +9,57 @@
#include "netlist/devices/net_lib.h"
NETLIST_START(msx)
- /* The BJT is used as an amplifier. RESCHED_LOOPS must be relatively high to
- * allow Newton-Raphson to finish. */
+ /* The BJT is used as an amplifier. RESCHED_LOOPS must be relatively high to
+ * allow Newton-Raphson to finish. */
- CLOCK(clk, 1000) // 1000 Hz
- SOLVER(Solver, 48000)
- PARAM(Solver.ACCURACY, 1e-5)
- //PARAM(Solver.CONVERG, 0.3)
- PARAM(Solver.GS_LOOPS, 50)
+ CLOCK(clk, 1000) // 1000 Hz
+ SOLVER(Solver, 48000)
+ PARAM(Solver.ACCURACY, 1e-5)
+ //PARAM(Solver.CONVERG, 0.3)
+ PARAM(Solver.GS_LOOPS, 50)
- RES(RAY8910, 2345) // Max Voltage
+ RES(RAY8910, 2345) // Max Voltage
- ANALOG_INPUT(V5, 5)
- ANALOG_INPUT(V12, 12)
+ ANALOG_INPUT(V5, 5)
+ ANALOG_INPUT(V12, 12)
- ANALOG_INPUT(SOUND, 5)
- ANALOG_INPUT(SND, 5)
+ ANALOG_INPUT(SOUND, 5)
+ ANALOG_INPUT(SND, 5)
- NET_MODEL("ss9014 NPN(is=2.87599e-14 bf=377.5 vaf=123 ikf=1.1841 ise=4.7863e-15 ne=1.5 br=4.79 var=11.29 ikr=0.275423 isc=1.44544e-14 nc=1.5 rb=200 irb=1e-5 rbm=10 re=0.56 rc=5 cje=1.7205e-11 vje=0.6905907 mje=0.3193434 tf=5.89463e-10 cjc=6.2956p vjc=0.4164212 mjc=0.2559546 xcjc=0.451391 xtb=1.8881 eg=1.2415 xti=3 fc=0.5 Vceo=45 Icrating=0.1 mfg=Fairchild)")
+ NET_MODEL("ss9014 NPN(is=2.87599e-14 bf=377.5 vaf=123 ikf=1.1841 ise=4.7863e-15 ne=1.5 br=4.79 var=11.29 ikr=0.275423 isc=1.44544e-14 nc=1.5 rb=200 irb=1e-5 rbm=10 re=0.56 rc=5 cje=1.7205e-11 vje=0.6905907 mje=0.3193434 tf=5.89463e-10 cjc=6.2956p vjc=0.4164212 mjc=0.2559546 xcjc=0.451391 xtb=1.8881 eg=1.2415 xti=3 fc=0.5 Vceo=45 Icrating=0.1 mfg=Fairchild)")
- RES(R24, RES_K(51))
- RES(R23, RES_K(5))
- RES(R21, RES_K(51))
- RES(R20, RES_K(1))
- RES(R9, RES_K(10))
- RES(R8, 330)
+ RES(R24, RES_K(51))
+ RES(R23, RES_K(5))
+ RES(R21, RES_K(51))
+ RES(R20, RES_K(1))
+ RES(R9, RES_K(10))
+ RES(R8, 330)
- CAP(C55, CAP_U(5)) // Guessed
+ CAP(C55, CAP_U(5)) // Guessed
- //NET_C(RAY8910.1, SND)
- NET_C(RAY8910.1, clk)
+ //NET_C(RAY8910.1, SND)
+ NET_C(RAY8910.1, clk)
- //NET_C(C55.1, SOUND)
- NET_C(C55.1, V5)
- NET_C(C55.2, R24.1)
- NET_C(R24.2, R23.2)
- NET_C(R23.1, RAY8910.2)
- NET_C(R23.1, R20.1)
- NET_C(R20.2, GND)
+ //NET_C(C55.1, SOUND)
+ NET_C(C55.1, V5)
+ NET_C(C55.2, R24.1)
+ NET_C(R24.2, R23.2)
+ NET_C(R23.1, RAY8910.2)
+ NET_C(R23.1, R20.1)
+ NET_C(R20.2, GND)
- NET_C(R21.1, V5)
- NET_C(R21.2, R23.2)
+ NET_C(R21.1, V5)
+ NET_C(R21.2, R23.2)
- QBJT_EB(T2, "ss9014")
+ QBJT_EB(T2, "ss9014")
- NET_C(R9.1, V12)
- NET_C(R9.2, T2.C)
- NET_C(R21.2, T2.B)
- NET_C(R8.1, T2.E)
- NET_C(R8.2, GND)
+ NET_C(R9.1, V12)
+ NET_C(R9.2, T2.C)
+ NET_C(R21.2, T2.B)
+ NET_C(R8.1, T2.E)
+ NET_C(R8.2, GND)
- //LOG(logB, T2.B)
- LOG(logC, T2.C)
+ //LOG(logB, T2.B)
+ LOG(logC, T2.C)
NETLIST_END()
diff --git a/src/lib/netlist/examples/ne555_astable.c b/src/lib/netlist/examples/ne555_astable.c
index 0348d3ae4d3..f71076b4e96 100644
--- a/src/lib/netlist/examples/ne555_astable.c
+++ b/src/lib/netlist/examples/ne555_astable.c
@@ -11,43 +11,43 @@
NETLIST_START(ne555_astable)
- /*
- * Astable ne555
- *
- */
+ /*
+ * Astable ne555
+ *
+ */
- /* Standard stuff */
+ /* Standard stuff */
- SOLVER(Solver, 48000)
+ SOLVER(Solver, 48000)
- ANALOG_INPUT(V5, 5) // 5V
+ ANALOG_INPUT(V5, 5) // 5V
- /* Wiring up the ne555 */
+ /* Wiring up the ne555 */
- // astable NE555, 1.13 ms period
+ // astable NE555, 1.13 ms period
- RES(RA, 5000)
- RES(RB, 3000)
- CAP(C, 0.15e-6)
- NE555(555)
+ RES(RA, 5000)
+ RES(RB, 3000)
+ CAP(C, 0.15e-6)
+ NE555(555)
- NET_C(GND, 555.GND)
- NET_C(V5, 555.VCC)
- NET_C(V5, 555.RESET)
+ NET_C(GND, 555.GND)
+ NET_C(V5, 555.VCC)
+ NET_C(V5, 555.RESET)
- NET_C(RA.1, 555.VCC)
- NET_C(RA.2, 555.DISCH)
+ NET_C(RA.1, 555.VCC)
+ NET_C(RA.2, 555.DISCH)
- NET_C(RB.1, 555.DISCH)
- NET_C(RB.2, 555.TRIG)
+ NET_C(RB.1, 555.DISCH)
+ NET_C(RB.2, 555.TRIG)
- NET_C(RB.2, 555.THRESH)
+ NET_C(RB.2, 555.THRESH)
- NET_C(555.TRIG, C.1)
- NET_C(C.2, GND)
+ NET_C(555.TRIG, C.1)
+ NET_C(C.2, GND)
- LOG(log2, C.1)
- LOG(log3, 555.OUT)
+ LOG(log2, C.1)
+ LOG(log3, 555.OUT)
NETLIST_END()
//! [ne555_example]
diff --git a/src/lib/netlist/examples/nmos_fet.cpp b/src/lib/netlist/examples/nmos_fet.cpp
index 53c6b4a6fc9..5bec1a97411 100644
--- a/src/lib/netlist/examples/nmos_fet.cpp
+++ b/src/lib/netlist/examples/nmos_fet.cpp
@@ -10,37 +10,37 @@
#include "netlist/analog/nld_twoterm.h"
NETLIST_START(nmos)
- /* Standard stuff */
+ /* Standard stuff */
- CLOCK(clk, 100) // 100 Hz
- SOLVER(Solver, 48000)
- PARAM(Solver.ACCURACY, 1e-9)
+ CLOCK(clk, 100) // 100 Hz
+ SOLVER(Solver, 48000)
+ PARAM(Solver.ACCURACY, 1e-9)
PARAM(Solver.NR_LOOPS, 50000)
PARAM(Solver.DYNAMIC_TS, 1)
PARAM(Solver.DYNAMIC_MIN_TIMESTEP, 1e-9)
- ANALOG_INPUT(V5, 5)
- ANALOG_INPUT(V3, 3.5)
+ ANALOG_INPUT(V5, 5)
+ ANALOG_INPUT(V3, 3.5)
- /* NMOS - example */
+ /* NMOS - example */
NET_MODEL("MM NMOS(VTO=1.0 KP=2e-3 LAMBDA=2E-2)")
- MOSFET(M, "MM")
+ MOSFET(M, "MM")
- RES(RB, 1000)
- RES(RC, 10000)
+ RES(RB, 1000)
+ RES(RC, 10000)
- NET_C(RC.1, V5)
- NET_C(RC.2, M.D)
- NET_C(RB.1, clk)
- //NET_C(RB.1, V3)
- NET_C(RB.2, M.G)
- NET_C(M.S, GND)
+ NET_C(RC.1, V5)
+ NET_C(RC.2, M.D)
+ NET_C(RB.1, clk)
+ //NET_C(RB.1, V3)
+ NET_C(RB.2, M.G)
+ NET_C(M.S, GND)
- // put some load on M.D
+ // put some load on M.D
- RES(RCE, 150000)
- NET_C(RCE.1, M.D)
- NET_C(RCE.2, GND)
+ RES(RCE, 150000)
+ NET_C(RCE.1, M.D)
+ NET_C(RCE.2, GND)
// capacitance over G - S
@@ -48,7 +48,7 @@ NETLIST_START(nmos)
NET_C(M.D, C.1)
NET_C(M.S, C.2)
- LOG(log_G, M.G)
- LOG(log_D, M.D)
+ LOG(log_G, M.G)
+ LOG(log_D, M.D)
NETLIST_END()
diff --git a/src/lib/netlist/examples/norton_opamp.c b/src/lib/netlist/examples/norton_opamp.c
index 8e077a91df2..a6cf52ce152 100644
--- a/src/lib/netlist/examples/norton_opamp.c
+++ b/src/lib/netlist/examples/norton_opamp.c
@@ -8,119 +8,119 @@
NETLIST_START(main)
- /* Standard stuff */
-
- CLOCK(clk, 10000) // 1000 Hz
- SOLVER(Solver, 48000)
- ANALOG_INPUT(V5, 5)
- PARAM(Solver.ACCURACY, 1e-6)
- PARAM(Solver.DYNAMIC_TS, 0)
- PARAM(Solver.SOR_FACTOR, 1.0)
- //PARAM(Solver.CONVERG, 1.0)
- PARAM(Solver.GS_LOOPS, 5)
-
- SUBMODEL(op1, opamp_fast)
- /* Wired as non - inverting amplifier like in LM3900 datasheet */
-
- RES(R1, 25000)
- RES(R2, 100000)
- RES(R3, 200000)
- CAP(C1, CAP_U(0.05))
-
- NET_C(clk, C1.1)
- NET_C(C1.2, R1.1)
-
- NET_C(op1.VM, GND)
- NET_C(op1.VP, V5 )
- NET_C(op1.PLUS, R1.2, R3.1)
- NET_C(R3.2, V5)
- //NET_C(R3.2, GND)
- NET_C(op1.MINUS, R2.2)
- NET_C(op1.OUT, R2.1)
-
- RES(RL, 10000)
- NET_C(RL.2, GND)
- NET_C(RL.1, op1.OUT)
-
- LOG(logX, op1.OUT)
- LOG(logY, clk)
+ /* Standard stuff */
+
+ CLOCK(clk, 10000) // 1000 Hz
+ SOLVER(Solver, 48000)
+ ANALOG_INPUT(V5, 5)
+ PARAM(Solver.ACCURACY, 1e-6)
+ PARAM(Solver.DYNAMIC_TS, 0)
+ PARAM(Solver.SOR_FACTOR, 1.0)
+ //PARAM(Solver.CONVERG, 1.0)
+ PARAM(Solver.GS_LOOPS, 5)
+
+ SUBMODEL(op1, opamp_fast)
+ /* Wired as non - inverting amplifier like in LM3900 datasheet */
+
+ RES(R1, 25000)
+ RES(R2, 100000)
+ RES(R3, 200000)
+ CAP(C1, CAP_U(0.05))
+
+ NET_C(clk, C1.1)
+ NET_C(C1.2, R1.1)
+
+ NET_C(op1.VM, GND)
+ NET_C(op1.VP, V5 )
+ NET_C(op1.PLUS, R1.2, R3.1)
+ NET_C(R3.2, V5)
+ //NET_C(R3.2, GND)
+ NET_C(op1.MINUS, R2.2)
+ NET_C(op1.OUT, R2.1)
+
+ RES(RL, 10000)
+ NET_C(RL.2, GND)
+ NET_C(RL.1, op1.OUT)
+
+ LOG(logX, op1.OUT)
+ LOG(logY, clk)
NETLIST_END()
NETLIST_START(opamp)
- /* Opamp model from
- *
- * http://www.ecircuitcenter.com/Circuits/opmodel1/opmodel1.htm
- *
- * Bandwidth 10Mhz
- *
- */
-
- /* Terminal definitions for calling netlists */
-
- ALIAS(PLUS, G1.IP) // Positive input
- ALIAS(MINUS, G2.IN) // Negative input
- ALIAS(OUT, EBUF.OP) // Opamp output ...
- ALIAS(VM, EBUF.ON) // V- terminal
- ALIAS(VP, DUMMY.I) // V+ terminal
-
- DUMMY_INPUT(DUMMY)
-
- /* The opamp model */
-
- CCCS(G1)
- CCCS(G2)
- //PARAM(G1.G, 100) // typical OP-AMP amplification 100 * 1000 = 100000
- PARAM(G1.G, 1000000) // typical OP-AMP amplification 100 * 1000 = 100000
- PARAM(G2.G, 1000000) // typical OP-AMP amplification 100 * 1000 = 100000
- RES(RP1, 1000)
- CAP(CP1, 1.59e-6) // <== change to 1.59e-3 for 10Khz bandwidth
- VCVS(EBUF)
- PARAM(EBUF.RO, 50)
- PARAM(EBUF.G, 1)
+ /* Opamp model from
+ *
+ * http://www.ecircuitcenter.com/Circuits/opmodel1/opmodel1.htm
+ *
+ * Bandwidth 10Mhz
+ *
+ */
+
+ /* Terminal definitions for calling netlists */
+
+ ALIAS(PLUS, G1.IP) // Positive input
+ ALIAS(MINUS, G2.IN) // Negative input
+ ALIAS(OUT, EBUF.OP) // Opamp output ...
+ ALIAS(VM, EBUF.ON) // V- terminal
+ ALIAS(VP, DUMMY.I) // V+ terminal
+
+ DUMMY_INPUT(DUMMY)
+
+ /* The opamp model */
+
+ CCCS(G1)
+ CCCS(G2)
+ //PARAM(G1.G, 100) // typical OP-AMP amplification 100 * 1000 = 100000
+ PARAM(G1.G, 1000000) // typical OP-AMP amplification 100 * 1000 = 100000
+ PARAM(G2.G, 1000000) // typical OP-AMP amplification 100 * 1000 = 100000
+ RES(RP1, 1000)
+ CAP(CP1, 1.59e-6) // <== change to 1.59e-3 for 10Khz bandwidth
+ VCVS(EBUF)
+ PARAM(EBUF.RO, 50)
+ PARAM(EBUF.G, 1)
// NET_C(EBUF.ON, GND)
- NET_C(G1.ON, GND)
- NET_C(G2.ON, GND)
- NET_C(RP1.2, GND)
- NET_C(CP1.2, GND)
- NET_C(EBUF.IN, GND)
+ NET_C(G1.ON, GND)
+ NET_C(G2.ON, GND)
+ NET_C(RP1.2, GND)
+ NET_C(CP1.2, GND)
+ NET_C(EBUF.IN, GND)
- NET_C(G1.IN, G2.IP, GND)
+ NET_C(G1.IN, G2.IP, GND)
- NET_C(RP1.1, G1.OP)
- NET_C(RP1.1, G2.OP)
- NET_C(CP1.1, RP1.1)
- NET_C(EBUF.IP, RP1.1)
+ NET_C(RP1.1, G1.OP)
+ NET_C(RP1.1, G2.OP)
+ NET_C(CP1.1, RP1.1)
+ NET_C(EBUF.IP, RP1.1)
NETLIST_END()
NETLIST_START(opamp_fast)
- /*
- * Fast norton opamp model without bandwidth
- */
+ /*
+ * Fast norton opamp model without bandwidth
+ */
- /* Terminal definitions for calling netlists */
+ /* Terminal definitions for calling netlists */
- ALIAS(PLUS, R1.1) // Positive input
- ALIAS(MINUS, R2.1) // Negative input
- ALIAS(OUT, G1.OP) // Opamp output ...
- ALIAS(VM, G1.ON) // V- terminal
- ALIAS(VP, DUMMY.I) // V+ terminal
+ ALIAS(PLUS, R1.1) // Positive input
+ ALIAS(MINUS, R2.1) // Negative input
+ ALIAS(OUT, G1.OP) // Opamp output ...
+ ALIAS(VM, G1.ON) // V- terminal
+ ALIAS(VP, DUMMY.I) // V+ terminal
- DUMMY_INPUT(DUMMY)
+ DUMMY_INPUT(DUMMY)
- /* The opamp model */
+ /* The opamp model */
- RES(R1, 1)
- RES(R2, 1)
- NET_C(R1.1, G1.IP)
- NET_C(R2.1, G1.IN)
- NET_C(R1.2, R2.2, G1.ON)
- VCVS(G1)
- PARAM(G1.G, 1000000)
- PARAM(G1.RO, RES_K(8))
+ RES(R1, 1)
+ RES(R2, 1)
+ NET_C(R1.1, G1.IP)
+ NET_C(R2.1, G1.IN)
+ NET_C(R1.2, R2.2, G1.ON)
+ VCVS(G1)
+ PARAM(G1.G, 1000000)
+ PARAM(G1.RO, RES_K(8))
NETLIST_END()
diff --git a/src/lib/netlist/examples/opamp.c b/src/lib/netlist/examples/opamp.c
index b13d92dab67..b3730b29b51 100644
--- a/src/lib/netlist/examples/opamp.c
+++ b/src/lib/netlist/examples/opamp.c
@@ -10,91 +10,91 @@
NETLIST_START(main)
- /* Standard stuff */
+ /* Standard stuff */
- CLOCK(clk, 1000) // 1000 Hz
- SOLVER(Solver, 480000)
- PARAM(Solver.ACCURACY, 1e-10)
- PARAM(Solver.NR_LOOPS, 30000 )
- //PARAM(Solver.CONVERG, 1.0)
- PARAM(Solver.GS_LOOPS, 30)
+ CLOCK(clk, 1000) // 1000 Hz
+ SOLVER(Solver, 480000)
+ PARAM(Solver.ACCURACY, 1e-10)
+ PARAM(Solver.NR_LOOPS, 30000 )
+ //PARAM(Solver.CONVERG, 1.0)
+ PARAM(Solver.GS_LOOPS, 30)
- // Tie up +5 to opamps thought it's not currently needed
- // Stay compatible
- ANALOG_INPUT(V5, 5)
- NET_C(op.VCC, V5)
- NET_C(op1.VCC, V5)
+ // Tie up +5 to opamps thought it's not currently needed
+ // Stay compatible
+ ANALOG_INPUT(V5, 5)
+ NET_C(op.VCC, V5)
+ NET_C(op1.VCC, V5)
- /* Opamp wired as impedance changer */
- SUBMODEL(opamp, op)
+ /* Opamp wired as impedance changer */
+ SUBMODEL(opamp, op)
- NET_C(op.GND, GND)
- NET_C(op.PLUS, clk)
- NET_C(op.MINUS, op.OUT)
+ NET_C(op.GND, GND)
+ NET_C(op.PLUS, clk)
+ NET_C(op.MINUS, op.OUT)
- SUBMODEL(opamp, op1)
- /* Wired as inverting amplifier connected to output of first opamp */
+ SUBMODEL(opamp, op1)
+ /* Wired as inverting amplifier connected to output of first opamp */
- RES(R1, 100000)
- RES(R2, 200000)
+ RES(R1, 100000)
+ RES(R2, 200000)
- NET_C(op1.GND, GND)
- NET_C(op1.PLUS, GND)
- NET_C(op1.MINUS, R2.2)
- NET_C(op1.MINUS, R1.2)
+ NET_C(op1.GND, GND)
+ NET_C(op1.PLUS, GND)
+ NET_C(op1.MINUS, R2.2)
+ NET_C(op1.MINUS, R1.2)
- NET_C(op.OUT, R1.1)
- NET_C(op1.OUT, R2.1)
+ NET_C(op.OUT, R1.1)
+ NET_C(op1.OUT, R2.1)
- RES(RL, 1000)
- NET_C(RL.2, GND)
- NET_C(RL.1, op1.OUT)
+ RES(RL, 1000)
+ NET_C(RL.2, GND)
+ NET_C(RL.1, op1.OUT)
- LOG(log_X, op1.OUT)
- LOG(log_Y, clk)
+ LOG(log_X, op1.OUT)
+ LOG(log_Y, clk)
NETLIST_END()
NETLIST_START(opamp)
- /* Opamp model from
- *
- * http://www.ecircuitcenter.com/Circuits/opmodel1/opmodel1.htm
- *
- * Bandwidth 10Mhz
- *
- */
+ /* Opamp model from
+ *
+ * http://www.ecircuitcenter.com/Circuits/opmodel1/opmodel1.htm
+ *
+ * Bandwidth 10Mhz
+ *
+ */
- /* Terminal definitions for calling netlists */
+ /* Terminal definitions for calling netlists */
- ALIAS(PLUS, G1.IP) // Positive input
- ALIAS(MINUS, G1.IN) // Negative input
- ALIAS(OUT, EBUF.OP) // Opamp output ...
+ ALIAS(PLUS, G1.IP) // Positive input
+ ALIAS(MINUS, G1.IN) // Negative input
+ ALIAS(OUT, EBUF.OP) // Opamp output ...
- ALIAS(GND, EBUF.ON) // GND terminal
- ALIAS(VCC, DUMMY.I) // VCC terminal
- DUMMY_INPUT(DUMMY)
+ ALIAS(GND, EBUF.ON) // GND terminal
+ ALIAS(VCC, DUMMY.I) // VCC terminal
+ DUMMY_INPUT(DUMMY)
- /* The opamp model */
+ /* The opamp model */
- LVCCS(G1)
- PARAM(G1.G, 0.0021)
+ LVCCS(G1)
+ PARAM(G1.G, 0.0021)
PARAM(G1.CURLIM, 0.002)
- RES(RP1, 1e7)
- CAP(CP1, 0.00333e-6)
- VCVS(EBUF)
- PARAM(EBUF.RO, 50)
- PARAM(EBUF.G, 1)
+ RES(RP1, 1e7)
+ CAP(CP1, 0.00333e-6)
+ VCVS(EBUF)
+ PARAM(EBUF.RO, 50)
+ PARAM(EBUF.G, 1)
// NET_C(EBUF.ON, GND)
- NET_C(G1.ON, GND)
- NET_C(RP1.2, GND)
- NET_C(CP1.2, GND)
- NET_C(EBUF.IN, GND)
+ NET_C(G1.ON, GND)
+ NET_C(RP1.2, GND)
+ NET_C(CP1.2, GND)
+ NET_C(EBUF.IN, GND)
- NET_C(RP1.1, G1.OP)
- NET_C(CP1.1, RP1.1)
- NET_C(EBUF.IP, RP1.1)
+ NET_C(RP1.1, G1.OP)
+ NET_C(CP1.1, RP1.1)
+ NET_C(EBUF.IP, RP1.1)
NETLIST_END()
@@ -110,12 +110,12 @@ NETLIST_START(opamp_mod)
*
* Simple Opamp Model Calculation
*
- * First Pole Frequency 5 Hz
- * Unity Gain Frequency 11,000 Hz
- * RP 100,000 Ohm
- * DC Gain / Aol 2200
- * CP 0.318 uF
- * KG 0.022
+ * First Pole Frequency 5 Hz
+ * Unity Gain Frequency 11,000 Hz
+ * RP 100,000 Ohm
+ * DC Gain / Aol 2200
+ * CP 0.318 uF
+ * KG 0.022
*
*/
diff --git a/src/lib/netlist/examples/opamp_amplification_curve.cpp b/src/lib/netlist/examples/opamp_amplification_curve.cpp
index e1665244b0e..ed5d1709985 100644
--- a/src/lib/netlist/examples/opamp_amplification_curve.cpp
+++ b/src/lib/netlist/examples/opamp_amplification_curve.cpp
@@ -22,14 +22,14 @@
NETLIST_START(main)
- /* Standard stuff */
-
- //VARCLOCK(clk, "0.5 / pow(10, 1 + T * 4)")
- //CLOCK(clk, 1000)
- SOLVER(Solver, 48000)
- PARAM(Solver.ACCURACY, 1e-7)
- PARAM(Solver.NR_LOOPS, 300)
- PARAM(Solver.DYNAMIC_TS, 1)
+ /* Standard stuff */
+
+ //VARCLOCK(clk, "0.5 / pow(10, 1 + T * 4)")
+ //CLOCK(clk, 1000)
+ SOLVER(Solver, 48000)
+ PARAM(Solver.ACCURACY, 1e-7)
+ PARAM(Solver.NR_LOOPS, 300)
+ PARAM(Solver.DYNAMIC_TS, 1)
PARAM(Solver.DYNAMIC_MIN_TIMESTEP, 1e-7)
VS(vs, 0)
@@ -59,36 +59,36 @@ NETLIST_START(main)
PARAM(vs.R, 0.001)
ALIAS(clk, vs.1)
NET_C(vs.2, GND)
- ANALOG_INPUT(V12, 12)
- ANALOG_INPUT(VM12, -12)
+ ANALOG_INPUT(V12, 12)
+ ANALOG_INPUT(VM12, -12)
- OPAMP(op, OPAMP_TEST)
+ OPAMP(op, OPAMP_TEST)
- NET_C(op.GND, VM12)
- NET_C(op.VCC, V12)
+ NET_C(op.GND, VM12)
+ NET_C(op.VCC, V12)
- /* Opamp B wired as inverting amplifier connected to output of first opamp */
+ /* Opamp B wired as inverting amplifier connected to output of first opamp */
- RES(R1, 100)
- RES(RP, 100)
- RES(R2, 10000000)
+ RES(R1, 100)
+ RES(RP, 100)
+ RES(R2, 10000000)
- NET_C(op.PLUS, RP.1)
+ NET_C(op.PLUS, RP.1)
NET_C(RP.2, GND)
- NET_C(op.MINUS, R2.2)
- NET_C(op.MINUS, R1.2)
+ NET_C(op.MINUS, R2.2)
+ NET_C(op.MINUS, R1.2)
- NET_C(clk, R1.1)
- NET_C(op.OUT, R2.1)
+ NET_C(clk, R1.1)
+ NET_C(op.OUT, R2.1)
- RES(RL, 2000)
- NET_C(RL.2, GND)
- NET_C(RL.1, op.OUT)
+ RES(RL, 2000)
+ NET_C(RL.2, GND)
+ NET_C(RL.1, op.OUT)
AFUNC(f, 1, "A0 * 1000")
NET_C(f.A0, op.OUT)
#if 1
- LOG(log_Y, R1.1)
- LOG(log_Z, f)
+ LOG(log_Y, R1.1)
+ LOG(log_Z, f)
#endif
NETLIST_END()
diff --git a/src/lib/netlist/examples/rc.c b/src/lib/netlist/examples/rc.c
index 1850da313da..140440011b9 100644
--- a/src/lib/netlist/examples/rc.c
+++ b/src/lib/netlist/examples/rc.c
@@ -7,25 +7,25 @@
NETLIST_START(rc)
- /*
- * delay circuit
- *
- */
+ /*
+ * delay circuit
+ *
+ */
- /* Standard stuff */
+ /* Standard stuff */
- SOLVER(Solver, 48000)
- PARAM(Solver.ACCURACY, 1e-6)
- CLOCK(clk, 20000)
+ SOLVER(Solver, 48000)
+ PARAM(Solver.ACCURACY, 1e-6)
+ CLOCK(clk, 20000)
- CAP(C1, 0.022e-6)
- RES(R1, 10000)
- RES(R2, 20000)
+ CAP(C1, 0.022e-6)
+ RES(R1, 10000)
+ RES(R2, 20000)
- NET_C(clk, R2.1)
- NET_C(R2.2, R1.1, C1.1)
- NET_C(C1.2, R1.2, GND)
+ NET_C(clk, R2.1)
+ NET_C(R2.2, R1.1, C1.1)
+ NET_C(C1.2, R1.2, GND)
- LOG(tt, C1.1)
+ LOG(tt, C1.1)
NETLIST_END()
diff --git a/src/lib/netlist/examples/rl.c b/src/lib/netlist/examples/rl.c
index 2848348c440..b9f4e4e64c0 100644
--- a/src/lib/netlist/examples/rl.c
+++ b/src/lib/netlist/examples/rl.c
@@ -7,26 +7,26 @@
NETLIST_START(lr)
- /*
- * delay circuit
- *
- */
+ /*
+ * delay circuit
+ *
+ */
- /* Standard stuff */
+ /* Standard stuff */
- SOLVER(Solver, 48000)
- PARAM(Solver.ACCURACY, 1e-6)
- CLOCK(clk, 50)
+ SOLVER(Solver, 48000)
+ PARAM(Solver.ACCURACY, 1e-6)
+ CLOCK(clk, 50)
PARAM(Solver.METHOD, "MAT_CR")
- IND(L1, 10)
- RES(R1, 10000)
-
- NET_C(clk, L1.1)
- NET_C(L1.2, R1.1)
- NET_C(R1.2, GND)
+ IND(L1, 10)
+ RES(R1, 10000)
- //LOG(log_1, R1.1)
- //LOG(log_2, clk)
+ NET_C(clk, L1.1)
+ NET_C(L1.2, R1.1)
+ NET_C(R1.2, GND)
+
+ //LOG(log_1, R1.1)
+ //LOG(log_2, clk)
NETLIST_END()
diff --git a/src/lib/netlist/examples/sn74ls629_osc.c b/src/lib/netlist/examples/sn74ls629_osc.c
index f40c464f55c..3f797d9474d 100644
--- a/src/lib/netlist/examples/sn74ls629_osc.c
+++ b/src/lib/netlist/examples/sn74ls629_osc.c
@@ -9,26 +9,26 @@
NETLIST_START(ls629)
- /*
- * Astable ne555
- *
- */
+ /*
+ * Astable ne555
+ *
+ */
- /* Standard stuff */
+ /* Standard stuff */
- SOLVER(Solver, 48000)
+ SOLVER(Solver, 48000)
- ANALOG_INPUT(V5, 5) // 5V
- ANALOG_INPUT(VF, 2.5) // 5V
- ANALOG_INPUT(VR, 5) // 5V
+ ANALOG_INPUT(V5, 5) // 5V
+ ANALOG_INPUT(VF, 2.5) // 5V
+ ANALOG_INPUT(VR, 5) // 5V
- SN74LS629(OSC, 0.022e-6)
+ SN74LS629(OSC, 0.022e-6)
- NET_C(GND, OSC.GND)
- NET_C(VR, OSC.RNG)
- NET_C(VF, OSC.FC)
- NET_C(GND, OSC.ENQ)
+ NET_C(GND, OSC.GND)
+ NET_C(VR, OSC.RNG)
+ NET_C(VF, OSC.FC)
+ NET_C(GND, OSC.ENQ)
- LOG(log2, OSC.Y)
+ LOG(log2, OSC.Y)
NETLIST_END()
diff --git a/src/lib/netlist/examples/test.c b/src/lib/netlist/examples/test.c
index 9a75dd3ad91..bee32494710 100644
--- a/src/lib/netlist/examples/test.c
+++ b/src/lib/netlist/examples/test.c
@@ -10,78 +10,78 @@
#include "netlist/devices/net_lib.h"
NETLIST_START(bjt)
- /* Standard stuff */
-
- CLOCK(clk, 1000) // 1000 Hz
- SOLVER(Solver, 48000)
-
- ANALOG_INPUT(V3, 3)
- ANALOG_INPUT(STOPG, 0)
- ALIAS(SRSTQ, RYf.2)
- ALIAS(SRST, RYc.2)
- NET_C(antenna, GND)
- ALIAS(runQ, Q1.C)
-
- TTL_7404_INVERT(e4d, STOPG)
-
- RES(RYf, 50) // output impedance
- RES(RYc, 50) // output impedance
-
- TTL_7404_INVERT(c9f, RYc.2)
- TTL_7404_INVERT(c9c, RYf.2)
- NET_C(c9f.Q, RYf.1)
- NET_C(c9c.Q, RYc.1)
-
- SWITCH2(coinsw, RYc.2, RYf.2)
-
- NET_C(coinsw.Q, GND)
-
- /* Antenna circuit */
- /* Also has a diode to clamp negative voltages - omitted here */
- NETDEV_QNPN(Q3, BC237B)
- ALIAS(antenna, Q3.B)
- NET_C(GND, Q3.E)
- RES(RX5, 100)
- CAP(CX1, 100)
- NET_C(RX5.1, CX1.1)
- NET_C(RX5.1, Q3.C)
- NET_C(RX5.2, GND)
- NET_C(CX1.2, GND)
- NETDEV_QNPN(Q1, BC237B)
- NET_C(Q1.B, RX5.1)
- NET_C(Q1.E, GND)
-
- DIODE(D3, 1N914)
- NET_C(D3.A, Q1.C)
- NET_C(D3.K, SRSTQ)
-
- DIODE(D2, 1N914)
- RES(RX4, 220)
- NET_C(D2.K, e4d.Q)
- NET_C(D2.A, RX4.1)
- NET_C(RX4.2, Q3.C)
-
- RES(RX1, 100)
- RES(RX2, 100)
- RES(RX3, 330)
- CAP(CX2, CAP_U(0.1))
-
- NET_C(RX3.2, D3.A)
- NET_C(RX3.1, RX1.2)
- NET_C(RX1.1, V3)
-
- NET_C(RX1.1, CX2.1)
- NET_C(RX1.2, CX2.2)
-
- NETDEV_QPNP(Q2, BC556B)
- NET_C(Q2.E, V3)
- NET_C(Q2.B, RX1.2)
- NET_C(Q2.C, RX2.2)
-
- NET_C(RX2.1, D2.A)
-
-
- //LOG(logB, Q1.B)
- //LOG(logC, Q1.C)
+ /* Standard stuff */
+
+ CLOCK(clk, 1000) // 1000 Hz
+ SOLVER(Solver, 48000)
+
+ ANALOG_INPUT(V3, 3)
+ ANALOG_INPUT(STOPG, 0)
+ ALIAS(SRSTQ, RYf.2)
+ ALIAS(SRST, RYc.2)
+ NET_C(antenna, GND)
+ ALIAS(runQ, Q1.C)
+
+ TTL_7404_INVERT(e4d, STOPG)
+
+ RES(RYf, 50) // output impedance
+ RES(RYc, 50) // output impedance
+
+ TTL_7404_INVERT(c9f, RYc.2)
+ TTL_7404_INVERT(c9c, RYf.2)
+ NET_C(c9f.Q, RYf.1)
+ NET_C(c9c.Q, RYc.1)
+
+ SWITCH2(coinsw, RYc.2, RYf.2)
+
+ NET_C(coinsw.Q, GND)
+
+ /* Antenna circuit */
+ /* Also has a diode to clamp negative voltages - omitted here */
+ NETDEV_QNPN(Q3, BC237B)
+ ALIAS(antenna, Q3.B)
+ NET_C(GND, Q3.E)
+ RES(RX5, 100)
+ CAP(CX1, 100)
+ NET_C(RX5.1, CX1.1)
+ NET_C(RX5.1, Q3.C)
+ NET_C(RX5.2, GND)
+ NET_C(CX1.2, GND)
+ NETDEV_QNPN(Q1, BC237B)
+ NET_C(Q1.B, RX5.1)
+ NET_C(Q1.E, GND)
+
+ DIODE(D3, 1N914)
+ NET_C(D3.A, Q1.C)
+ NET_C(D3.K, SRSTQ)
+
+ DIODE(D2, 1N914)
+ RES(RX4, 220)
+ NET_C(D2.K, e4d.Q)
+ NET_C(D2.A, RX4.1)
+ NET_C(RX4.2, Q3.C)
+
+ RES(RX1, 100)
+ RES(RX2, 100)
+ RES(RX3, 330)
+ CAP(CX2, CAP_U(0.1))
+
+ NET_C(RX3.2, D3.A)
+ NET_C(RX3.1, RX1.2)
+ NET_C(RX1.1, V3)
+
+ NET_C(RX1.1, CX2.1)
+ NET_C(RX1.2, CX2.2)
+
+ NETDEV_QPNP(Q2, BC556B)
+ NET_C(Q2.E, V3)
+ NET_C(Q2.B, RX1.2)
+ NET_C(Q2.C, RX2.2)
+
+ NET_C(RX2.1, D2.A)
+
+
+ //LOG(logB, Q1.B)
+ //LOG(logC, Q1.C)
NETLIST_END()
diff --git a/src/lib/netlist/examples/todo.c b/src/lib/netlist/examples/todo.c
index 62c713e86fd..6e9257f5410 100644
--- a/src/lib/netlist/examples/todo.c
+++ b/src/lib/netlist/examples/todo.c
@@ -43,47 +43,47 @@ NETLIST_END()
#if 0
- RES(R1, 10)
- RES(R2, 10)
- RES(R3, 10)
- NET_C(V5,R1.1)
- NET_C(R1.2, R2.1)
- NET_C(R2.2, R3.1)
- NET_C(R3.2, GND)
+ RES(R1, 10)
+ RES(R2, 10)
+ RES(R3, 10)
+ NET_C(V5,R1.1)
+ NET_C(R1.2, R2.1)
+ NET_C(R2.2, R3.1)
+ NET_C(R3.2, GND)
#endif
#if 0
- RES(R4, 1000)
- CAP(C1, 1e-6)
- NET_C(V5,R4.1)
- NET_C(R4.2, C1.1)
- NET_C(C1.2, GND)
- //LOG(log1, C1.1)
+ RES(R4, 1000)
+ CAP(C1, 1e-6)
+ NET_C(V5,R4.1)
+ NET_C(R4.2, C1.1)
+ NET_C(C1.2, GND)
+ //LOG(log1, C1.1)
#endif
#if 0
- RES(R5, 1000)
- NETDEV_1N914(D1)
- NET_C(V5, R5.1)
- NET_C(R5.2, D1.A)
- NET_C(D1.K, GND)
- //LOG(log1, D1.A)
+ RES(R5, 1000)
+ NETDEV_1N914(D1)
+ NET_C(V5, R5.1)
+ NET_C(R5.2, D1.A)
+ NET_C(D1.K, GND)
+ //LOG(log1, D1.A)
#endif
#if 0
#endif
#if 0
- NETDEV_VCVS(VV)
- RES(R1, 1000)
- RES(R2, 10000)
-
- NET_C(V5, R1.1)
- NET_C(R1.2, VV.IN)
- NET_C(R2.1, VV.OP)
- NET_C(R2.2, VV.IN)
- NET_C(VV.ON, GND)
- NET_C(VV.IP, GND)
- LOG(logX, VV.OP)
+ NETDEV_VCVS(VV)
+ RES(R1, 1000)
+ RES(R2, 10000)
+
+ NET_C(V5, R1.1)
+ NET_C(R1.2, VV.IN)
+ NET_C(R2.1, VV.OP)
+ NET_C(R2.2, VV.IN)
+ NET_C(VV.ON, GND)
+ NET_C(VV.IP, GND)
+ LOG(logX, VV.OP)
#endif
@@ -91,50 +91,50 @@ NETLIST_END()
#endif
#if 0
- NETDEV_VCVS(VV)
- PARAM(VV.G, 100000) // typical OP-AMP amplification
- PARAM(VV.RO, 50) // typical OP-AMP amplification
- RES(R1, 1000)
- RES(R3, 10000) // ==> 10x amplification (inverting)
-
- NET_C(4V, R1.1)
- NET_C(R1.2, VV.IN)
- NET_C(R3.1, VV.IN)
- NET_C(R3.2, VV.OP)
- NET_C(VV.ON, GND)
- NET_C(VV.IP, GND)
- LOG(logX, VV.OP)
- LOG(logY, 4V)
+ NETDEV_VCVS(VV)
+ PARAM(VV.G, 100000) // typical OP-AMP amplification
+ PARAM(VV.RO, 50) // typical OP-AMP amplification
+ RES(R1, 1000)
+ RES(R3, 10000) // ==> 10x amplification (inverting)
+
+ NET_C(4V, R1.1)
+ NET_C(R1.2, VV.IN)
+ NET_C(R3.1, VV.IN)
+ NET_C(R3.2, VV.OP)
+ NET_C(VV.ON, GND)
+ NET_C(VV.IP, GND)
+ LOG(logX, VV.OP)
+ LOG(logY, 4V)
#endif
#if 0
- // Impedance converter with resistor
- NETDEV_VCVS(VV)
- PARAM(VV.G, 100000) // typical OP-AMP amplification
- PARAM(VV.RO, 50) // typical OP-AMP amplification
- RES(R3, 10000)
-
- NET_C(4V, VV.IP)
- NET_C(R3.1, VV.IN)
- NET_C(R3.2, VV.OP)
- NET_C(VV.ON, GND)
- LOG(logX, VV.OP)
- LOG(logY, 4V)
+ // Impedance converter with resistor
+ NETDEV_VCVS(VV)
+ PARAM(VV.G, 100000) // typical OP-AMP amplification
+ PARAM(VV.RO, 50) // typical OP-AMP amplification
+ RES(R3, 10000)
+
+ NET_C(4V, VV.IP)
+ NET_C(R3.1, VV.IN)
+ NET_C(R3.2, VV.OP)
+ NET_C(VV.ON, GND)
+ LOG(logX, VV.OP)
+ LOG(logY, 4V)
#endif
#if 0
- // Impedance converter without resistor
- NETDEV_VCVS(VV)
- PARAM(VV.G, 100000) // typical OP-AMP amplification
- PARAM(VV.RO, 50) // typical OP-AMP amplification
-
- NET_C(4V, VV.IP)
- NET_C(VV.IN, VV.OP)
- NET_C(VV.ON, GND)
- LOG(logX, VV.OP)
- LOG(logY, 4V)
+ // Impedance converter without resistor
+ NETDEV_VCVS(VV)
+ PARAM(VV.G, 100000) // typical OP-AMP amplification
+ PARAM(VV.RO, 50) // typical OP-AMP amplification
+
+ NET_C(4V, VV.IP)
+ NET_C(VV.IN, VV.OP)
+ NET_C(VV.ON, GND)
+ LOG(logX, VV.OP)
+ LOG(logY, 4V)
#endif
diff --git a/src/lib/netlist/examples/vccs.c b/src/lib/netlist/examples/vccs.c
index 27ebf5a64e0..0e76ba6b219 100644
--- a/src/lib/netlist/examples/vccs.c
+++ b/src/lib/netlist/examples/vccs.c
@@ -10,21 +10,21 @@
NETLIST_START(vccs)
- CLOCK(clk, 1000) // 1000 Hz
- SOLVER(Solver, 48000)
- PARAM(Solver.ACCURACY, 1e-12)
- PARAM(Solver.GS_LOOPS, 10000)
+ CLOCK(clk, 1000) // 1000 Hz
+ SOLVER(Solver, 48000)
+ PARAM(Solver.ACCURACY, 1e-12)
+ PARAM(Solver.GS_LOOPS, 10000)
- VCCS(VV)
- PARAM(VV.G, 100) // typical OP-AMP amplification
- RES(R2, 1)
+ VCCS(VV)
+ PARAM(VV.G, 100) // typical OP-AMP amplification
+ RES(R2, 1)
- NET_C(clk, VV.IN)
- NET_C(R2.1, VV.OP)
- NET_C(R2.2, GND)
- NET_C(VV.ON, GND)
- NET_C(VV.IP, GND)
- LOG(logX, VV.OP)
- LOG(logY, clk)
+ NET_C(clk, VV.IN)
+ NET_C(R2.1, VV.OP)
+ NET_C(R2.2, GND)
+ NET_C(VV.ON, GND)
+ NET_C(VV.IP, GND)
+ LOG(logX, VV.OP)
+ LOG(logY, clk)
NETLIST_END()
diff --git a/src/lib/netlist/examples/vccs1.c b/src/lib/netlist/examples/vccs1.c
index 7e6dd1ea48c..b3513b325b7 100644
--- a/src/lib/netlist/examples/vccs1.c
+++ b/src/lib/netlist/examples/vccs1.c
@@ -10,26 +10,26 @@
NETLIST_START(vccs)
- CLOCK(clk, 1000) // 1000 Hz
- SOLVER(Solver, 48000)
- PARAM(Solver.ACCURACY, 1e-6)
-
-
- VCCS(VV)
- PARAM(VV.G, 100000) // typical OP-AMP amplification
- RES(R1, 10000)
- RES(R2, 1)
- RES(R3, 1000)
-
- NET_C(clk, R1.1)
- NET_C(R1.2, VV.IN)
- NET_C(R2.1, VV.OP)
- NET_C(R3.1, VV.IN)
- NET_C(R3.2, VV.OP)
- NET_C(R2.2, GND)
- NET_C(VV.ON, GND)
- NET_C(VV.IP, GND)
- LOG(logX, VV.OP)
- LOG(logY, clk)
+ CLOCK(clk, 1000) // 1000 Hz
+ SOLVER(Solver, 48000)
+ PARAM(Solver.ACCURACY, 1e-6)
+
+
+ VCCS(VV)
+ PARAM(VV.G, 100000) // typical OP-AMP amplification
+ RES(R1, 10000)
+ RES(R2, 1)
+ RES(R3, 1000)
+
+ NET_C(clk, R1.1)
+ NET_C(R1.2, VV.IN)
+ NET_C(R2.1, VV.OP)
+ NET_C(R3.1, VV.IN)
+ NET_C(R3.2, VV.OP)
+ NET_C(R2.2, GND)
+ NET_C(VV.ON, GND)
+ NET_C(VV.IP, GND)
+ LOG(logX, VV.OP)
+ LOG(logY, clk)
NETLIST_END()
diff --git a/src/lib/netlist/examples/vs.c b/src/lib/netlist/examples/vs.c
index 7d72398e297..583b94d7c4f 100644
--- a/src/lib/netlist/examples/vs.c
+++ b/src/lib/netlist/examples/vs.c
@@ -11,10 +11,10 @@
NETLIST_START(vs)
- /* Standard stuff */
+ /* Standard stuff */
- SOLVER(Solver, 480)
- PARAM(Solver.ACCURACY, 1e-6)
+ SOLVER(Solver, 480)
+ PARAM(Solver.ACCURACY, 1e-6)
PARAM(Solver.METHOD, "MAT_CR")
PARAM(Solver.DYNAMIC_TS, 1)
@@ -26,7 +26,7 @@ NETLIST_START(vs)
NET_C(R1.2, VS1.N)
NET_C(GND, VS1.N)
- //LOG(tt, VS1.P)
- //LOG(tt1, R1.1)
+ //LOG(tt, VS1.P)
+ //LOG(tt1, R1.1)
NETLIST_END()
diff --git a/src/lib/netlist/examples/vs_cs.c b/src/lib/netlist/examples/vs_cs.c
index 9b39106a540..252eb9cad3f 100644
--- a/src/lib/netlist/examples/vs_cs.c
+++ b/src/lib/netlist/examples/vs_cs.c
@@ -11,20 +11,20 @@
NETLIST_START(rc)
- /*
- * delay circuit
- *
- */
+ /*
+ * delay circuit
+ *
+ */
- /* Standard stuff */
+ /* Standard stuff */
- SOLVER(Solver, 48000)
- PARAM(Solver.ACCURACY, 1e-6)
- CLOCK(clk, 20000)
+ SOLVER(Solver, 48000)
+ PARAM(Solver.ACCURACY, 1e-6)
+ CLOCK(clk, 20000)
/* Voltage source. Inner resistance will make clock visible */
- RES(R1, 1000)
+ RES(R1, 1000)
VS(VS1, 1)
NET_C(R1.1, clk)
NET_C(R1.2, VS1.P)
@@ -34,8 +34,8 @@ NETLIST_START(rc)
* need negative current
*/
- RES(R2, 1000)
- RES(R3, 1000)
+ RES(R2, 1000)
+ RES(R3, 1000)
CS(CS1, -0.001)
NET_C(CS1.P, R2.1)
NET_C(R2.2, R3.1)
@@ -46,7 +46,7 @@ NETLIST_START(rc)
NET_C(C1.2, R3.2)
- LOG(tt, VS1.P)
- LOG(tx, R2.2)
+ LOG(tt, VS1.P)
+ LOG(tx, R2.2)
NETLIST_END()