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author couriersud <couriersud@users.noreply.github.com>2022-07-05 08:23:45 +0200
committer GitHub <noreply@github.com>2022-07-05 08:23:45 +0200
commit93d60e7c6a00e1dbe0d8e78197532c66f0259dcd (patch)
treeba23ca90fccbb386f82f3ce324696e2c68834590 /src/lib/netlist/documentation
parentee66f0344f09072df22542def6426e3c5dda2b6d (diff)
netlist: gtrak10 performance and other improvements and fixes (#10032)
- added support parameter FORCE_TRISTATE_LOGIC on mk28000 - add system device SYS_PULSE to generate pulse based on input changes parameters are delay, pulse width, input polarity and output polarity - add USE_SPEED_HACKS define to gtrak10 to enable the use of the above Brings gtrak10 from 18% to 120%. - Improved interlaced video support in fixfreq.cpp Added two interlace modes: progressive and interlaced which can be selected in machine configuration. - more clang format work - rename link to connection - introduced typed aliases. This information may be used later to rewrite netlists. - added a three terminal base device This will allow the analog code to be more easily comparable to literature about MNA (Modal node analysis). BJT code is now a lot better readable. - fix doxygen consistency - added an example for a cmos inverter based on NMOS/PMOS fets. - TRUTHTABLE_START was renamed to TRUTH_TABLE - truth tables are now enclosed in braces - netlists are now enclosed in braces - TRUTHTABLE_END() and NETLIST_END() removed from files - Fixed static solver script - Add file path to includes in nltool
Diffstat (limited to 'src/lib/netlist/documentation')
-rw-r--r--src/lib/netlist/documentation/primer_1.dox.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/lib/netlist/documentation/primer_1.dox.h b/src/lib/netlist/documentation/primer_1.dox.h
index 11d22a99a13..6c2642fbcde 100644
--- a/src/lib/netlist/documentation/primer_1.dox.h
+++ b/src/lib/netlist/documentation/primer_1.dox.h
@@ -19,6 +19,7 @@ Now in netlist syntax this looks like:
#include "netlist/devices/net_lib.h"
NETLIST_START(charge_discharge)
+{
ANALOG_INPUT(V5, 5) // Clock needs a 5V power supply
@@ -34,7 +35,7 @@ NETLIST_START(charge_discharge)
NET_C(V5, I.VCC)
ALIAS(O, R.2) // Output O == C.1 == R.2
-NETLIST_END()
+}
~~~
Save this example as e.g. test1.cpp. Now that's a c++ extension. The background