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author Miodrag Milanovic <mmicko@gmail.com>2013-04-30 06:36:06 +0000
committer Miodrag Milanovic <mmicko@gmail.com>2013-04-30 06:36:06 +0000
commit4bf717996f56eb03dc735c83dae5450b7fc98d75 (patch)
treea63a55bcc180e342382e9c9a680f0c643fd05248 /src/emu
parentf35b95a00e64c63422116039aeae272029b58e51 (diff)
Cleanups and version bumpmame0148u4
Diffstat (limited to 'src/emu')
-rw-r--r--src/emu/cpu/psx/gte.c2
-rw-r--r--src/emu/cpu/z8000/8000dasm.c4
-rw-r--r--src/emu/cpu/z8000/z8000.h4
-rw-r--r--src/emu/debug/debugcpu.c8
-rw-r--r--src/emu/emu.mak2
-rw-r--r--src/emu/machine/6850acia.h2
-rw-r--r--src/emu/machine/8042kbdc.c2
-rw-r--r--src/emu/machine/8042kbdc.h22
-rw-r--r--src/emu/machine/mcf5206e.c247
-rw-r--r--src/emu/machine/mcf5206e.h3
-rw-r--r--src/emu/machine/s3c2400.h2
-rw-r--r--src/emu/machine/s3c2410.h2
-rw-r--r--src/emu/machine/s3c2440.h2
-rw-r--r--src/emu/sound/spu.c2
-rw-r--r--src/emu/video/dl1416.c2
-rw-r--r--src/emu/video/psx.c3
-rw-r--r--src/emu/video/voodoo.c2
-rw-r--r--src/emu/video/voodoo.h2
18 files changed, 154 insertions, 159 deletions
diff --git a/src/emu/cpu/psx/gte.c b/src/emu/cpu/psx/gte.c
index 20fe25088d7..1783b1df341 100644
--- a/src/emu/cpu/psx/gte.c
+++ b/src/emu/cpu/psx/gte.c
@@ -296,7 +296,7 @@ INT32 gte::BOUNDS( int44 value, int max_flag, int min_flag )
{
FLAG |= max_flag;
}
-
+
if( value.negative_overflow() )
{
FLAG |= min_flag;
diff --git a/src/emu/cpu/z8000/8000dasm.c b/src/emu/cpu/z8000/8000dasm.c
index 51580e8af39..3752683ce36 100644
--- a/src/emu/cpu/z8000/8000dasm.c
+++ b/src/emu/cpu/z8000/8000dasm.c
@@ -81,8 +81,8 @@ static const char *const ints[4] = {
"", "vi", "nvi", "vi,nvi"
};
-int z8k_segm; /* Current disassembler mode: 0 - non-segmented, 1 - segmented */
-int z8k_segm_mode = Z8K_SEGM_MODE_AUTO; /* User disassembler mode setting: segmented, non-segmented, auto */
+int z8k_segm; /* Current disassembler mode: 0 - non-segmented, 1 - segmented */
+int z8k_segm_mode = Z8K_SEGM_MODE_AUTO; /* User disassembler mode setting: segmented, non-segmented, auto */
void z8k_disass_mode(running_machine &machine, int ref, int params, const char *param[])
{
diff --git a/src/emu/cpu/z8000/z8000.h b/src/emu/cpu/z8000/z8000.h
index 97ce36c0188..5cd6a3d325a 100644
--- a/src/emu/cpu/z8000/z8000.h
+++ b/src/emu/cpu/z8000/z8000.h
@@ -38,7 +38,7 @@ extern void z8k_disass_mode(running_machine &machine, int ref, int params, const
/* possible values for z8k_segm_mode */
#define Z8K_SEGM_MODE_NONSEG 0
-#define Z8K_SEGM_MODE_SEG 1
-#define Z8K_SEGM_MODE_AUTO 2
+#define Z8K_SEGM_MODE_SEG 1
+#define Z8K_SEGM_MODE_AUTO 2
#endif /* __Z8000_H__ */
diff --git a/src/emu/debug/debugcpu.c b/src/emu/debug/debugcpu.c
index 23dc2d7ede4..d73acee4e13 100644
--- a/src/emu/debug/debugcpu.c
+++ b/src/emu/debug/debugcpu.c
@@ -2672,7 +2672,7 @@ bool device_debug::comment_remove(offs_t addr)
const char *device_debug::comment_text(offs_t addr) const
{
- const UINT32 crc = compute_opcode_crc32(addr);
+ const UINT32 crc = compute_opcode_crc32(addr);
dasm_comment* comment = m_comment_set.find(dasm_comment(addr, crc, "", 0));
if (comment == NULL) return NULL;
return comment->m_text;
@@ -3523,7 +3523,7 @@ void device_debug::tracer::flush()
device_debug::dasm_pc_tag::dasm_pc_tag(const offs_t& address, const UINT32& crc)
: m_address(address),
- m_crc(crc)
+ m_crc(crc)
{
}
@@ -3533,7 +3533,7 @@ device_debug::dasm_pc_tag::dasm_pc_tag(const offs_t& address, const UINT32& crc)
device_debug::dasm_comment::dasm_comment(offs_t address, UINT32 crc, const char *text, rgb_t color)
: dasm_pc_tag(address, crc),
- m_text(text),
- m_color(color)
+ m_text(text),
+ m_color(color)
{
}
diff --git a/src/emu/emu.mak b/src/emu/emu.mak
index b15166e50f8..1d765a36a92 100644
--- a/src/emu/emu.mak
+++ b/src/emu/emu.mak
@@ -251,7 +251,7 @@ EMUMACHINEOBJS = \
$(EMUMACHINE)/pc16552d.o \
$(EMUMACHINE)/pcf8593.o \
$(EMUMACHINE)/pci.o \
- $(EMUMACHINE)/pckeybrd.o \
+ $(EMUMACHINE)/pckeybrd.o \
$(EMUMACHINE)/pd4990a.o \
$(EMUMACHINE)/pic8259.o \
$(EMUMACHINE)/pit8253.o \
diff --git a/src/emu/machine/6850acia.h b/src/emu/machine/6850acia.h
index 52f323d2164..2f188b1e11b 100644
--- a/src/emu/machine/6850acia.h
+++ b/src/emu/machine/6850acia.h
@@ -173,7 +173,7 @@ private:
serial_state m_rx_state;
serial_state m_tx_state;
int m_irq;
- bool m_dcd_triggered;
+ bool m_dcd_triggered;
emu_timer *m_rx_timer;
emu_timer *m_tx_timer;
diff --git a/src/emu/machine/8042kbdc.c b/src/emu/machine/8042kbdc.c
index a23597d8445..abf880c50bf 100644
--- a/src/emu/machine/8042kbdc.c
+++ b/src/emu/machine/8042kbdc.c
@@ -225,7 +225,7 @@ void kbdc8042_device::device_config_complete()
memset(&m_gate_a20_cb, 0, sizeof(m_gate_a20_cb));
memset(&m_input_buffer_full_func, 0, sizeof(m_input_buffer_full_func));
memset(&m_output_buffer_empty_cb, 0, sizeof(m_output_buffer_empty_cb));
- memset(&m_speaker_cb, 0, sizeof(m_speaker_cb));
+ memset(&m_speaker_cb, 0, sizeof(m_speaker_cb));
}
}
diff --git a/src/emu/machine/8042kbdc.h b/src/emu/machine/8042kbdc.h
index 67b1013104f..142ce8534a4 100644
--- a/src/emu/machine/8042kbdc.h
+++ b/src/emu/machine/8042kbdc.h
@@ -34,18 +34,18 @@ enum kbdc8042_type_t
struct kbdc8042_interface
{
- kbdc8042_type_t m_keybtype;
+ kbdc8042_type_t m_keybtype;
// interface to the host pc
devcb_write_line m_system_reset_cb;
devcb_write_line m_gate_a20_cb;
devcb_write_line m_input_buffer_full_cb;
devcb_write_line m_output_buffer_empty_cb;
-
- devcb_write8 m_speaker_cb;
- devcb_read8 m_getout2_cb;
+
+ devcb_write8 m_speaker_cb;
+ devcb_read8 m_getout2_cb;
};
-// ======================> kbdc8042_device
+// ======================> kbdc8042_device
class kbdc8042_device : public device_t,
public kbdc8042_interface
@@ -53,7 +53,7 @@ class kbdc8042_device : public device_t,
public:
// construction/destruction
kbdc8042_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
-
+
DECLARE_READ8_MEMBER( data_r );
DECLARE_WRITE8_MEMBER( data_w );
@@ -68,7 +68,7 @@ protected:
virtual void device_start();
virtual void device_reset();
virtual void device_config_complete();
-
+
UINT8 m_inport, m_outport, m_data, m_command;
struct {
@@ -93,14 +93,14 @@ protected:
int m_offset1;
int m_poll_delay;
-
+
devcb_resolved_write_line m_system_reset_func;
devcb_resolved_write_line m_gate_a20_func;
devcb_resolved_write_line m_input_buffer_full_func;
devcb_resolved_write_line m_output_buffer_empty_func;
-
- devcb_resolved_write8 m_speaker_func;
- devcb_resolved_read8 m_getout2_func;
+
+ devcb_resolved_write8 m_speaker_func;
+ devcb_resolved_read8 m_getout2_func;
};
// device type definition
diff --git a/src/emu/machine/mcf5206e.c b/src/emu/machine/mcf5206e.c
index 87ab12f599d..80f17bbe803 100644
--- a/src/emu/machine/mcf5206e.c
+++ b/src/emu/machine/mcf5206e.c
@@ -30,7 +30,6 @@ mcf5206e_peripheral_device::mcf5206e_peripheral_device(const machine_config &mco
void mcf5206e_peripheral_device::device_config_complete()
{
-
}
@@ -40,7 +39,6 @@ void mcf5206e_peripheral_device::device_config_complete()
void mcf5206e_peripheral_device::device_start()
{
-
}
@@ -52,7 +50,6 @@ READ32_MEMBER(mcf5206e_peripheral_device::dev_r)
WRITE32_MEMBER(mcf5206e_peripheral_device::dev_w)
{
-
}
@@ -86,133 +83,133 @@ READ32_MEMBER(mcf5206e_peripheral_device::seta2_coldfire_regs_r)
ADDRESS REG WIDTH NAME/DESCRIPTION INIT VALUE (MR=Master Reset, NR=Normal Reset) Read or Write access
-op MOVEC with $C0F MBAR 32 Module Base Address Register uninit (except V=0) W
-$003 SIMR 8 SIM Configuration Register C0 R/W
-$014 ICR1 8 Interrupt Control Register 1 - External IRQ1/IPL1 04 R/W
-$015 ICR2 8 Interrupt Control Register 2 - External IPL2 08 R/W
-$016 ICR3 8 Interrupt Control Register 3 - External IPL3 0C R/W
-$017 ICR4 8 Interrupt Control Register 4 - External IRQ4/IPL4 10 R/W
-$018 ICR5 8 Interrupt Control Register 5 - External IPL5 14 R/W
-$019 ICR6 8 Interrupt Control Register 6 - External IPL6 18 R/W
-$01A ICR7 8 Interrupt Control Register 7 - External IRQ7/IPL7 1C R/W
-$01B ICR8 8 Interrupt Control Register 8 - SWT 1C R/W
-$01C ICR9 8 Interrupt Control Register 9 - Timer 1 Interrupt 80 R/W
-$01D ICR10 8 Interrupt Control Register 10 - Timer 2 Interrupt 80 R/W
-$01E ICR11 8 Interrupt Control Register 11 - MBUS Interrupt 80 R/W
-$01F ICR12 8 Interrupt Control Register 12 - UART 1 Interrupt 00 R/W
-$020 ICR13 8 Interrupt Control Register 13 - UART 2 Interrupt 00 R/W
-$036 IMR 16 Interrupt Mask Register 3FFE R/W
-$03A IPR 16 Interrupt Pending Register 0000 R
-$040 RSR 8 Reset Status Register 80 / 20 R/W
-$041 SYPCR 8 System Protection Control Register 00 R/W
-$042 SWIVR 8 Software Watchdog Interrupt Vector Register 0F R/W
-$043 SWSR 8 Software Watchdog Service Register uninit W
-$046 DCRR 16 DRAM Controller Refresh MR 0000 - NR uninit R/W
-$04A DCTR 16 DRAM Controller Timing Register MR 0000 - NR uninit R/W
-$04C DCAR0 16 DRAM Controller 0 Address Register MR uninit - NR uninit R/W
-$050 DCMR0 32 DRAM Controller 0 Mask Register MR uninit - NR uninit R/W
-$057 DCCR0 8 DRAM Controller 0 Control Register MR 00 - NR 00 R/W
-$058 DCAR1 16 DRAM Controller 1 Address Register MR uninit - NR uninit R/W
-$05C DCMR1 32 DRAM Controller 1 Mask Register MR uninit - NR uninit R/W
-$063 DCCR1 8 DRAM Controller 1 Control Register MR 00 - NR 00 R/W
+op MOVEC with $C0F MBAR 32 Module Base Address Register uninit (except V=0) W
+$003 SIMR 8 SIM Configuration Register C0 R/W
+$014 ICR1 8 Interrupt Control Register 1 - External IRQ1/IPL1 04 R/W
+$015 ICR2 8 Interrupt Control Register 2 - External IPL2 08 R/W
+$016 ICR3 8 Interrupt Control Register 3 - External IPL3 0C R/W
+$017 ICR4 8 Interrupt Control Register 4 - External IRQ4/IPL4 10 R/W
+$018 ICR5 8 Interrupt Control Register 5 - External IPL5 14 R/W
+$019 ICR6 8 Interrupt Control Register 6 - External IPL6 18 R/W
+$01A ICR7 8 Interrupt Control Register 7 - External IRQ7/IPL7 1C R/W
+$01B ICR8 8 Interrupt Control Register 8 - SWT 1C R/W
+$01C ICR9 8 Interrupt Control Register 9 - Timer 1 Interrupt 80 R/W
+$01D ICR10 8 Interrupt Control Register 10 - Timer 2 Interrupt 80 R/W
+$01E ICR11 8 Interrupt Control Register 11 - MBUS Interrupt 80 R/W
+$01F ICR12 8 Interrupt Control Register 12 - UART 1 Interrupt 00 R/W
+$020 ICR13 8 Interrupt Control Register 13 - UART 2 Interrupt 00 R/W
+$036 IMR 16 Interrupt Mask Register 3FFE R/W
+$03A IPR 16 Interrupt Pending Register 0000 R
+$040 RSR 8 Reset Status Register 80 / 20 R/W
+$041 SYPCR 8 System Protection Control Register 00 R/W
+$042 SWIVR 8 Software Watchdog Interrupt Vector Register 0F R/W
+$043 SWSR 8 Software Watchdog Service Register uninit W
+$046 DCRR 16 DRAM Controller Refresh MR 0000 - NR uninit R/W
+$04A DCTR 16 DRAM Controller Timing Register MR 0000 - NR uninit R/W
+$04C DCAR0 16 DRAM Controller 0 Address Register MR uninit - NR uninit R/W
+$050 DCMR0 32 DRAM Controller 0 Mask Register MR uninit - NR uninit R/W
+$057 DCCR0 8 DRAM Controller 0 Control Register MR 00 - NR 00 R/W
+$058 DCAR1 16 DRAM Controller 1 Address Register MR uninit - NR uninit R/W
+$05C DCMR1 32 DRAM Controller 1 Mask Register MR uninit - NR uninit R/W
+$063 DCCR1 8 DRAM Controller 1 Control Register MR 00 - NR 00 R/W
--------- CHIP SELECTS -----------
-$064 CSAR0 16 Chip-Select 0 Address Register 0000 R/W
-$068 CSMR0 32 Chip-Select 0 Mask Register 00000000 R/W
-$06E CSCR0 16 Chip-Select 0 Control Register 3C1F, 3C5F, 3C9F, 3CDF, 3D1F, 3D5F, 3D9F, 3DDF R/W
- AA set by IRQ 7 at reset
- PS1 set by IRQ 4 at reset
- PS0 set by IRQ 1 at reset
-$070 CSAR1 16 Chip-Select 1 Address Register uninit R/W
-$074 CSMR1 32 Chip-Select 1 Mask Register uninit R/W
-$07A CSCR1 16 Chip-Select 1 Control Register uninit *1 R/W
-$07C CSAR2 16 Chip-Select 2 Address Register uninit R/W
-$080 CSMR2 32 Chip-Select 2 Mask Register uninit R/W
-$086 CSCR2 16 Chip-Select 2 Control Register uninit *1 R/W
-$088 CSAR3 16 Chip-Select 3 Address Register uninit R/W
-$08C CSMR3 32 Chip-Select 3 Mask Register uninit R/W
-$092 CSCR3 16 Chip-Select 3 Control Register uninit *1 R/W
-$094 CSAR4 16 Chip-Select 4 Address Register uninit R/W
-$098 CSMR4 32 Chip-Select 4 Mask Register uninit R/W
-$09E CSCR4 16 Chip-Select 4 Control Register uninit *1 R/W
-$0A0 CSAR5 16 Chip-Select 5 Address Register uninit R/W
-$0A4 CSMR5 32 Chip-Select 5 Mask Register uninit R/W
-$0AA CSCR5 16 Chip-Select 5 Control Register uninit *1 R/W
-$0AC CSAR6 16 Chip-Select 6 Address Register uninit R/W
-$0B0 CSMR6 32 Chip-Select 6 Mask Register uninit R/W
-$0B6 CSCR6 16 Chip-Select 6 Control Register uninit *1 R/W
-$0B8 CSAR7 16 Chip-Select 7 Address Register uninit R/W
-$0BC CSMR7 32 Chip-Select 7 Mask Register uninit R/W
-$0C2 CSCR7 16 Chip-Select 7 Control Register uninit *1 R/W
-$0C6 DMCR 16 Default Memory Control Register 0000 R/W
-$0CA PAR 16 Pin Assignment Register 00 R/W
+$064 CSAR0 16 Chip-Select 0 Address Register 0000 R/W
+$068 CSMR0 32 Chip-Select 0 Mask Register 00000000 R/W
+$06E CSCR0 16 Chip-Select 0 Control Register 3C1F, 3C5F, 3C9F, 3CDF, 3D1F, 3D5F, 3D9F, 3DDF R/W
+ AA set by IRQ 7 at reset
+ PS1 set by IRQ 4 at reset
+ PS0 set by IRQ 1 at reset
+$070 CSAR1 16 Chip-Select 1 Address Register uninit R/W
+$074 CSMR1 32 Chip-Select 1 Mask Register uninit R/W
+$07A CSCR1 16 Chip-Select 1 Control Register uninit *1 R/W
+$07C CSAR2 16 Chip-Select 2 Address Register uninit R/W
+$080 CSMR2 32 Chip-Select 2 Mask Register uninit R/W
+$086 CSCR2 16 Chip-Select 2 Control Register uninit *1 R/W
+$088 CSAR3 16 Chip-Select 3 Address Register uninit R/W
+$08C CSMR3 32 Chip-Select 3 Mask Register uninit R/W
+$092 CSCR3 16 Chip-Select 3 Control Register uninit *1 R/W
+$094 CSAR4 16 Chip-Select 4 Address Register uninit R/W
+$098 CSMR4 32 Chip-Select 4 Mask Register uninit R/W
+$09E CSCR4 16 Chip-Select 4 Control Register uninit *1 R/W
+$0A0 CSAR5 16 Chip-Select 5 Address Register uninit R/W
+$0A4 CSMR5 32 Chip-Select 5 Mask Register uninit R/W
+$0AA CSCR5 16 Chip-Select 5 Control Register uninit *1 R/W
+$0AC CSAR6 16 Chip-Select 6 Address Register uninit R/W
+$0B0 CSMR6 32 Chip-Select 6 Mask Register uninit R/W
+$0B6 CSCR6 16 Chip-Select 6 Control Register uninit *1 R/W
+$0B8 CSAR7 16 Chip-Select 7 Address Register uninit R/W
+$0BC CSMR7 32 Chip-Select 7 Mask Register uninit R/W
+$0C2 CSCR7 16 Chip-Select 7 Control Register uninit *1 R/W
+$0C6 DMCR 16 Default Memory Control Register 0000 R/W
+$0CA PAR 16 Pin Assignment Register 00 R/W
--------- TIMER MODULE -----------
-$100 TMR1 16 Timer 1 Mode Register 0000 R/W
-$104 TRR1 16 Timer 1 Reference Register FFFF R/W
-$108 TCR1 16 Timer 1 Capture Register 0000 R
-$10C TCN1 16 Timer 1 Counter 0000 R/W
-$111 TER1 8 Timer 1 Event Register 00 R/W
-$120 TMR2 16 Timer 2 Mode Register 0000 R/W
-$124 TRR2 16 Timer 2 Reference Register FFFF R/W
-$128 TCR2 16 Timer 2 Capture Register 0000 R
-$12C TCN2 16 Timer 2 Counter 0000 R/W
-$131 TER2 8 Timer 2 Event Register 00 R/W
+$100 TMR1 16 Timer 1 Mode Register 0000 R/W
+$104 TRR1 16 Timer 1 Reference Register FFFF R/W
+$108 TCR1 16 Timer 1 Capture Register 0000 R
+$10C TCN1 16 Timer 1 Counter 0000 R/W
+$111 TER1 8 Timer 1 Event Register 00 R/W
+$120 TMR2 16 Timer 2 Mode Register 0000 R/W
+$124 TRR2 16 Timer 2 Reference Register FFFF R/W
+$128 TCR2 16 Timer 2 Capture Register 0000 R
+$12C TCN2 16 Timer 2 Counter 0000 R/W
+$131 TER2 8 Timer 2 Event Register 00 R/W
------------ UART SERIAL PORTS -----------
-$140 UMR1,2 8 UART 1 Mode Registers 00 R/W
-$144 USR 8 UART 1 Status Register 00 R
- UCSR 8 UART 1 Clock-Select Register DD W
-$148 UCR 8 UART 1 Command Register 00 W
-$14C URB 8 UART 1 Receive Buffer FF R
- UTB 8 UART 1 Transmit Buffer 00 W
-$150 UIPCR 8 UART Input Port Change Register 0F R
- UACR 8 UART 1 Auxilary Control Register 00 W
-$154 UISR 8 UART 1 Interrupt Status Register 00 R
- UIMR 8 UART 1 Interrupt Mask Register 00 W
-$158 UBG1 8 UART 1 Baud Rate Generator Prescale MSB uninit W
-$15C UBG2 8 UART 1 Baud Rate Generator Prescale LSB uninit W
-$170 UIVR 8 UART 1 Interrupt Vector Register 0F R/W
-$174 UIP 8 UART 1 Input Port Register FF R
-$178 UOP1 8 UART 1 Output Port Bit Set CMD UOP1[7-1]=undef; UOP1=0 W
-$17C UOP0 8 UART 1 Output Port Bit Reset CMD uninit W
-
-$180 UMR1,2 8 UART 2 Mode Registers 00 R/W
-$184 USR 8 UART 2 Status Register 00 R
- UCSR 8 UART 2 Clock-Select Register DD W
-$188 UCR 8 UART 2 Command Register 00 W
-$18C URB 8 UART 2 Receive Buffer FF R
- UTB 8 UART 2 Transmit Buffer 00 W
-$190 UIPCR 8 UART 2 Input Port Change Register 0F R
- UACR 8 UART 2 Auxilary Control Register 00 W
-$194 UISR 8 UART 2 Interrupt Status Register 00 R
- UIMR 8 UART 2 Interrupt Mask Register 00 W
-$198 UBG1 8 UART 2 Baud Rate Generator Prescale MSB uninit R/W
-$19C UBG2 8 UART 2 Barud Rate Generator Prescale LSB uninit R/W
-$1B0 UIVR 8 UART 2 Interrupt Vector Register 0F R/W
-$1B4 UIP 8 UART 2 Input Port Register FF R
-$1B8 UOP1 8 UART 2 Output Port Bit Set CMD UOP1[7-1]=undef; UOP1=0 W
-$1BC UOP0 8 UART 2 Output Port Bit Reset CMD uninit W
-
-$1C5 PPDDR 8 Port A Data Direction Register 00 R/W
-$1C9 PPDAT 8 Port A Data Register 00 R/W
+$140 UMR1,2 8 UART 1 Mode Registers 00 R/W
+$144 USR 8 UART 1 Status Register 00 R
+ UCSR 8 UART 1 Clock-Select Register DD W
+$148 UCR 8 UART 1 Command Register 00 W
+$14C URB 8 UART 1 Receive Buffer FF R
+ UTB 8 UART 1 Transmit Buffer 00 W
+$150 UIPCR 8 UART Input Port Change Register 0F R
+ UACR 8 UART 1 Auxilary Control Register 00 W
+$154 UISR 8 UART 1 Interrupt Status Register 00 R
+ UIMR 8 UART 1 Interrupt Mask Register 00 W
+$158 UBG1 8 UART 1 Baud Rate Generator Prescale MSB uninit W
+$15C UBG2 8 UART 1 Baud Rate Generator Prescale LSB uninit W
+$170 UIVR 8 UART 1 Interrupt Vector Register 0F R/W
+$174 UIP 8 UART 1 Input Port Register FF R
+$178 UOP1 8 UART 1 Output Port Bit Set CMD UOP1[7-1]=undef; UOP1=0 W
+$17C UOP0 8 UART 1 Output Port Bit Reset CMD uninit W
+
+$180 UMR1,2 8 UART 2 Mode Registers 00 R/W
+$184 USR 8 UART 2 Status Register 00 R
+ UCSR 8 UART 2 Clock-Select Register DD W
+$188 UCR 8 UART 2 Command Register 00 W
+$18C URB 8 UART 2 Receive Buffer FF R
+ UTB 8 UART 2 Transmit Buffer 00 W
+$190 UIPCR 8 UART 2 Input Port Change Register 0F R
+ UACR 8 UART 2 Auxilary Control Register 00 W
+$194 UISR 8 UART 2 Interrupt Status Register 00 R
+ UIMR 8 UART 2 Interrupt Mask Register 00 W
+$198 UBG1 8 UART 2 Baud Rate Generator Prescale MSB uninit R/W
+$19C UBG2 8 UART 2 Barud Rate Generator Prescale LSB uninit R/W
+$1B0 UIVR 8 UART 2 Interrupt Vector Register 0F R/W
+$1B4 UIP 8 UART 2 Input Port Register FF R
+$1B8 UOP1 8 UART 2 Output Port Bit Set CMD UOP1[7-1]=undef; UOP1=0 W
+$1BC UOP0 8 UART 2 Output Port Bit Reset CMD uninit W
+
+$1C5 PPDDR 8 Port A Data Direction Register 00 R/W
+$1C9 PPDAT 8 Port A Data Register 00 R/W
------------ MBUS -----------
-$1E0 MADR 8 M-Bus Address Register 00 R/W
-$1E4 MFDR 8 M-Bus Frequency Divider Register 00 R/W
-$1E8 MBCR 8 M-Bus Control Register 00 R/W
-$1EC MBSR 8 M-Bus Status Register 00 R/W
-$1F0 MBDR 8 M-Bus Data I/O Register 00 R/W
+$1E0 MADR 8 M-Bus Address Register 00 R/W
+$1E4 MFDR 8 M-Bus Frequency Divider Register 00 R/W
+$1E8 MBCR 8 M-Bus Control Register 00 R/W
+$1EC MBSR 8 M-Bus Status Register 00 R/W
+$1F0 MBDR 8 M-Bus Data I/O Register 00 R/W
------------ DMA Controller -----------
-$200 DMASAR0 32 Source Address Register 0 00 R/W
-$204 DMADAR0 32 Destination Address Register 0 00 R/W
-$208 DCR0 16 DMA Control Register 0 00 R/W
-$20C BCR0 16 Byte Count Register 0 00 R/W
-$210 DSR0 8 Status Register 0 00 R/W
-$214 DIVR0 8 Interrupt Vector Register 0 0F R/W
-$240 DMASAR1 32 Source Address Register 1 00 R/W
-$244 DMADAR1 32 Destination Address Register 1 00 R/W
-$248 DCR1 16 DMA Control Register 1 00 R/W
-$24C BCR1 16 Byte Count Register 1 00 R/W
-$250 DSR1 8 Status Register 1 00 R/W
-$254 DIVR1 8 Interrupt Vector Register 1 0F R/W
+$200 DMASAR0 32 Source Address Register 0 00 R/W
+$204 DMADAR0 32 Destination Address Register 0 00 R/W
+$208 DCR0 16 DMA Control Register 0 00 R/W
+$20C BCR0 16 Byte Count Register 0 00 R/W
+$210 DSR0 8 Status Register 0 00 R/W
+$214 DIVR0 8 Interrupt Vector Register 0 0F R/W
+$240 DMASAR1 32 Source Address Register 1 00 R/W
+$244 DMADAR1 32 Destination Address Register 1 00 R/W
+$248 DCR1 16 DMA Control Register 1 00 R/W
+$24C BCR1 16 Byte Count Register 1 00 R/W
+$250 DSR1 8 Status Register 1 00 R/W
+$254 DIVR1 8 Interrupt Vector Register 1 0F R/W
*1 - uninit except BRST=ASET=WRAH=RDAH=WR=RD=0
-*/ \ No newline at end of file
+*/
diff --git a/src/emu/machine/mcf5206e.h b/src/emu/machine/mcf5206e.h
index 161bb0de5ae..9f4e53112fe 100644
--- a/src/emu/machine/mcf5206e.h
+++ b/src/emu/machine/mcf5206e.h
@@ -18,8 +18,7 @@
***************************************************************************/
#define MCFG_MCF5206E_PERIPHERAL_ADD(_tag) \
- MCFG_DEVICE_ADD(_tag, MCF5206E_PERIPHERAL, 0) \
-
+ MCFG_DEVICE_ADD(_tag, MCF5206E_PERIPHERAL, 0)
/***************************************************************************
TYPE DEFINITIONS
diff --git a/src/emu/machine/s3c2400.h b/src/emu/machine/s3c2400.h
index c0855737665..c189d7ec15f 100644
--- a/src/emu/machine/s3c2400.h
+++ b/src/emu/machine/s3c2400.h
@@ -753,7 +753,7 @@ struct s3c24xx_t
devcb_resolved_write8 address_w;
devcb_resolved_read8 nand_data_r;
devcb_resolved_write8 nand_data_w;
-
+
};
#endif
diff --git a/src/emu/machine/s3c2410.h b/src/emu/machine/s3c2410.h
index a9b2e370909..dfbfe9833f6 100644
--- a/src/emu/machine/s3c2410.h
+++ b/src/emu/machine/s3c2410.h
@@ -900,7 +900,7 @@ struct s3c24xx_t
devcb_resolved_write8 address_w;
devcb_resolved_read8 nand_data_r;
devcb_resolved_write8 nand_data_w;
-
+
};
#endif
diff --git a/src/emu/machine/s3c2440.h b/src/emu/machine/s3c2440.h
index a5865c91dcf..a88e90b30a0 100644
--- a/src/emu/machine/s3c2440.h
+++ b/src/emu/machine/s3c2440.h
@@ -970,7 +970,7 @@ struct s3c24xx_t
devcb_resolved_write8 command_w;
devcb_resolved_write8 address_w;
devcb_resolved_read8 nand_data_r;
- devcb_resolved_write8 nand_data_w;
+ devcb_resolved_write8 nand_data_w;
};
#endif
diff --git a/src/emu/sound/spu.c b/src/emu/sound/spu.c
index 5b0e96c4d49..51172cd68b7 100644
--- a/src/emu/sound/spu.c
+++ b/src/emu/sound/spu.c
@@ -2488,7 +2488,7 @@ void spu_device::generate_cdda(void *ptr, const unsigned int sz)
m_cd_out_ptr=(m_cd_out_ptr+2)&0x3ff;
//if((m_cd_out_ptr == ((spureg.irq_addr << 3) & ~0x400)) && (spureg.ctrl & spuctrl_irq_enable))
- // m_irq_handler(1);
+ // m_irq_handler(1);
dp[0]=clamp(dp[0]+vl);
dp[1]=clamp(dp[1]+vr);
diff --git a/src/emu/video/dl1416.c b/src/emu/video/dl1416.c
index 11a672e1298..4584cef0161 100644
--- a/src/emu/video/dl1416.c
+++ b/src/emu/video/dl1416.c
@@ -127,7 +127,7 @@ INLINE dl1416_state *get_safe_token(device_t *device)
static DEVICE_START( dl1416 )
{
dl1416_state *dl1416 = get_safe_token(device);
-
+
/* register for state saving */
state_save_register_item(device->machine(), "dl1416", device->tag(), 0, dl1416->chip_enable);
state_save_register_item(device->machine(), "dl1416", device->tag(), 0, dl1416->cursor_enable);
diff --git a/src/emu/video/psx.c b/src/emu/video/psx.c
index fba7dd1a8a0..eefb06428a5 100644
--- a/src/emu/video/psx.c
+++ b/src/emu/video/psx.c
@@ -1347,8 +1347,7 @@ INLINE int CullVertex( int a, int b )
n_leftpoint = n_point; \
} \
} \
- n_rightpoint = n_leftpoint; \
-
+ n_rightpoint = n_leftpoint;
void psxgpu_device::FlatPolygon( int n_points )
{
INT16 n_y;
diff --git a/src/emu/video/voodoo.c b/src/emu/video/voodoo.c
index d3caab4cf58..872caabbb7b 100644
--- a/src/emu/video/voodoo.c
+++ b/src/emu/video/voodoo.c
@@ -1033,7 +1033,7 @@ static TIMER_CALLBACK( vblank_callback )
{
if (LOG_VBLANK_SWAP) logerror("---- vblank flush begin\n");
flush_fifos(v, machine.time());
- if (LOG_VBLANK_SWAP) logerror("---- vblank flush end\n");
+ if (LOG_VBLANK_SWAP) logerror("---- vblank flush end\n");
}
/* increment the count */
diff --git a/src/emu/video/voodoo.h b/src/emu/video/voodoo.h
index fed896c0b27..5e8063c35d2 100644
--- a/src/emu/video/voodoo.h
+++ b/src/emu/video/voodoo.h
@@ -74,7 +74,7 @@ struct voodoo_config
UINT8 tmumem1;
const char * screen;
const char * cputag;
- devcb_write_line vblank;
+ devcb_write_line vblank;
devcb_write_line stall;
};