diff options
author | Miodrag Milanovic <mmicko@gmail.com> | 2013-02-11 07:44:56 +0000 |
---|---|---|
committer | Miodrag Milanovic <mmicko@gmail.com> | 2013-02-11 07:44:56 +0000 |
commit | a440a8e0200a36491ae540f6f00beae59c148549 (patch) | |
tree | b4c31ebadaa2857396c37178674086420bf1658f /src/emu | |
parent | 4b0b4e6b2fa7eb5105859f561354662d479f53be (diff) |
Cleanups and version bumpmame0148u1
Diffstat (limited to 'src/emu')
63 files changed, 1943 insertions, 1969 deletions
diff --git a/src/emu/cpu/arm7/arm7core.h b/src/emu/cpu/arm7/arm7core.h index 73dcd4d5593..8c803237065 100644 --- a/src/emu/cpu/arm7/arm7core.h +++ b/src/emu/cpu/arm7/arm7core.h @@ -93,7 +93,7 @@ enum }; /* Coprocessor-related macros */ -#define COPRO_TLB_BASE arm->tlbBase +#define COPRO_TLB_BASE arm->tlbBase #define COPRO_TLB_BASE_MASK 0xffffc000 #define COPRO_TLB_VADDR_FLTI_MASK 0xfff00000 #define COPRO_TLB_VADDR_FLTI_MASK_SHIFT 18 @@ -117,7 +117,7 @@ enum #define COPRO_TLB_SECTION_TABLE 2 #define COPRO_TLB_FINE_TABLE 3 -#define COPRO_CTRL arm->control +#define COPRO_CTRL arm->control #define COPRO_CTRL_MMU_EN 0x00000001 #define COPRO_CTRL_ADDRFAULT_EN 0x00000002 #define COPRO_CTRL_DCACHE_EN 0x00000004 @@ -143,12 +143,12 @@ enum #define COPRO_DOMAIN_ACCESS_CONTROL arm->domainAccessControl -#define COPRO_FAULT_STATUS_D arm->faultStatus[0] -#define COPRO_FAULT_STATUS_P arm->faultStatus[1] +#define COPRO_FAULT_STATUS_D arm->faultStatus[0] +#define COPRO_FAULT_STATUS_P arm->faultStatus[1] -#define COPRO_FAULT_ADDRESS arm->faultAddress +#define COPRO_FAULT_ADDRESS arm->faultAddress -#define COPRO_FCSE_PID arm->fcsePID +#define COPRO_FCSE_PID arm->fcsePID /* Coprocessor Registers */ #define ARM7COPRO_REGS \ diff --git a/src/emu/cpu/arm7/arm7drc.c b/src/emu/cpu/arm7/arm7drc.c index 858173f88a5..26ead621a2b 100644 --- a/src/emu/cpu/arm7/arm7drc.c +++ b/src/emu/cpu/arm7/arm7drc.c @@ -120,7 +120,7 @@ struct arm7imp_state /* core state */ drc_cache * cache; /* pointer to the DRC code cache */ drcuml_state * drcuml; /* DRC UML generator state */ - arm7_frontend * drcfe; /* pointer to the DRC front-end state */ + arm7_frontend * drcfe; /* pointer to the DRC front-end state */ UINT32 drcoptions; /* configurable DRC options */ /* internal stuff */ @@ -143,13 +143,13 @@ struct arm7imp_state code_handle * out_of_cycles; /* out of cycles exception handler */ code_handle * tlb_translate; /* tlb translation handler */ code_handle * detect_fault; /* tlb fault detection handler */ - code_handle * check_irq; /* irq check handler */ - code_handle * read8; /* read byte */ - code_handle * write8; /* write byte */ - code_handle * read16; /* read half */ - code_handle * write16; /* write half */ - code_handle * read32; /* read word */ - code_handle * write32; /* write word */ + code_handle * check_irq; /* irq check handler */ + code_handle * read8; /* read byte */ + code_handle * write8; /* write byte */ + code_handle * read16; /* read half */ + code_handle * write16; /* write half */ + code_handle * read32; /* read word */ + code_handle * write32; /* write word */ /* fast RAM */ UINT32 fastram_select; @@ -335,15 +335,15 @@ static void arm7_init(arm7_flavor flavor, int bigendian, legacy_cpu_device *devi { arm->impstate->drcuml->get_backend_info(beinfo); if (beinfo.direct_iregs > 4) - { // PC + { // PC arm->impstate->regmap[eR15] = I4; } if (beinfo.direct_iregs > 5) - { // Status + { // Status arm->impstate->regmap[eCPSR] = I5; } if (beinfo.direct_iregs > 6) - { // SP + { // SP arm->impstate->regmap[eR13] = I6; } } @@ -1340,8 +1340,8 @@ static void code_compile_block(arm_state *arm, UINT8 mode, offs_t pc) /* if the last instruction can change modes, use a variable mode; otherwise, assume the same mode */ /*if (seqlast->flags & OPFLAG_CAN_CHANGE_MODES) - UML_HASHJMP(block, mem(&arm->impstate->mode), nextpc, *arm->impstate->nocode); - // hashjmp <mode>,nextpc,nocode + UML_HASHJMP(block, mem(&arm->impstate->mode), nextpc, *arm->impstate->nocode); + // hashjmp <mode>,nextpc,nocode else*/ if (seqlast->next() == NULL || seqlast->next()->pc != nextpc) UML_HASHJMP(block, arm->impstate->mode, nextpc, *arm->impstate->nocode); // hashjmp <mode>,nextpc,nocode @@ -1422,7 +1422,7 @@ static void static_generate_entry_point(arm_state *arm) alloc_handle(drcuml, &arm->impstate->tlb_translate, "tlb_translate"); alloc_handle(drcuml, &arm->impstate->entry, "entry"); - UML_HANDLE(block, *arm->impstate->entry); // handle entry + UML_HANDLE(block, *arm->impstate->entry); // handle entry /* load fast integer registers */ load_fast_iregs(arm, block); @@ -1430,7 +1430,7 @@ static void static_generate_entry_point(arm_state *arm) UML_CALLH(block, *arm->impstate->check_irq); /* generate a hash jump via the current mode and PC */ - UML_HASHJMP(block, 0, mem(&arm->pc), *arm->impstate->nocode); // hashjmp 0,<pc>,nocode + UML_HASHJMP(block, 0, mem(&arm->pc), *arm->impstate->nocode); // hashjmp 0,<pc>,nocode block->end(); } @@ -1458,7 +1458,7 @@ static void static_generate_check_irq(arm_state *arm) /* generate a hash jump via the current mode and PC */ alloc_handle(drcuml, &arm->impstate->check_irq, "check_irq"); - UML_HANDLE(block, *arm->impstate->check_irq); // handle check_irq + UML_HANDLE(block, *arm->impstate->check_irq); // handle check_irq /* Exception priorities: Reset @@ -1470,135 +1470,135 @@ static void static_generate_check_irq(arm_state *arm) Software Interrupt */ - UML_ADD(block, I0, mem(&R15), 4); // add i0, PC, 4 ;insn pc + UML_ADD(block, I0, mem(&R15), 4); // add i0, PC, 4 ;insn pc // Data Abort - UML_TEST(block, mem(&arm->pendingAbtD, 1); // test pendingAbtD, 1 - UML_JMPc(block, COND_Z, nodabt = label++); // jmpz nodabt - - UML_ROLINS(block, mem(&GET_CPSR), eARM7_MODE_ABT, 0, MODE_FLAG) // rolins CPSR, eARM7_MODE_ABT, 0, MODE_FLAG - UML_MOV(block, mem(&GET_REGISTER(arm, 14)), I0); // mov LR, i0 - UML_MOV(block, mem(&GET_REGISTER(arm, SPSR)), mem(&GET_CPSR)); // mov SPSR, CPSR - UML_OR(block, mem(&GET_CPSR), mem(&GET_CPSR), I_MASK); // or CPSR, CPSR, I_MASK - UML_ROLAND(block, mem(&GET_CPSR), mem(&GET_CPSR), 0, ~T_MASK); // roland CPSR, CPSR, 0, ~T_MASK - UML_MOV(block, mem(&R15), 0x00000010); // mov PC, 0x10 (Data Abort vector address) - UML_MOV(block, mem(&arm->pendingAbtD, 0); // mov pendingAbtD, 0 - UML_JMP(block, irqadjust = label++); // jmp irqadjust + UML_TEST(block, mem(&arm->pendingAbtD, 1); // test pendingAbtD, 1 + UML_JMPc(block, COND_Z, nodabt = label++); // jmpz nodabt + + UML_ROLINS(block, mem(&GET_CPSR), eARM7_MODE_ABT, 0, MODE_FLAG) // rolins CPSR, eARM7_MODE_ABT, 0, MODE_FLAG + UML_MOV(block, mem(&GET_REGISTER(arm, 14)), I0); // mov LR, i0 + UML_MOV(block, mem(&GET_REGISTER(arm, SPSR)), mem(&GET_CPSR)); // mov SPSR, CPSR + UML_OR(block, mem(&GET_CPSR), mem(&GET_CPSR), I_MASK); // or CPSR, CPSR, I_MASK + UML_ROLAND(block, mem(&GET_CPSR), mem(&GET_CPSR), 0, ~T_MASK); // roland CPSR, CPSR, 0, ~T_MASK + UML_MOV(block, mem(&R15), 0x00000010); // mov PC, 0x10 (Data Abort vector address) + UML_MOV(block, mem(&arm->pendingAbtD, 0); // mov pendingAbtD, 0 + UML_JMP(block, irqadjust = label++); // jmp irqadjust UML_LABEL(block, nodabt); // nodabt: // FIQ - UML_TEST(block, mem(&arm->pendingFiq, 1); // test pendingFiq, 1 - UML_JMPc(block, COND_Z, nofiq = label++); // jmpz nofiq - UML_TEST(block, mem(&GET_CPSR), F_MASK); // test CPSR, F_MASK - UML_JMPc(block, COND_Z, nofiq); // jmpz nofiq + UML_TEST(block, mem(&arm->pendingFiq, 1); // test pendingFiq, 1 + UML_JMPc(block, COND_Z, nofiq = label++); // jmpz nofiq + UML_TEST(block, mem(&GET_CPSR), F_MASK); // test CPSR, F_MASK + UML_JMPc(block, COND_Z, nofiq); // jmpz nofiq - UML_MOV(block, mem(&GET_REGISTER(arm, 14)), I0); // mov LR, i0 - UML_MOV(block, mem(&GET_REGISTER(arm, SPSR)), mem(&GET_CPSR)); // mov SPSR, CPSR - UML_OR(block, mem(&GET_CPSR), mem(&GET_CPSR), I_MASK | F_MASK); // or CPSR, CPSR, I_MASK | F_MASK - UML_ROLAND(block, mem(&GET_CPSR), mem(&CPSR), 0, ~T_MASK); // roland CPSR, CPSR, 0, ~T_MASK - UML_MOV(block, mem(&R15), 0x0000001c); // mov PC, 0x1c (FIQ vector address) - UML_MOV(block, mem(&arm->pendingFiq, 0); // mov pendingFiq, 0 - UML_JMP(block, irqadjust); // jmp irqadjust + UML_MOV(block, mem(&GET_REGISTER(arm, 14)), I0); // mov LR, i0 + UML_MOV(block, mem(&GET_REGISTER(arm, SPSR)), mem(&GET_CPSR)); // mov SPSR, CPSR + UML_OR(block, mem(&GET_CPSR), mem(&GET_CPSR), I_MASK | F_MASK); // or CPSR, CPSR, I_MASK | F_MASK + UML_ROLAND(block, mem(&GET_CPSR), mem(&CPSR), 0, ~T_MASK); // roland CPSR, CPSR, 0, ~T_MASK + UML_MOV(block, mem(&R15), 0x0000001c); // mov PC, 0x1c (FIQ vector address) + UML_MOV(block, mem(&arm->pendingFiq, 0); // mov pendingFiq, 0 + UML_JMP(block, irqadjust); // jmp irqadjust - UML_LABEL(block, nofiq); // nofiq: + UML_LABEL(block, nofiq); // nofiq: // IRQ - UML_TEST(block, mem(&arm->pendingIrq, 1); // test pendingIrq, 1 - UML_JMPc(block, COND_Z, noirq = label++); // jmpz noirq - UML_TEST(block, mem(&GET_CPSR), I_MASK); // test CPSR, I_MASK - UML_JMPc(block, COND_Z, noirq); // jmpz noirq - - UML_MOV(block, mem(&GET_REGISTER(arm, 14)), I0); // mov LR, i0 - UML_TEST(block, mem(&GET_CPSR), SR_MODE32); // test CPSR, MODE32 - UML_JMPc(block, COND_NZ, irq32 = label++); // jmpnz irq32 - UML_AND(block, I1, I0, 0xf4000000); // and i1, i0, 0xf4000000 - UML_OR(block, mem(&R15), I1, 0x0800001a); // or PC, i1, 0x0800001a - UML_AND(block, I1, mem(&GET_CPSR), 0x0fffff3f); // and i1, CPSR, 0x0fffff3f - UML_ROLAND(block, I0, mem(&R15), 32-20, 0x0000000c); // roland i0, R15, 32-20, 0x0000000c - UML_ROLINS(block, I0, mem(&R15), 0, 0xf0000000); // rolins i0, R15, 0, 0xf0000000 - UML_OR(block, mem(&GET_CPSR), I0, I1); // or CPSR, i0, i1 - UML_JMP(block, irqadjust); // jmp irqadjust - - UML_LABEL(block, irq32); // irq32: - UML_MOV(block, mem(&GET_REGISTER(arm, SPSR)), mem(&GET_CPSR)); // mov SPSR, CPSR - UML_OR(block, mem(&GET_CPSR), mem(&GET_CPSR), I_MASK); // or CPSR, CPSR, I_MASK - UML_ROLAND(block, mem(&GET_CPSR), mem(&CPSR), 0, ~T_MASK); // roland CPSR, CPSR, 0, ~T_MASK - UML_MOV(block, mem(&R15), 0x00000018); // mov PC, 0x18 (IRQ vector address) - - UML_JMP(block, irqadjust); // jmp irqadjust - - UML_LABEL(block, noirq); // noirq: + UML_TEST(block, mem(&arm->pendingIrq, 1); // test pendingIrq, 1 + UML_JMPc(block, COND_Z, noirq = label++); // jmpz noirq + UML_TEST(block, mem(&GET_CPSR), I_MASK); // test CPSR, I_MASK + UML_JMPc(block, COND_Z, noirq); // jmpz noirq + + UML_MOV(block, mem(&GET_REGISTER(arm, 14)), I0); // mov LR, i0 + UML_TEST(block, mem(&GET_CPSR), SR_MODE32); // test CPSR, MODE32 + UML_JMPc(block, COND_NZ, irq32 = label++); // jmpnz irq32 + UML_AND(block, I1, I0, 0xf4000000); // and i1, i0, 0xf4000000 + UML_OR(block, mem(&R15), I1, 0x0800001a); // or PC, i1, 0x0800001a + UML_AND(block, I1, mem(&GET_CPSR), 0x0fffff3f); // and i1, CPSR, 0x0fffff3f + UML_ROLAND(block, I0, mem(&R15), 32-20, 0x0000000c); // roland i0, R15, 32-20, 0x0000000c + UML_ROLINS(block, I0, mem(&R15), 0, 0xf0000000); // rolins i0, R15, 0, 0xf0000000 + UML_OR(block, mem(&GET_CPSR), I0, I1); // or CPSR, i0, i1 + UML_JMP(block, irqadjust); // jmp irqadjust + + UML_LABEL(block, irq32); // irq32: + UML_MOV(block, mem(&GET_REGISTER(arm, SPSR)), mem(&GET_CPSR)); // mov SPSR, CPSR + UML_OR(block, mem(&GET_CPSR), mem(&GET_CPSR), I_MASK); // or CPSR, CPSR, I_MASK + UML_ROLAND(block, mem(&GET_CPSR), mem(&CPSR), 0, ~T_MASK); // roland CPSR, CPSR, 0, ~T_MASK + UML_MOV(block, mem(&R15), 0x00000018); // mov PC, 0x18 (IRQ vector address) + + UML_JMP(block, irqadjust); // jmp irqadjust + + UML_LABEL(block, noirq); // noirq: // Prefetch Abort - UML_TEST(block, mem(&arm->pendingAbtP, 1); // test pendingAbtP, 1 - UML_JMPc(block, COND_Z, nopabt = label++); // jmpz nopabt - - UML_ROLINS(block, mem(&GET_CPSR), eARM7_MODE_ABT, 0, MODE_FLAG) // rolins CPSR, eARM7_MODE_ABT, 0, MODE_FLAG - UML_MOV(block, mem(&GET_REGISTER(arm, 14)), I0); // mov LR, i0 - UML_MOV(block, mem(&GET_REGISTER(arm, SPSR)), mem(&GET_CPSR)); // mov SPSR, CPSR - UML_OR(block, mem(&GET_CPSR), mem(&GET_CPSR), I_MASK); // or CPSR, CPSR, I_MASK - UML_ROLAND(block, mem(&GET_CPSR), mem(&CPSR), 0, ~T_MASK); // roland CPSR, CPSR, 0, ~T_MASK - UML_MOV(block, mem(&R15), 0x0000000c); // mov PC, 0x0c (Prefetch Abort vector address) - UML_MOV(block, mem(&arm->pendingAbtP, 0); // mov pendingAbtP, 0 - UML_JMP(block, irqadjust); // jmp irqadjust + UML_TEST(block, mem(&arm->pendingAbtP, 1); // test pendingAbtP, 1 + UML_JMPc(block, COND_Z, nopabt = label++); // jmpz nopabt + + UML_ROLINS(block, mem(&GET_CPSR), eARM7_MODE_ABT, 0, MODE_FLAG) // rolins CPSR, eARM7_MODE_ABT, 0, MODE_FLAG + UML_MOV(block, mem(&GET_REGISTER(arm, 14)), I0); // mov LR, i0 + UML_MOV(block, mem(&GET_REGISTER(arm, SPSR)), mem(&GET_CPSR)); // mov SPSR, CPSR + UML_OR(block, mem(&GET_CPSR), mem(&GET_CPSR), I_MASK); // or CPSR, CPSR, I_MASK + UML_ROLAND(block, mem(&GET_CPSR), mem(&CPSR), 0, ~T_MASK); // roland CPSR, CPSR, 0, ~T_MASK + UML_MOV(block, mem(&R15), 0x0000000c); // mov PC, 0x0c (Prefetch Abort vector address) + UML_MOV(block, mem(&arm->pendingAbtP, 0); // mov pendingAbtP, 0 + UML_JMP(block, irqadjust); // jmp irqadjust UML_LABEL(block, nopabt); // nopabt: // Undefined instruction - UML_TEST(block, mem(&arm->pendingUnd, 1); // test pendingUnd, 1 - UML_JMPc(block, COND_Z, nopabt = label++); // jmpz nound - - UML_ROLINS(block, mem(&GET_CPSR), eARM7_MODE_UND, 0, MODE_FLAG) // rolins CPSR, eARM7_MODE_UND, 0, MODE_FLAG - UML_MOV(block, I1, -4); // mov i1, -4 - UML_TEST(block, mem(&GET_CPSR), T_MASK); // test CPSR, T_MASK - UML_MOVc(block, COND_NZ, I1, -2); // movnz i1, -2 - UML_ADD(block, mem(&GET_REGISTER(arm, 14)), I0, I1); // add LR, i0, i1 - UML_MOV(block, mem(&GET_REGISTER(arm, SPSR)), mem(&GET_CPSR)); // mov SPSR, CPSR - UML_OR(block, mem(&GET_CPSR), mem(&GET_CPSR), I_MASK); // or CPSR, CPSR, I_MASK - UML_ROLAND(block, mem(&GET_CPSR), mem(&CPSR), 0, ~T_MASK); // roland CPSR, CPSR, 0, ~T_MASK - UML_MOV(block, mem(&R15), 0x00000004); // mov PC, 0x0c (Undefined Insn vector address) - UML_MOV(block, mem(&arm->pendingUnd, 0); // mov pendingUnd, 0 - UML_JMP(block, irqadjust); // jmp irqadjust + UML_TEST(block, mem(&arm->pendingUnd, 1); // test pendingUnd, 1 + UML_JMPc(block, COND_Z, nopabt = label++); // jmpz nound + + UML_ROLINS(block, mem(&GET_CPSR), eARM7_MODE_UND, 0, MODE_FLAG) // rolins CPSR, eARM7_MODE_UND, 0, MODE_FLAG + UML_MOV(block, I1, -4); // mov i1, -4 + UML_TEST(block, mem(&GET_CPSR), T_MASK); // test CPSR, T_MASK + UML_MOVc(block, COND_NZ, I1, -2); // movnz i1, -2 + UML_ADD(block, mem(&GET_REGISTER(arm, 14)), I0, I1); // add LR, i0, i1 + UML_MOV(block, mem(&GET_REGISTER(arm, SPSR)), mem(&GET_CPSR)); // mov SPSR, CPSR + UML_OR(block, mem(&GET_CPSR), mem(&GET_CPSR), I_MASK); // or CPSR, CPSR, I_MASK + UML_ROLAND(block, mem(&GET_CPSR), mem(&CPSR), 0, ~T_MASK); // roland CPSR, CPSR, 0, ~T_MASK + UML_MOV(block, mem(&R15), 0x00000004); // mov PC, 0x0c (Undefined Insn vector address) + UML_MOV(block, mem(&arm->pendingUnd, 0); // mov pendingUnd, 0 + UML_JMP(block, irqadjust); // jmp irqadjust UML_LABEL(block, nopabt); // nopabt: // Software Interrupt - UML_TEST(block, mem(&arm->pendingSwi, 1); // test pendingSwi, 1 - UML_JMPc(block, COND_Z, done = label++); // jmpz done - - UML_ROLINS(block, mem(&GET_CPSR), eARM7_MODE_SVC, 0, MODE_FLAG) // rolins CPSR, eARM7_MODE_SVC, 0, MODE_FLAG - UML_MOV(block, I1, -4); // mov i1, -4 - UML_TEST(block, mem(&GET_CPSR), T_MASK); // test CPSR, T_MASK - UML_MOVc(block, COND_NZ, I1, -2); // movnz i1, -2 - UML_ADD(block, mem(&GET_REGISTER(arm, 14)), I0, I1); // add LR, i0, i1 - - UML_TEST(block, mem(&GET_CPSR), SR_MODE32); // test CPSR, MODE32 - UML_JMPc(block, COND_NZ, swi32 = label++); // jmpnz swi32 - UML_AND(block, I1, I0, 0xf4000000); // and i1, i0, 0xf4000000 - UML_OR(block, mem(&R15), I1, 0x0800001b); // or PC, i1, 0x0800001b - UML_AND(block, I1, mem(&GET_CPSR), 0x0fffff3f); // and i1, CPSR, 0x0fffff3f - UML_ROLAND(block, I0, mem(&R15), 32-20, 0x0000000c); // roland i0, R15, 32-20, 0x0000000c - UML_ROLINS(block, I0, mem(&R15), 0, 0xf0000000); // rolins i0, R15, 0, 0xf0000000 - UML_OR(block, mem(&GET_CPSR), I0, I1); // or CPSR, i0, i1 - UML_MOV(block, mem(&arm->pendingSwi, 0); // mov pendingSwi, 0 - UML_JMP(block, irqadjust); // jmp irqadjust - - UML_LABEL(block, swi32); // irq32: - UML_MOV(block, mem(&GET_REGISTER(arm, SPSR)), mem(&GET_CPSR)); // mov SPSR, CPSR - UML_OR(block, mem(&GET_CPSR), mem(&GET_CPSR), I_MASK); // or CPSR, CPSR, I_MASK - UML_ROLAND(block, mem(&GET_CPSR), mem(&CPSR), 0, ~T_MASK); // roland CPSR, CPSR, 0, ~T_MASK - UML_MOV(block, mem(&R15), 0x00000008); // mov PC, 0x08 (SWI vector address) - UML_MOV(block, mem(&arm->pendingSwi, 0); // mov pendingSwi, 0 - UML_JMP(block, irqadjust); // jmp irqadjust - - UML_LABEL(block, irqadjust); // irqadjust: - UML_MOV(block, I1, 0); // mov i1, 0 - UML_TEST(block, mem(&COPRO_CTRL), COPRO_CTRL_MMU_EN | COPRO_CTRL_INTVEC_ADJUST); // test COPRO_CTRL, MMU_EN | INTVEC_ADJUST - UML_MOVc(block, COND_NZ, I1, 0xffff0000); // movnz i1, 0xffff0000 - UML_OR(block, mem(&R15), mem(R15), I1); // or PC, i1 - - UML_LABEL(block, done); // done: + UML_TEST(block, mem(&arm->pendingSwi, 1); // test pendingSwi, 1 + UML_JMPc(block, COND_Z, done = label++); // jmpz done + + UML_ROLINS(block, mem(&GET_CPSR), eARM7_MODE_SVC, 0, MODE_FLAG) // rolins CPSR, eARM7_MODE_SVC, 0, MODE_FLAG + UML_MOV(block, I1, -4); // mov i1, -4 + UML_TEST(block, mem(&GET_CPSR), T_MASK); // test CPSR, T_MASK + UML_MOVc(block, COND_NZ, I1, -2); // movnz i1, -2 + UML_ADD(block, mem(&GET_REGISTER(arm, 14)), I0, I1); // add LR, i0, i1 + + UML_TEST(block, mem(&GET_CPSR), SR_MODE32); // test CPSR, MODE32 + UML_JMPc(block, COND_NZ, swi32 = label++); // jmpnz swi32 + UML_AND(block, I1, I0, 0xf4000000); // and i1, i0, 0xf4000000 + UML_OR(block, mem(&R15), I1, 0x0800001b); // or PC, i1, 0x0800001b + UML_AND(block, I1, mem(&GET_CPSR), 0x0fffff3f); // and i1, CPSR, 0x0fffff3f + UML_ROLAND(block, I0, mem(&R15), 32-20, 0x0000000c); // roland i0, R15, 32-20, 0x0000000c + UML_ROLINS(block, I0, mem(&R15), 0, 0xf0000000); // rolins i0, R15, 0, 0xf0000000 + UML_OR(block, mem(&GET_CPSR), I0, I1); // or CPSR, i0, i1 + UML_MOV(block, mem(&arm->pendingSwi, 0); // mov pendingSwi, 0 + UML_JMP(block, irqadjust); // jmp irqadjust + + UML_LABEL(block, swi32); // irq32: + UML_MOV(block, mem(&GET_REGISTER(arm, SPSR)), mem(&GET_CPSR)); // mov SPSR, CPSR + UML_OR(block, mem(&GET_CPSR), mem(&GET_CPSR), I_MASK); // or CPSR, CPSR, I_MASK + UML_ROLAND(block, mem(&GET_CPSR), mem(&CPSR), 0, ~T_MASK); // roland CPSR, CPSR, 0, ~T_MASK + UML_MOV(block, mem(&R15), 0x00000008); // mov PC, 0x08 (SWI vector address) + UML_MOV(block, mem(&arm->pendingSwi, 0); // mov pendingSwi, 0 + UML_JMP(block, irqadjust); // jmp irqadjust + + UML_LABEL(block, irqadjust); // irqadjust: + UML_MOV(block, I1, 0); // mov i1, 0 + UML_TEST(block, mem(&COPRO_CTRL), COPRO_CTRL_MMU_EN | COPRO_CTRL_INTVEC_ADJUST); // test COPRO_CTRL, MMU_EN | INTVEC_ADJUST + UML_MOVc(block, COND_NZ, I1, 0xffff0000); // movnz i1, 0xffff0000 + UML_OR(block, mem(&R15), mem(R15), I1); // or PC, i1 + + UML_LABEL(block, done); // done: block->end(); }; @@ -1620,7 +1620,7 @@ static void static_generate_nocode_handler(arm_state *arm) alloc_handle(drcuml, &arm->impstate->nocode, "nocode"); UML_HANDLE(block, *arm->impstate->nocode); // handle nocode UML_GETEXP(block, I0); // getexp i0 - UML_MOV(block, mem(&R15), I0); // mov [pc],i0 + UML_MOV(block, mem(&R15), I0); // mov [pc],i0 save_fast_iregs(arm, block); UML_EXIT(block, EXECUTE_MISSING_CODE); // exit EXECUTE_MISSING_CODE @@ -1643,9 +1643,9 @@ static void static_generate_out_of_cycles(arm_state *arm) /* generate a hash jump via the current mode and PC */ alloc_handle(drcuml, &arm->impstate->out_of_cycles, "out_of_cycles"); - UML_HANDLE(block, *arm->impstate->out_of_cycles); // handle out_of_cycles + UML_HANDLE(block, *arm->impstate->out_of_cycles); // handle out_of_cycles UML_GETEXP(block, I0); // getexp i0 - UML_MOV(block, mem(&R15), I0); // mov <pc>,i0 + UML_MOV(block, mem(&R15), I0); // mov <pc>,i0 save_fast_iregs(arm, block); UML_EXIT(block, EXECUTE_OUT_OF_CYCLES); // exit EXECUTE_OUT_OF_CYCLES @@ -1672,63 +1672,63 @@ static void static_generate_detect_fault(arm_state *arm, code_handle **handleptr /* add a global entry for this */ alloc_handle(drcuml, &arm->impstate->detect_fault, "detect_fault"); - UML_HANDLE(block, *arm->impstate->detect_fault); // handle detect_fault + UML_HANDLE(block, *arm->impstate->detect_fault); // handle detect_fault - UML_ROLAND(block, I6, I4, 32-4, 0x0f<<1); // roland i6, i4, 32-4, 0xf<<1 - UML_ROLAND(block, I6, mem(&COPRO_DOMAIN_ACCESS_CONTROL), I6, 3);// roland i6, COPRO_DOMAIN_ACCESS_CONTROL, i6, 3 + UML_ROLAND(block, I6, I4, 32-4, 0x0f<<1); // roland i6, i4, 32-4, 0xf<<1 + UML_ROLAND(block, I6, mem(&COPRO_DOMAIN_ACCESS_CONTROL), I6, 3);// roland i6, COPRO_DOMAIN_ACCESS_CONTROL, i6, 3 // if permission == 3, FAULT_NONE - UML_CMP(block, I6, 3); // cmp i6, 3 - UML_MOVc(block, COND_E, I6, FAULT_NONE); // move i6, FAULT_NONE - UML_JMPc(block, COND_E, donefault = label++); // jmpe donefault + UML_CMP(block, I6, 3); // cmp i6, 3 + UML_MOVc(block, COND_E, I6, FAULT_NONE); // move i6, FAULT_NONE + UML_JMPc(block, COND_E, donefault = label++); // jmpe donefault // if permission == 0 || permission == 2, FAULT_DOMAIN - UML_CMP(block, I6, 1); // cmp i6, 1 - UML_MOVc(block, COND_NE, I6, FAULT_DOMAIN); // movne i6, FAULT_DOMAIN - UML_JMPc(block, COND_NE, donefault); // jmpne donefault + UML_CMP(block, I6, 1); // cmp i6, 1 + UML_MOVc(block, COND_NE, I6, FAULT_DOMAIN); // movne i6, FAULT_DOMAIN + UML_JMPc(block, COND_NE, donefault); // jmpne donefault // if permission == 1 - UML_CMP(block, I5, 3); // cmp i5, 3 - UML_MOVc(block, COND_E, I6, FAULT_NONE); // move i6, FAULT_NONE - UML_JMPc(block, COND_E, donefault); // jmpe donefault - UML_CMP(block, I5, 0); // cmp i5, 1 - UML_JMPc(block, COND_NE, checkuser = label++); // jmpne checkuser - UML_ROLAND(block, I6, mem(&COPRO_CTRL), // roland i6, COPRO_CTRL, 32 - COPRO_CTRL_SYSTEM_SHIFT, - 32 - COPRO_CTRL_SYSTEM_SHIFT, // COPRO_CTRL_SYSTEM | COPRO_CTRL_ROM + UML_CMP(block, I5, 3); // cmp i5, 3 + UML_MOVc(block, COND_E, I6, FAULT_NONE); // move i6, FAULT_NONE + UML_JMPc(block, COND_E, donefault); // jmpe donefault + UML_CMP(block, I5, 0); // cmp i5, 1 + UML_JMPc(block, COND_NE, checkuser = label++); // jmpne checkuser + UML_ROLAND(block, I6, mem(&COPRO_CTRL), // roland i6, COPRO_CTRL, 32 - COPRO_CTRL_SYSTEM_SHIFT, + 32 - COPRO_CTRL_SYSTEM_SHIFT, // COPRO_CTRL_SYSTEM | COPRO_CTRL_ROM COPRO_CTRL_SYSTEM | COPRO_CTRL_ROM); // if s == 0 && r == 0, FAULT_PERMISSION - UML_CMP(block, I6, 0); // cmp i6, 0 - UML_MOVc(block, COND_E, I6, FAULT_PERMISSION); // move i6, FAULT_PERMISSION - UML_JMPc(block, COND_E, donefault); // jmpe donefault + UML_CMP(block, I6, 0); // cmp i6, 0 + UML_MOVc(block, COND_E, I6, FAULT_PERMISSION); // move i6, FAULT_PERMISSION + UML_JMPc(block, COND_E, donefault); // jmpe donefault // if s == 1 && r == 1, FAULT_PERMISSION - UML_CMP(block, I6, 3); // cmp i6, 3 - UML_MOVc(block, COND_E, I6, FAULT_PERMISSION); // move i6, FAULT_PERMISSION - UML_JMPc(block, COND_E, donefault); // jmpe donefault + UML_CMP(block, I6, 3); // cmp i6, 3 + UML_MOVc(block, COND_E, I6, FAULT_PERMISSION); // move i6, FAULT_PERMISSION + UML_JMPc(block, COND_E, donefault); // jmpe donefault // if flags & TLB_WRITE, FAULT_PERMISSION - UML_TEST(block, I2, ARM7_TLB_WRITE); // test i2, ARM7_TLB_WRITE - UML_MOVc(block, COND_NZ, I6, FAULT_PERMISSION); // move i6, FAULT_PERMISSION - UML_JMPc(block, COND_NZ, donefault); // jmpe donefault + UML_TEST(block, I2, ARM7_TLB_WRITE); // test i2, ARM7_TLB_WRITE + UML_MOVc(block, COND_NZ, I6, FAULT_PERMISSION); // move i6, FAULT_PERMISSION + UML_JMPc(block, COND_NZ, donefault); // jmpe donefault // if r == 1 && s == 0, FAULT_NONE - UML_CMP(block, I6, 2); // cmp i6, 2 - UML_MOVc(block, COND_E, I6, FAULT_NONE); // move i6, FAULT_NONE - UML_JMPc(block, COND_E, donefault); // jmpe donefault - UML_AND(block, I6, mem(&GET_CPSR), MODE_FLAG); // and i6, GET_CPSR, MODE_FLAG - UML_CMP(block, I6, eARM7_MODE_USER); // cmp i6, eARM7_MODE_USER + UML_CMP(block, I6, 2); // cmp i6, 2 + UML_MOVc(block, COND_E, I6, FAULT_NONE); // move i6, FAULT_NONE + UML_JMPc(block, COND_E, donefault); // jmpe donefault + UML_AND(block, I6, mem(&GET_CPSR), MODE_FLAG); // and i6, GET_CPSR, MODE_FLAG + UML_CMP(block, I6, eARM7_MODE_USER); // cmp i6, eARM7_MODE_USER // if r == 0 && s == 1 && usermode, FAULT_PERMISSION - UML_MOVc(block, COND_E, I6, FAULT_PERMISSION); // move i6, FAULT_PERMISSION - UML_MOVc(block, COND_NE, I6, FAULT_NONE); // movne i6, FAULT_NONE - UML_JMP(block, donefault); // jmp donefault + UML_MOVc(block, COND_E, I6, FAULT_PERMISSION); // move i6, FAULT_PERMISSION + UML_MOVc(block, COND_NE, I6, FAULT_NONE); // movne i6, FAULT_NONE + UML_JMP(block, donefault); // jmp donefault - UML_LABEL(block, checkuser); // checkuser: + UML_LABEL(block, checkuser); // checkuser: // if !write, FAULT_NONE - UML_TEST(block, I2, ARM7_TLB_WRITE); // test i2, ARM7_TLB_WRITE - UML_MOVc(block, COND_Z, I6, FAULT_NONE); // movz i6, FAULT_NONE - UML_JMPc(block, COND_Z, donefault); // jmp donefault - UML_AND(block, I6, mem(&GET_CPSR), MODE_FLAG); // and i6, GET_CPSR, MODE_FLAG - UML_CMP(block, I6, eARM7_MODE_USER); // cmp i6, eARM7_MODE_USER - UML_MOVc(block, COND_E, I6, FAULT_PERMISSION); // move i6, FAULT_PERMISSION - UML_MOVc(block, COND_NE, I6, FAULT_NONE); // move i6, FAULT_NONE - - UML_LABEL(block, donefault); // donefault: - UML_RET(block); // ret + UML_TEST(block, I2, ARM7_TLB_WRITE); // test i2, ARM7_TLB_WRITE + UML_MOVc(block, COND_Z, I6, FAULT_NONE); // movz i6, FAULT_NONE + UML_JMPc(block, COND_Z, donefault); // jmp donefault + UML_AND(block, I6, mem(&GET_CPSR), MODE_FLAG); // and i6, GET_CPSR, MODE_FLAG + UML_CMP(block, I6, eARM7_MODE_USER); // cmp i6, eARM7_MODE_USER + UML_MOVc(block, COND_E, I6, FAULT_PERMISSION); // move i6, FAULT_PERMISSION + UML_MOVc(block, COND_NE, I6, FAULT_NONE); // move i6, FAULT_NONE + + UML_LABEL(block, donefault); // donefault: + UML_RET(block); // ret } /*------------------------------------------------------------------ @@ -1761,179 +1761,179 @@ static void static_generate_tlb_translate(arm_state *arm, code_handle **handlept block = drcuml->begin_block(170); alloc_handle(drcuml, &arm->impstate->tlb_translate, "tlb_translate"); - UML_HANDLE(block, *arm->impstate->tlb_translate); // handle tlb_translate + UML_HANDLE(block, *arm->impstate->tlb_translate); // handle tlb_translate // I3: vaddr - UML_CMP(block, I0, 32 * 1024 * 1024); // cmp i0, 32*1024*1024 - UML_JMPc(block, COND_GE, nopid = label++); // jmpge nopid - UML_AND(block, I3, mem(&COPRO_FCSE_PID), 0xfe000000); // and i3, COPRO_FCSE_PID, 0xfe000000 - UML_ADD(block, I3, I3, I0); // add i3, i3, i0 + UML_CMP(block, I0, 32 * 1024 * 1024); // cmp i0, 32*1024*1024 + UML_JMPc(block, COND_GE, nopid = label++); // jmpge nopid + UML_AND(block, I3, mem(&COPRO_FCSE_PID), 0xfe000000); // and i3, COPRO_FCSE_PID, 0xfe000000 + UML_ADD(block, I3, I3, I0); // add i3, i3, i0 // I4: desc_lvl1 - UML_AND(block, I4, mem(&COPRO_TLB_BASE), COPRO_TLB_BASE_MASK); // and i4, COPRO_TLB_BASE, COPRO_TLB_BASE_MASK - UML_ROLINS(block, I4, I3, 32 - COPRO_TLB_VADDR_FLTI_MASK_SHIFT, // rolins i4, i3, 32-COPRO_TLB_VADDR_FLTI_MASK_SHIFT, - COPRO_TLB_VADDR_FLTI_MASK); // COPRO_TLB_VADDR_FLTI_MASK - UML_READ(block, I4, I4, SIZE_DWORD, SPACE_PROGRAM); // read32 i4, i4, PROGRAM + UML_AND(block, I4, mem(&COPRO_TLB_BASE), COPRO_TLB_BASE_MASK); // and i4, COPRO_TLB_BASE, COPRO_TLB_BASE_MASK + UML_ROLINS(block, I4, I3, 32 - COPRO_TLB_VADDR_FLTI_MASK_SHIFT, // rolins i4, i3, 32-COPRO_TLB_VADDR_FLTI_MASK_SHIFT, + COPRO_TLB_VADDR_FLTI_MASK); // COPRO_TLB_VADDR_FLTI_MASK + UML_READ(block, I4, I4, SIZE_DWORD, SPACE_PROGRAM); // read32 i4, i4, PROGRAM // I7: desc_lvl1 & 3 - UML_AND(block, I7, I4, 3); // and i7, i4, 3 + UML_AND(block, I7, I4, 3); // and i7, i4, 3 - UML_CMP(block, I7, COPRO_TLB_UNMAPPED); // cmp i7, COPRO_TLB_UNMAPPED - UML_JMPc(block, COND_NE, nounmapped = label++); // jmpne nounmapped + UML_CMP(block, I7, COPRO_TLB_UNMAPPED); // cmp i7, COPRO_TLB_UNMAPPED + UML_JMPc(block, COND_NE, nounmapped = label++); // jmpne nounmapped // TLB Unmapped - UML_TEST(block, I2, ARM7_TLB_ABORT_D); // test i2, ARM7_TLB_ABORT_D - UML_MOVc(block, COND_E, mem(&COPRO_FAULT_STATUS_D), (5 << 0)); // move COPRO_FAULT_STATUS_D, (5 << 0) - UML_MOVc(block, COND_E, mem(&COPRO_FAULT_ADDRESS), I3); // move COPRO_FAULT_ADDRESS, i3 - UML_MOVc(block, COND_E, mem(&arm->pendingAbtD), 1); // move pendingAbtD, 1 - UML_MOVc(block, COND_E, I2, 0); // move i2, 0 + UML_TEST(block, I2, ARM7_TLB_ABORT_D); // test i2, ARM7_TLB_ABORT_D + UML_MOVc(block, COND_E, mem(&COPRO_FAULT_STATUS_D), (5 << 0)); // move COPRO_FAULT_STATUS_D, (5 << 0) + UML_MOVc(block, COND_E, mem(&COPRO_FAULT_ADDRESS), I3); // move COPRO_FAULT_ADDRESS, i3 + UML_MOVc(block, COND_E, mem(&arm->pendingAbtD), 1); // move pendingAbtD, 1 + UML_MOVc(block, COND_E, I2, 0); // move i2, 0 UML_RETc(block, COND_E); // rete - UML_TEST(block, I2, ARM7_TLB_ABORT_P); // test i2, ARM7_TLB_ABORT_P - UML_MOVc(block, COND_E, mem(&arm->pendingAbtP), 1); // move pendingAbtP, 1 - UML_MOV(block, I2, 0); // mov i2, 0 - UML_RET(block); // ret + UML_TEST(block, I2, ARM7_TLB_ABORT_P); // test i2, ARM7_TLB_ABORT_P + UML_MOVc(block, COND_E, mem(&arm->pendingAbtP), 1); // move pendingAbtP, 1 + UML_MOV(block, I2, 0); // mov i2, 0 + UML_RET(block); // ret - UML_LABEL(block, nounmapped); // nounmapped: - UML_CMP(block, I7, COPRO_TLB_COARSE_TABLE); // cmp i7, COPRO_TLB_COARSE_TABLE - UML_JMPc(block, COND_NE, nocoarse = label++); // jmpne nocoarse + UML_LABEL(block, nounmapped); // nounmapped: + UML_CMP(block, I7, COPRO_TLB_COARSE_TABLE); // cmp i7, COPRO_TLB_COARSE_TABLE + UML_JMPc(block, COND_NE, nocoarse = label++); // jmpne nocoarse - UML_ROLAND(block, I5, I4, 32-4, 0x0f<<1); // roland i5, i4, 32-4, 0xf<<1 - UML_ROLAND(block, I5, mem(&COPRO_DOMAIN_ACCESS_CONTROL), I5, 3);// roland i5, COPRO_DOMAIN_ACCESS_CONTROL, i5, 3 - UML_CMP(block, I5, 1); // cmp i5, 1 - UML_JMPc(block, COND_E, level2 = label++); // jmpe level2 - UML_CMP(block, I5, 3); // cmp i5, 3 - UML_JMPc(block, COND_NE, nofine = label++); // jmpne nofine - UML_LABEL(block, level2); // level2: + UML_ROLAND(block, I5, I4, 32-4, 0x0f<<1); // roland i5, i4, 32-4, 0xf<<1 + UML_ROLAND(block, I5, mem(&COPRO_DOMAIN_ACCESS_CONTROL), I5, 3);// roland i5, COPRO_DOMAIN_ACCESS_CONTROL, i5, 3 + UML_CMP(block, I5, 1); // cmp i5, 1 + UML_JMPc(block, COND_E, level2 = label++); // jmpe level2 + UML_CMP(block, I5, 3); // cmp i5, 3 + UML_JMPc(block, COND_NE, nofine = label++); // jmpne nofine + UML_LABEL(block, level2); // level2: // I7: desc_level2 - UML_AND(block, I7, I4, COPRO_TLB_CFLD_ADDR_MASK); // and i7, i4, COPRO_TLB_CFLD_ADDR_MASK - UML_ROLINS(block, I7, I3, 32 - COPRO_TLB_VADDR_CSLTI_MASK_SHIFT,// rolins i7, i3, 32 - COPRO_TLB_VADDR_CSLTI_MASK_SHIFT - COPRO_TLB_VADDR_CSLTI_MASK); // COPRO_TLB_VADDR_CSLTI_MASK - UML_READ(block, I7, I7, SIZE_DWORD, SPACE_PROGRAM); // read32 i7, i7, PROGRAM - UML_JMP(block, nofine); // jmp nofine + UML_AND(block, I7, I4, COPRO_TLB_CFLD_ADDR_MASK); // and i7, i4, COPRO_TLB_CFLD_ADDR_MASK + UML_ROLINS(block, I7, I3, 32 - COPRO_TLB_VADDR_CSLTI_MASK_SHIFT,// rolins i7, i3, 32 - COPRO_TLB_VADDR_CSLTI_MASK_SHIFT + COPRO_TLB_VADDR_CSLTI_MASK); // COPRO_TLB_VADDR_CSLTI_MASK + UML_READ(block, I7, I7, SIZE_DWORD, SPACE_PROGRAM); // read32 i7, i7, PROGRAM + UML_JMP(block, nofine); // jmp nofine - UML_LABEL(block, nocoarse); // nocoarse: - UML_CMP(block, I7, COPRO_TLB_SECTION_TABLE); // cmp i7, COPRO_TLB_SECTION_TABLE - UML_JMPc(block, COND_NE, nosection = label++); // jmpne nosection + UML_LABEL(block, nocoarse); // nocoarse: + UML_CMP(block, I7, COPRO_TLB_SECTION_TABLE); // cmp i7, COPRO_TLB_SECTION_TABLE + UML_JMPc(block, COND_NE, nosection = label++); // jmpne nosection - UML_ROLAND(block, I5, I4, 32-10, 3); // roland i7, i4, 32-10, 3 + UML_ROLAND(block, I5, I4, 32-10, 3); // roland i7, i4, 32-10, 3 // result in I6 - UML_CALLH(block, *arm->impstate->detect_fault); // callh detect_fault - UML_CMP(block, I6, FAULT_NONE); // cmp i6, FAULT_NONE - UML_JMPc(block, COND_NE, handlefault = label++); // jmpne handlefault + UML_CALLH(block, *arm->impstate->detect_fault); // callh detect_fault + UML_CMP(block, I6, FAULT_NONE); // cmp i6, FAULT_NONE + UML_JMPc(block, COND_NE, handlefault = label++); // jmpne handlefault // no fault, return translated address - UML_AND(block, I0, I3, ~COPRO_TLB_SECTION_PAGE_MASK); // and i0, i3, ~COPRO_TLB_SECTION_PAGE_MASK - UML_ROLINS(block, I0, I4, 0, COPRO_TLB_SECTION_PAGE_MASK); // rolins i0, i4, COPRO_TLB_SECTION_PAGE_MASK - UML_MOV(block, I2, 1); // mov i2, 1 - UML_RET(block); // ret - - UML_LABEL(block, handlefault); // handlefault: - UML_TEST(block, I2, ARM7_TLB_ABORT_D); // test i2, ARM7_TLB_ABORT_D - UML_JMPc(block, COND_Z, prefetch = label++); // jmpz prefetch - UML_MOV(block, mem(&COPRO_FAULT_ADDRESS), I3); // mov COPRO_FAULT_ADDRESS, i3 - UML_MOV(block, mem(&arm->pendingAbtD), 1); // mov arm->pendingAbtD, 1 - UML_ROLAND(block, I5, I4, 31, 0xf0); // roland i5, i4, 31, 0xf0 - UML_CMP(block, I6, FAULT_DOMAIN); // cmp i6, FAULT_DOMAIN - UML_MOVc(block, COND_E, I6, 9 << 0); // move i6, 9 << 0 - UML_MOVc(block, COND_NE, I6, 13 << 0); // movne i6, 13 << 0 - UML_OR(block, mem(&COPRO_FAULT_STATUS_D), I5, I6); // or COPRO_FAULT_STATUS_D, i5, i6 - UML_MOV(block, I2, 0); // mov i2, 0 - UML_RET(block); // ret - - UML_LABEL(block, prefetch); // prefetch: - UML_MOV(block, mem(&arm->pendingAbtP), 1); // mov arm->pendingAbtP, 1 - UML_MOV(block, I2, 0); // mov i2, 0 - UML_RET(block); // ret - - UML_LABEL(block, nosection); // nosection: - UML_CMP(block, I7, COPRO_TLB_FINE_TABLE); // cmp i7, COPRO_TLB_FINE_TABLE - UML_JMPc(block, COND_NE, nofine); // jmpne nofine + UML_AND(block, I0, I3, ~COPRO_TLB_SECTION_PAGE_MASK); // and i0, i3, ~COPRO_TLB_SECTION_PAGE_MASK + UML_ROLINS(block, I0, I4, 0, COPRO_TLB_SECTION_PAGE_MASK); // rolins i0, i4, COPRO_TLB_SECTION_PAGE_MASK + UML_MOV(block, I2, 1); // mov i2, 1 + UML_RET(block); // ret + + UML_LABEL(block, handlefault); // handlefault: + UML_TEST(block, I2, ARM7_TLB_ABORT_D); // test i2, ARM7_TLB_ABORT_D + UML_JMPc(block, COND_Z, prefetch = label++); // jmpz prefetch + UML_MOV(block, mem(&COPRO_FAULT_ADDRESS), I3); // mov COPRO_FAULT_ADDRESS, i3 + UML_MOV(block, mem(&arm->pendingAbtD), 1); // mov arm->pendingAbtD, 1 + UML_ROLAND(block, I5, I4, 31, 0xf0); // roland i5, i4, 31, 0xf0 + UML_CMP(block, I6, FAULT_DOMAIN); // cmp i6, FAULT_DOMAIN + UML_MOVc(block, COND_E, I6, 9 << 0); // move i6, 9 << 0 + UML_MOVc(block, COND_NE, I6, 13 << 0); // movne i6, 13 << 0 + UML_OR(block, mem(&COPRO_FAULT_STATUS_D), I5, I6); // or COPRO_FAULT_STATUS_D, i5, i6 + UML_MOV(block, I2, 0); // mov i2, 0 + UML_RET(block); // ret + + UML_LABEL(block, prefetch); // prefetch: + UML_MOV(block, mem(&arm->pendingAbtP), 1); // mov arm->pendingAbtP, 1 + UML_MOV(block, I2, 0); // mov i2, 0 + UML_RET(block); // ret + + UML_LABEL(block, nosection); // nosection: + UML_CMP(block, I7, COPRO_TLB_FINE_TABLE); // cmp i7, COPRO_TLB_FINE_TABLE + UML_JMPc(block, COND_NE, nofine); // jmpne nofine // Not yet implemented - UML_MOV(block, I2, 1); // mov i2, 1 - UML_RET(block); // ret + UML_MOV(block, I2, 1); // mov i2, 1 + UML_RET(block); // ret - UML_LABEL(block, nofine); // nofine: + UML_LABEL(block, nofine); // nofine: // I7: desc_lvl2 - UML_AND(block, I6, I7, 3); // and i6, i7, 3 - UML_CMP(block, I6, COPRO_TLB_UNMAPPED); // cmp i6, COPRO_TLB_UNMAPPED - UML_JMPc(block, COND_NE, nounmapped2 = label++); // jmpne nounmapped2 - - UML_TEST(block, I2, ARM7_TLB_ABORT_D); // test i2, ARM7_TLB_ABORT_D - UML_JMPc(block, COND_Z, prefetch2 = label++); // jmpz prefetch2 - UML_MOV(block, mem(&COPRO_FAULT_ADDRESS), I3); // mov COPRO_FAULT_ADDRESS, i3 - UML_MOV(block, mem(&arm->pendingAbtD), 1); // mov arm->pendingAbtD, 1 - UML_ROLAND(block, I5, I4, 31, 0xf0); // roland i5, i4, 31, 0xf0 - UML_OR(block, I5, I5, 7 << 0); // or i5, i5, 7 << 0 - UML_OR(block, mem(&COPRO_FAULT_STATUS_D), I5, I6); // or COPRO_FAULT_STATUS_D, i5, i6 - UML_MOV(block, I2, 0); // mov i2, 0 - UML_RET(block); // ret - - UML_LABEL(block, prefetch2); // prefetch2: - UML_MOV(block, mem(&arm->pendingAbtP), 1); // mov arm->pendingAbtP, 1 - UML_MOV(block, I2, 0); // mov i2, 0 - UML_RET(block); // ret - - UML_LABEL(block, nounmapped2); // nounmapped2: - UML_CMP(block, I6, COPRO_TLB_LARGE_PAGE); // cmp i6, COPRO_TLB_LARGE_PAGE - UML_JMPc(block, COND_NE, nolargepage = label++); // jmpne nolargepage - - UML_AND(block, I0, I3, ~COPRO_TLB_LARGE_PAGE_MASK); // and i0, i3, ~COPRO_TLB_LARGE_PAGE_MASK - UML_ROLINS(block, I0, I7, 0, COPRO_TLB_LARGE_PAGE_MASK); // rolins i0, i7, 0, COPRO_TLB_LARGE_PAGE_MASK - UML_MOV(block, I2, 1); // mov i2, 1 - UML_RET(block); // ret - - UML_LABEL(block, nolargepage); // nolargepage: - UML_CMP(block, I6, COPRO_TLB_SMALL_PAGE); // cmp i6, COPRO_TLB_SMALL_PAGE - UML_JMPc(block, COND_NE, nosmallpage = label++); // jmpne nosmallpage - - UML_ROLAND(block, I5, I3, 32-9, 3<<1); // roland i5, i3, 32-9, 3<<1 - UML_ROLAND(block, I6, I7, 32-4, 0xff); // roland i6, i7, 32-4, 0xff - UML_SHR(block, I5, I7, I5); // shr i5, i7, i5 - UML_AND(block, I5, I5, 3); // and i5, i5, 3 + UML_AND(block, I6, I7, 3); // and i6, i7, 3 + UML_CMP(block, I6, COPRO_TLB_UNMAPPED); // cmp i6, COPRO_TLB_UNMAPPED + UML_JMPc(block, COND_NE, nounmapped2 = label++); // jmpne nounmapped2 + + UML_TEST(block, I2, ARM7_TLB_ABORT_D); // test i2, ARM7_TLB_ABORT_D + UML_JMPc(block, COND_Z, prefetch2 = label++); // jmpz prefetch2 + UML_MOV(block, mem(&COPRO_FAULT_ADDRESS), I3); // mov COPRO_FAULT_ADDRESS, i3 + UML_MOV(block, mem(&arm->pendingAbtD), 1); // mov arm->pendingAbtD, 1 + UML_ROLAND(block, I5, I4, 31, 0xf0); // roland i5, i4, 31, 0xf0 + UML_OR(block, I5, I5, 7 << 0); // or i5, i5, 7 << 0 + UML_OR(block, mem(&COPRO_FAULT_STATUS_D), I5, I6); // or COPRO_FAULT_STATUS_D, i5, i6 + UML_MOV(block, I2, 0); // mov i2, 0 + UML_RET(block); // ret + + UML_LABEL(block, prefetch2); // prefetch2: + UML_MOV(block, mem(&arm->pendingAbtP), 1); // mov arm->pendingAbtP, 1 + UML_MOV(block, I2, 0); // mov i2, 0 + UML_RET(block); // ret + + UML_LABEL(block, nounmapped2); // nounmapped2: + UML_CMP(block, I6, COPRO_TLB_LARGE_PAGE); // cmp i6, COPRO_TLB_LARGE_PAGE + UML_JMPc(block, COND_NE, nolargepage = label++); // jmpne nolargepage + + UML_AND(block, I0, I3, ~COPRO_TLB_LARGE_PAGE_MASK); // and i0, i3, ~COPRO_TLB_LARGE_PAGE_MASK + UML_ROLINS(block, I0, I7, 0, COPRO_TLB_LARGE_PAGE_MASK); // rolins i0, i7, 0, COPRO_TLB_LARGE_PAGE_MASK + UML_MOV(block, I2, 1); // mov i2, 1 + UML_RET(block); // ret + + UML_LABEL(block, nolargepage); // nolargepage: + UML_CMP(block, I6, COPRO_TLB_SMALL_PAGE); // cmp i6, COPRO_TLB_SMALL_PAGE + UML_JMPc(block, COND_NE, nosmallpage = label++); // jmpne nosmallpage + + UML_ROLAND(block, I5, I3, 32-9, 3<<1); // roland i5, i3, 32-9, 3<<1 + UML_ROLAND(block, I6, I7, 32-4, 0xff); // roland i6, i7, 32-4, 0xff + UML_SHR(block, I5, I7, I5); // shr i5, i7, i5 + UML_AND(block, I5, I5, 3); // and i5, i5, 3 // result in I6 - UML_CALLH(block, *arm->impstate->detect_fault); // callh detect_fault - - UML_CMP(block, I6, FAULT_NONE); // cmp i6, FAULT_NONE - UML_JMPc(block, COND_NE, smallfault = label++); // jmpne smallfault - UML_AND(block, I0, I7, COPRO_TLB_SMALL_PAGE_MASK); // and i0, i7, COPRO_TLB_SMALL_PAGE_MASK - UML_ROLINS(block, I0, I3, 0, ~COPRO_TLB_SMALL_PAGE_MASK); // rolins i0, i3, 0, ~COPRO_TLB_SMALL_PAGE_MASK - UML_MOV(block, I2, 1); // mov i2, 1 - UML_RET(block); // ret - - UML_LABEL(block, smallfault); // smallfault: - UML_TEST(block, I2, ARM7_TLB_ABORT_D); // test i2, ARM7_TLB_ABORT_D - UML_JMPc(block, COND_NZ, smallprefetch = label++); // jmpnz smallprefetch - UML_MOV(block, mem(&COPRO_FAULT_ADDRESS), I3); // mov COPRO_FAULT_ADDRESS, i3 - UML_MOV(block, mem(&arm->pendingAbtD), 1); // mov pendingAbtD, 1 - UML_CMP(block, I6, FAULT_DOMAIN); // cmp i6, FAULT_DOMAIN - UML_MOVc(block, COND_E, I5, 11 << 0); // move i5, 11 << 0 - UML_MOVc(block, COND_NE, I5, 15 << 0); // movne i5, 15 << 0 - UML_ROLINS(block, I5, I4, 31, 0xf0); // rolins i5, i4, 31, 0xf0 - UML_MOV(block, mem(&COPRO_FAULT_STATUS_D), I5); // mov COPRO_FAULT_STATUS_D, i5 - UML_MOV(block, I2, 0); // mov i2, 0 - UML_RET(block); // ret - - UML_LABEL(block, smallprefetch); // smallprefetch: - UML_MOV(block, mem(&arm->pendingAbtP), 1); // mov pendingAbtP, 1 - UML_MOV(block, I2, 0); // mov i2, 0 - UML_RET(block); // ret - - UML_LABEL(block, nosmallpage); // nosmallpage: - UML_CMP(block, I6, COPRO_TLB_TINY_PAGE); // cmp i6, COPRO_TLB_TINY_PAGE - UML_JMPc(block, COND_NE, notinypage = label++); // jmpne notinypage - - UML_AND(block, I0, I3, ~COPRO_TLB_TINY_PAGE_MASK); // and i0, i3, ~COPRO_TLB_TINY_PAGE_MASK - UML_ROLINS(block, I0, I7, 0, COPRO_TLB_TINY_PAGE_MASK); // rolins i0, i7, 0, COPRO_TLB_TINY_PAGE_MASK - UML_MOV(block, I2, 1); // mov i2, 1 - UML_RET(block); // ret - - UML_LABEL(block, notinypage); // notinypage: - UML_MOV(block, I0, I3); // mov i0, i3 - UML_RET(block); // ret + UML_CALLH(block, *arm->impstate->detect_fault); // callh detect_fault + + UML_CMP(block, I6, FAULT_NONE); // cmp i6, FAULT_NONE + UML_JMPc(block, COND_NE, smallfault = label++); // jmpne smallfault + UML_AND(block, I0, I7, COPRO_TLB_SMALL_PAGE_MASK); // and i0, i7, COPRO_TLB_SMALL_PAGE_MASK + UML_ROLINS(block, I0, I3, 0, ~COPRO_TLB_SMALL_PAGE_MASK); // rolins i0, i3, 0, ~COPRO_TLB_SMALL_PAGE_MASK + UML_MOV(block, I2, 1); // mov i2, 1 + UML_RET(block); // ret + + UML_LABEL(block, smallfault); // smallfault: + UML_TEST(block, I2, ARM7_TLB_ABORT_D); // test i2, ARM7_TLB_ABORT_D + UML_JMPc(block, COND_NZ, smallprefetch = label++); // jmpnz smallprefetch + UML_MOV(block, mem(&COPRO_FAULT_ADDRESS), I3); // mov COPRO_FAULT_ADDRESS, i3 + UML_MOV(block, mem(&arm->pendingAbtD), 1); // mov pendingAbtD, 1 + UML_CMP(block, I6, FAULT_DOMAIN); // cmp i6, FAULT_DOMAIN + UML_MOVc(block, COND_E, I5, 11 << 0); // move i5, 11 << 0 + UML_MOVc(block, COND_NE, I5, 15 << 0); // movne i5, 15 << 0 + UML_ROLINS(block, I5, I4, 31, 0xf0); // rolins i5, i4, 31, 0xf0 + UML_MOV(block, mem(&COPRO_FAULT_STATUS_D), I5); // mov COPRO_FAULT_STATUS_D, i5 + UML_MOV(block, I2, 0); // mov i2, 0 + UML_RET(block); // ret + + UML_LABEL(block, smallprefetch); // smallprefetch: + UML_MOV(block, mem(&arm->pendingAbtP), 1); // mov pendingAbtP, 1 + UML_MOV(block, I2, 0); // mov i2, 0 + UML_RET(block); // ret + + UML_LABEL(block, nosmallpage); // nosmallpage: + UML_CMP(block, I6, COPRO_TLB_TINY_PAGE); // cmp i6, COPRO_TLB_TINY_PAGE + UML_JMPc(block, COND_NE, notinypage = label++); // jmpne notinypage + + UML_AND(block, I0, I3, ~COPRO_TLB_TINY_PAGE_MASK); // and i0, i3, ~COPRO_TLB_TINY_PAGE_MASK + UML_ROLINS(block, I0, I7, 0, COPRO_TLB_TINY_PAGE_MASK); // rolins i0, i7, 0, COPRO_TLB_TINY_PAGE_MASK + UML_MOV(block, I2, 1); // mov i2, 1 + UML_RET(block); // ret + + UML_LABEL(block, notinypage); // notinypage: + UML_MOV(block, I0, I3); // mov i0, i3 + UML_RET(block); // ret block->end(); } @@ -1957,21 +1957,21 @@ static void static_generate_memory_accessor(arm_state *arm, int size, bool istlb /* add a global entry for this */ alloc_handle(drcuml, handleptr, name); - UML_HANDLE(block, **handleptr); // handle *handleptr + UML_HANDLE(block, **handleptr); // handle *handleptr if (istlb) { - UML_TEST(block, mem(&COPRO_CTRL), COPRO_CTRL_MMU_EN); // test COPRO_CTRL, COPRO_CTRL_MMU_EN + UML_TEST(block, mem(&COPRO_CTRL), COPRO_CTRL_MMU_EN); // test COPRO_CTRL, COPRO_CTRL_MMU_EN if (iswrite) { - UML_MOVc(block, COND_NZ, I3, ARM7_TLB_WRITE); // movnz i3, ARM7_TLB_WRITE + UML_MOVc(block, COND_NZ, I3, ARM7_TLB_WRITE); // movnz i3, ARM7_TLB_WRITE } else { - UML_MOVc(block, COND_NZ, I3, ARM7_TLB_READ); // movnz i3, ARM7_TLB_READ + UML_MOVc(block, COND_NZ, I3, ARM7_TLB_READ); // movnz i3, ARM7_TLB_READ } - UML_OR(block, I2, I2, I3); // or i2, i2, i3 - UML_CALLHc(block, COND_NZ, *arm->impstate->tlb_translate); // callhnz tlb_translate + UML_OR(block, I2, I2, I3); // or i2, i2, i3 + UML_CALLHc(block, COND_NZ, *arm->impstate->tlb_translate); // callhnz tlb_translate } /* general case: assume paging and perform a translation */ @@ -1985,13 +1985,13 @@ static void static_generate_memory_accessor(arm_state *arm, int size, bool istlb UINT32 skip = label++; if (arm->impstate->fastram[ramnum].end != 0xffffffff) { - UML_CMP(block, I0, arm->impstate->fastram[ramnum].end); // cmp i0, end - UML_JMPc(block, COND_A, skip); // ja skip + UML_CMP(block, I0, arm->impstate->fastram[ramnum].end); // cmp i0, end + UML_JMPc(block, COND_A, skip); // ja skip } if (arm->impstate->fastram[ramnum].start != 0x00000000) { - UML_CMP(block, I0, arm->impstate->fastram[ramnum].start); // cmp i0, fastram_start - UML_JMPc(block, COND_B, skip); // jb skip + UML_CMP(block, I0, arm->impstate->fastram[ramnum].start); // cmp i0, fastram_start + UML_JMPc(block, COND_B, skip); // jb skip } if (!iswrite) @@ -2000,19 +2000,19 @@ static void static_generate_memory_accessor(arm_state *arm, int size, bool istlb { UML_XOR(block, I0, I0, (arm->endianess == ENDIANNESS_BIG) ? BYTE4_XOR_BE(0) : BYTE4_XOR_LE(0)); // xor i0, i0, bytexor - UML_LOAD(block, I0, fastbase, I0, SIZE_BYTE, SCALE_x1); // load i0, fastbase, i0, byte + UML_LOAD(block, I0, fastbase, I0, SIZE_BYTE, SCALE_x1); // load i0, fastbase, i0, byte } else if (size == 2) { UML_XOR(block, I0, I0, (arm->endianess == ENDIANNESS_BIG) ? WORD_XOR_BE(0) : WORD_XOR_LE(0)); // xor i0, i0, wordxor - UML_LOAD(block, I0, fastbase, I0, SIZE_WORD, SCALE_x1); // load i0, fastbase, i0, word_x1 + UML_LOAD(block, I0, fastbase, I0, SIZE_WORD, SCALE_x1); // load i0, fastbase, i0, word_x1 } else if (size == 4) { - UML_LOAD(block, I0, fastbase, I0, SIZE_DWORD, SCALE_x1); // load i0, fastbase, i0, dword_x1 + UML_LOAD(block, I0, fastbase, I0, SIZE_DWORD, SCALE_x1); // load i0, fastbase, i0, dword_x1 } - UML_RET(block); // ret + UML_RET(block); // ret } else { @@ -2020,22 +2020,22 @@ static void static_generate_memory_accessor(arm_state *arm, int size, bool istlb { UML_XOR(block, I0, I0, (arm->endianess == ENDIANNESS_BIG) ? BYTE4_XOR_BE(0) : BYTE4_XOR_LE(0)); // xor i0, i0, bytexor - UML_STORE(block, fastbase, I0, I1, SIZE_BYTE, SCALE_x1); // store fastbase, i0, i1, byte + UML_STORE(block, fastbase, I0, I1, SIZE_BYTE, SCALE_x1); // store fastbase, i0, i1, byte } else if (size == 2) { UML_XOR(block, I0, I0, arm->bigendian ? WORD_XOR_BE(0) : WORD_XOR_LE(0)); // xor i0, i0, wordxor - UML_STORE(block, fastbase, I0, I1, SIZE_WORD, SCALE_x1); // store fastbase, i0, i1, word_x1 + UML_STORE(block, fastbase, I0, I1, SIZE_WORD, SCALE_x1); // store fastbase, i0, i1, word_x1 } else if (size == 4) { - UML_STORE(block, fastbase, I0, I1, SIZE_DWORD, SCALE_x1); // store fastbase,i0,i1,dword_x1 + UML_STORE(block, fastbase, I0, I1, SIZE_DWORD, SCALE_x1); // store fastbase,i0,i1,dword_x1 } UML_RET(block); // ret } - UML_LABEL(block, skip); // skip: + UML_LABEL(block, skip); // skip: } } } @@ -2045,33 +2045,33 @@ static void static_generate_memory_accessor(arm_state *arm, int size, bool istlb case 1: if (iswrite) { - UML_WRITE(block, I0, I1, SIZE_BYTE, SPACE_PROGRAM); // write i0, i1, program_byte + UML_WRITE(block, I0, I1, SIZE_BYTE, SPACE_PROGRAM); // write i0, i1, program_byte } else { - UML_READ(block, I0, I0, SIZE_BYTE, SPACE_PROGRAM); // read i0, i0, program_byte + UML_READ(block, I0, I0, SIZE_BYTE, SPACE_PROGRAM); // read i0, i0, program_byte } break; case 2: if (iswrite) { - UML_WRITE(block, I0, I1, SIZE_WORD, SPACE_PROGRAM); // write i0,i1,program_word + UML_WRITE(block, I0, I1, SIZE_WORD, SPACE_PROGRAM); // write i0,i1,program_word } else { - UML_READ(block, I0, I0, SIZE_WORD, SPACE_PROGRAM); // read i0,i0,program_word + UML_READ(block, I0, I0, SIZE_WORD, SPACE_PROGRAM); // read i0,i0,program_word } break; case 4: if (iswrite) { - UML_WRITE(block, I0, I1, SIZE_DWORD, SPACE_PROGRAM); // write i0,i1,program_dword + UML_WRITE(block, I0, I1, SIZE_DWORD, SPACE_PROGRAM); // write i0,i1,program_dword } else { - UML_READ(block, I0, I0, SIZE_DWORD, SPACE_PROGRAM); // read i0,i0,program_dword + UML_READ(block, I0, I0, SIZE_DWORD, SPACE_PROGRAM); // read i0,i0,program_dword } break; } @@ -2106,7 +2106,7 @@ static void generate_update_cycles(arm_state *arm, drcuml_block *block, compiler { UML_SUB(block, mem(&arm->icount), mem(&arm->icount), MAPVAR_CYCLES); // sub icount,icount,cycles UML_MAPVAR(block, MAPVAR_CYCLES, 0); // mapvar cycles,0 - UML_EXHc(block, COND_S, *arm->impstate->out_of_cycles, param); // exh out_of_cycles,nextpc + UML_EXHc(block, COND_S, *arm->impstate->out_of_cycles, param); // exh out_of_cycles,nextpc } compiler->cycles = 0; } @@ -2132,19 +2132,19 @@ static void generate_checksum_block(arm_state *arm, drcuml_block *block, compile { UINT32 sum = seqhead->opptr.l[0]; void *base = arm->direct->read_decrypted_ptr(seqhead->physpc); - UML_LOAD(block, I0, base, 0, SIZE_DWORD, SCALE_x4); // load i0,base,0,dword + UML_LOAD(block, I0, base, 0, SIZE_DWORD, SCALE_x4); // load i0,base,0,dword if (seqhead->delay.first() != NULL && seqhead->physpc != seqhead->delay.first()->physpc) { base = arm->direct->read_decrypted_ptr(seqhead->delay.first()->physpc); - UML_LOAD(block, I1, base, 0, SIZE_DWORD, SCALE_x4); // load i1,base,dword - UML_ADD(block, I0, I0, I1); // add i0,i0,i1 + UML_LOAD(block, I1, base, 0, SIZE_DWORD, SCALE_x4); // load i1,base,dword + UML_ADD(block, I0, I0, I1); // add i0,i0,i1 sum += seqhead->delay.first()->opptr.l[0]; } - UML_CMP(block, I0, sum); // cmp i0,opptr[0] - UML_EXHc(block, COND_NE, *arm->impstate->nocode, epc(seqhead)); // exne nocode,seqhead->pc + UML_CMP(block, I0, sum); // cmp i0,opptr[0] + UML_EXHc(block, COND_NE, *arm->impstate->nocode, epc(seqhead)); // exne nocode,seqhead->pc } } @@ -2153,26 +2153,26 @@ static void generate_checksum_block(arm_state *arm, drcuml_block *block, compile { UINT32 sum = 0; void *base = arm->direct->read_decrypted_ptr(seqhead->physpc); - UML_LOAD(block, I0, base, 0, SIZE_DWORD, SCALE_x4); // load i0,base,0,dword + UML_LOAD(block, I0, base, 0, SIZE_DWORD, SCALE_x4); // load i0,base,0,dword sum += seqhead->opptr.l[0]; for (curdesc = seqhead->next(); curdesc != seqlast->next(); curdesc = curdesc->next()) if (!(curdesc->flags & OPFLAG_VIRTUAL_NOOP)) { base = arm->direct->read_decrypted_ptr(curdesc->physpc); - UML_LOAD(block, I1, base, 0, SIZE_DWORD, SCALE_x4); // load i1,base,dword - UML_ADD(block, I0, I0, I1); // add i0,i0,i1 + UML_LOAD(block, I1, base, 0, SIZE_DWORD, SCALE_x4); // load i1,base,dword + UML_ADD(block, I0, I0, I1); // add i0,i0,i1 sum += curdesc->opptr.l[0]; if (curdesc->delay.first() != NULL && (curdesc == seqlast || (curdesc->next() != NULL && curdesc->next()->physpc != curdesc->delay.first()->physpc))) { base = arm->direct->read_decrypted_ptr(curdesc->delay.first()->physpc); - UML_LOAD(block, I1, base, 0, SIZE_DWORD, SCALE_x4); // load i1,base,dword - UML_ADD(block, I0, I0, I1); // add i0,i0,i1 + UML_LOAD(block, I1, base, 0, SIZE_DWORD, SCALE_x4); // load i1,base,dword + UML_ADD(block, I0, I0, I1); // add i0,i0,i1 sum += curdesc->delay.first()->opptr.l[0]; } } - UML_CMP(block, I0, sum); // cmp i0,sum - UML_EXHc(block, COND_NE, *arm->impstate->nocode, epc(seqhead)); // exne nocode,seqhead->pc + UML_CMP(block, I0, sum); // cmp i0,sum + UML_EXHc(block, COND_NE, *arm->impstate->nocode, epc(seqhead)); // exne nocode,seqhead->pc } } @@ -2199,7 +2199,7 @@ static void generate_sequence_instruction(arm_state *arm, drcuml_block *block, c compiler->cycles += desc->cycles; /* update the icount map variable */ - UML_MAPVAR(block, MAPVAR_CYCLES, compiler->cycles); // mapvar CYCLES,compiler->cycles + UML_MAPVAR(block, MAPVAR_CYCLES, compiler->cycles); // mapvar CYCLES,compiler->cycles /* is this a hotspot? */ for (hotnum = 0; hotnum < MIPS3_MAX_HOTSPOTS; hotnum++) @@ -2212,22 +2212,22 @@ static void generate_sequence_instruction(arm_state *arm, drcuml_block *block, c } /* update the icount map variable */ - UML_MAPVAR(block, MAPVAR_CYCLES, compiler->cycles); // mapvar CYCLES,compiler->cycles + UML_MAPVAR(block, MAPVAR_CYCLES, compiler->cycles); // mapvar CYCLES,compiler->cycles /* if we are debugging, call the debugger */ if ((arm->device->machine().debug_flags & DEBUG_FLAG_ENABLED) != 0) { - UML_MOV(block, mem(&R15), desc->pc); // mov [pc],desc->pc + UML_MOV(block, mem(&R15), desc->pc); // mov [pc],desc->pc save_fast_iregs(arm, block); - UML_DEBUG(block, desc->pc); // debug desc->pc + UML_DEBUG(block, desc->pc); // debug desc->pc } /* if we hit an unmapped address, fatal error */ if (desc->flags & OPFLAG_COMPILER_UNMAPPED) { - UML_MOV(block, mem(&R15), desc->pc); // mov R15,desc->pc + UML_MOV(block, mem(&R15), desc->pc); // mov R15,desc->pc save_fast_iregs(arm, block); - UML_EXIT(block, EXECUTE_UNMAPPED_CODE); // exit EXECUTE_UNMAPPED_CODE + UML_EXIT(block, EXECUTE_UNMAPPED_CODE); // exit EXECUTE_UNMAPPED_CODE } /* otherwise, unless this is a virtual no-op, it's a regular instruction */ @@ -2236,9 +2236,9 @@ static void generate_sequence_instruction(arm_state *arm, drcuml_block *block, c /* compile the instruction */ if (!generate_opcode(arm, block, compiler, desc)) { - UML_MOV(block, mem(&R15), desc->pc); // mov R15,desc->pc - UML_MOV(block, mem(&arm->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l - UML_CALLC(block, cfunc_unimplemented, arm); // callc cfunc_unimplemented + UML_MOV(block, mem(&R15), desc->pc); // mov R15,desc->pc + UML_MOV(block, mem(&arm->impstate->arg0), desc->opptr.l[0]); // mov [arg0],desc->opptr.l + UML_CALLC(block, cfunc_unimplemented, arm); // callc cfunc_unimplemented } } } @@ -2256,7 +2256,7 @@ static void generate_delay_slot_and_branch(arm_state *arm, drcuml_block *block, /* update the cycles and jump through the hash table to the target */ if (desc->targetpc != BRANCH_TARGET_DYNAMIC) { - generate_update_cycles(arm, block, &compiler_temp, desc->targetpc, TRUE); // <subtract cycles> + generate_update_cycles(arm, block, &compiler_temp, desc->targetpc, TRUE); // <subtract cycles> UML_HASHJMP(block, 0, desc->targetpc, *arm->impstate->nocode); // hashjmp 0,desc->targetpc,nocode } @@ -2627,13 +2627,13 @@ static int generate_opcode(arm_state *arm, drcuml_block *block, compiler_state * UML_AND(block, I0, DRC_PC, ~3); } - UML_TEST(block, mem(&COPRO_CTRL), COPRO_CTRL_MMU_EN); // test COPRO_CTRL, COPRO_CTRL_MMU_EN - UML_MOVc(block, COND_NZ, I2, ARM7_TLB_ABORT_P | ARM7_TLB_READ); // movnz i0, ARM7_TLB_ABORT_P | ARM7_TLB_READ - UML_CALLHc(block, COND_NZ, *arm->impstate->tlb_translate); // callhnz tlb_translate); + UML_TEST(block, mem(&COPRO_CTRL), COPRO_CTRL_MMU_EN); // test COPRO_CTRL, COPRO_CTRL_MMU_EN + UML_MOVc(block, COND_NZ, I2, ARM7_TLB_ABORT_P | ARM7_TLB_READ); // movnz i0, ARM7_TLB_ABORT_P | ARM7_TLB_READ + UML_CALLHc(block, COND_NZ, *arm->impstate->tlb_translate); // callhnz tlb_translate); if (T_IS_SET(GET_CPSR)) { - UML_CALLH(block, *arm->impstate->drcthumb[(op & 0xffc0) >> 6); // callh drcthumb[op] + UML_CALLH(block, *arm->impstate->drcthumb[(op & 0xffc0) >> 6); // callh drcthumb[op] return TRUE; } @@ -2739,7 +2739,7 @@ static int generate_opcode(arm_state *arm, drcuml_block *block, compiler_state * UML_LABEL(block, unexecuted); UML_ADD(block, DRC_PC, DRC_PC, 4); - UML_ADD(block, MAPVAR_CYCLES, MAPVAR_CYCLES, 2); // add cycles, cycles, 2 + UML_ADD(block, MAPVAR_CYCLES, MAPVAR_CYCLES, 2); // add cycles, cycles, 2 UML_LABEL(block, skip); diff --git a/src/emu/cpu/arm7/arm7help.h b/src/emu/cpu/arm7/arm7help.h index e425014928b..6b67dbf6885 100644 --- a/src/emu/cpu/arm7/arm7help.h +++ b/src/emu/cpu/arm7/arm7help.h @@ -42,22 +42,22 @@ extern void SwitchMode(arm_state *arm, int cpsr_mode_val); | HandleALUNZFlags(rd))); \ R15 += 2; -#define DRCHandleThumbALUAddFlags(rd, rn, op2) \ - UML_AND(block, DRC_CPSR, DRC_CPSR, ~(N_MASK | Z_MASK | V_MASK | C_MASK)); \ - DRCHandleALUNZFlags(rd); \ - UML_XOR(block, I1, rn, ~0); \ - UML_CMP(block, I1, op2); \ - UML_MOVc(block, COND_B, I1, C_BIT); \ - UML_MOVc(block, COND_AE, I1, 0); \ - UML_OR(block, I0, I0, I1); \ - UML_XOR(block, I1, rn, op2); \ - UML_XOR(block, I2, rn, rd); \ - UML_AND(block, I1, I1, I2); \ - UML_TEST(block, I1, 1 << 31); \ - UML_MOVc(block, COND_NZ, I1, V_BIT); \ - UML_MOVc(block, COND_Z, I1, 0); \ - UML_OR(block, I0, I0, I1); \ - UML_OR(block, DRC_CPSR, DRC_CPSR, I0); \ +#define DRCHandleThumbALUAddFlags(rd, rn, op2) \ + UML_AND(block, DRC_CPSR, DRC_CPSR, ~(N_MASK | Z_MASK | V_MASK | C_MASK)); \ + DRCHandleALUNZFlags(rd); \ + UML_XOR(block, I1, rn, ~0); \ + UML_CMP(block, I1, op2); \ + UML_MOVc(block, COND_B, I1, C_BIT); \ + UML_MOVc(block, COND_AE, I1, 0); \ + UML_OR(block, I0, I0, I1); \ + UML_XOR(block, I1, rn, op2); \ + UML_XOR(block, I2, rn, rd); \ + UML_AND(block, I1, I1, I2); \ + UML_TEST(block, I1, 1 << 31); \ + UML_MOVc(block, COND_NZ, I1, V_BIT); \ + UML_MOVc(block, COND_Z, I1, 0); \ + UML_OR(block, I0, I0, I1); \ + UML_OR(block, DRC_CPSR, DRC_CPSR, I0); \ UML_ADD(block, DRC_PC, DRC_PC, 2); #define HandleALUSubFlags(rd, rn, op2) \ @@ -75,31 +75,31 @@ extern void SwitchMode(arm_state *arm, int cpsr_mode_val); | HandleALUNZFlags(rd))); \ R15 += 2; -#define DRCHandleThumbALUSubFlags(rd, rn, op2) \ - UML_AND(block, DRC_CPSR, DRC_CPSR, ~(N_MASK | Z_MASK | V_MASK | C_MASK)); \ - DRCHandleALUNZFlags(rd); \ - UML_XOR(block, I1, rn, op2); \ - UML_XOR(block, I2, rn, rd); \ - UML_AND(block, I1, I1, I2); \ - UML_TEST(block, I1, 1 << 31); \ - UML_MOVc(block, COND_NZ, I1, V_BIT); \ - UML_MOVc(block, COND_Z, I1, 0); \ - UML_OR(block, I0, I0, I1); \ - UML_OR(block, DRC_CPSR, DRC_CPSR, I0); \ - UML_AND(block, I0, rd, 1 << 31); \ - UML_AND(block, I1, op2, 1 << 31); \ - UML_AND(block, I2, rn, 1 << 31); \ - UML_XOR(block, I2, I2, ~0); \ - UML_AND(block, I1, I1, I2); \ - UML_AND(block, I2, I2, I0); \ - UML_OR(block, I1, I1, I2); \ - UML_AND(block, I2, op2, 1 << 31); \ - UML_AND(block, I2, I2, I0); \ - UML_OR(block, I1, I1, I2); \ - UML_TEST(block, I1, 1 << 31); \ - UML_MOVc(block, COND_NZ, I0, C_MASK); \ - UML_MOVc(block, COND_Z, I0, 0); \ - UML_OR(block, DRC_CPSR, DRC_CPSR, I0); \ +#define DRCHandleThumbALUSubFlags(rd, rn, op2) \ + UML_AND(block, DRC_CPSR, DRC_CPSR, ~(N_MASK | Z_MASK | V_MASK | C_MASK)); \ + DRCHandleALUNZFlags(rd); \ + UML_XOR(block, I1, rn, op2); \ + UML_XOR(block, I2, rn, rd); \ + UML_AND(block, I1, I1, I2); \ + UML_TEST(block, I1, 1 << 31); \ + UML_MOVc(block, COND_NZ, I1, V_BIT); \ + UML_MOVc(block, COND_Z, I1, 0); \ + UML_OR(block, I0, I0, I1); \ + UML_OR(block, DRC_CPSR, DRC_CPSR, I0); \ + UML_AND(block, I0, rd, 1 << 31); \ + UML_AND(block, I1, op2, 1 << 31); \ + UML_AND(block, I2, rn, 1 << 31); \ + UML_XOR(block, I2, I2, ~0); \ + UML_AND(block, I1, I1, I2); \ + UML_AND(block, I2, I2, I0); \ + UML_OR(block, I1, I1, I2); \ + UML_AND(block, I2, op2, 1 << 31); \ + UML_AND(block, I2, I2, I0); \ + UML_OR(block, I1, I1, I2); \ + UML_TEST(block, I1, 1 << 31); \ + UML_MOVc(block, COND_NZ, I0, C_MASK); \ + UML_MOVc(block, COND_Z, I0, 0); \ + UML_OR(block, DRC_CPSR, DRC_CPSR, I0); \ UML_ADD(block, DRC_PC, DRC_PC, 2); /* Set NZC flags for logical operations. */ @@ -109,11 +109,11 @@ extern void SwitchMode(arm_state *arm, int cpsr_mode_val); #define HandleALUNZFlags(rd) \ (((rd) & SIGN_BIT) | ((!(rd)) << Z_BIT)) -#define DRCHandleALUNZFlags(rd) \ - UML_AND(block, I0, rd, SIGN_BIT); \ - UML_CMP(block, rd, 0); \ - UML_MOVc(block, COND_E, I1, 1); \ - UML_MOVc(block, COND_NE, I1, 0); \ +#define DRCHandleALUNZFlags(rd) \ + UML_AND(block, I0, rd, SIGN_BIT); \ + UML_CMP(block, rd, 0); \ + UML_MOVc(block, COND_E, I1, 1); \ + UML_MOVc(block, COND_NE, I1, 0); \ UML_ROLINS(block, I0, I1, Z_BIT, 1 << Z_BIT); // Long ALU Functions use bit 63 @@ -127,23 +127,23 @@ extern void SwitchMode(arm_state *arm, int cpsr_mode_val); | (((sc) != 0) << C_BIT))); \ R15 += 4; -#define DRC_RD mem(&GET_REGISTER(arm, rd)) -#define DRC_RS mem(&GET_REGISTER(arm, rs)) -#define DRC_CPSR mem(&GET_CPSR) -#define DRC_PC mem(&R15) -#define DRC_REG(i) mem(&arm->r[(i)]); - -#define DRCHandleALULogicalFlags(rd, sc) \ - if (insn & INSN_S) \ - { \ - UML_AND(block, DRC_CPSR, DRC_CPSR, ~(N_MASK | Z_MASK | C_MASK); \ - DRCHandleALUNZFlags(rd); \ - UML_TEST(block, sc, ~0); \ - UML_MOVc(block, COND_Z, I1, C_BIT); \ - UML_MOVc(block, COND_NZ, I1, 0); \ - UML_OR(block, I0, I0, I1); \ - UML_OR(block, DRC_CPSR, DRC_CPSR, I0); \ - } \ +#define DRC_RD mem(&GET_REGISTER(arm, rd)) +#define DRC_RS mem(&GET_REGISTER(arm, rs)) +#define DRC_CPSR mem(&GET_CPSR) +#define DRC_PC mem(&R15) +#define DRC_REG(i) mem(&arm->r[(i)]); + +#define DRCHandleALULogicalFlags(rd, sc) \ + if (insn & INSN_S) \ + { \ + UML_AND(block, DRC_CPSR, DRC_CPSR, ~(N_MASK | Z_MASK | C_MASK); \ + DRCHandleALUNZFlags(rd); \ + UML_TEST(block, sc, ~0); \ + UML_MOVc(block, COND_Z, I1, C_BIT); \ + UML_MOVc(block, COND_NZ, I1, 0); \ + UML_OR(block, I0, I0, I1); \ + UML_OR(block, DRC_CPSR, DRC_CPSR, I0); \ + } \ UML_ADD(block, DRC_PC, DRC_PC, 4); void set_cpsr( arm_state *arm, UINT32 val); diff --git a/src/emu/cpu/arm7/arm7tdrc.c b/src/emu/cpu/arm7/arm7tdrc.c index b22ac905fd0..7159b63bc0a 100644 --- a/src/emu/cpu/arm7/arm7tdrc.c +++ b/src/emu/cpu/arm7/arm7tdrc.c @@ -8,149 +8,149 @@ arm7thumb_drcophandler drcthumb_handler[0x40*0x10] = { // #define THUMB_SHIFT_R ((UINT16)0x0800) - drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, - drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, - drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, - drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, - drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, - drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, - drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, - drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, + drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, + drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, + drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, + drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, drctg00_0, + drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, + drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, + drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, + drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, drctg00_1, // #define THUMB_INSN_ADDSUB ((UINT16)0x0800) // #define THUMB_ADDSUB_TYPE ((UINT16)0x0600) - drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, - drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, - drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, - drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, - drctg01_10, drctg01_10, drctg01_10, drctg01_10, drctg01_10, drctg01_10, drctg01_10, drctg01_10, - drctg01_11, drctg01_11, drctg01_11, drctg01_11, drctg01_11, drctg01_11, drctg01_11, drctg01_11, - drctg01_12, drctg01_12, drctg01_12, drctg01_12, drctg01_12, drctg01_12, drctg01_12, drctg01_12, - drctg01_13, drctg01_13, drctg01_13, drctg01_13, drctg01_13, drctg01_13, drctg01_13, drctg01_13, + drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, + drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, + drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, + drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, drctg01_0, + drctg01_10, drctg01_10, drctg01_10, drctg01_10, drctg01_10, drctg01_10, drctg01_10, drctg01_10, + drctg01_11, drctg01_11, drctg01_11, drctg01_11, drctg01_11, drctg01_11, drctg01_11, drctg01_11, + drctg01_12, drctg01_12, drctg01_12, drctg01_12, drctg01_12, drctg01_12, drctg01_12, drctg01_12, + drctg01_13, drctg01_13, drctg01_13, drctg01_13, drctg01_13, drctg01_13, drctg01_13, drctg01_13, // #define THUMB_INSN_CMP ((UINT16)0x0800) - drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, - drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, - drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, - drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, - drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, - drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, - drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, - drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, + drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, + drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, + drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, + drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, drctg02_0, + drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, + drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, + drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, + drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, drctg02_1, // #define THUMB_INSN_SUB ((UINT16)0x0800) - drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, - drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, - drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, - drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, - drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, - drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, - drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, - drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, + drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, + drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, + drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, + drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, drctg03_0, + drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, + drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, + drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, + drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, drctg03_1, //#define THUMB_GROUP4_TYPE ((UINT16)0x0c00) //#define THUMB_ALUOP_TYPE ((UINT16)0x03c0) // #define THUMB_HIREG_OP ((UINT16)0x0300) // #define THUMB_HIREG_H ((UINT16)0x00c0) - drctg04_00_00, drctg04_00_01, drctg04_00_02, drctg04_00_03, drctg04_00_04, drctg04_00_05, drctg04_00_06, drctg04_00_07, - drctg04_00_08, drctg04_00_09, drctg04_00_0a, drctg04_00_0b, drctg04_00_0c, drctg04_00_0d, drctg04_00_0e, drctg04_00_0f, - drctg04_01_00, drctg04_01_01, drctg04_01_02, drctg04_01_03, drctg04_01_10, drctg04_01_11, drctg04_01_12, drctg04_01_13, - drctg04_01_20, drctg04_01_21, drctg04_01_22, drctg04_01_23, drctg04_01_30, drctg04_01_31, drctg04_01_32, drctg04_01_33, - drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, - drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, - drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, - drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, + drctg04_00_00, drctg04_00_01, drctg04_00_02, drctg04_00_03, drctg04_00_04, drctg04_00_05, drctg04_00_06, drctg04_00_07, + drctg04_00_08, drctg04_00_09, drctg04_00_0a, drctg04_00_0b, drctg04_00_0c, drctg04_00_0d, drctg04_00_0e, drctg04_00_0f, + drctg04_01_00, drctg04_01_01, drctg04_01_02, drctg04_01_03, drctg04_01_10, drctg04_01_11, drctg04_01_12, drctg04_01_13, + drctg04_01_20, drctg04_01_21, drctg04_01_22, drctg04_01_23, drctg04_01_30, drctg04_01_31, drctg04_01_32, drctg04_01_33, + drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, + drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, + drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, + drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, drctg04_0203, //#define THUMB_GROUP5_TYPE ((UINT16)0x0e00) - drctg05_0, drctg05_0, drctg05_0, drctg05_0, drctg05_0, drctg05_0, drctg05_0, drctg05_0, - drctg05_1, drctg05_1, drctg05_1, drctg05_1, drctg05_1, drctg05_1, drctg05_1, drctg05_1, - drctg05_2, drctg05_2, drctg05_2, drctg05_2, drctg05_2, drctg05_2, drctg05_2, drctg05_2, - drctg05_3, drctg05_3, drctg05_3, drctg05_3, drctg05_3, drctg05_3, drctg05_3, drctg05_3, - drctg05_4, drctg05_4, drctg05_4, drctg05_4, drctg05_4, drctg05_4, drctg05_4, drctg05_4, - drctg05_5, drctg05_5, drctg05_5, drctg05_5, drctg05_5, drctg05_5, drctg05_5, drctg05_5, - drctg05_6, drctg05_6, drctg05_6, drctg05_6, drctg05_6, drctg05_6, drctg05_6, drctg05_6, - drctg05_7, drctg05_7, drctg05_7, drctg05_7, drctg05_7, drctg05_7, drctg05_7, drctg05_7, + drctg05_0, drctg05_0, drctg05_0, drctg05_0, drctg05_0, drctg05_0, drctg05_0, drctg05_0, + drctg05_1, drctg05_1, drctg05_1, drctg05_1, drctg05_1, drctg05_1, drctg05_1, drctg05_1, + drctg05_2, drctg05_2, drctg05_2, drctg05_2, drctg05_2, drctg05_2, drctg05_2, drctg05_2, + drctg05_3, drctg05_3, drctg05_3, drctg05_3, drctg05_3, drctg05_3, drctg05_3, drctg05_3, + drctg05_4, drctg05_4, drctg05_4, drctg05_4, drctg05_4, drctg05_4, drctg05_4, drctg05_4, + drctg05_5, drctg05_5, drctg05_5, drctg05_5, drctg05_5, drctg05_5, drctg05_5, drctg05_5, + drctg05_6, drctg05_6, drctg05_6, drctg05_6, drctg05_6, drctg05_6, drctg05_6, drctg05_6, + drctg05_7, drctg05_7, drctg05_7, drctg05_7, drctg05_7, drctg05_7, drctg05_7, drctg05_7, //#define THUMB_LSOP_L ((UINT16)0x0800) - drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, - drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, - drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, - drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, - drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, - drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, - drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, - drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, + drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, + drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, + drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, + drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, drctg06_0, + drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, + drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, + drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, + drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, drctg06_1, //#define THUMB_LSOP_L ((UINT16)0x0800) - drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, - drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, - drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, - drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, - drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, - drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, - drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, - drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, + drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, + drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, + drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, + drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, drctg07_0, + drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, + drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, + drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, + drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, drctg07_1, // #define THUMB_HALFOP_L ((UINT16)0x0800) - drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, - drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, - drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, - drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, - drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, - drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, - drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, - drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, + drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, + drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, + drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, + drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, drctg08_0, + drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, + drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, + drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, + drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, drctg08_1, // #define THUMB_STACKOP_L ((UINT16)0x0800) - drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, - drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, - drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, - drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, - drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, - drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, - drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, - drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, + drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, + drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, + drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, + drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, drctg09_0, + drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, + drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, + drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, + drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, drctg09_1, // #define THUMB_RELADDR_SP ((UINT16)0x0800) - drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, - drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, - drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, - drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, - drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, - drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, - drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, - drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, + drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, + drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, + drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, + drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, drctg0a_0, + drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, + drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, + drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, + drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, drctg0a_1, // #define THUMB_STACKOP_TYPE ((UINT16)0x0f00) - drctg0b_0, drctg0b_0, drctg0b_0, drctg0b_0, drctg0b_1, drctg0b_1, drctg0b_1, drctg0b_1, - drctg0b_2, drctg0b_2, drctg0b_2, drctg0b_2, drctg0b_3, drctg0b_3, drctg0b_3, drctg0b_3, - drctg0b_4, drctg0b_4, drctg0b_4, drctg0b_4, drctg0b_5, drctg0b_5, drctg0b_5, drctg0b_5, - drctg0b_6, drctg0b_6, drctg0b_6, drctg0b_6, drctg0b_7, drctg0b_7, drctg0b_7, drctg0b_7, - drctg0b_8, drctg0b_8, drctg0b_8, drctg0b_8, drctg0b_9, drctg0b_9, drctg0b_9, drctg0b_9, - drctg0b_a, drctg0b_a, drctg0b_a, drctg0b_a, drctg0b_b, drctg0b_b, drctg0b_b, drctg0b_b, - drctg0b_c, drctg0b_c, drctg0b_c, drctg0b_c, drctg0b_d, drctg0b_d, drctg0b_d, drctg0b_d, - drctg0b_e, drctg0b_e, drctg0b_e, drctg0b_e, drctg0b_f, drctg0b_f, drctg0b_f, drctg0b_f, + drctg0b_0, drctg0b_0, drctg0b_0, drctg0b_0, drctg0b_1, drctg0b_1, drctg0b_1, drctg0b_1, + drctg0b_2, drctg0b_2, drctg0b_2, drctg0b_2, drctg0b_3, drctg0b_3, drctg0b_3, drctg0b_3, + drctg0b_4, drctg0b_4, drctg0b_4, drctg0b_4, drctg0b_5, drctg0b_5, drctg0b_5, drctg0b_5, + drctg0b_6, drctg0b_6, drctg0b_6, drctg0b_6, drctg0b_7, drctg0b_7, drctg0b_7, drctg0b_7, + drctg0b_8, drctg0b_8, drctg0b_8, drctg0b_8, drctg0b_9, drctg0b_9, drctg0b_9, drctg0b_9, + drctg0b_a, drctg0b_a, drctg0b_a, drctg0b_a, drctg0b_b, drctg0b_b, drctg0b_b, drctg0b_b, + drctg0b_c, drctg0b_c, drctg0b_c, drctg0b_c, drctg0b_d, drctg0b_d, drctg0b_d, drctg0b_d, + drctg0b_e, drctg0b_e, drctg0b_e, drctg0b_e, drctg0b_f, drctg0b_f, drctg0b_f, drctg0b_f, // #define THUMB_MULTLS ((UINT16)0x0800) - drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, - drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, - drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, - drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, - drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, - drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, - drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, - drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, + drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, + drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, + drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, + drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, drctg0c_0, + drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, + drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, + drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, + drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, drctg0c_1, // #define THUMB_COND_TYPE ((UINT16)0x0f00) - drctg0d_0, drctg0d_0, drctg0d_0, drctg0d_0, drctg0d_1, drctg0d_1, drctg0d_1, drctg0d_1, - drctg0d_2, drctg0d_2, drctg0d_2, drctg0d_2, drctg0d_3, drctg0d_3, drctg0d_3, drctg0d_3, - drctg0d_4, drctg0d_4, drctg0d_4, drctg0d_4, drctg0d_5, drctg0d_5, drctg0d_5, drctg0d_5, - drctg0d_6, drctg0d_6, drctg0d_6, drctg0d_6, drctg0d_7, drctg0d_7, drctg0d_7, drctg0d_7, - drctg0d_8, drctg0d_8, drctg0d_8, drctg0d_8, drctg0d_9, drctg0d_9, drctg0d_9, drctg0d_9, - drctg0d_a, drctg0d_a, drctg0d_a, drctg0d_a, drctg0d_b, drctg0d_b, drctg0d_b, drctg0d_b, - drctg0d_c, drctg0d_c, drctg0d_c, drctg0d_c, drctg0d_d, drctg0d_d, drctg0d_d, drctg0d_d, - drctg0d_e, drctg0d_e, drctg0d_e, drctg0d_e, drctg0d_f, drctg0d_f, drctg0d_f, drctg0d_f, + drctg0d_0, drctg0d_0, drctg0d_0, drctg0d_0, drctg0d_1, drctg0d_1, drctg0d_1, drctg0d_1, + drctg0d_2, drctg0d_2, drctg0d_2, drctg0d_2, drctg0d_3, drctg0d_3, drctg0d_3, drctg0d_3, + drctg0d_4, drctg0d_4, drctg0d_4, drctg0d_4, drctg0d_5, drctg0d_5, drctg0d_5, drctg0d_5, + drctg0d_6, drctg0d_6, drctg0d_6, drctg0d_6, drctg0d_7, drctg0d_7, drctg0d_7, drctg0d_7, + drctg0d_8, drctg0d_8, drctg0d_8, drctg0d_8, drctg0d_9, drctg0d_9, drctg0d_9, drctg0d_9, + drctg0d_a, drctg0d_a, drctg0d_a, drctg0d_a, drctg0d_b, drctg0d_b, drctg0d_b, drctg0d_b, + drctg0d_c, drctg0d_c, drctg0d_c, drctg0d_c, drctg0d_d, drctg0d_d, drctg0d_d, drctg0d_d, + drctg0d_e, drctg0d_e, drctg0d_e, drctg0d_e, drctg0d_f, drctg0d_f, drctg0d_f, drctg0d_f, // #define THUMB_BLOP_LO ((UINT16)0x0800) - drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, - drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, - drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, - drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, - drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, - drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, - drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, - drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, + drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, + drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, + drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, + drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, drctg0e_0, + drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, + drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, + drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, + drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, drctg0e_1, // #define THUMB_BLOP_LO ((UINT16)0x0800) - drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, - drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, - drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, - drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, - drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, - drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, - drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, - drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, + drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, + drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, + drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, + drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, drctg0f_0, + drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, + drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, + drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, + drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, drctg0f_1, }; /* Shift operations */ @@ -1578,4 +1578,4 @@ const void drctg0f_1(arm_state *arm, drcuml_block *block, compiler_state *compil UML_MOV(block, DRC_PC, I0); } -#endif // ARM7_USE_DRC
\ No newline at end of file +#endif // ARM7_USE_DRC diff --git a/src/emu/cpu/cpu.mak b/src/emu/cpu/cpu.mak index 7164e95e61e..f2026947a68 100644 --- a/src/emu/cpu/cpu.mak +++ b/src/emu/cpu/cpu.mak @@ -287,7 +287,7 @@ OBJDIRS += $(CPUOBJ)/es5510 CPUOBJS += $(CPUOBJ)/es5510/es5510.o endif -$(CPUOBJ)/es5510.o: $(CPUSRC)/es5510/es5510.c \ +$(CPUOBJ)/es5510.o: $(CPUSRC)/es5510/es5510.c \ $(CPUSRC)/es5510/es5510.h diff --git a/src/emu/cpu/dsp16/dsp16.c b/src/emu/cpu/dsp16/dsp16.c index d8a0ecf6190..f2ba79621a8 100644 --- a/src/emu/cpu/dsp16/dsp16.c +++ b/src/emu/cpu/dsp16/dsp16.c @@ -30,46 +30,46 @@ const device_type DSP16 = &device_creator<dsp16_device>; dsp16_device::dsp16_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : cpu_device(mconfig, DSP16, "DSP16", tag, owner, clock), - m_program_config("program", ENDIANNESS_LITTLE, 16, 16, -1), - m_data_config("data", ENDIANNESS_LITTLE, 16, 16, -1), - m_i(0), - m_pc(0), - m_pt(0), - m_pr(0), - m_pi(0), - m_j(0), - m_k(0), - m_rb(0), - m_re(0), - m_r0(0), - m_r1(0), - m_r2(0), - m_r3(0), - m_x(0), - m_y(0), - m_p(0), - m_a0(0), - m_a1(0), - m_auc(0), - m_psw(0), - m_c0(0), - m_c1(0), - m_c2(0), - m_sioc(0), - m_srta(0), - m_sdx(0), - m_pioc(0), - m_pdx0(0), - m_pdx1(0), - m_ppc(0), - m_cacheStart(CACHE_INVALID), - m_cacheEnd(CACHE_INVALID), - m_cacheRedoNextPC(CACHE_INVALID), - m_cacheIterations(0), - m_program(NULL), - m_data(NULL), - m_direct(NULL), - m_icount(0) + m_program_config("program", ENDIANNESS_LITTLE, 16, 16, -1), + m_data_config("data", ENDIANNESS_LITTLE, 16, 16, -1), + m_i(0), + m_pc(0), + m_pt(0), + m_pr(0), + m_pi(0), + m_j(0), + m_k(0), + m_rb(0), + m_re(0), + m_r0(0), + m_r1(0), + m_r2(0), + m_r3(0), + m_x(0), + m_y(0), + m_p(0), + m_a0(0), + m_a1(0), + m_auc(0), + m_psw(0), + m_c0(0), + m_c1(0), + m_c2(0), + m_sioc(0), + m_srta(0), + m_sdx(0), + m_pioc(0), + m_pdx0(0), + m_pdx1(0), + m_ppc(0), + m_cacheStart(CACHE_INVALID), + m_cacheEnd(CACHE_INVALID), + m_cacheRedoNextPC(CACHE_INVALID), + m_cacheIterations(0), + m_program(NULL), + m_data(NULL), + m_direct(NULL), + m_icount(0) { // Allocate & setup } @@ -195,8 +195,8 @@ void dsp16_device::device_reset() const address_space_config *dsp16_device::memory_space_config(address_spacenum spacenum) const { return (spacenum == AS_PROGRAM) ? &m_program_config : - (spacenum == AS_DATA) ? &m_data_config : - NULL; + (spacenum == AS_DATA) ? &m_data_config : + NULL; } @@ -325,7 +325,7 @@ void dsp16_device::execute_run() do { // debugging - m_ppc = m_pc; // copy PC to previous PC + m_ppc = m_pc; // copy PC to previous PC debugger_instruction_hook(this, m_pc); // instruction fetch & execute diff --git a/src/emu/cpu/dsp16/dsp16.h b/src/emu/cpu/dsp16/dsp16.h index b87f775a8e7..274f6f72f57 100644 --- a/src/emu/cpu/dsp16/dsp16.h +++ b/src/emu/cpu/dsp16/dsp16.h @@ -55,7 +55,7 @@ protected: // CPU registers // ROM Address Arithmetic Unit (XAAU) - UINT16 m_i; // 12 bits + UINT16 m_i; // 12 bits UINT16 m_pc; UINT16 m_pt; UINT16 m_pr; @@ -73,9 +73,9 @@ protected: UINT16 m_x; UINT32 m_y; UINT32 m_p; - UINT64 m_a0; // 36 bits - UINT64 m_a1; // 36 bits - UINT8 m_auc; // 6 bits + UINT64 m_a0; // 36 bits + UINT64 m_a1; // 36 bits + UINT8 m_auc; // 6 bits UINT16 m_psw; UINT8 m_c0; UINT8 m_c1; @@ -85,8 +85,8 @@ protected: UINT16 m_srta; UINT16 m_sdx; UINT16 m_pioc; - UINT16 m_pdx0; // pdx0 & pdx1 refer to the same physical register (page 6-1) - UINT16 m_pdx1; // but we keep them seperate for logic's sake. + UINT16 m_pdx0; // pdx0 & pdx1 refer to the same physical register (page 6-1) + UINT16 m_pdx1; // but we keep them seperate for logic's sake. // internal stuff UINT16 m_ppc; @@ -143,12 +143,12 @@ extern const device_type DSP16; enum { - DSP16_I, // ROM Address Arithmetic Unit (XAAU) + DSP16_I, // ROM Address Arithmetic Unit (XAAU) DSP16_PC, DSP16_PT, DSP16_PR, DSP16_PI, - DSP16_J, // RAM Address Arithmetic Unit (YAAU) + DSP16_J, // RAM Address Arithmetic Unit (YAAU) DSP16_K, DSP16_RB, DSP16_RE, @@ -156,7 +156,7 @@ enum DSP16_R1, DSP16_R2, DSP16_R3, - DSP16_X, // Data Arithmetic Unit (DAU) + DSP16_X, // Data Arithmetic Unit (DAU) DSP16_Y, DSP16_P, DSP16_A0, @@ -170,8 +170,8 @@ enum DSP16_SRTA, DSP16_SDX, DSP16_PIOC, - DSP16_PDX0, - DSP16_PDX1 + DSP16_PDX0, + DSP16_PDX1 }; diff --git a/src/emu/cpu/dsp16/dsp16dis.c b/src/emu/cpu/dsp16/dsp16dis.c index 9b58d190306..8b648f7a6d3 100644 --- a/src/emu/cpu/dsp16/dsp16dis.c +++ b/src/emu/cpu/dsp16/dsp16dis.c @@ -234,8 +234,8 @@ bool disasmSIField(const UINT8& SI) { switch (SI) { - case 0x00: return 0; // Not a software interrupt - case 0x01: return 1; // Software Interrupt + case 0x00: return 0; // Not a software interrupt + case 0x01: return 1; // Software Interrupt } return false; } @@ -505,7 +505,7 @@ CPU_DISASSEMBLE( dsp16a ) const UINT8 R = (op & 0x03f0) >> 4; astring yString = disasmYField(Y); astring rString = disasmRField(R); - // TODO: page 3-31 "special function encoding" + // TODO: page 3-31 "special function encoding" sprintf(buffer, "%s = %s", yString.cstr(), rString.cstr()); break; } diff --git a/src/emu/cpu/dsp16/dsp16ops.c b/src/emu/cpu/dsp16/dsp16ops.c index 778d0b7b1af..4bd704bade9 100644 --- a/src/emu/cpu/dsp16/dsp16ops.c +++ b/src/emu/cpu/dsp16/dsp16ops.c @@ -49,24 +49,24 @@ bool dsp16_device::conditionTest(const UINT8& CON) { switch (CON) { - case 0x00: return (m_psw & 0x8000); // mi (negative result) - case 0x01: printf("UNIMPLEMENTED condition check @ PC 0x%04x\n", m_pc); return false; // pl (positive result) - case 0x02: printf("UNIMPLEMENTED condition check @ PC 0x%04x\n", m_pc); return false; // eq (result == 0) - case 0x03: printf("UNIMPLEMENTED condition check @ PC 0x%04x\n", m_pc); return false; // ne (result != 0) - case 0x04: printf("UNIMPLEMENTED condition check @ PC 0x%04x\n", m_pc); return false; // lvs (logical overflow set) - case 0x05: printf("UNIMPLEMENTED condition check @ PC 0x%04x\n", m_pc); return false; // lvc (logical overflow clear) - case 0x06: printf("UNIMPLEMENTED condition check @ PC 0x%04x\n", m_pc); return false; // mvs (math. overflow set) - case 0x07: printf("UNIMPLEMENTED condition check @ PC 0x%04x\n", m_pc); return false; // mvc (math. overflow clear) - case 0x08: printf("UNIMPLEMENTED condition check @ PC 0x%04x\n", m_pc); return false; // heads (random bit set) - case 0x09: printf("UNIMPLEMENTED condition check @ PC 0x%04x\n", m_pc); return false; // tails (random bit clear) - case 0x0a: printf("UNIMPLEMENTED condition check @ PC 0x%04x\n", m_pc); return false; // c0ge (counter0 >= 0) - case 0x0b: printf("UNIMPLEMENTED condition check @ PC 0x%04x\n", m_pc); return false; // c0lt (counter0 < 0) - case 0x0c: printf("UNIMPLEMENTED condition check @ PC 0x%04x\n", m_pc); return false; // c1ge (counter1 >= 0) - case 0x0d: printf("UNIMPLEMENTED condition check @ PC 0x%04x\n", m_pc); return false; // c1lt (counter1 < 0) - case 0x0e: printf("UNIMPLEMENTED condition check @ PC 0x%04x\n", m_pc); return false; // true (always) - case 0x0f: printf("UNIMPLEMENTED condition check @ PC 0x%04x\n", m_pc); return false; // false (never) - case 0x10: printf("UNIMPLEMENTED condition check @ PC 0x%04x\n", m_pc); return false; // gt (result > 0 - case 0x11: printf("UNIMPLEMENTED condition check @ PC 0x%04x\n", m_pc); return false; // le (result <= 0) + case 0x00: return (m_psw & 0x8000); // mi (negative result) + case 0x01: printf("UNIMPLEMENTED condition check @ PC 0x%04x\n", m_pc); return false; // pl (positive result) + case 0x02: printf("UNIMPLEMENTED condition check @ PC 0x%04x\n", m_pc); return false; // eq (result == 0) + case 0x03: printf("UNIMPLEMENTED condition check @ PC 0x%04x\n", m_pc); return false; // ne (result != 0) + case 0x04: printf("UNIMPLEMENTED condition check @ PC 0x%04x\n", m_pc); return false; // lvs (logical overflow set) + case 0x05: printf("UNIMPLEMENTED condition check @ PC 0x%04x\n", m_pc); return false; // lvc (logical overflow clear) + case 0x06: printf("UNIMPLEMENTED condition check @ PC 0x%04x\n", m_pc); return false; // mvs (math. overflow set) + case 0x07: printf("UNIMPLEMENTED condition check @ PC 0x%04x\n", m_pc); return false; // mvc (math. overflow clear) + case 0x08: printf("UNIMPLEMENTED condition check @ PC 0x%04x\n", m_pc); return false; // heads (random bit set) + case 0x09: printf("UNIMPLEMENTED condition check @ PC 0x%04x\n", m_pc); return false; // tails (random bit clear) + case 0x0a: printf("UNIMPLEMENTED condition check @ PC 0x%04x\n", m_pc); return false; // c0ge (counter0 >= 0) + case 0x0b: printf("UNIMPLEMENTED condition check @ PC 0x%04x\n", m_pc); return false; // c0lt (counter0 < 0) + case 0x0c: printf("UNIMPLEMENTED condition check @ PC 0x%04x\n", m_pc); return false; // c1ge (counter1 >= 0) + case 0x0d: printf("UNIMPLEMENTED condition check @ PC 0x%04x\n", m_pc); return false; // c1lt (counter1 < 0) + case 0x0e: printf("UNIMPLEMENTED condition check @ PC 0x%04x\n", m_pc); return false; // true (always) + case 0x0f: printf("UNIMPLEMENTED condition check @ PC 0x%04x\n", m_pc); return false; // false (never) + case 0x10: printf("UNIMPLEMENTED condition check @ PC 0x%04x\n", m_pc); return false; // gt (result > 0 + case 0x11: printf("UNIMPLEMENTED condition check @ PC 0x%04x\n", m_pc); return false; // le (result <= 0) default: logerror("Unrecognized condition at PC=0x%04x\n", m_pc); break; } return false; @@ -112,11 +112,11 @@ void* dsp16_device::registerFromRTable(const UINT8 &R) case 0x10: return (void*)&m_x; case 0x11: return (void*)&m_y; case 0x12: return (void*)addressYL(); - case 0x13: return (void*)&m_auc; // zero extended + case 0x13: return (void*)&m_auc; // zero extended case 0x14: return (void*)&m_psw; - case 0x15: return (void*)&m_c0; // sign extended - case 0x16: return (void*)&m_c1; // sign extended - case 0x17: return (void*)&m_c2; // sign extended + case 0x15: return (void*)&m_c0; // sign extended + case 0x16: return (void*)&m_c1; // sign extended + case 0x17: return (void*)&m_c2; // sign extended case 0x18: return (void*)&m_sioc; case 0x19: return (void*)&m_srta; case 0x1a: return (void*)&m_sdx; @@ -137,20 +137,20 @@ void dsp16_device::executeF1Field(const UINT8& F1, const UINT8& D, const UINT8& //UINT64* destinationReg = NULL; //switch (D) //{ - // case 0x00: destinationReg = &m_a0; - // case 0x01: destinationReg = &m_a1; - // default: break; + // case 0x00: destinationReg = &m_a0; + // case 0x01: destinationReg = &m_a1; + // default: break; //} // Which source is being used? //UINT64* sourceReg = NULL; //switch (S) //{ - // case 0x00: sourceReg = &m_a0; - // case 0x01: sourceReg = &m_a1; - // default: break; + // case 0x00: sourceReg = &m_a0; + // case 0x01: sourceReg = &m_a1; + // default: break; //} - + switch (F1) { case 0x00: printf("UNIMPLEMENTED F1 operation @ PC 0x%04x\n", m_pc); break; @@ -201,7 +201,7 @@ void dsp16_device::executeYFieldPost(const UINT8& Y) case 0x03: opReg = &m_r3; break; default: break; } - + const UINT8 lower = Y & 0x03; switch (lower) { @@ -341,7 +341,7 @@ void dsp16_device::execute_one(const UINT16& op, UINT8& cycles, UINT8& pcAdvance case 0x00: m_pt++; break; case 0x01: m_pt += m_i; break; } - cycles = 2; // TODO: 1 if cached + cycles = 2; // TODO: 1 if cached pcAdvance = 1; break; } @@ -355,15 +355,15 @@ void dsp16_device::execute_one(const UINT16& op, UINT8& cycles, UINT8& pcAdvance const UINT8 F1 = (op & 0x01e0) >> 5; bool useA1 = (opcode == 0x1b); if (Y != 0x00) printf("Unknown opcode @ PC=0x%04x", m_pc); - m_y = (useA1) ? (m_a1 & 0xffffffff) : (m_a0 & 0xffffffff); // TODO: What happens to Ax when it goes 32 bit (pc=3f & pc=47)? + m_y = (useA1) ? (m_a1 & 0xffffffff) : (m_a0 & 0xffffffff); // TODO: What happens to Ax when it goes 32 bit (pc=3f & pc=47)? executeF1Field(F1, D, S); - writeRegister(&m_x, data_read(m_pt)); // TODO: EXM Pin & internal/external ROM? Research. + writeRegister(&m_x, data_read(m_pt)); // TODO: EXM Pin & internal/external ROM? Research. switch (X) { case 0x00: m_pt++; break; case 0x01: m_pt += m_i; break; } - cycles = 2; // TODO: 1 if cached + cycles = 2; // TODO: 1 if cached pcAdvance = 1; break; } @@ -425,30 +425,30 @@ void dsp16_device::execute_one(const UINT16& op, UINT8& cycles, UINT8& pcAdvance const UINT8 S = (op & 0x0200) >> 9; const UINT8 D = (op & 0x0400) >> 10; const UINT8 F1 = (op & 0x01e0) >> 5; - executeF1Field(F1, D, S); - UINT16 temp = 0x0000; - UINT16* rN = (UINT16*)registerFromYFieldUpper(Z); - switch (X) - { - case 0x00: - temp = m_y & 0x0000ffff; - m_y &= 0xffff0000; - m_y |= data_read(*rN); - executeZFieldPartOne(Z, rN); - data_write(*rN, temp); - executeZFieldPartTwo(Z, rN); - break; - case 0x01: - temp = (m_y & 0xffff0000) >> 16; - m_y &= 0x0000ffff; - m_y |= (data_read(*rN) << 16); - executeZFieldPartOne(Z, rN); - data_write(*rN, temp); - executeZFieldPartTwo(Z, rN); - break; - } - cycles = 2; - pcAdvance = 1; + executeF1Field(F1, D, S); + UINT16 temp = 0x0000; + UINT16* rN = (UINT16*)registerFromYFieldUpper(Z); + switch (X) + { + case 0x00: + temp = m_y & 0x0000ffff; + m_y &= 0xffff0000; + m_y |= data_read(*rN); + executeZFieldPartOne(Z, rN); + data_write(*rN, temp); + executeZFieldPartTwo(Z, rN); + break; + case 0x01: + temp = (m_y & 0xffff0000) >> 16; + m_y &= 0x0000ffff; + m_y |= (data_read(*rN) << 16); + executeZFieldPartOne(Z, rN); + data_write(*rN, temp); + executeZFieldPartTwo(Z, rN); + break; + } + cycles = 2; + pcAdvance = 1; break; } case 0x1d: @@ -539,7 +539,7 @@ void dsp16_device::execute_one(const UINT16& op, UINT8& cycles, UINT8& pcAdvance // if CON [goto/call/return] : (page 3-22) const UINT8 CON = (op & 0x001f); bool conditionFulfilled = conditionTest(CON); - cycles = 3; // TODO: This may need to interact with the next opcode to make sure it doesn't exceed 3? + cycles = 3; // TODO: This may need to interact with the next opcode to make sure it doesn't exceed 3? pcAdvance = 1; if (!conditionFulfilled) { @@ -577,7 +577,7 @@ void dsp16_device::execute_one(const UINT16& op, UINT8& cycles, UINT8& pcAdvance } void* sourceReg = registerFromRTable(R); *destinationReg &= U64(0x00000ffff); - *destinationReg |= (*(UINT16*)sourceReg) << 16; // TODO: Fix for all registers + *destinationReg |= (*(UINT16*)sourceReg) << 16; // TODO: Fix for all registers if (*(UINT16*)sourceReg & 0x8000) *destinationReg |= U64(0xf00000000); // TODO: Special function encoding @@ -639,7 +639,7 @@ void dsp16_device::execute_one(const UINT16& op, UINT8& cycles, UINT8& pcAdvance const INT8 M = (op & 0x00ff); const UINT8 R = (op & 0x0e00) >> 9; void* reg = registerFromRImmediateField(R); - writeRegister(reg, (INT16)M); // Sign extend 8 bit int + writeRegister(reg, (INT16)M); // Sign extend 8 bit int cycles = 1; pcAdvance = 1; break; @@ -656,14 +656,14 @@ void dsp16_device::execute_one(const UINT16& op, UINT8& cycles, UINT8& pcAdvance // Do m_cacheStart = m_pc + 1; m_cacheEnd = m_pc + NI + 1; - m_cacheIterations = K-1; // -1 because we check the counter @ the end + m_cacheIterations = K-1; // -1 because we check the counter @ the end cycles = 1; pcAdvance = 1; } else { // Redo - m_cacheIterations = K-1; // -1 because we check the counter @ the end + m_cacheIterations = K-1; // -1 because we check the counter @ the end m_cacheRedoNextPC = m_pc + 1; m_pc = m_cacheStart; pcAdvance = 0; diff --git a/src/emu/cpu/es5510/es5510.c b/src/emu/cpu/es5510/es5510.c index 72705b188cd..0e1a6590f18 100644 --- a/src/emu/cpu/es5510/es5510.c +++ b/src/emu/cpu/es5510/es5510.c @@ -29,106 +29,106 @@ char *stpcpy_int (char *dst, const char *src) } inline static UINT8 setFlag(UINT8 ccr, UINT8 flag) { - return ccr | flag; + return ccr | flag; } inline static UINT8 clearFlag(UINT8 ccr, UINT8 flag) { - return ccr & ~flag; + return ccr & ~flag; } inline static UINT8 setFlagTo(UINT8 ccr, UINT8 flag, bool set) { - return set ? setFlag(ccr, flag) : clearFlag(ccr, flag); + return set ? setFlag(ccr, flag) : clearFlag(ccr, flag); } inline static bool isFlagSet(UINT8 ccr, UINT8 flag) { - return (ccr & flag) != 0; + return (ccr & flag) != 0; } inline static INT32 add(INT32 a, INT32 b, UINT8 &flags) { - INT32 aSign = a & 0x00800000; - INT32 bSign = (b & 0x00800000) == 0; - INT32 result = a + b; - INT32 resultSign = result & 0x00800000; - bool overflow = (aSign == bSign) && (aSign != resultSign); - bool carry = result & 0x01000000; - bool negative = resultSign != 0; - bool lessThan = (overflow && !negative) || (!overflow && negative); - flags = setFlagTo(flags, FLAG_C, carry); - flags = setFlagTo(flags, FLAG_N, negative); - flags = setFlagTo(flags, FLAG_Z, result == 0); - flags = setFlagTo(flags, FLAG_V, overflow); - flags = setFlagTo(flags, FLAG_LT, lessThan); - return result; + INT32 aSign = a & 0x00800000; + INT32 bSign = (b & 0x00800000) == 0; + INT32 result = a + b; + INT32 resultSign = result & 0x00800000; + bool overflow = (aSign == bSign) && (aSign != resultSign); + bool carry = result & 0x01000000; + bool negative = resultSign != 0; + bool lessThan = (overflow && !negative) || (!overflow && negative); + flags = setFlagTo(flags, FLAG_C, carry); + flags = setFlagTo(flags, FLAG_N, negative); + flags = setFlagTo(flags, FLAG_Z, result == 0); + flags = setFlagTo(flags, FLAG_V, overflow); + flags = setFlagTo(flags, FLAG_LT, lessThan); + return result; } inline static INT32 saturate(INT32 value, UINT8 &flags) { - if (isFlagSet(flags, FLAG_V)) { - return isFlagSet(flags, FLAG_N) ? 0x00800000 : 0x007fffff; - } else { - return value; - } + if (isFlagSet(flags, FLAG_V)) { + return isFlagSet(flags, FLAG_N) ? 0x00800000 : 0x007fffff; + } else { + return value; + } } inline static INT32 negate(INT32 value) { - return (value ^ 0x00ffffff) + 1; + return (value ^ 0x00ffffff) + 1; } inline static INT32 asl(INT32 value, int shift, UINT8 &flags) { - INT32 signBefore = value & 0x00800000; - INT32 result = (value << shift) & 0x00ffffff; - INT32 signAfter = result & 0x00800000; - bool overflow = signBefore != signAfter; - flags = setFlagTo(flags, FLAG_V, overflow); - return saturate(result, flags); + INT32 signBefore = value & 0x00800000; + INT32 result = (value << shift) & 0x00ffffff; + INT32 signAfter = result & 0x00800000; + bool overflow = signBefore != signAfter; + flags = setFlagTo(flags, FLAG_V, overflow); + return saturate(result, flags); } es5510_device::es5510_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) - : cpu_device(mconfig, ES5510, "ES5510", tag, owner, clock) + : cpu_device(mconfig, ES5510, "ES5510", tag, owner, clock) { - // Initialize ESP to mostly zeroed, configured for 64k samples of delay line memory, running (not halted) - icount = 0; - pc = 0; - state = STATE_HALTED; - memset(gpr, 0, 0xc0 * sizeof(gpr[0])); - ser0r = 0; - ser0l = 0; - ser1r = 0; - ser1l = 0; - ser2r = 0; - ser2l = 0; - ser3r = 0; - ser3l = 0; - machl = 0; - dil = 0; - memsiz = 0x00ffffff; - memmask = 0x00000000; - memincrement = 0x01000000; - memshift = 24; - dlength = 0; - abase = 0; - bbase = 0; - dbase = 0; - sigreg = 1; - mulshift = 1; - ccr = 0; - cmr = 0; - dol[0] = dol[1] = 0; - dol_count = 0; - - memset(instr, 0, 160 * sizeof(instr[0])); - memset(dram, 0, (1<<20) * sizeof(dram[0])); - - dol_latch = 0; - dil_latch = 0; - dadr_latch = 0; - gpr_latch = 0; - instr_latch = 0; - ram_sel = 0; - host_control = 0; - - memset(&alu, 0, sizeof(alu)); - memset(&mulacc, 0, sizeof(mulacc)); + // Initialize ESP to mostly zeroed, configured for 64k samples of delay line memory, running (not halted) + icount = 0; + pc = 0; + state = STATE_HALTED; + memset(gpr, 0, 0xc0 * sizeof(gpr[0])); + ser0r = 0; + ser0l = 0; + ser1r = 0; + ser1l = 0; + ser2r = 0; + ser2l = 0; + ser3r = 0; + ser3l = 0; + machl = 0; + dil = 0; + memsiz = 0x00ffffff; + memmask = 0x00000000; + memincrement = 0x01000000; + memshift = 24; + dlength = 0; + abase = 0; + bbase = 0; + dbase = 0; + sigreg = 1; + mulshift = 1; + ccr = 0; + cmr = 0; + dol[0] = dol[1] = 0; + dol_count = 0; + + memset(instr, 0, 160 * sizeof(instr[0])); + memset(dram, 0, (1<<20) * sizeof(dram[0])); + + dol_latch = 0; + dil_latch = 0; + dadr_latch = 0; + gpr_latch = 0; + instr_latch = 0; + ram_sel = 0; + host_control = 0; + + memset(&alu, 0, sizeof(alu)); + memset(&mulacc, 0, sizeof(mulacc)); } typedef es5510_device::alu_op_t alu_op_t; @@ -141,733 +141,733 @@ static inline INT64 SX64(INT64 x) { return (x & U64(0x0000800000000000)) ? x | U static inline INT64 SC64(INT64 x) { return x & U64(0x0000ffffffffffff); } static inline const char * const REGNAME(UINT8 r) { - static char rn[8]; - if (r < 234) { sprintf(rn, "GPR_%02x", r); return rn; } - switch(r) { - case 234: return "SER0R"; - case 235: return "SER0L"; - case 236: return "SER1R"; - case 237: return "SER1L"; - case 238: return "SER2R"; - case 239: return "SER2L"; - case 240: return "SER3R"; - case 241: return "SER3L"; - case 242: return "MACL"; - case 243: return "MACH"; - case 244: return "DIL/MEMSIZ"; - case 245: return "DLENGTH"; - case 246: return "ABASE"; - case 247: return "BBASE"; - case 248: return "DBASE"; - case 249: return "SIGREG"; - case 250: return "CCR"; - case 251: return "CMR"; - case 252: return "MINUS1"; - case 253: return "MIN"; - case 254: return "MAX"; - case 255: return "ZERO"; - } - return NULL; + static char rn[8]; + if (r < 234) { sprintf(rn, "GPR_%02x", r); return rn; } + switch(r) { + case 234: return "SER0R"; + case 235: return "SER0L"; + case 236: return "SER1R"; + case 237: return "SER1L"; + case 238: return "SER2R"; + case 239: return "SER2L"; + case 240: return "SER3R"; + case 241: return "SER3L"; + case 242: return "MACL"; + case 243: return "MACH"; + case 244: return "DIL/MEMSIZ"; + case 245: return "DLENGTH"; + case 246: return "ABASE"; + case 247: return "BBASE"; + case 248: return "DBASE"; + case 249: return "SIGREG"; + case 250: return "CCR"; + case 251: return "CMR"; + case 252: return "MINUS1"; + case 253: return "MIN"; + case 254: return "MAX"; + case 255: return "ZERO"; + } + return NULL; } static inline char * DESCRIBE_REG(char *s, UINT8 r) { - return stpcpy_int(s, REGNAME(r)); + return stpcpy_int(s, REGNAME(r)); } const alu_op_t es5510_device::ALU_OPS[16] = { - { 2, "ADD" }, - { 2, "SUB" }, - { 2, "ADDU" }, - { 2, "SUBU" }, - { 2, "CMP" }, - { 2, "AND" }, - { 2, "OR" }, - { 2, "XOR" }, - { 1, "ABS" }, - { 1, "MOV" }, - { 1, "ASL2" }, - { 1, "ASL8" }, - { 1, "LS15" }, - { 2, "DIFF" }, - { 1, "ASR" }, - { 0, "END" }, + { 2, "ADD" }, + { 2, "SUB" }, + { 2, "ADDU" }, + { 2, "SUBU" }, + { 2, "CMP" }, + { 2, "AND" }, + { 2, "OR" }, + { 2, "XOR" }, + { 1, "ABS" }, + { 1, "MOV" }, + { 1, "ASL2" }, + { 1, "ASL8" }, + { 1, "LS15" }, + { 2, "DIFF" }, + { 1, "ASR" }, + { 0, "END" }, }; // The CMP operation is not affected by being skippable #define OP_CMP (4) const op_select_t es5510_device::OPERAND_SELECT[16] = { - { es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG }, - { es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_DELAY }, - { es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_BOTH }, - { es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_REG }, - { es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_BOTH }, - { es5510_device::SRC_DST_REG, es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG }, - { es5510_device::SRC_DST_REG, es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_REG }, - { es5510_device::SRC_DST_REG, es5510_device::SRC_DST_BOTH, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG }, - { es5510_device::SRC_DST_REG, es5510_device::SRC_DST_BOTH, es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_REG }, - { es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG }, - { es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_DELAY }, - { es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_BOTH }, - { es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_REG }, - { es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_BOTH }, - { es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_BOTH, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG }, - { es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_BOTH, es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_REG }, + { es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG }, + { es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_DELAY }, + { es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_BOTH }, + { es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_REG }, + { es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_BOTH }, + { es5510_device::SRC_DST_REG, es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG }, + { es5510_device::SRC_DST_REG, es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_REG }, + { es5510_device::SRC_DST_REG, es5510_device::SRC_DST_BOTH, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG }, + { es5510_device::SRC_DST_REG, es5510_device::SRC_DST_BOTH, es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_REG }, + { es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG }, + { es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_DELAY }, + { es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_BOTH }, + { es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_REG }, + { es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_BOTH }, + { es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_BOTH, es5510_device::SRC_DST_REG, es5510_device::SRC_DST_REG }, + { es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_BOTH, es5510_device::SRC_DST_DELAY, es5510_device::SRC_DST_REG }, }; static inline char * DESCRIBE_SRC_DST(char *s, UINT8 reg, op_src_dst_t src_dst) { - switch (src_dst) { - case es5510_device::SRC_DST_REG: - return DESCRIBE_REG(s, reg); - case es5510_device::SRC_DST_DELAY: - return stpcpy_int(s, "Delay"); - case es5510_device::SRC_DST_BOTH: - s = DESCRIBE_REG(s, reg); - return stpcpy_int(s, ",Delay"); - } - // should never happen! - return s; + switch (src_dst) { + case es5510_device::SRC_DST_REG: + return DESCRIBE_REG(s, reg); + case es5510_device::SRC_DST_DELAY: + return stpcpy_int(s, "Delay"); + case es5510_device::SRC_DST_BOTH: + s = DESCRIBE_REG(s, reg); + return stpcpy_int(s, ",Delay"); + } + // should never happen! + return s; } const es5510_device::ram_control_t es5510_device::RAM_CONTROL[8] = { - { es5510_device::RAM_CYCLE_READ, es5510_device::RAM_CONTROL_DELAY, "Read Delay+%06x" }, - { es5510_device::RAM_CYCLE_WRITE, es5510_device::RAM_CONTROL_DELAY, "Write Delay+%06x" }, - { es5510_device::RAM_CYCLE_READ, es5510_device::RAM_CONTROL_TABLE_A, "Read Table A+%06x" }, - { es5510_device::RAM_CYCLE_WRITE, es5510_device::RAM_CONTROL_TABLE_A, "Write Table A+%06x" }, - { es5510_device::RAM_CYCLE_READ, es5510_device::RAM_CONTROL_TABLE_B, "Read Table B+%06x" }, - { es5510_device::RAM_CYCLE_DUMP_FIFO, es5510_device::RAM_CONTROL_DELAY, "Read Delay+%06x and Dump FIFO" }, - { es5510_device::RAM_CYCLE_READ, es5510_device::RAM_CONTROL_IO, "Read I/O at %06x" }, - { es5510_device::RAM_CYCLE_WRITE, es5510_device::RAM_CONTROL_IO, "Write I/o %06x" }, + { es5510_device::RAM_CYCLE_READ, es5510_device::RAM_CONTROL_DELAY, "Read Delay+%06x" }, + { es5510_device::RAM_CYCLE_WRITE, es5510_device::RAM_CONTROL_DELAY, "Write Delay+%06x" }, + { es5510_device::RAM_CYCLE_READ, es5510_device::RAM_CONTROL_TABLE_A, "Read Table A+%06x" }, + { es5510_device::RAM_CYCLE_WRITE, es5510_device::RAM_CONTROL_TABLE_A, "Write Table A+%06x" }, + { es5510_device::RAM_CYCLE_READ, es5510_device::RAM_CONTROL_TABLE_B, "Read Table B+%06x" }, + { es5510_device::RAM_CYCLE_DUMP_FIFO, es5510_device::RAM_CONTROL_DELAY, "Read Delay+%06x and Dump FIFO" }, + { es5510_device::RAM_CYCLE_READ, es5510_device::RAM_CONTROL_IO, "Read I/O at %06x" }, + { es5510_device::RAM_CYCLE_WRITE, es5510_device::RAM_CONTROL_IO, "Write I/o %06x" }, }; static inline char * DESCRIBE_RAM(char *s, UINT8 ramControl, UINT32 gprContents) { - return s + sprintf(s, es5510_device::RAM_CONTROL[ramControl].description, SC(gprContents)); + return s + sprintf(s, es5510_device::RAM_CONTROL[ramControl].description, SC(gprContents)); } static inline char * DESCRIBE_ALU(char *s, UINT8 opcode, UINT8 aReg, UINT8 bReg, const op_select_t &opSelect) { - const alu_op_t &op = es5510_device::ALU_OPS[opcode]; + const alu_op_t &op = es5510_device::ALU_OPS[opcode]; - switch (op.operands) { - case 0: - return stpcpy_int(s, op.opcode); + switch (op.operands) { + case 0: + return stpcpy_int(s, op.opcode); - case 1: - s += sprintf(s, "%s %s >", op.opcode, REGNAME(bReg)); - return DESCRIBE_SRC_DST(s, aReg, opSelect.alu_dst); - - case 2: - s += sprintf(s, "%s %s,", op.opcode, REGNAME(bReg)); - s = DESCRIBE_SRC_DST(s, aReg, opSelect.alu_src); - s += sprintf(s, " >"); - return DESCRIBE_SRC_DST(s, aReg, opSelect.alu_dst); - } - return s; + case 1: + s += sprintf(s, "%s %s >", op.opcode, REGNAME(bReg)); + return DESCRIBE_SRC_DST(s, aReg, opSelect.alu_dst); + + case 2: + s += sprintf(s, "%s %s,", op.opcode, REGNAME(bReg)); + s = DESCRIBE_SRC_DST(s, aReg, opSelect.alu_src); + s += sprintf(s, " >"); + return DESCRIBE_SRC_DST(s, aReg, opSelect.alu_dst); + } + return s; } static inline char * DESCRIBE_MAC(char *s, UINT8 mac, UINT8 cReg, UINT8 dReg, const op_select_t &opSelect) { - if (mac) - { - s += sprintf(s, "MAC + "); - } - s = DESCRIBE_REG(s, dReg); - s += sprintf(s, " * "); - s = DESCRIBE_SRC_DST(s, cReg, opSelect.mac_src); - s += sprintf(s, " >"); - return DESCRIBE_SRC_DST(s, cReg, opSelect.mac_dst); + if (mac) + { + s += sprintf(s, "MAC + "); + } + s = DESCRIBE_REG(s, dReg); + s += sprintf(s, " * "); + s = DESCRIBE_SRC_DST(s, cReg, opSelect.mac_src); + s += sprintf(s, " >"); + return DESCRIBE_SRC_DST(s, cReg, opSelect.mac_dst); } static inline char * DESCRIBE_INSTR(char *s, UINT64 instr, UINT32 gpr) { - UINT8 dReg = (UINT8)((instr >> 40) & 0xff); - UINT8 cReg = (UINT8)((instr >> 32) & 0xff); - UINT8 bReg = (UINT8)((instr >> 24) & 0xff); - UINT8 aReg = (UINT8)((instr >> 16) & 0xff); - UINT8 aluOpcode = (UINT8)((instr >> 12) & 0x0f); - UINT8 operandSelect = (UINT8)((instr >> 8) & 0x0f); - UINT8 skip = (UINT8)((instr >> 7) & 0x01); - UINT8 mac = (UINT8)((instr >> 6) & 0x01); - UINT8 ramControl = (UINT8)((instr >> 3) & 0x07); - - const op_select_t &opSelect = es5510_device::OPERAND_SELECT[operandSelect]; - - s = DESCRIBE_ALU(s, aluOpcode, aReg, bReg, opSelect); - s += sprintf(s, "; "); - s = DESCRIBE_MAC(s, mac, cReg, dReg, opSelect); - s += sprintf(s, "; "); - s = DESCRIBE_RAM(s, ramControl, gpr); - if (skip) { - s += sprintf(s, "; skippable"); - } + UINT8 dReg = (UINT8)((instr >> 40) & 0xff); + UINT8 cReg = (UINT8)((instr >> 32) & 0xff); + UINT8 bReg = (UINT8)((instr >> 24) & 0xff); + UINT8 aReg = (UINT8)((instr >> 16) & 0xff); + UINT8 aluOpcode = (UINT8)((instr >> 12) & 0x0f); + UINT8 operandSelect = (UINT8)((instr >> 8) & 0x0f); + UINT8 skip = (UINT8)((instr >> 7) & 0x01); + UINT8 mac = (UINT8)((instr >> 6) & 0x01); + UINT8 ramControl = (UINT8)((instr >> 3) & 0x07); + + const op_select_t &opSelect = es5510_device::OPERAND_SELECT[operandSelect]; + + s = DESCRIBE_ALU(s, aluOpcode, aReg, bReg, opSelect); + s += sprintf(s, "; "); + s = DESCRIBE_MAC(s, mac, cReg, dReg, opSelect); + s += sprintf(s, "; "); + s = DESCRIBE_RAM(s, ramControl, gpr); + if (skip) { + s += sprintf(s, "; skippable"); + } - return s; + return s; } READ8_MEMBER(es5510_device::host_r) { - // printf("%06x: DSP read offset %04x (data is %04x)\n",space.device().safe_pc(),offset,dsp_ram[offset]); - - // VFX hack - if (mame_stricmp(space.machine().system().name, "vfx") == 0) - { - if (space.device().safe_pc() == 0xc091f0) - { - return space.device().state().state_int(M68K_D2); - } - } - - switch(offset) - { - case 0x00: logerror("ES5510: Read GPR latch[2]: %02x\n", (gpr_latch >> 16) & 0xff); return (gpr_latch >> 16) & 0xff; - case 0x01: logerror("ES5510: Read GPR latch[1]: %02x\n", (gpr_latch >> 8) & 0xff); return (gpr_latch >> 8) & 0xff; - case 0x02: logerror("ES5510: Read GPR latch[0]: %02x\n", (gpr_latch >> 0) & 0xff); return (gpr_latch >> 0) & 0xff; - - case 0x03: logerror("ES5510: Read INSTR latch[5]: %02x\n", (UINT8)((instr_latch >> 40) & 0xff)); return (instr_latch >> 40) & 0xff; - case 0x04: logerror("ES5510: Read INSTR latch[4]: %02x\n", (UINT8)((instr_latch >> 32) & 0xff)); return (instr_latch >> 32) & 0xff; - case 0x05: logerror("ES5510: Read INSTR latch[3]: %02x\n", (UINT8)((instr_latch >> 24) & 0xff)); return (instr_latch >> 24) & 0xff; - case 0x06: logerror("ES5510: Read INSTR latch[2]: %02x\n", (UINT8)((instr_latch >> 16) & 0xff)); return (instr_latch >> 16) & 0xff; - case 0x07: logerror("ES5510: Read INSTR latch[1]: %02x\n", (UINT8)((instr_latch >> 8) & 0xff)); return (instr_latch >> 8) & 0xff; - case 0x08: logerror("ES5510: Read INSTR latch[0]: %02x\n", (UINT8)((instr_latch >> 0) & 0xff)); return (instr_latch >> 0) & 0xff; - - case 0x09: logerror("ES5510: Read DIL latch[2]: %02x\n", (dil_latch >> 16) & 0xff); return (dil_latch >> 16) & 0xff; - case 0x0a: logerror("ES5510: Read DIL latch[1]: %02x\n", (dil_latch >> 8) & 0xff); return (dil_latch >> 8) & 0xff; - case 0x0b: logerror("ES5510: Read DIL latch[0]: %02x\n", (dil_latch >> 0) & 0xff); return (dil_latch >> 0) & 0xff; //TODO: docs says that this always returns 0 - - case 0x0c: logerror("ES5510: Read DOL latch[2]: %02x\n", (dol_latch >> 16) & 0xff); return (dol_latch >> 16) & 0xff; - case 0x0d: logerror("ES5510: Read DOL latch[1]: %02x\n", (dol_latch >> 8) & 0xff); return (dol_latch >> 8) & 0xff; - case 0x0e: logerror("ES5510: Read DOL latch[0]: %02x\n", (dol_latch >> 0) & 0xff); return (dol_latch >> 0) & 0xff; //TODO: docs says that this always returns 0 - - case 0x0f: logerror("ES5510: Read DADR latch[2]: %02x\n", (dadr_latch >> 16) & 0xff); return (dadr_latch >> 16) & 0xff; - case 0x10: logerror("ES5510: Read DADR latch[1]: %02x\n", (dadr_latch >> 8) & 0xff); return (dadr_latch >> 8) & 0xff; - case 0x11: logerror("ES5510: Read DADR latch[0]: %02x\n", (dadr_latch >> 0) & 0xff); return (dadr_latch >> 0) & 0xff; - - case 0x12: logerror("ES5510: Reading Host Control\n"); return 0; // Host Control - - case 0x16: return 0x27; // Program Counter, for test purposes only - } - - // default: 0. - return 0x00; + // printf("%06x: DSP read offset %04x (data is %04x)\n",space.device().safe_pc(),offset,dsp_ram[offset]); + + // VFX hack + if (mame_stricmp(space.machine().system().name, "vfx") == 0) + { + if (space.device().safe_pc() == 0xc091f0) + { + return space.device().state().state_int(M68K_D2); + } + } + + switch(offset) + { + case 0x00: logerror("ES5510: Read GPR latch[2]: %02x\n", (gpr_latch >> 16) & 0xff); return (gpr_latch >> 16) & 0xff; + case 0x01: logerror("ES5510: Read GPR latch[1]: %02x\n", (gpr_latch >> 8) & 0xff); return (gpr_latch >> 8) & 0xff; + case 0x02: logerror("ES5510: Read GPR latch[0]: %02x\n", (gpr_latch >> 0) & 0xff); return (gpr_latch >> 0) & 0xff; + + case 0x03: logerror("ES5510: Read INSTR latch[5]: %02x\n", (UINT8)((instr_latch >> 40) & 0xff)); return (instr_latch >> 40) & 0xff; + case 0x04: logerror("ES5510: Read INSTR latch[4]: %02x\n", (UINT8)((instr_latch >> 32) & 0xff)); return (instr_latch >> 32) & 0xff; + case 0x05: logerror("ES5510: Read INSTR latch[3]: %02x\n", (UINT8)((instr_latch >> 24) & 0xff)); return (instr_latch >> 24) & 0xff; + case 0x06: logerror("ES5510: Read INSTR latch[2]: %02x\n", (UINT8)((instr_latch >> 16) & 0xff)); return (instr_latch >> 16) & 0xff; + case 0x07: logerror("ES5510: Read INSTR latch[1]: %02x\n", (UINT8)((instr_latch >> 8) & 0xff)); return (instr_latch >> 8) & 0xff; + case 0x08: logerror("ES5510: Read INSTR latch[0]: %02x\n", (UINT8)((instr_latch >> 0) & 0xff)); return (instr_latch >> 0) & 0xff; + + case 0x09: logerror("ES5510: Read DIL latch[2]: %02x\n", (dil_latch >> 16) & 0xff); return (dil_latch >> 16) & 0xff; + case 0x0a: logerror("ES5510: Read DIL latch[1]: %02x\n", (dil_latch >> 8) & 0xff); return (dil_latch >> 8) & 0xff; + case 0x0b: logerror("ES5510: Read DIL latch[0]: %02x\n", (dil_latch >> 0) & 0xff); return (dil_latch >> 0) & 0xff; //TODO: docs says that this always returns 0 + + case 0x0c: logerror("ES5510: Read DOL latch[2]: %02x\n", (dol_latch >> 16) & 0xff); return (dol_latch >> 16) & 0xff; + case 0x0d: logerror("ES5510: Read DOL latch[1]: %02x\n", (dol_latch >> 8) & 0xff); return (dol_latch >> 8) & 0xff; + case 0x0e: logerror("ES5510: Read DOL latch[0]: %02x\n", (dol_latch >> 0) & 0xff); return (dol_latch >> 0) & 0xff; //TODO: docs says that this always returns 0 + + case 0x0f: logerror("ES5510: Read DADR latch[2]: %02x\n", (dadr_latch >> 16) & 0xff); return (dadr_latch >> 16) & 0xff; + case 0x10: logerror("ES5510: Read DADR latch[1]: %02x\n", (dadr_latch >> 8) & 0xff); return (dadr_latch >> 8) & 0xff; + case 0x11: logerror("ES5510: Read DADR latch[0]: %02x\n", (dadr_latch >> 0) & 0xff); return (dadr_latch >> 0) & 0xff; + + case 0x12: logerror("ES5510: Reading Host Control\n"); return 0; // Host Control + + case 0x16: return 0x27; // Program Counter, for test purposes only + } + + // default: 0. + return 0x00; } WRITE8_MEMBER(es5510_device::host_w) { - static char buf[1024]; - switch (offset) { - case 0x00: - gpr_latch = (gpr_latch&0x00ffff) | ((data&0xff)<<16); - logerror("ES5510: Write GPR latch[2] = %02x -> %06x (%d)\n", data, gpr_latch, SX(gpr_latch)); - break; - case 0x01: - gpr_latch = (gpr_latch&0xff00ff) | ((data&0xff)<< 8); - logerror("ES5510: Write GPR latch[1] = %02x -> %06x (%d)\n", data, gpr_latch, SX(gpr_latch)); - break; - case 0x02: - gpr_latch = (gpr_latch&0xffff00) | ((data&0xff)<< 0); - logerror("ES5510: Write GPR latch[0] = %02x -> %06x (%d)\n", data, gpr_latch, SX(gpr_latch)); - break; - - /* 0x03 to 0x08 INSTR Register */ - case 0x03: instr_latch = ((instr_latch&U64(0x00ffffffffff)) | ((INT64)data&0xff)<<40); logerror("ES5510: Write INSTR latch[5] = %02x -> %012" I64FMT "x\n", data, instr_latch); break; - case 0x04: instr_latch = ((instr_latch&U64(0xff00ffffffff)) | ((INT64)data&0xff)<<32); logerror("ES5510: Write INSTR latch[4] = %02x -> %012" I64FMT "x\n", data, instr_latch); break; - case 0x05: instr_latch = ((instr_latch&U64(0xffff00ffffff)) | ((INT64)data&0xff)<<24); logerror("ES5510: Write INSTR latch[3] = %02x -> %012" I64FMT "x\n", data, instr_latch); break; - case 0x06: instr_latch = ((instr_latch&U64(0xffffff00ffff)) | ((INT64)data&0xff)<<16); logerror("ES5510: Write INSTR latch[2] = %02x -> %012" I64FMT "x\n", data, instr_latch); break; - case 0x07: instr_latch = ((instr_latch&U64(0xffffffff00ff)) | ((INT64)data&0xff)<< 8); logerror("ES5510: Write INSTR latch[1] = %02x -> %012" I64FMT "x\n", data, instr_latch); break; - case 0x08: instr_latch = ((instr_latch&U64(0xffffffffff00)) | ((INT64)data&0xff)<< 0); logerror("ES5510: Write INSTR latch[0] = %02x -> %012" I64FMT "x\n", data, instr_latch); break; - - /* 0x09 to 0x0b DIL Register (r/o) */ - - case 0x0c: dol_latch = (dol_latch&0x00ffff) | ((data&0xff)<<16); logerror("ES5510: Write DOL latch[2] = %02x -> %06x (%d)\n", data, dol_latch, SX(dol_latch)); break; - case 0x0d: dol_latch = (dol_latch&0xff00ff) | ((data&0xff)<< 8); logerror("ES5510: Write DOL latch[1] = %02x -> %06x (%d)\n", data, dol_latch, SX(dol_latch)); break; - case 0x0e: dol_latch = (dol_latch&0xffff00) | ((data&0xff)<< 0); logerror("ES5510: Write DOL latch[0] = %02x -> %06x (%d)\n", data, dol_latch, SX(dol_latch)); break; //TODO: docs says that this always returns 0xff - - case 0x0f: - dadr_latch = (dadr_latch&0x00ffff) | ((data&0xff)<<16); - if (ram_sel) - { - dil_latch = dram[dadr_latch]; - } - else - { - dram[dadr_latch] = dol_latch; - } - break; - - case 0x10: dadr_latch = (dadr_latch&0xff00ff) | ((data&0xff)<< 8); break; - case 0x11: dadr_latch = (dadr_latch&0xffff00) | ((data&0xff)<< 0); break; - - /* 0x12 Host Control */ - - case 0x14: ram_sel = data & 0x80; /* bit 6 is i/o select, everything else is undefined */break; - - /* 0x16 Program Counter (test purpose, r/o?) */ - /* 0x17 Internal Refresh counter (test purpose) */ - /* 0x18 Host Serial Control */ - case 0x18: - logerror("ES5510: Write Host Serial control %02x: %s, %s, ser3 %s, ser2 %s, ser1 %s, ser0 %s\n", data, - data&0x80 ? "Master" : "Slave", - data&0x40 ? "Sony" : "I2S", - data & 0x20 ? "Out" : "In", - data & 0x10 ? "Out" : "In", - data & 0x08 ? "Out" : "In", - data & 0x04 ? "Out" : "In"); - break; - - /* 0x1f Halt enable (w) / Frame Counter (r) */ - case 0x1F: - logerror("ES5510: Write Halt Enable %02x; HALT line is %d\n", data, input_state(ES5510_HALT)); - if (input_state(ES5510_HALT)) { - logerror("ES5510: Write to Halt Enable while HALT line is asserted: Halting!\n"); - state = STATE_HALTED; - } - break; - - case 0x80: /* Read select - GPR + INSTR */ - logerror("ES5510: Read INSTR+GPR %02x (%s): %012" I64FMT "x %06x (%d)\n", data, REGNAME(data & 0xff), instr[data] & U64(0xffffffffffff), gpr[data] & 0xffffff, gpr[data]); - - /* Check if an INSTR address is selected */ - if (data < 0xa0) { - instr_latch = instr[data]; - } - if (data < 0xc0) { - gpr_latch = gpr[data] & 0xffffff; - } else if (data >= 0xea) { - gpr_latch = read_reg(data); - } - break; - - case 0xa0: /* Write select - GPR */ - logerror("ES5510: Write GPR %02x (%s): %06x (%d)\n",data, REGNAME(data&0xff), gpr_latch, SX(gpr_latch)); - write_reg(data, gpr_latch); - break; - - case 0xc0: /* Write select - INSTR */ - DESCRIBE_INSTR(buf, instr_latch, gpr[data]); - logerror("ES5510: Write INSTR %02x %012" I64FMT "x: %s\n",data, instr_latch&U64(0xffffffffffff), buf); - if (data < 0xa0) { - instr[data] = instr_latch&U64(0xffffffffffff); - } - break; - - case 0xe0: /* Write select - GPR + INSTR */ - DESCRIBE_INSTR(buf, instr_latch, gpr_latch); - logerror("ES5510: Write INSTR+GPR %02x (%s): %012" I64FMT "x %06x (%d): %s\n",data, REGNAME(data&0xff), instr_latch, gpr_latch, SX(gpr_latch), buf); - if (data < 0xa0) { - instr[data] = instr_latch; - } - write_reg(data, gpr_latch); - break; - } + static char buf[1024]; + switch (offset) { + case 0x00: + gpr_latch = (gpr_latch&0x00ffff) | ((data&0xff)<<16); + logerror("ES5510: Write GPR latch[2] = %02x -> %06x (%d)\n", data, gpr_latch, SX(gpr_latch)); + break; + case 0x01: + gpr_latch = (gpr_latch&0xff00ff) | ((data&0xff)<< 8); + logerror("ES5510: Write GPR latch[1] = %02x -> %06x (%d)\n", data, gpr_latch, SX(gpr_latch)); + break; + case 0x02: + gpr_latch = (gpr_latch&0xffff00) | ((data&0xff)<< 0); + logerror("ES5510: Write GPR latch[0] = %02x -> %06x (%d)\n", data, gpr_latch, SX(gpr_latch)); + break; + + /* 0x03 to 0x08 INSTR Register */ + case 0x03: instr_latch = ((instr_latch&U64(0x00ffffffffff)) | ((INT64)data&0xff)<<40); logerror("ES5510: Write INSTR latch[5] = %02x -> %012" I64FMT "x\n", data, instr_latch); break; + case 0x04: instr_latch = ((instr_latch&U64(0xff00ffffffff)) | ((INT64)data&0xff)<<32); logerror("ES5510: Write INSTR latch[4] = %02x -> %012" I64FMT "x\n", data, instr_latch); break; + case 0x05: instr_latch = ((instr_latch&U64(0xffff00ffffff)) | ((INT64)data&0xff)<<24); logerror("ES5510: Write INSTR latch[3] = %02x -> %012" I64FMT "x\n", data, instr_latch); break; + case 0x06: instr_latch = ((instr_latch&U64(0xffffff00ffff)) | ((INT64)data&0xff)<<16); logerror("ES5510: Write INSTR latch[2] = %02x -> %012" I64FMT "x\n", data, instr_latch); break; + case 0x07: instr_latch = ((instr_latch&U64(0xffffffff00ff)) | ((INT64)data&0xff)<< 8); logerror("ES5510: Write INSTR latch[1] = %02x -> %012" I64FMT "x\n", data, instr_latch); break; + case 0x08: instr_latch = ((instr_latch&U64(0xffffffffff00)) | ((INT64)data&0xff)<< 0); logerror("ES5510: Write INSTR latch[0] = %02x -> %012" I64FMT "x\n", data, instr_latch); break; + + /* 0x09 to 0x0b DIL Register (r/o) */ + + case 0x0c: dol_latch = (dol_latch&0x00ffff) | ((data&0xff)<<16); logerror("ES5510: Write DOL latch[2] = %02x -> %06x (%d)\n", data, dol_latch, SX(dol_latch)); break; + case 0x0d: dol_latch = (dol_latch&0xff00ff) | ((data&0xff)<< 8); logerror("ES5510: Write DOL latch[1] = %02x -> %06x (%d)\n", data, dol_latch, SX(dol_latch)); break; + case 0x0e: dol_latch = (dol_latch&0xffff00) | ((data&0xff)<< 0); logerror("ES5510: Write DOL latch[0] = %02x -> %06x (%d)\n", data, dol_latch, SX(dol_latch)); break; //TODO: docs says that this always returns 0xff + + case 0x0f: + dadr_latch = (dadr_latch&0x00ffff) | ((data&0xff)<<16); + if (ram_sel) + { + dil_latch = dram[dadr_latch]; + } + else + { + dram[dadr_latch] = dol_latch; + } + break; + + case 0x10: dadr_latch = (dadr_latch&0xff00ff) | ((data&0xff)<< 8); break; + case 0x11: dadr_latch = (dadr_latch&0xffff00) | ((data&0xff)<< 0); break; + + /* 0x12 Host Control */ + + case 0x14: ram_sel = data & 0x80; /* bit 6 is i/o select, everything else is undefined */break; + + /* 0x16 Program Counter (test purpose, r/o?) */ + /* 0x17 Internal Refresh counter (test purpose) */ + /* 0x18 Host Serial Control */ + case 0x18: + logerror("ES5510: Write Host Serial control %02x: %s, %s, ser3 %s, ser2 %s, ser1 %s, ser0 %s\n", data, + data&0x80 ? "Master" : "Slave", + data&0x40 ? "Sony" : "I2S", + data & 0x20 ? "Out" : "In", + data & 0x10 ? "Out" : "In", + data & 0x08 ? "Out" : "In", + data & 0x04 ? "Out" : "In"); + break; + + /* 0x1f Halt enable (w) / Frame Counter (r) */ + case 0x1F: + logerror("ES5510: Write Halt Enable %02x; HALT line is %d\n", data, input_state(ES5510_HALT)); + if (input_state(ES5510_HALT)) { + logerror("ES5510: Write to Halt Enable while HALT line is asserted: Halting!\n"); + state = STATE_HALTED; + } + break; + + case 0x80: /* Read select - GPR + INSTR */ + logerror("ES5510: Read INSTR+GPR %02x (%s): %012" I64FMT "x %06x (%d)\n", data, REGNAME(data & 0xff), instr[data] & U64(0xffffffffffff), gpr[data] & 0xffffff, gpr[data]); + + /* Check if an INSTR address is selected */ + if (data < 0xa0) { + instr_latch = instr[data]; + } + if (data < 0xc0) { + gpr_latch = gpr[data] & 0xffffff; + } else if (data >= 0xea) { + gpr_latch = read_reg(data); + } + break; + + case 0xa0: /* Write select - GPR */ + logerror("ES5510: Write GPR %02x (%s): %06x (%d)\n",data, REGNAME(data&0xff), gpr_latch, SX(gpr_latch)); + write_reg(data, gpr_latch); + break; + + case 0xc0: /* Write select - INSTR */ + DESCRIBE_INSTR(buf, instr_latch, gpr[data]); + logerror("ES5510: Write INSTR %02x %012" I64FMT "x: %s\n",data, instr_latch&U64(0xffffffffffff), buf); + if (data < 0xa0) { + instr[data] = instr_latch&U64(0xffffffffffff); + } + break; + + case 0xe0: /* Write select - GPR + INSTR */ + DESCRIBE_INSTR(buf, instr_latch, gpr_latch); + logerror("ES5510: Write INSTR+GPR %02x (%s): %012" I64FMT "x %06x (%d): %s\n",data, REGNAME(data&0xff), instr_latch, gpr_latch, SX(gpr_latch), buf); + if (data < 0xa0) { + instr[data] = instr_latch; + } + write_reg(data, gpr_latch); + break; + } } void es5510_device::device_start() { - m_icountptr = &icount; - state_add(STATE_GENPC,"GENPC", pc).noshow(); + m_icountptr = &icount; + state_add(STATE_GENPC,"GENPC", pc).noshow(); } void es5510_device::device_reset() { - pc = 0x00; - memset(gpr, 0, sizeof(*gpr) * 0xc0); - memset(instr, 0, sizeof(*instr) * 0xa0); - memset(dram, 0, sizeof(*dram) * (1<<20)); - state = STATE_RUNNING; - dil_latch = dol_latch = dadr_latch = gpr_latch = 0; - instr_latch = UINT64(0); - ram_sel = 0; - host_control = 0; - memset(&ram, 0, sizeof(ram_t)); - memset(&ram_p, 0, sizeof(ram_t)); - memset(&ram_pp, 0, sizeof(ram_t)); + pc = 0x00; + memset(gpr, 0, sizeof(*gpr) * 0xc0); + memset(instr, 0, sizeof(*instr) * 0xa0); + memset(dram, 0, sizeof(*dram) * (1<<20)); + state = STATE_RUNNING; + dil_latch = dol_latch = dadr_latch = gpr_latch = 0; + instr_latch = UINT64(0); + ram_sel = 0; + host_control = 0; + memset(&ram, 0, sizeof(ram_t)); + memset(&ram_p, 0, sizeof(ram_t)); + memset(&ram_pp, 0, sizeof(ram_t)); } const address_space_config *es5510_device::memory_space_config(address_spacenum spacenum) const { - return 0; + return 0; } UINT64 es5510_device::execute_clocks_to_cycles(UINT64 clocks) const { - return clocks / 3; + return clocks / 3; } UINT64 es5510_device::execute_cycles_to_clocks(UINT64 cycles) const { - return cycles * 3; + return cycles * 3; } UINT32 es5510_device::execute_min_cycles() const { - return 1; + return 1; } UINT32 es5510_device::execute_max_cycles() const { - return 1; + return 1; } UINT32 es5510_device::execute_input_lines() const { - return 1; + return 1; } void es5510_device::execute_run() { - while (icount > 0) { - if (state == STATE_HALTED) { - // Currently halted, sample the HALT line - if (input_state(ES5510_HALT)) { + while (icount > 0) { + if (state == STATE_HALTED) { + // Currently halted, sample the HALT line + if (input_state(ES5510_HALT)) { // remain halted host_control |= 0x04; // Signal Host Access OK - } else { + } else { logerror("ES5501: Starting!\n"); state = STATE_RUNNING; - + UINT8 addr; char buf[1024]; for (addr = 0; addr < 0xa0; addr++) { - DESCRIBE_INSTR(buf, instr[addr], gpr[addr]); - logerror("%02x: %012" I64FMT "x %06x %s\n", addr, instr[addr], gpr[addr]&0xffffff, buf); + DESCRIBE_INSTR(buf, instr[addr], gpr[addr]); + logerror("%02x: %012" I64FMT "x %06x %s\n", addr, instr[addr], gpr[addr]&0xffffff, buf); } for (; addr < 0xc0; addr++) { - logerror("%02x: %06x (%d)\n", addr, gpr[addr]&0xffffff, gpr[addr]); + logerror("%02x: %06x (%d)\n", addr, gpr[addr]&0xffffff, gpr[addr]); } - } - } else { - // currently running, execute one instruction. + } + } else { + // currently running, execute one instruction. + + ram_pp = ram_p; + ram_p = ram; - ram_pp = ram_p; - ram_p = ram; - - // *** T0, clock high - // --- nothing to do! + // *** T0, clock high + // --- nothing to do! - // *** T0, clock low - // --- Read instruction N - UINT64 instr = this->instr[pc]; + // *** T0, clock low + // --- Read instruction N + UINT64 instr = this->instr[pc]; - // --- RAM cycle N-2 (if a Read cycle): data read from bus is stored in DIL - if (ram_pp.cycle != RAM_CYCLE_WRITE) { + // --- RAM cycle N-2 (if a Read cycle): data read from bus is stored in DIL + if (ram_pp.cycle != RAM_CYCLE_WRITE) { if (ram_pp.io) { // read from I/O and store into DIL - dil = 0; // read_io(ram_pp.address);; + dil = 0; // read_io(ram_pp.address);; } else { // read from DRAM and store into DIL - dil = dram[ram_pp.address]; + dil = dram[ram_pp.address]; } - } + } - // --- start of RAM cycle N - ram_control_t ramControl = RAM_CONTROL[((instr >> 3) & 0x07)]; - ram.cycle = ramControl.cycle; - ram.io = ramControl.access == RAM_CONTROL_IO; + // --- start of RAM cycle N + ram_control_t ramControl = RAM_CONTROL[((instr >> 3) & 0x07)]; + ram.cycle = ramControl.cycle; + ram.io = ramControl.access == RAM_CONTROL_IO; - // --- RAM cycle N: read offset N - INT32 offset = gpr[pc]; - switch(ramControl.access) { - case RAM_CONTROL_DELAY: + // --- RAM cycle N: read offset N + INT32 offset = gpr[pc]; + switch(ramControl.access) { + case RAM_CONTROL_DELAY: ram.address = (((dbase + offset) % (dlength + 1)) & memmask) >> memshift; break; - case RAM_CONTROL_TABLE_A: + case RAM_CONTROL_TABLE_A: ram.address = ((abase + offset) & memmask) >> memshift; break; - case RAM_CONTROL_TABLE_B: + case RAM_CONTROL_TABLE_B: ram.address = ((bbase + offset) & memmask) >> memshift; break; - case RAM_CONTROL_IO: + case RAM_CONTROL_IO: ram.address = offset & 0x00fffff0; // mask off the low 4 bits break; - } - - // *** T1, clock high - // --- Decode instruction N; - // we will do this both here and in stages as the different parts of the instruction complete & recommence. - - UINT8 operandSelect = (UINT8)((instr >> 8) & 0x0f); - const op_select_t &opSelect = OPERAND_SELECT[operandSelect]; - bool skip = false; - bool skippable = ((instr >> 7) & 0x01) != 0; // aka the 'SKIP' bit in the instruction word - if (skippable) { + } + + // *** T1, clock high + // --- Decode instruction N; + // we will do this both here and in stages as the different parts of the instruction complete & recommence. + + UINT8 operandSelect = (UINT8)((instr >> 8) & 0x0f); + const op_select_t &opSelect = OPERAND_SELECT[operandSelect]; + bool skip = false; + bool skippable = ((instr >> 7) & 0x01) != 0; // aka the 'SKIP' bit in the instruction word + if (skippable) { bool skipConditionSatisfied = (ccr & cmr & FLAG_MASK) != 0; if (isFlagSet(cmr, FLAG_NOT)) { - skipConditionSatisfied = !skipConditionSatisfied; + skipConditionSatisfied = !skipConditionSatisfied; } skip = skipConditionSatisfied; - } + } - // --- Write Multiplier result N-1 - if (mulacc.write_result) { + // --- Write Multiplier result N-1 + if (mulacc.write_result) { mulacc.product = (mulacc.cValue * mulacc.dValue) << mulshift; mulacc.result = (mulacc.accumulate ? machl : 0) + mulacc.product; INT32 tmp = (mulacc.result & U64(0x0000ffffff000000)) >> 24; if (mulacc.dst & SRC_DST_REG) { - machl = mulacc.result; - write_reg(mulacc.cReg, tmp); + machl = mulacc.result; + write_reg(mulacc.cReg, tmp); } if (mulacc.dst & SRC_DST_DELAY) { - write_to_dol(tmp); + write_to_dol(tmp); } - } - - // *** T1, clock low - // --- Start of multiplier cycle N - mulacc.cReg = (UINT8)((instr >> 32) & 0xff); - mulacc.dReg = (UINT8)((instr >> 40) & 0xff); - mulacc.src = opSelect.mac_src; - mulacc.dst = opSelect.mac_dst; - mulacc.accumulate = ((instr >> 6) & 0x01) != 0; - mulacc.write_result = skip; - - // --- Read Multiplier Operands N - if (mulacc.src == SRC_DST_REG) { + } + + // *** T1, clock low + // --- Start of multiplier cycle N + mulacc.cReg = (UINT8)((instr >> 32) & 0xff); + mulacc.dReg = (UINT8)((instr >> 40) & 0xff); + mulacc.src = opSelect.mac_src; + mulacc.dst = opSelect.mac_dst; + mulacc.accumulate = ((instr >> 6) & 0x01) != 0; + mulacc.write_result = skip; + + // --- Read Multiplier Operands N + if (mulacc.src == SRC_DST_REG) { mulacc.cValue = read_reg(mulacc.cReg); - } else { // must be SRC_DST_DELAY + } else { // must be SRC_DST_DELAY mulacc.cValue = dil; - } - mulacc.dValue = read_reg(mulacc.dReg); - - // *** T2, clock high - // --- Write ALU Result N-1 - if (alu.write_result) { + } + mulacc.dValue = read_reg(mulacc.dReg); + + // *** T2, clock high + // --- Write ALU Result N-1 + if (alu.write_result) { UINT8 flags = ccr; alu.result = alu_operation(alu.op, alu.aValue, alu.bValue, flags); if (alu.dst & SRC_DST_REG) { - write_reg(alu.aReg, alu.result); + write_reg(alu.aReg, alu.result); } if (alu.dst & SRC_DST_DELAY) { - write_to_dol(alu.result); + write_to_dol(alu.result); } if (alu.update_ccr) { - ccr = flags; - } - } - - // *** T2, clock low - // --- Start of ALU cycle N - alu.aReg = (instr >> 16) & 0xff; - alu.bReg = (instr >> 24) & 0xff; - alu.op = (instr >> 12) & 0x0f; - alu.src = opSelect.alu_src; - alu.dst = opSelect.alu_dst; - alu.write_result = skip; - alu.update_ccr = !skippable || (alu.op == OP_CMP); - - // --- Read ALU Operands N - alu_op_t aluOp = ALU_OPS[alu.op]; - if (aluOp.operands == 2) { + ccr = flags; + } + } + + // *** T2, clock low + // --- Start of ALU cycle N + alu.aReg = (instr >> 16) & 0xff; + alu.bReg = (instr >> 24) & 0xff; + alu.op = (instr >> 12) & 0x0f; + alu.src = opSelect.alu_src; + alu.dst = opSelect.alu_dst; + alu.write_result = skip; + alu.update_ccr = !skippable || (alu.op == OP_CMP); + + // --- Read ALU Operands N + alu_op_t aluOp = ALU_OPS[alu.op]; + if (aluOp.operands == 2) { if (alu.src == SRC_DST_REG) { - alu.aValue = read_reg(alu.aReg); + alu.aValue = read_reg(alu.aReg); } else { // must be SRC_DST_DELAY - alu.aValue = dil; + alu.aValue = dil; } - } - if (aluOp.operands >= 1) { + } + if (aluOp.operands >= 1) { alu.bValue = read_reg(alu.bReg); - } + } - // --- RAM cycle N-1 - if (ram_p.cycle != RAM_CYCLE_READ) { + // --- RAM cycle N-1 + if (ram_p.cycle != RAM_CYCLE_READ) { if (ram_p.cycle == RAM_CYCLE_WRITE) { - // If this is a write cycle, write the frontmost DOL value to RAM or I/O - if (ram_p.io) { - // write_io(ram_p.io, dol[0]); - } else { - dram[ram_p.address] = dol[0]; - } + // If this is a write cycle, write the frontmost DOL value to RAM or I/O + if (ram_p.io) { + // write_io(ram_p.io, dol[0]); + } else { + dram[ram_p.address] = dol[0]; + } } // If this is a Write or Dump cycle, eject the frontmost DL value. dol[0] = dol[1]; if (dol_count > 0) { - --dol_count; + --dol_count; } - } + } - ++pc; - } - --icount; - } + ++pc; + } + --icount; + } } UINT32 es5510_device::disasm_min_opcode_bytes() const { - return 6; + return 6; } UINT32 es5510_device::disasm_max_opcode_bytes() const { - return 6; + return 6; } offs_t es5510_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) { - return pc; + return pc; } INT32 es5510_device::read_reg(UINT8 reg) { - if (reg < 0xc0) { - return gpr[reg]; - } else { - switch(reg) - { - case 234: return ser0r; - case 235: return ser0l; - case 236: return ser1r; - case 237: return ser1l; - case 238: return ser2r; - case 239: return ser2l; - case 240: return ser3r; - case 241: return ser3l; - case 242: return (machl >> 0) & 0x00ffffff; - case 243: return (machl >> 24) & 0x00ffffff; - case 244: return dil; // DIL when reading - case 245: return dlength; - case 246: return abase; - case 247: return bbase; - case 248: return dbase; - case 249: return sigreg; - case 250: return ccr; - case 251: return cmr; - case 252: return 0x00ffffff; - case 253: return 0x00800000; - case 254: return 0x007fffff; - case 255: return 0x00000000; - default: - // unknown SPR - return 0; - } - } + if (reg < 0xc0) { + return gpr[reg]; + } else { + switch(reg) + { + case 234: return ser0r; + case 235: return ser0l; + case 236: return ser1r; + case 237: return ser1l; + case 238: return ser2r; + case 239: return ser2l; + case 240: return ser3r; + case 241: return ser3l; + case 242: return (machl >> 0) & 0x00ffffff; + case 243: return (machl >> 24) & 0x00ffffff; + case 244: return dil; // DIL when reading + case 245: return dlength; + case 246: return abase; + case 247: return bbase; + case 248: return dbase; + case 249: return sigreg; + case 250: return ccr; + case 251: return cmr; + case 252: return 0x00ffffff; + case 253: return 0x00800000; + case 254: return 0x007fffff; + case 255: return 0x00000000; + default: + // unknown SPR + return 0; + } + } } INT8 countLowOnes(INT32 x) { - INT8 n = 0; - while ((x & 1) == 1) { - ++n; - x >>= 1; - } - return n; + INT8 n = 0; + while ((x & 1) == 1) { + ++n; + x >>= 1; + } + return n; } void es5510_device::write_reg(UINT8 reg, INT32 value) { - value &= 0x00ffffff; - if (reg < 0xc0) { - gpr[reg] = value; - } else { - switch(reg) - { - case 234: ser0r = value; - case 235: ser0l = value; - case 236: ser1r = value; - case 237: ser1l = value; - case 238: ser2r = value; - case 239: ser2l = value; - case 240: ser3r = value; - case 241: ser3l = value; - case 242: machl = (machl & ~((INT64)0x00ffffff << 0)) | (value << 0); - case 243: machl = (machl & ~((INT64)0x00ffffff << 24)) | (value << 24); - case 244: - memshift = countLowOnes(value); - memsiz = 0x00ffffff >> (24 - memshift); - memmask = 0x00ffffff & ~memsiz; - memincrement = 1 << memshift; - case 245: dlength = value; - case 246: abase = value; - case 247: bbase = value; - case 248: dbase = value; - case 249: sigreg = (value != 0); - case 250: ccr = (value >> 16) & FLAG_MASK; - case 251: cmr = (value >> 16) & (FLAG_MASK | FLAG_NOT); - case 252: // no-op - case 253: // no-op - case 254: // no-op - case 255: // no-op - default: - // unknown register - ; - } - } + value &= 0x00ffffff; + if (reg < 0xc0) { + gpr[reg] = value; + } else { + switch(reg) + { + case 234: ser0r = value; + case 235: ser0l = value; + case 236: ser1r = value; + case 237: ser1l = value; + case 238: ser2r = value; + case 239: ser2l = value; + case 240: ser3r = value; + case 241: ser3l = value; + case 242: machl = (machl & ~((INT64)0x00ffffff << 0)) | (value << 0); + case 243: machl = (machl & ~((INT64)0x00ffffff << 24)) | (value << 24); + case 244: + memshift = countLowOnes(value); + memsiz = 0x00ffffff >> (24 - memshift); + memmask = 0x00ffffff & ~memsiz; + memincrement = 1 << memshift; + case 245: dlength = value; + case 246: abase = value; + case 247: bbase = value; + case 248: dbase = value; + case 249: sigreg = (value != 0); + case 250: ccr = (value >> 16) & FLAG_MASK; + case 251: cmr = (value >> 16) & (FLAG_MASK | FLAG_NOT); + case 252: // no-op + case 253: // no-op + case 254: // no-op + case 255: // no-op + default: + // unknown register + ; + } + } } void es5510_device::write_to_dol(INT32 value) { - if (dol_count >= 2) { - dol[0] = dol[1]; - dol[1] = value; - } else { - dol[dol_count++] = value; - } + if (dol_count >= 2) { + dol[0] = dol[1]; + dol[1] = value; + } else { + dol[dol_count++] = value; + } } INT32 es5510_device::alu_operation(UINT8 op, INT32 a, INT32 b, UINT8 &flags) { - switch(op) { - case 0x0: // ADD - return saturate(add(a, b, flags), flags); - - case 0x1: // SUB - return saturate(add(a, negate(b), flags), flags); - - case 0x2: // ADDU - return add(a, b, flags); - - case 0x3: // SUBU - return add(a, negate(b), flags); - - case 0x4: // CMP - add(a, negate(b), flags); - return a; - - case 0x5: // AND - a &= b; - setFlagTo(flags, FLAG_N, (a & 0x0080000000) != 0); - setFlagTo(flags, FLAG_Z, a == 0); - return a; - - case 0x6: // OR - a |= b; - setFlagTo(flags, FLAG_N, (a & 0x0080000000) != 0); - setFlagTo(flags, FLAG_Z, a == 0); - return a; - - case 0x7: // XOR - a ^= b; - setFlagTo(flags, FLAG_N, (a & 0x0080000000) != 0); - setFlagTo(flags, FLAG_Z, a == 0); - return a; - - case 0x8: // ABS - { - clearFlag(flags, FLAG_N); - bool isNegative = (a & 0x00800000) != 0; - setFlagTo(flags, FLAG_C, isNegative); - if (isNegative) { - a = (a ^ 0x00ffffff) + 1; - } - return a; - } - - case 0x9: // MOV - return b; - - case 0xA: // ASL2 - return asl(b, 2, flags); - - case 0xB: // ASL8 - return asl(b, 8, flags); - - case 0xC: // LS15 - return (b << 15) & 0x007fffff; - - case 0xD: // DIFF - return add(0x007fffff, negate(b), flags); - - case 0xE: // ASR - return (b >> 1) | (b & 0x00800000); - - case 0xF: // END - // sample the HALT line - if (input_state(ES5510_HALT)) { - // halt - state = STATE_HALTED; - host_control |= 0x04; // Signal Host Access OK - } - // update the delay line base pointer - dbase -= memincrement; - if (dbase < 0) { - dbase = dlength; - } - - default: - return 0; - } + switch(op) { + case 0x0: // ADD + return saturate(add(a, b, flags), flags); + + case 0x1: // SUB + return saturate(add(a, negate(b), flags), flags); + + case 0x2: // ADDU + return add(a, b, flags); + + case 0x3: // SUBU + return add(a, negate(b), flags); + + case 0x4: // CMP + add(a, negate(b), flags); + return a; + + case 0x5: // AND + a &= b; + setFlagTo(flags, FLAG_N, (a & 0x0080000000) != 0); + setFlagTo(flags, FLAG_Z, a == 0); + return a; + + case 0x6: // OR + a |= b; + setFlagTo(flags, FLAG_N, (a & 0x0080000000) != 0); + setFlagTo(flags, FLAG_Z, a == 0); + return a; + + case 0x7: // XOR + a ^= b; + setFlagTo(flags, FLAG_N, (a & 0x0080000000) != 0); + setFlagTo(flags, FLAG_Z, a == 0); + return a; + + case 0x8: // ABS + { + clearFlag(flags, FLAG_N); + bool isNegative = (a & 0x00800000) != 0; + setFlagTo(flags, FLAG_C, isNegative); + if (isNegative) { + a = (a ^ 0x00ffffff) + 1; + } + return a; + } + + case 0x9: // MOV + return b; + + case 0xA: // ASL2 + return asl(b, 2, flags); + + case 0xB: // ASL8 + return asl(b, 8, flags); + + case 0xC: // LS15 + return (b << 15) & 0x007fffff; + + case 0xD: // DIFF + return add(0x007fffff, negate(b), flags); + + case 0xE: // ASR + return (b >> 1) | (b & 0x00800000); + + case 0xF: // END + // sample the HALT line + if (input_state(ES5510_HALT)) { + // halt + state = STATE_HALTED; + host_control |= 0x04; // Signal Host Access OK + } + // update the delay line base pointer + dbase -= memincrement; + if (dbase < 0) { + dbase = dlength; + } + + default: + return 0; + } } diff --git a/src/emu/cpu/es5510/es5510.h b/src/emu/cpu/es5510/es5510.h index 0ebb2462357..cdc42b27a0c 100644 --- a/src/emu/cpu/es5510/es5510.h +++ b/src/emu/cpu/es5510/es5510.h @@ -13,163 +13,163 @@ #include "emu.h" class es5510_device : public cpu_device { - public: - es5510_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - - DECLARE_READ8_MEMBER(host_r); - DECLARE_WRITE8_MEMBER(host_w); - - DECLARE_READ16_MEMBER(ser_r); - DECLARE_WRITE16_MEMBER(ser_w); - - enum line_t { - ES5510_HALT = 0 - }; - - enum state_t { - STATE_RUNNING = 0, - STATE_HALTED = 1 - }; - - struct alu_op_t { - int operands; - const char * const opcode; - }; - - enum op_src_dst_t { - SRC_DST_REG = 1 << 0, - SRC_DST_DELAY = 1 << 1, - SRC_DST_BOTH = (1 << 0) | (1 << 1) - }; - - struct op_select_t { - const op_src_dst_t alu_src; - const op_src_dst_t alu_dst; - const op_src_dst_t mac_src; - const op_src_dst_t mac_dst; - }; - - enum ram_control_access_t { - RAM_CONTROL_DELAY = 0, - RAM_CONTROL_TABLE_A, - RAM_CONTROL_TABLE_B, - RAM_CONTROL_IO - }; - - enum ram_cycle_t { - RAM_CYCLE_READ = 0, - RAM_CYCLE_WRITE = 1, - RAM_CYCLE_DUMP_FIFO = 2 - }; - - struct ram_control_t { - ram_cycle_t cycle; - ram_control_access_t access; - const char * const description; - }; - - static const alu_op_t ALU_OPS[16]; - static const op_select_t OPERAND_SELECT[16]; - static const ram_control_t RAM_CONTROL[8]; - - struct alu_t { - UINT8 aReg; - UINT8 bReg; - op_src_dst_t src; - op_src_dst_t dst; - UINT8 op; - INT32 aValue; - INT32 bValue; - INT32 result; - bool update_ccr; - bool write_result; - }; - - struct mulacc_t { - UINT8 cReg; - UINT8 dReg; - op_src_dst_t src; - op_src_dst_t dst; - bool accumulate; - INT64 cValue; - INT64 dValue; - INT64 product; - INT64 result; - bool write_result; - }; - - struct ram_t { - INT32 address; // up to 20 bits, left-justified within the right 24 bits of the 32-bit word - bool io; // I/O space, rather than delay line memory - ram_cycle_t cycle; // cycle type - }; - - protected: - virtual void device_start(); - virtual void device_reset(); - virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const; - virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const; - virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const; - virtual UINT32 execute_min_cycles() const; - virtual UINT32 execute_max_cycles() const; - virtual UINT32 execute_input_lines() const; - virtual void execute_run(); - virtual UINT32 disasm_min_opcode_bytes() const; - virtual UINT32 disasm_max_opcode_bytes() const; - virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); - - INT32 read_reg(UINT8 reg); - void write_reg(UINT8 reg, INT32 value); - void write_to_dol(INT32 value); - - INT32 alu_operation(UINT8 op, INT32 aValue, INT32 bValue, UINT8 &flags); - - private: - int icount; - UINT8 pc; - state_t state; - INT32 gpr[0xc0]; // 24 bits, right justified and sign extended - INT32 ser0r; - INT32 ser0l; - INT32 ser1r; - INT32 ser1l; - INT32 ser2r; - INT32 ser2l; - INT32 ser3r; - INT32 ser3l; - INT64 machl; // 48 bits, right justified and sign extended - INT32 dil; - INT32 memsiz; - INT32 memmask; - INT32 memincrement; - INT8 memshift; - INT32 dlength; - INT32 abase; - INT32 bbase; - INT32 dbase; - INT32 sigreg; - int mulshift; - INT8 ccr; // really, 5 bits, left justified - INT8 cmr; // really, 6 bits, left justified - INT32 dol[2]; - int dol_count; - - UINT64 instr[160]; // 48 bits, right justified - UINT16 dram[1<<20]; // there are up to 20 address bits (at least 16 expected), left justified within the 24 bits of a gpr or dadr; we preallocate all of it. - - // latch registers for host interaction - INT32 dol_latch; // 24 bits - INT32 dil_latch; // 24 bits - UINT32 dadr_latch; // 24 bits - INT32 gpr_latch; // 24 bits, holding up to 20 address bits, left justified - UINT64 instr_latch; // 48 bits, right justified - UINT8 ram_sel; // effectively a boolean - UINT8 host_control; // - - // currently executing instruction(s) - alu_t alu; - mulacc_t mulacc; - ram_t ram, ram_p, ram_pp; // ram operations for cycles N, N-1 and N-2 + public: + es5510_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + + DECLARE_READ8_MEMBER(host_r); + DECLARE_WRITE8_MEMBER(host_w); + + DECLARE_READ16_MEMBER(ser_r); + DECLARE_WRITE16_MEMBER(ser_w); + + enum line_t { + ES5510_HALT = 0 + }; + + enum state_t { + STATE_RUNNING = 0, + STATE_HALTED = 1 + }; + + struct alu_op_t { + int operands; + const char * const opcode; + }; + + enum op_src_dst_t { + SRC_DST_REG = 1 << 0, + SRC_DST_DELAY = 1 << 1, + SRC_DST_BOTH = (1 << 0) | (1 << 1) + }; + + struct op_select_t { + const op_src_dst_t alu_src; + const op_src_dst_t alu_dst; + const op_src_dst_t mac_src; + const op_src_dst_t mac_dst; + }; + + enum ram_control_access_t { + RAM_CONTROL_DELAY = 0, + RAM_CONTROL_TABLE_A, + RAM_CONTROL_TABLE_B, + RAM_CONTROL_IO + }; + + enum ram_cycle_t { + RAM_CYCLE_READ = 0, + RAM_CYCLE_WRITE = 1, + RAM_CYCLE_DUMP_FIFO = 2 + }; + + struct ram_control_t { + ram_cycle_t cycle; + ram_control_access_t access; + const char * const description; + }; + + static const alu_op_t ALU_OPS[16]; + static const op_select_t OPERAND_SELECT[16]; + static const ram_control_t RAM_CONTROL[8]; + + struct alu_t { + UINT8 aReg; + UINT8 bReg; + op_src_dst_t src; + op_src_dst_t dst; + UINT8 op; + INT32 aValue; + INT32 bValue; + INT32 result; + bool update_ccr; + bool write_result; + }; + + struct mulacc_t { + UINT8 cReg; + UINT8 dReg; + op_src_dst_t src; + op_src_dst_t dst; + bool accumulate; + INT64 cValue; + INT64 dValue; + INT64 product; + INT64 result; + bool write_result; + }; + + struct ram_t { + INT32 address; // up to 20 bits, left-justified within the right 24 bits of the 32-bit word + bool io; // I/O space, rather than delay line memory + ram_cycle_t cycle; // cycle type + }; + + protected: + virtual void device_start(); + virtual void device_reset(); + virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const; + virtual UINT64 execute_clocks_to_cycles(UINT64 clocks) const; + virtual UINT64 execute_cycles_to_clocks(UINT64 cycles) const; + virtual UINT32 execute_min_cycles() const; + virtual UINT32 execute_max_cycles() const; + virtual UINT32 execute_input_lines() const; + virtual void execute_run(); + virtual UINT32 disasm_min_opcode_bytes() const; + virtual UINT32 disasm_max_opcode_bytes() const; + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); + + INT32 read_reg(UINT8 reg); + void write_reg(UINT8 reg, INT32 value); + void write_to_dol(INT32 value); + + INT32 alu_operation(UINT8 op, INT32 aValue, INT32 bValue, UINT8 &flags); + + private: + int icount; + UINT8 pc; + state_t state; + INT32 gpr[0xc0]; // 24 bits, right justified and sign extended + INT32 ser0r; + INT32 ser0l; + INT32 ser1r; + INT32 ser1l; + INT32 ser2r; + INT32 ser2l; + INT32 ser3r; + INT32 ser3l; + INT64 machl; // 48 bits, right justified and sign extended + INT32 dil; + INT32 memsiz; + INT32 memmask; + INT32 memincrement; + INT8 memshift; + INT32 dlength; + INT32 abase; + INT32 bbase; + INT32 dbase; + INT32 sigreg; + int mulshift; + INT8 ccr; // really, 5 bits, left justified + INT8 cmr; // really, 6 bits, left justified + INT32 dol[2]; + int dol_count; + + UINT64 instr[160]; // 48 bits, right justified + UINT16 dram[1<<20]; // there are up to 20 address bits (at least 16 expected), left justified within the 24 bits of a gpr or dadr; we preallocate all of it. + + // latch registers for host interaction + INT32 dol_latch; // 24 bits + INT32 dil_latch; // 24 bits + UINT32 dadr_latch; // 24 bits + INT32 gpr_latch; // 24 bits, holding up to 20 address bits, left justified + UINT64 instr_latch; // 48 bits, right justified + UINT8 ram_sel; // effectively a boolean + UINT8 host_control; // + + // currently executing instruction(s) + alu_t alu; + mulacc_t mulacc; + ram_t ram, ram_p, ram_pp; // ram operations for cycles N, N-1 and N-2 }; extern const device_type ES5510; diff --git a/src/emu/cpu/lr35902/lr35902.h b/src/emu/cpu/lr35902/lr35902.h index 8a9da5cdaa5..95e8f4a16a7 100644 --- a/src/emu/cpu/lr35902/lr35902.h +++ b/src/emu/cpu/lr35902/lr35902.h @@ -5,15 +5,12 @@ #define MCFG_LR35902_TIMER_CB(_devcb) \ - lr35902_cpu_device::set_timer_cb(*device, DEVCB2_##_devcb); \ - + lr35902_cpu_device::set_timer_cb(*device, DEVCB2_##_devcb); #define MCFG_LR35902_HALT_BUG \ - lr35902_cpu_device::set_halt_bug(*device); \ - + lr35902_cpu_device::set_halt_bug(*device); // This should be removed/improved once all gameboy boot roms have been dumped #define MCFG_LR35902_RESET_VALUES(_regs) \ - lr35902_cpu_device::set_reset_values(*device, _regs); \ - + lr35902_cpu_device::set_reset_values(*device, _regs); enum { diff --git a/src/emu/cpu/m6502/m6502.h b/src/emu/cpu/m6502/m6502.h index 9fe6c9180a9..97b662fe8ee 100644 --- a/src/emu/cpu/m6502/m6502.h +++ b/src/emu/cpu/m6502/m6502.h @@ -128,7 +128,7 @@ protected: DASM_imz, /* load immediate byte, store to zero page address (M740) */ DASM_spg, /* "special page": implied FF00 plus immediate value (M740)*/ DASM_biz, /* bit, zero page (M740) */ - DASM_bzr /* bit, zero page, relative offset (M740) */ + DASM_bzr /* bit, zero page, relative offset (M740) */ }; enum { diff --git a/src/emu/cpu/mips/r3000.c b/src/emu/cpu/mips/r3000.c index 9366100810b..f2583757106 100644 --- a/src/emu/cpu/mips/r3000.c +++ b/src/emu/cpu/mips/r3000.c @@ -75,36 +75,36 @@ HELPER MACROS ***************************************************************************/ -#define RSREG ((m_op >> 21) & 31) -#define RTREG ((m_op >> 16) & 31) -#define RDREG ((m_op >> 11) & 31) -#define SHIFT ((m_op >> 6) & 31) +#define RSREG ((m_op >> 21) & 31) +#define RTREG ((m_op >> 16) & 31) +#define RDREG ((m_op >> 11) & 31) +#define SHIFT ((m_op >> 6) & 31) -#define RSVAL m_r[RSREG] -#define RTVAL m_r[RTREG] -#define RDVAL m_r[RDREG] +#define RSVAL m_r[RSREG] +#define RTVAL m_r[RTREG] +#define RDVAL m_r[RDREG] -#define SIMMVAL ((INT16)m_op) -#define UIMMVAL ((UINT16)m_op) -#define LIMMVAL (m_op & 0x03ffffff) +#define SIMMVAL ((INT16)m_op) +#define UIMMVAL ((UINT16)m_op) +#define LIMMVAL (m_op & 0x03ffffff) -#define ADDPC(x) do { m_nextpc = m_pc + ((x) << 2); } while (0) -#define ADDPCL(x,l) do { m_nextpc = m_pc + ((x) << 2); m_r[l] = m_pc + 4; } while (0) -#define ABSPC(x) do { m_nextpc = (m_pc & 0xf0000000) | ((x) << 2); } while (0) -#define ABSPCL(x,l) do { m_nextpc = (m_pc & 0xf0000000) | ((x) << 2); m_r[l] = m_pc + 4; } while (0) -#define SETPC(x) do { m_nextpc = (x); } while (0) -#define SETPCL(x,l) do { m_nextpc = (x); m_r[l] = m_pc + 4; } while (0) +#define ADDPC(x) do { m_nextpc = m_pc + ((x) << 2); } while (0) +#define ADDPCL(x,l) do { m_nextpc = m_pc + ((x) << 2); m_r[l] = m_pc + 4; } while (0) +#define ABSPC(x) do { m_nextpc = (m_pc & 0xf0000000) | ((x) << 2); } while (0) +#define ABSPCL(x,l) do { m_nextpc = (m_pc & 0xf0000000) | ((x) << 2); m_r[l] = m_pc + 4; } while (0) +#define SETPC(x) do { m_nextpc = (x); } while (0) +#define SETPCL(x,l) do { m_nextpc = (x); m_r[l] = m_pc + 4; } while (0) -#define RBYTE(x) (this->*m_cur->m_read_byte)(x) -#define RWORD(x) (this->*m_cur->m_read_word)(x) -#define RLONG(x) (this->*m_cur->m_read_dword)(x) +#define RBYTE(x) (this->*m_cur->m_read_byte)(x) +#define RWORD(x) (this->*m_cur->m_read_word)(x) +#define RLONG(x) (this->*m_cur->m_read_dword)(x) -#define WBYTE(x,v) (this->*m_cur->m_write_byte)(x, v) -#define WWORD(x,v) (this->*m_cur->m_write_word)(x, v) -#define WLONG(x,v) (this->*m_cur->m_write_dword)(x, v) +#define WBYTE(x,v) (this->*m_cur->m_write_byte)(x, v) +#define WWORD(x,v) (this->*m_cur->m_write_word)(x, v) +#define WLONG(x,v) (this->*m_cur->m_write_dword)(x, v) -#define SR m_cpr[0][COP0_Status] -#define CAUSE m_cpr[0][COP0_Cause] +#define SR m_cpr[0][COP0_Status] +#define CAUSE m_cpr[0][COP0_Cause] //************************************************************************** @@ -227,7 +227,7 @@ void r3000_device::device_start() m_icache_size = 4096; m_dcache_size = 2048; break; - } + } case CHIP_TYPE_R3052: { m_icache_size = 8192; @@ -238,17 +238,17 @@ void r3000_device::device_start() // TODO: R3071 and R3081 have configurable cache sizes case CHIP_TYPE_R3071: { - m_icache_size = 16384; // or 8kB - m_dcache_size = 4096; // or 8kB + m_icache_size = 16384; // or 8kB + m_dcache_size = 4096; // or 8kB break; } case CHIP_TYPE_R3081: { - m_icache_size = 16384; // or 8kB - m_dcache_size = 4096; // or 8kB + m_icache_size = 16384; // or 8kB + m_dcache_size = 4096; // or 8kB m_hasfpu = true; break; - } + } } // allocate cache memory @@ -286,7 +286,7 @@ void r3000_device::device_start() m_lwr = &r3000_device::lwr_le; m_swl = &r3000_device::swl_le; m_swr = &r3000_device::swr_le; - + m_cache_hand.m_read_byte = &r3000_device::readcache_le; m_cache_hand.m_read_word = &r3000_device::readcache_le_word; m_cache_hand.m_read_dword = &r3000_device::readcache_le_dword; @@ -302,44 +302,44 @@ void r3000_device::device_start() m_in_brcond3.resolve_safe(0); // register our state for the debugger - state_add(STATE_GENPC, "GENPC", m_pc).noshow(); - state_add(STATE_GENPCBASE, "GENPCBASE", m_ppc).noshow(); - state_add(STATE_GENSP, "GENSP", m_r[31]).noshow(); - state_add(STATE_GENFLAGS, "GENFLAGS", SR).callimport().callexport().formatstr("%6s").noshow(); - state_add(R3000_PC, "PC", m_pc); - state_add(R3000_SR, "SR", SR); - state_add(R3000_R0, "R0", m_r[0]); - state_add(R3000_R1, "R1", m_r[1]); - state_add(R3000_R2, "R2", m_r[2]); - state_add(R3000_R3, "R3", m_r[3]); - state_add(R3000_R4, "R4", m_r[4]); - state_add(R3000_R5, "R5", m_r[5]); - state_add(R3000_R6, "R6", m_r[6]); - state_add(R3000_R7, "R7", m_r[7]); - state_add(R3000_R8, "R8", m_r[8]); - state_add(R3000_R9, "R9", m_r[9]); - state_add(R3000_R10, "R10", m_r[10]); - state_add(R3000_R11, "R11", m_r[11]); - state_add(R3000_R12, "R12", m_r[12]); - state_add(R3000_R13, "R13", m_r[13]); - state_add(R3000_R14, "R14", m_r[14]); - state_add(R3000_R15, "R15", m_r[15]); - state_add(R3000_R16, "R16", m_r[16]); - state_add(R3000_R17, "R17", m_r[17]); - state_add(R3000_R18, "R18", m_r[18]); - state_add(R3000_R19, "R19", m_r[19]); - state_add(R3000_R20, "R20", m_r[20]); - state_add(R3000_R21, "R21", m_r[21]); - state_add(R3000_R22, "R22", m_r[22]); - state_add(R3000_R23, "R23", m_r[23]); - state_add(R3000_R24, "R24", m_r[24]); - state_add(R3000_R25, "R25", m_r[25]); - state_add(R3000_R26, "R26", m_r[26]); - state_add(R3000_R27, "R27", m_r[27]); - state_add(R3000_R28, "R28", m_r[28]); - state_add(R3000_R29, "R29", m_r[29]); - state_add(R3000_R30, "R30", m_r[30]); - state_add(R3000_R31, "R31", m_r[31]); + state_add(STATE_GENPC, "GENPC", m_pc).noshow(); + state_add(STATE_GENPCBASE, "GENPCBASE", m_ppc).noshow(); + state_add(STATE_GENSP, "GENSP", m_r[31]).noshow(); + state_add(STATE_GENFLAGS, "GENFLAGS", SR).callimport().callexport().formatstr("%6s").noshow(); + state_add(R3000_PC, "PC", m_pc); + state_add(R3000_SR, "SR", SR); + state_add(R3000_R0, "R0", m_r[0]); + state_add(R3000_R1, "R1", m_r[1]); + state_add(R3000_R2, "R2", m_r[2]); + state_add(R3000_R3, "R3", m_r[3]); + state_add(R3000_R4, "R4", m_r[4]); + state_add(R3000_R5, "R5", m_r[5]); + state_add(R3000_R6, "R6", m_r[6]); + state_add(R3000_R7, "R7", m_r[7]); + state_add(R3000_R8, "R8", m_r[8]); + state_add(R3000_R9, "R9", m_r[9]); + state_add(R3000_R10, "R10", m_r[10]); + state_add(R3000_R11, "R11", m_r[11]); + state_add(R3000_R12, "R12", m_r[12]); + state_add(R3000_R13, "R13", m_r[13]); + state_add(R3000_R14, "R14", m_r[14]); + state_add(R3000_R15, "R15", m_r[15]); + state_add(R3000_R16, "R16", m_r[16]); + state_add(R3000_R17, "R17", m_r[17]); + state_add(R3000_R18, "R18", m_r[18]); + state_add(R3000_R19, "R19", m_r[19]); + state_add(R3000_R20, "R20", m_r[20]); + state_add(R3000_R21, "R21", m_r[21]); + state_add(R3000_R22, "R22", m_r[22]); + state_add(R3000_R23, "R23", m_r[23]); + state_add(R3000_R24, "R24", m_r[24]); + state_add(R3000_R25, "R25", m_r[25]); + state_add(R3000_R26, "R26", m_r[26]); + state_add(R3000_R27, "R27", m_r[27]); + state_add(R3000_R28, "R28", m_r[28]); + state_add(R3000_R29, "R29", m_r[29]); + state_add(R3000_R30, "R30", m_r[30]); + state_add(R3000_R31, "R31", m_r[31]); // register our state for saving save_item(NAME(m_pc)); @@ -358,7 +358,7 @@ void r3000_device::device_start() //------------------------------------------------- -// device_post_load - +// device_post_load - //------------------------------------------------- void r3000_device::device_post_load() { @@ -749,8 +749,8 @@ inline void r3000_device::handle_cop0() case 0x08: /* BC */ switch (RTREG) { - case 0x00: /* BCzF */ if (!m_in_brcond0()) ADDPC(SIMMVAL); break; - case 0x01: /* BCzT */ if (m_in_brcond0()) ADDPC(SIMMVAL); break; + case 0x00: /* BCzF */ if (!m_in_brcond0()) ADDPC(SIMMVAL); break; + case 0x01: /* BCzT */ if (m_in_brcond0()) ADDPC(SIMMVAL); break; case 0x02: /* BCzFL */ invalid_instruction(); break; case 0x03: /* BCzTL */ invalid_instruction(); break; default: invalid_instruction(); break; @@ -828,8 +828,8 @@ inline void r3000_device::handle_cop1() case 0x08: /* BC */ switch (RTREG) { - case 0x00: /* BCzF */ if (!m_in_brcond1()) ADDPC(SIMMVAL); break; - case 0x01: /* BCzT */ if (m_in_brcond1()) ADDPC(SIMMVAL); break; + case 0x00: /* BCzF */ if (!m_in_brcond1()) ADDPC(SIMMVAL); break; + case 0x01: /* BCzT */ if (m_in_brcond1()) ADDPC(SIMMVAL); break; case 0x02: /* BCzFL */ invalid_instruction(); break; case 0x03: /* BCzTL */ invalid_instruction(); break; default: invalid_instruction(); break; @@ -894,8 +894,8 @@ inline void r3000_device::handle_cop2() case 0x08: /* BC */ switch (RTREG) { - case 0x00: /* BCzF */ if (!m_in_brcond2()) ADDPC(SIMMVAL); break; - case 0x01: /* BCzT */ if (m_in_brcond2()) ADDPC(SIMMVAL); break; + case 0x00: /* BCzF */ if (!m_in_brcond2()) ADDPC(SIMMVAL); break; + case 0x01: /* BCzT */ if (m_in_brcond2()) ADDPC(SIMMVAL); break; case 0x02: /* BCzFL */ invalid_instruction(); break; case 0x03: /* BCzTL */ invalid_instruction(); break; default: invalid_instruction(); break; @@ -960,8 +960,8 @@ inline void r3000_device::handle_cop3() case 0x08: /* BC */ switch (RTREG) { - case 0x00: /* BCzF */ if (!m_in_brcond3()) ADDPC(SIMMVAL); break; - case 0x01: /* BCzT */ if (m_in_brcond3()) ADDPC(SIMMVAL); break; + case 0x00: /* BCzF */ if (!m_in_brcond3()) ADDPC(SIMMVAL); break; + case 0x01: /* BCzT */ if (m_in_brcond3()) ADDPC(SIMMVAL); break; case 0x02: /* BCzFL */ invalid_instruction(); break; case 0x03: /* BCzTL */ invalid_instruction(); break; default: invalid_instruction(); break; diff --git a/src/emu/cpu/mips/r3000.h b/src/emu/cpu/mips/r3000.h index 07711920f3b..edbc823d27c 100644 --- a/src/emu/cpu/mips/r3000.h +++ b/src/emu/cpu/mips/r3000.h @@ -13,7 +13,7 @@ /*************************************************************************** INTERFACE CONFIGURATION MACROS ***************************************************************************/ - + #define MCFG_R3000_ENDIANNESS(_endianness) \ r3000_device::static_set_endianness(*device, _endianness); @@ -134,12 +134,12 @@ protected: // memory accessors struct r3000_data_accessors { - UINT8 (r3000_device::*m_read_byte)(offs_t byteaddress); - UINT16 (r3000_device::*m_read_word)(offs_t byteaddress); - UINT32 (r3000_device::*m_read_dword)(offs_t byteaddress); - void (r3000_device::*m_write_byte)(offs_t byteaddress, UINT8 data); - void (r3000_device::*m_write_word)(offs_t byteaddress, UINT16 data); - void (r3000_device::*m_write_dword)(offs_t byteaddress, UINT32 data); + UINT8 (r3000_device::*m_read_byte)(offs_t byteaddress); + UINT16 (r3000_device::*m_read_word)(offs_t byteaddress); + UINT32 (r3000_device::*m_read_dword)(offs_t byteaddress); + void (r3000_device::*m_write_byte)(offs_t byteaddress, UINT8 data); + void (r3000_device::*m_write_word)(offs_t byteaddress, UINT16 data); + void (r3000_device::*m_write_dword)(offs_t byteaddress, UINT32 data); }; UINT32 readop(offs_t pc); @@ -213,13 +213,13 @@ protected: direct_read_data *m_direct; // configuration - chip_type m_chip_type; - bool m_hasfpu; - endianness_t m_endianness; + chip_type m_chip_type; + bool m_hasfpu; + endianness_t m_endianness; // core registers UINT32 m_pc; - UINT32 m_nextpc; + UINT32 m_nextpc; UINT32 m_hi; UINT32 m_lo; UINT32 m_r[32]; @@ -229,8 +229,8 @@ protected: UINT32 m_ccr[4][32]; // internal stuff - UINT32 m_ppc; - UINT32 m_op; + UINT32 m_ppc; + UINT32 m_op; int m_icount; int m_interrupt_cycles; @@ -254,10 +254,10 @@ protected: size_t m_dcache_size; // I/O - devcb2_read_line m_in_brcond0; - devcb2_read_line m_in_brcond1; - devcb2_read_line m_in_brcond2; - devcb2_read_line m_in_brcond3; + devcb2_read_line m_in_brcond0; + devcb2_read_line m_in_brcond1; + devcb2_read_line m_in_brcond2; + devcb2_read_line m_in_brcond3; }; diff --git a/src/emu/cpu/scudsp/scudspdasm.c b/src/emu/cpu/scudsp/scudspdasm.c index afb750cf5ed..a69d86f83e5 100644 --- a/src/emu/cpu/scudsp/scudspdasm.c +++ b/src/emu/cpu/scudsp/scudspdasm.c @@ -239,9 +239,9 @@ static UINT8 add_table(UINT32 cur_opcode) static UINT32 decode_opcode(UINT32 pc, const SCUDSP_OPCODE *op_table,UINT32 cur_opcode) { -// INT8 rel8; -// UINT32 imm32; -// UINT8 op2; +// INT8 rel8; +// UINT32 imm32; +// UINT8 op2; UINT32 flags = 0; //if (!strcmp(op_table->mnemonic, "jsr") || !strcmp(op_table->mnemonic, "bsr")) diff --git a/src/emu/cpu/sh2/sh2.c b/src/emu/cpu/sh2/sh2.c index 88156208635..23e0d2d05c5 100644 --- a/src/emu/cpu/sh2/sh2.c +++ b/src/emu/cpu/sh2/sh2.c @@ -1860,7 +1860,7 @@ INLINE void op0000(sh2_state *sh2, UINT16 opcode) case 0x06: MOVLS0(sh2, Rm, Rn); break; case 0x07: MULL(sh2, Rm, Rn); break; case 0x08: CLRT(sh2); break; - case 0x09: NOP(); break; + case 0x09: NOP(); break; case 0x0a: STSMACH(sh2, Rn); break; case 0x0b: RTS(sh2); break; case 0x0c: MOVBL0(sh2, Rm, Rn); break; diff --git a/src/emu/cpu/sh2/sh2comn.c b/src/emu/cpu/sh2/sh2comn.c index 0d6f798f79e..b692018df1c 100644 --- a/src/emu/cpu/sh2/sh2comn.c +++ b/src/emu/cpu/sh2/sh2comn.c @@ -32,7 +32,7 @@ INLINE UINT32 RL(sh2_state *sh2, offs_t A) if (A >= 0xc0000000) /* Cache Data Array */ return sh2->program->read_dword(A); - /* 0x60000000 Cache Address Data Array */ + /* 0x60000000 Cache Address Data Array */ if (A >= 0x40000000) /* Cache Associative Purge Area */ return 0xa5a5a5a5; @@ -56,7 +56,7 @@ INLINE void WL(sh2_state *sh2, offs_t A, UINT32 V) return; } - /* 0x60000000 Cache Address Data Array */ + /* 0x60000000 Cache Address Data Array */ if (A >= 0x40000000) /* Cache Associative Purge Area */ return; @@ -575,13 +575,13 @@ WRITE32_HANDLER( sh2_internal_w ) // Standby and cache case 0x24: // SBYCR, CCR /* - CCR - xx-- ---- ---- ---- Way 0/1 - ---x ---- ---- ---- Cache Purge (CP) - ---- x--- ---- ---- Two-Way Mode (TW) - ---- -x-- ---- ---- Data Replacement Disable (OD) - ---- --x- ---- ---- Instruction Replacement Disable (ID) - ---- ---x ---- ---- Cache Enable (CE) + CCR + xx-- ---- ---- ---- Way 0/1 + ---x ---- ---- ---- Cache Purge (CP) + ---- x--- ---- ---- Two-Way Mode (TW) + ---- -x-- ---- ---- Data Replacement Disable (OD) + ---- --x- ---- ---- Instruction Replacement Disable (ID) + ---- ---x ---- ---- Cache Enable (CE) */ break; diff --git a/src/emu/cpu/sh2/sh2drc.c b/src/emu/cpu/sh2/sh2drc.c index b56ced65b56..ecb0c98cc66 100644 --- a/src/emu/cpu/sh2/sh2drc.c +++ b/src/emu/cpu/sh2/sh2drc.c @@ -1807,7 +1807,7 @@ static int generate_group_0(sh2_state *sh2, drcuml_block *block, compiler_state { switch (opcode & 0x3F) { - case 0x00: // these are all illegal + case 0x00: // these are all illegal case 0x01: case 0x10: case 0x11: diff --git a/src/emu/cpu/sharc/sharcdsm.c b/src/emu/cpu/sharc/sharcdsm.c index cfd09a3314f..320bd56746a 100644 --- a/src/emu/cpu/sharc/sharcdsm.c +++ b/src/emu/cpu/sharc/sharcdsm.c @@ -493,7 +493,7 @@ static UINT32 dasm_compute_dreg_dmpm(UINT32 pc, UINT64 opcode) compute(comp); print(", "); } - if (dmd) + if (dmd) { print("DM(%s, %s) = R%d, ", GET_DAG1_I(dmi), GET_DAG1_M(dmm), dmdreg); } diff --git a/src/emu/cpu/sm8500/sm8500.c b/src/emu/cpu/sm8500/sm8500.c index 19d05724109..6bf07b7fb39 100644 --- a/src/emu/cpu/sm8500/sm8500.c +++ b/src/emu/cpu/sm8500/sm8500.c @@ -419,4 +419,3 @@ void sm8500_cpu_device::execute_set_input( int inptnum, int state ) m_program->write_byte(0x12, m_IR0); m_program->write_byte(0x13, m_IR1); } - diff --git a/src/emu/cpu/sm8500/sm8500.h b/src/emu/cpu/sm8500/sm8500.h index 104b94a60e6..9ac92d7fcdc 100644 --- a/src/emu/cpu/sm8500/sm8500.h +++ b/src/emu/cpu/sm8500/sm8500.h @@ -4,12 +4,10 @@ #define __SM8500_H__ #define MCFG_SM8500_DMA_CB(_devcb) \ - sm8500_cpu_device::set_dma_cb(*device, DEVCB2_##_devcb); \ - + sm8500_cpu_device::set_dma_cb(*device, DEVCB2_##_devcb); #define MCFG_SM8500_TIMER_CB(_devcb) \ - sm8500_cpu_device::set_timer_cb(*device, DEVCB2_##_devcb); \ - + sm8500_cpu_device::set_timer_cb(*device, DEVCB2_##_devcb); enum { diff --git a/src/emu/debug/debugvw.c b/src/emu/debug/debugvw.c index 7cf655d908f..307d9575fe8 100644 --- a/src/emu/debug/debugvw.c +++ b/src/emu/debug/debugvw.c @@ -61,9 +61,9 @@ debug_view_source::debug_view_source(const char *name, device_t *device) : m_next(NULL), - m_name(name), - m_device(device), - m_is_octal(false) + m_name(name), + m_device(device), + m_is_octal(false) { device_execute_interface *intf; if (device && device->interface(intf)) @@ -92,9 +92,9 @@ debug_view_source::~debug_view_source() debug_view_source_list::debug_view_source_list(running_machine &machine) : m_machine(machine), - m_head(NULL), - m_tail(NULL), - m_count(0) + m_head(NULL), + m_tail(NULL), + m_count(0) { } @@ -206,24 +206,24 @@ const debug_view_source *debug_view_source_list::match_device(device_t *device) debug_view::debug_view(running_machine &machine, debug_view_type type, debug_view_osd_update_func osdupdate, void *osdprivate) : m_next(NULL), - m_type(type), - m_source(NULL), - m_source_list(machine), - m_osdupdate(osdupdate), - m_osdprivate(osdprivate), - m_visible(10,10), - m_total(10,10), - m_topleft(0,0), - m_cursor(0,0), - m_supports_cursor(false), - m_cursor_visible(false), - m_recompute(true), - m_update_level(0), - m_update_pending(true), - m_osd_update_pending(true), - m_viewdata(NULL), - m_viewdata_size(0), - m_machine(machine) + m_type(type), + m_source(NULL), + m_source_list(machine), + m_osdupdate(osdupdate), + m_osdprivate(osdprivate), + m_visible(10,10), + m_total(10,10), + m_topleft(0,0), + m_cursor(0,0), + m_supports_cursor(false), + m_cursor_visible(false), + m_recompute(true), + m_update_level(0), + m_update_pending(true), + m_osd_update_pending(true), + m_viewdata(NULL), + m_viewdata_size(0), + m_machine(machine) { // allocate memory for the buffer m_viewdata_size = m_visible.y * m_visible.x; @@ -451,7 +451,7 @@ void debug_view::view_click(const int button, const debug_view_xy& pos) debug_view_manager::debug_view_manager(running_machine &machine) : m_machine(machine), - m_viewlist(NULL) + m_viewlist(NULL) { } @@ -573,10 +573,10 @@ debug_view *debug_view_manager::append(debug_view *view) debug_view_expression::debug_view_expression(running_machine &machine) : m_machine(machine), - m_dirty(true), - m_result(0), - m_parsed(debug_cpu_get_global_symtable(machine)), - m_string("0") + m_dirty(true), + m_result(0), + m_parsed(debug_cpu_get_global_symtable(machine)), + m_string("0") { } diff --git a/src/emu/debug/debugvw.h b/src/emu/debug/debugvw.h index aba8094aebe..e5f4df80966 100644 --- a/src/emu/debug/debugvw.h +++ b/src/emu/debug/debugvw.h @@ -72,35 +72,35 @@ enum debug_view_notification // attribute bits for debug_view_char.attrib -const UINT8 DCA_NORMAL = 0x00; // in Windows: black on white -const UINT8 DCA_CHANGED = 0x01; // in Windows: red foreground -const UINT8 DCA_SELECTED = 0x02; // in Windows: light red background -const UINT8 DCA_INVALID = 0x04; // in Windows: dark blue foreground -const UINT8 DCA_DISABLED = 0x08; // in Windows: darker foreground -const UINT8 DCA_ANCILLARY = 0x10; // in Windows: grey background -const UINT8 DCA_CURRENT = 0x20; // in Windows: yellow background -const UINT8 DCA_COMMENT = 0x40; // in Windows: green foreground +const UINT8 DCA_NORMAL = 0x00; // in Windows: black on white +const UINT8 DCA_CHANGED = 0x01; // in Windows: red foreground +const UINT8 DCA_SELECTED = 0x02; // in Windows: light red background +const UINT8 DCA_INVALID = 0x04; // in Windows: dark blue foreground +const UINT8 DCA_DISABLED = 0x08; // in Windows: darker foreground +const UINT8 DCA_ANCILLARY = 0x10; // in Windows: grey background +const UINT8 DCA_CURRENT = 0x20; // in Windows: yellow background +const UINT8 DCA_COMMENT = 0x40; // in Windows: green foreground // special characters that can be passed to process_char() -const int DCH_UP = 1; // up arrow -const int DCH_DOWN = 2; // down arrow -const int DCH_LEFT = 3; // left arrow -const int DCH_RIGHT = 4; // right arrow -const int DCH_PUP = 5; // page up -const int DCH_PDOWN = 6; // page down -const int DCH_HOME = 7; // home -const int DCH_CTRLHOME = 8; // ctrl+home -const int DCH_END = 9; // end -const int DCH_CTRLEND = 10; // ctrl+end -const int DCH_CTRLRIGHT = 11; // ctrl+right -const int DCH_CTRLLEFT = 12; // ctrl+left +const int DCH_UP = 1; // up arrow +const int DCH_DOWN = 2; // down arrow +const int DCH_LEFT = 3; // left arrow +const int DCH_RIGHT = 4; // right arrow +const int DCH_PUP = 5; // page up +const int DCH_PDOWN = 6; // page down +const int DCH_HOME = 7; // home +const int DCH_CTRLHOME = 8; // ctrl+home +const int DCH_END = 9; // end +const int DCH_CTRLEND = 10; // ctrl+end +const int DCH_CTRLRIGHT = 11; // ctrl+right +const int DCH_CTRLLEFT = 12; // ctrl+left // special characters that can be passed to process_click() -const int DCK_LEFT_CLICK = 1; // left instantaneous click -const int DCK_RIGHT_CLICK = 2; // right instantaneous click -const int DCK_MIDDLE_CLICK = 3; // middle instantaneous click +const int DCK_LEFT_CLICK = 1; // left instantaneous click +const int DCK_RIGHT_CLICK = 2; // right instantaneous click +const int DCK_MIDDLE_CLICK = 3; // middle instantaneous click //************************************************************************** @@ -118,8 +118,8 @@ typedef void (*debug_view_osd_update_func)(debug_view &view, void *osdprivate); // a single "character" in the debug view has an ASCII value and an attribute byte struct debug_view_char { - UINT8 byte; - UINT8 attrib; + UINT8 byte; + UINT8 attrib; }; @@ -129,8 +129,8 @@ class debug_view_xy public: debug_view_xy(int _x = 0, int _y = 0) : x(_x), y(_y) { } - INT32 x; - INT32 y; + INT32 x; + INT32 y; }; @@ -154,10 +154,10 @@ public: private: // internal state - debug_view_source * m_next; // link to next item - astring m_name; // name of the source item - device_t * m_device; // associated device (if applicable) - bool m_is_octal; // is view in octal or hex + debug_view_source * m_next; // link to next item + astring m_name; // name of the source item + device_t * m_device; // associated device (if applicable) + bool m_is_octal; // is view in octal or hex }; @@ -186,10 +186,10 @@ public: private: // internal state - running_machine & m_machine; // reference to our machine - debug_view_source * m_head; // head of the list - debug_view_source * m_tail; // end of the tail - UINT32 m_count; // number of items in the list + running_machine & m_machine; // reference to our machine + debug_view_source * m_head; // head of the list + debug_view_source * m_tail; // end of the tail + UINT32 m_count; // number of items in the list }; @@ -248,33 +248,33 @@ protected: protected: // core view data - debug_view * m_next; // link to the next view - debug_view_type m_type; // type of view - const debug_view_source *m_source; // currently selected data source - debug_view_source_list m_source_list; // list of available data sources + debug_view * m_next; // link to the next view + debug_view_type m_type; // type of view + const debug_view_source *m_source; // currently selected data source + debug_view_source_list m_source_list; // list of available data sources // OSD data - debug_view_osd_update_func m_osdupdate; // callback for the update - void * m_osdprivate; // OSD-managed private data + debug_view_osd_update_func m_osdupdate; // callback for the update + void * m_osdprivate; // OSD-managed private data // visibility info - debug_view_xy m_visible; // visible size (in rows and columns) - debug_view_xy m_total; // total size (in rows and columns) - debug_view_xy m_topleft; // top-left visible position (in rows and columns) - debug_view_xy m_cursor; // cursor position - bool m_supports_cursor; // does this view support a cursor? - bool m_cursor_visible; // is the cursor visible? + debug_view_xy m_visible; // visible size (in rows and columns) + debug_view_xy m_total; // total size (in rows and columns) + debug_view_xy m_topleft; // top-left visible position (in rows and columns) + debug_view_xy m_cursor; // cursor position + bool m_supports_cursor; // does this view support a cursor? + bool m_cursor_visible; // is the cursor visible? // update info - bool m_recompute; // does this view require a recomputation? - UINT8 m_update_level; // update level; updates when this hits 0 - bool m_update_pending; // true if there is a pending update - bool m_osd_update_pending; // true if there is a pending update - debug_view_char * m_viewdata; // current array of view data - int m_viewdata_size; // number of elements of the viewdata array + bool m_recompute; // does this view require a recomputation? + UINT8 m_update_level; // update level; updates when this hits 0 + bool m_update_pending; // true if there is a pending update + bool m_osd_update_pending; // true if there is a pending update + debug_view_char * m_viewdata; // current array of view data + int m_viewdata_size; // number of elements of the viewdata array private: - running_machine & m_machine; // machine associated with this view + running_machine & m_machine; // machine associated with this view }; @@ -302,8 +302,8 @@ private: debug_view *append(debug_view *view); // internal state - running_machine & m_machine; // reference to our machine - debug_view * m_viewlist; // list of views + running_machine & m_machine; // reference to our machine + debug_view * m_viewlist; // list of views }; @@ -333,11 +333,11 @@ private: bool recompute(); // internal state - running_machine & m_machine; // reference to the machine - bool m_dirty; // true if the expression needs to be re-evaluated - UINT64 m_result; // last result from the expression - parsed_expression m_parsed; // parsed expression data - astring m_string; // copy of the expression string + running_machine & m_machine; // reference to the machine + bool m_dirty; // true if the expression needs to be re-evaluated + UINT64 m_result; // last result from the expression + parsed_expression m_parsed; // parsed expression data + astring m_string; // copy of the expression string }; diff --git a/src/emu/debug/dvdisasm.c b/src/emu/debug/dvdisasm.c index 53ecf9c5dd0..ba3955030f3 100644 --- a/src/emu/debug/dvdisasm.c +++ b/src/emu/debug/dvdisasm.c @@ -54,9 +54,9 @@ debug_view_disasm_source::debug_view_disasm_source(const char *name, device_t &device) : debug_view_source(name, &device), - m_device(device), - m_disasmintf(dynamic_cast<device_disasm_interface *>(&device)), - m_space(device.memory().space(AS_PROGRAM)) + m_device(device), + m_disasmintf(dynamic_cast<device_disasm_interface *>(&device)), + m_space(device.memory().space(AS_PROGRAM)) { } @@ -72,20 +72,20 @@ debug_view_disasm_source::debug_view_disasm_source(const char *name, device_t &d debug_view_disasm::debug_view_disasm(running_machine &machine, debug_view_osd_update_func osdupdate, void *osdprivate) : debug_view(machine, DVT_DISASSEMBLY, osdupdate, osdprivate), - m_right_column(DASM_RIGHTCOL_RAW), - m_backwards_steps(3), - m_dasm_width(DEFAULT_DASM_WIDTH), - m_last_direct_raw(NULL), - m_last_direct_decrypted(NULL), - m_last_change_count(0), - m_last_pcbyte(0), - m_divider1(0), - m_divider2(0), - m_divider3(0), - m_expression(machine), - m_allocated(0,0), - m_byteaddress(NULL), - m_dasm(NULL) + m_right_column(DASM_RIGHTCOL_RAW), + m_backwards_steps(3), + m_dasm_width(DEFAULT_DASM_WIDTH), + m_last_direct_raw(NULL), + m_last_direct_decrypted(NULL), + m_last_change_count(0), + m_last_pcbyte(0), + m_divider1(0), + m_divider2(0), + m_divider3(0), + m_expression(machine), + m_allocated(0,0), + m_byteaddress(NULL), + m_dasm(NULL) { // fail if no available sources enumerate_sources(); @@ -199,7 +199,7 @@ void debug_view_disasm::view_char(int chval) m_cursor.y = temp; break; - case DCH_HOME: // set the active column to the PC + case DCH_HOME: // set the active column to the PC { const debug_view_disasm_source &source = downcast<const debug_view_disasm_source &>(*m_source); offs_t pc = source.m_space.address_to_byte(source.m_device.safe_pc()) & source.m_space.logbytemask(); @@ -393,7 +393,7 @@ bool debug_view_disasm::recompute(offs_t pc, int startline, int lines) m_total.x = m_divider2 + 1 + char_num * maxbytes_clamped + (maxbytes_clamped / minbytes - 1) + 1; } else if (m_right_column == DASM_RIGHTCOL_COMMENTS) - m_total.x = m_divider2 + 1 + 50; // DEBUG_COMMENT_MAX_LINE_LENGTH + m_total.x = m_divider2 + 1 + 50; // DEBUG_COMMENT_MAX_LINE_LENGTH else m_total.x = m_divider2 + 1; diff --git a/src/emu/debug/dvdisasm.h b/src/emu/debug/dvdisasm.h index 64d25295d2d..1bfdbaf5ad7 100644 --- a/src/emu/debug/dvdisasm.h +++ b/src/emu/debug/dvdisasm.h @@ -77,9 +77,9 @@ public: private: // internal state - device_t & m_device; // underlying device - device_disasm_interface *m_disasmintf; // disassembly interface - address_space & m_space; // address space to display + device_t & m_device; // underlying device + device_disasm_interface *m_disasmintf; // disassembly interface + address_space & m_space; // address space to display }; @@ -123,19 +123,19 @@ private: bool recompute(offs_t pc, int startline, int lines); // internal state - disasm_right_column m_right_column; // right column contents - UINT32 m_backwards_steps; // number of backwards steps - UINT32 m_dasm_width; // width of the disassembly area - UINT8 * m_last_direct_raw; // last direct raw value - UINT8 * m_last_direct_decrypted;// last direct decrypted value - UINT32 m_last_change_count; // last comment change count - offs_t m_last_pcbyte; // last PC byte value - int m_divider1, m_divider2; // left and right divider columns - int m_divider3; // comment divider column - debug_view_expression m_expression; // expression-related information - debug_view_xy m_allocated; // allocated rows/columns - offs_t * m_byteaddress; // addresses of the instructions - char * m_dasm; // disassembled instructions + disasm_right_column m_right_column; // right column contents + UINT32 m_backwards_steps; // number of backwards steps + UINT32 m_dasm_width; // width of the disassembly area + UINT8 * m_last_direct_raw; // last direct raw value + UINT8 * m_last_direct_decrypted;// last direct decrypted value + UINT32 m_last_change_count; // last comment change count + offs_t m_last_pcbyte; // last PC byte value + int m_divider1, m_divider2; // left and right divider columns + int m_divider3; // comment divider column + debug_view_expression m_expression; // expression-related information + debug_view_xy m_allocated; // allocated rows/columns + offs_t * m_byteaddress; // addresses of the instructions + char * m_dasm; // disassembled instructions // constants static const int DEFAULT_DASM_LINES = 1000; diff --git a/src/emu/debug/dvmemory.c b/src/emu/debug/dvmemory.c index c0a6b045bd4..7782bb6c073 100644 --- a/src/emu/debug/dvmemory.c +++ b/src/emu/debug/dvmemory.c @@ -74,37 +74,37 @@ const debug_view_memory::memory_view_pos debug_view_memory::s_memory_pos_table[9 debug_view_memory_source::debug_view_memory_source(const char *name, address_space &space) : debug_view_source(name, &space.device()), - m_space(&space), - m_memintf(dynamic_cast<device_memory_interface *>(&space.device())), - m_base(NULL), - m_length(0), - m_offsetxor(0), - m_endianness(space.endianness()), - m_prefsize(space.data_width() / 8) + m_space(&space), + m_memintf(dynamic_cast<device_memory_interface *>(&space.device())), + m_base(NULL), + m_length(0), + m_offsetxor(0), + m_endianness(space.endianness()), + m_prefsize(space.data_width() / 8) { } debug_view_memory_source::debug_view_memory_source(const char *name, memory_region ®ion) : debug_view_source(name), - m_space(NULL), - m_memintf(NULL), - m_base(region), - m_length(region.bytes()), - m_offsetxor(NATIVE_ENDIAN_VALUE_LE_BE(region.width() - 1, 0)), - m_endianness(region.endianness()), - m_prefsize(MIN(region.width(), 8)) + m_space(NULL), + m_memintf(NULL), + m_base(region), + m_length(region.bytes()), + m_offsetxor(NATIVE_ENDIAN_VALUE_LE_BE(region.width() - 1, 0)), + m_endianness(region.endianness()), + m_prefsize(MIN(region.width(), 8)) { } debug_view_memory_source::debug_view_memory_source(const char *name, void *base, int element_size, int num_elements) : debug_view_source(name), - m_space(NULL), - m_memintf(NULL), - m_base(base), - m_length(element_size * num_elements), - m_offsetxor(0), - m_endianness(ENDIANNESS_NATIVE), - m_prefsize(MIN(element_size, 8)) + m_space(NULL), + m_memintf(NULL), + m_base(base), + m_length(element_size * num_elements), + m_offsetxor(0), + m_endianness(ENDIANNESS_NATIVE), + m_prefsize(MIN(element_size, 8)) { } @@ -120,15 +120,15 @@ debug_view_memory_source::debug_view_memory_source(const char *name, void *base, debug_view_memory::debug_view_memory(running_machine &machine, debug_view_osd_update_func osdupdate, void *osdprivate) : debug_view(machine, DVT_MEMORY, osdupdate, osdprivate), - m_expression(machine), - m_chunks_per_row(16), - m_bytes_per_chunk(1), - m_reverse_view(false), - m_ascii_view(true), - m_no_translation(false), - m_maxaddr(0), - m_bytes_per_row(16), - m_byte_offset(0) + m_expression(machine), + m_chunks_per_row(16), + m_bytes_per_chunk(1), + m_reverse_view(false), + m_ascii_view(true), + m_no_translation(false), + m_maxaddr(0), + m_bytes_per_row(16), + m_byte_offset(0) { // fail if no available sources enumerate_sources(); @@ -181,10 +181,10 @@ void debug_view_memory::enumerate_sources() break; // add pretty much anything that's not a timer (we may wish to cull other items later) - // also, don't trim the front of the name, it's important to know which VIA6522 we're looking at, e.g. - if (strncmp(itemname, "timer/", 6)) + // also, don't trim the front of the name, it's important to know which VIA6522 we're looking at, e.g. + if (strncmp(itemname, "timer/", 6)) { - name.cpy(itemname); + name.cpy(itemname); m_source_list.append(*auto_alloc(machine(), debug_view_memory_source(name, base, valsize, valcount))); } } @@ -653,10 +653,10 @@ bool debug_view_memory::read(UINT8 size, offs_t offs, UINT64 &data) { switch (size) { - case 1: data = debug_read_byte(*source.m_space, offs, !m_no_translation); break; - case 2: data = debug_read_word(*source.m_space, offs, !m_no_translation); break; - case 4: data = debug_read_dword(*source.m_space, offs, !m_no_translation); break; - case 8: data = debug_read_qword(*source.m_space, offs, !m_no_translation); break; + case 1: data = debug_read_byte(*source.m_space, offs, !m_no_translation); break; + case 2: data = debug_read_word(*source.m_space, offs, !m_no_translation); break; + case 4: data = debug_read_dword(*source.m_space, offs, !m_no_translation); break; + case 8: data = debug_read_qword(*source.m_space, offs, !m_no_translation); break; } } return ismapped; @@ -700,10 +700,10 @@ void debug_view_memory::write(UINT8 size, offs_t offs, UINT64 data) { switch (size) { - case 1: debug_write_byte(*source.m_space, offs, data, !m_no_translation); break; - case 2: debug_write_word(*source.m_space, offs, data, !m_no_translation); break; - case 4: debug_write_dword(*source.m_space, offs, data, !m_no_translation); break; - case 8: debug_write_qword(*source.m_space, offs, data, !m_no_translation); break; + case 1: debug_write_byte(*source.m_space, offs, data, !m_no_translation); break; + case 2: debug_write_word(*source.m_space, offs, data, !m_no_translation); break; + case 4: debug_write_dword(*source.m_space, offs, data, !m_no_translation); break; + case 8: debug_write_qword(*source.m_space, offs, data, !m_no_translation); break; } return; } diff --git a/src/emu/debug/dvmemory.h b/src/emu/debug/dvmemory.h index b370fdb51a9..06a9bcb9f16 100644 --- a/src/emu/debug/dvmemory.h +++ b/src/emu/debug/dvmemory.h @@ -60,13 +60,13 @@ public: address_space *space() const { return m_space; } private: - address_space *m_space; // address space we reference (if any) - device_memory_interface *m_memintf; // pointer to the memory interface of the device - void * m_base; // pointer to memory base - offs_t m_length; // length of memory - offs_t m_offsetxor; // XOR to apply to offsets - endianness_t m_endianness; // endianness of memory - UINT8 m_prefsize; // preferred bytes per chunk + address_space *m_space; // address space we reference (if any) + device_memory_interface *m_memintf; // pointer to the memory interface of the device + void * m_base; // pointer to memory base + offs_t m_length; // length of memory + offs_t m_offsetxor; // XOR to apply to offsets + endianness_t m_endianness; // endianness of memory + UINT8 m_prefsize; // preferred bytes per chunk }; @@ -127,31 +127,31 @@ private: void write(UINT8 size, offs_t offs, UINT64 data); // internal state - debug_view_expression m_expression; // expression describing the start address - UINT32 m_chunks_per_row; // number of chunks displayed per line - UINT8 m_bytes_per_chunk; // bytes per chunk - bool m_reverse_view; // reverse-endian view? - bool m_ascii_view; // display ASCII characters? - bool m_no_translation; // don't run addresses through the cpu translation hook - offs_t m_maxaddr; // (derived) maximum address to display - UINT32 m_bytes_per_row; // (derived) number of bytes displayed per line - UINT32 m_byte_offset; // (derived) offset of starting visible byte - astring m_addrformat; // (derived) format string to use to print addresses + debug_view_expression m_expression; // expression describing the start address + UINT32 m_chunks_per_row; // number of chunks displayed per line + UINT8 m_bytes_per_chunk; // bytes per chunk + bool m_reverse_view; // reverse-endian view? + bool m_ascii_view; // display ASCII characters? + bool m_no_translation; // don't run addresses through the cpu translation hook + offs_t m_maxaddr; // (derived) maximum address to display + UINT32 m_bytes_per_row; // (derived) number of bytes displayed per line + UINT32 m_byte_offset; // (derived) offset of starting visible byte + astring m_addrformat; // (derived) format string to use to print addresses struct section { bool contains(int x) const { return x >= m_pos && x < m_pos + m_width; } - INT32 m_pos; /* starting position */ - INT32 m_width; /* width of this section */ + INT32 m_pos; /* starting position */ + INT32 m_width; /* width of this section */ }; - section m_section[3]; // (derived) 3 sections to manage + section m_section[3]; // (derived) 3 sections to manage struct memory_view_pos { - UINT8 m_spacing; /* spacing between each entry */ - UINT8 m_shift[24]; /* shift for each character */ + UINT8 m_spacing; /* spacing between each entry */ + UINT8 m_shift[24]; /* shift for each character */ }; - static const memory_view_pos s_memory_pos_table[9]; // table for rendering at different chunk sizes + static const memory_view_pos s_memory_pos_table[9]; // table for rendering at different chunk sizes // constants static const int MEM_MAX_LINE_WIDTH = 1024; diff --git a/src/emu/diimage.c b/src/emu/diimage.c index ddfccce0a7f..c435e8df00e 100644 --- a/src/emu/diimage.c +++ b/src/emu/diimage.c @@ -67,8 +67,8 @@ const image_device_type_info device_image_interface::m_device_info_array[] = { IO_CDROM, "cdrom", "cdrm" }, /* 13 */ { IO_MAGTAPE, "magtape", "magt" }, /* 14 */ { IO_ROM, "romimage", "rom" }, /* 15 */ - { IO_MIDIIN, "midiin", "min" }, /* 16 */ - { IO_MIDIOUT, "midiout", "mout" } /* 17 */ + { IO_MIDIIN, "midiin", "min" }, /* 16 */ + { IO_MIDIOUT, "midiout", "mout" } /* 17 */ }; diff --git a/src/emu/diimage.h b/src/emu/diimage.h index 70da52c9263..15f75019a13 100644 --- a/src/emu/diimage.h +++ b/src/emu/diimage.h @@ -70,8 +70,8 @@ enum iodevice_t IO_CDROM, /* 14 - optical CD-ROM disc */ IO_MAGTAPE, /* 15 - Magentic tape */ IO_ROM, /* 16 - Individual ROM image - the Amstrad CPC has a few applications that were sold on 16kB ROMs */ - IO_MIDIIN, /* 17 - MIDI In port */ - IO_MIDIOUT, /* 18 - MIDI Out port */ + IO_MIDIIN, /* 17 - MIDI In port */ + IO_MIDIOUT, /* 18 - MIDI Out port */ IO_COUNT /* 19 - Total Number of IO_devices for searching */ }; diff --git a/src/emu/imagedev/midiin.c b/src/emu/imagedev/midiin.c index 97ed349cd64..75dfd047cdd 100644 --- a/src/emu/imagedev/midiin.c +++ b/src/emu/imagedev/midiin.c @@ -21,8 +21,8 @@ const device_type MIDIIN = &device_creator<midiin_device>; midiin_device::midiin_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : device_t(mconfig, MIDIIN, "MIDI In image device", tag, owner, clock), - device_image_interface(mconfig, *this), - device_serial_interface(mconfig, *this) + device_image_interface(mconfig, *this), + device_serial_interface(mconfig, *this) { } @@ -77,7 +77,7 @@ void midiin_device::device_timer(emu_timer &timer, device_timer_id id, int param int bytesRead; if (m_midi == NULL) { - return; + return; } while (osd_poll_midi_channel(m_midi)) @@ -122,8 +122,8 @@ void midiin_device::call_unload(void) { osd_close_midi_channel(m_midi); } - m_timer->enable(false); - m_midi = NULL; + m_timer->enable(false); + m_midi = NULL; } void midiin_device::tra_complete() @@ -131,7 +131,7 @@ void midiin_device::tra_complete() // is there more waiting to send? if (m_xmit_read != m_xmit_write) { -// printf("tx1 %02x\n", m_xmitring[m_xmit_read]); +// printf("tx1 %02x\n", m_xmitring[m_xmit_read]); transmit_register_setup(m_xmitring[m_xmit_read++]); if (m_xmit_read >= XMIT_RING_SIZE) { @@ -158,7 +158,7 @@ void midiin_device::xmit_char(UINT8 data) if (!m_tx_busy) { m_tx_busy = true; -// printf("tx0 %02x\n", data); +// printf("tx0 %02x\n", data); transmit_register_setup(data); } else @@ -175,4 +175,3 @@ void midiin_device::xmit_char(UINT8 data) void midiin_device::input_callback(UINT8 state) { } - diff --git a/src/emu/imagedev/midiout.c b/src/emu/imagedev/midiout.c index 3155a9b7057..c0de35d906d 100644 --- a/src/emu/imagedev/midiout.c +++ b/src/emu/imagedev/midiout.c @@ -44,7 +44,7 @@ void midiout_device::device_reset() } /*------------------------------------------------- - device_config_complete + device_config_complete -------------------------------------------------*/ void midiout_device::device_config_complete(void) @@ -94,4 +94,3 @@ void midiout_device::rcv_complete() // Rx completed receiving byte void midiout_device::input_callback(UINT8 state) { } - diff --git a/src/emu/machine/mos6551.c b/src/emu/machine/mos6551.c index 06c3927c95a..a20e1aebc9b 100644 --- a/src/emu/machine/mos6551.c +++ b/src/emu/machine/mos6551.c @@ -9,12 +9,12 @@ /* - TODO: + TODO: - - receiver disable - - IRQ on DCD/DSR change - - parity - - framing error + - receiver disable + - IRQ on DCD/DSR change + - parity + - framing error */ @@ -100,7 +100,7 @@ void mos6551_device::tra_complete() { transmit_register_setup(m_tdr); m_st |= ST_TDRE; - + if ((m_cmd & CMD_TC_MASK) == CMD_TC_TIE_RTS_LO) { m_st |= ST_IRQ; @@ -120,7 +120,7 @@ void mos6551_device::rcv_complete() { m_st |= ST_OR; } - + m_st &= ~(ST_FE | ST_PE); m_st |= ST_RDRF; @@ -159,7 +159,7 @@ void mos6551_device::update_serial() else { int baud = clock() / brg_divider[brg] / 16; - + set_tra_rate(baud); if (m_ctrl & CTRL_RXC_BRG) @@ -250,12 +250,12 @@ WRITE8_MEMBER( mos6551_device::write ) case 0: m_tdr = data; m_st &= ~ST_TDRE; - + if (is_transmit_register_empty()) { transmit_register_setup(m_tdr); m_st |= ST_TDRE; - + if ((m_cmd & CMD_TC_MASK) == CMD_TC_TIE_RTS_LO) { m_st |= ST_IRQ; diff --git a/src/emu/machine/mos6551.h b/src/emu/machine/mos6551.h index b3b1367461a..d11ec355328 100644 --- a/src/emu/machine/mos6551.h +++ b/src/emu/machine/mos6551.h @@ -93,17 +93,17 @@ protected: CTRL_BRG_9600, CTRL_BRG_19200, CTRL_BRG_MASK = 0x0f, - + CTRL_RXC_EXT = 0x00, CTRL_RXC_BRG = 0x10, CTRL_RXC_MASK = 0x10, - + CTRL_WL_8 = 0x00, CTRL_WL_7 = 0x20, CTRL_WL_6 = 0x40, CTRL_WL_5 = 0x60, CTRL_WL_MASK = 0x60, - + CTRL_SB_1 = 0x00, CTRL_SB_2 = 0x80, CTRL_SB_MASK = 0x80 @@ -112,9 +112,9 @@ protected: enum { CMD_DTR = 0x01, - + CMD_RIE = 0x02, - + CMD_TC_RTS_HI = 0x00, CMD_TC_TIE_RTS_LO = 0x04, CMD_TC_RTS_LO = 0x08, diff --git a/src/emu/machine/n68681.c b/src/emu/machine/n68681.c index 10dd04f86a6..e8d01d700c6 100644 --- a/src/emu/machine/n68681.c +++ b/src/emu/machine/n68681.c @@ -976,4 +976,3 @@ void duart68681_channel::ACR_updated() { write_chan_reg(1, CSR); } - diff --git a/src/emu/machine/s3c24xx.c b/src/emu/machine/s3c24xx.c index 4cbd9d9b3de..521effa5c8e 100644 --- a/src/emu/machine/s3c24xx.c +++ b/src/emu/machine/s3c24xx.c @@ -3679,7 +3679,7 @@ static DEVICE_RESET( s3c24xx ) static DEVICE_START( s3c24xx ) { s3c24xx_t *s3c24xx = get_token( device); - + s3c24xx->m_cpu = device->machine().device( "maincpu"); verboselog( device->machine(), 1, "s3c24xx device start\n"); diff --git a/src/emu/machine/wd_fdc.c b/src/emu/machine/wd_fdc.c index 0711626d948..bb353c176c6 100644 --- a/src/emu/machine/wd_fdc.c +++ b/src/emu/machine/wd_fdc.c @@ -1002,10 +1002,10 @@ void wd_fdc_t::sector_w(UINT8 val) if (inverted_bus) val ^= 0xff; // No more than one write in flight - // C1581 accesses this register with an INC opcode, + // C1581 accesses this register with an INC opcode, // i.e. write old value, write new value, and the new value gets ignored by this //if(sector_buffer != -1) - // return; + // return; sector_buffer = val; delay_cycles(t_sector, dden ? delay_register_commit*2 : delay_register_commit); diff --git a/src/emu/softlist.c b/src/emu/softlist.c index 501eca9c37d..1ebb56e4ba7 100644 --- a/src/emu/softlist.c +++ b/src/emu/softlist.c @@ -1478,7 +1478,7 @@ static struct rom_entry *software_find_romdata(software_part *swpart, const char data++; } - + if (data && !data->_name) data = NULL; } diff --git a/src/emu/sound/digitalk.c b/src/emu/sound/digitalk.c index ea78a5f807d..3af96b6eb13 100644 --- a/src/emu/sound/digitalk.c +++ b/src/emu/sound/digitalk.c @@ -263,29 +263,29 @@ const device_type DIGITALKER = &device_creator<digitalker_device>; digitalker_device::digitalker_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : device_t(mconfig, DIGITALKER, "Digitalker", tag, owner, clock), - device_sound_interface(mconfig, *this), - m_rom(NULL), - m_stream(NULL), - m_data(0), - m_cs(0), - m_cms(0), - m_wr(0), - m_intr(0), - m_bpos(0), - m_apos(0), - m_mode(0), - m_cur_segment(0), - m_cur_repeat(0), - m_segments(0), - m_repeats(0), - m_prev_pitch(0), - m_pitch(0), - m_pitch_pos(0), - m_stop_after(0), - m_cur_dac(0), - m_cur_bits(0), - m_zero_count(0), - m_dac_index(0) + device_sound_interface(mconfig, *this), + m_rom(NULL), + m_stream(NULL), + m_data(0), + m_cs(0), + m_cms(0), + m_wr(0), + m_intr(0), + m_bpos(0), + m_apos(0), + m_mode(0), + m_cur_segment(0), + m_cur_repeat(0), + m_segments(0), + m_repeats(0), + m_prev_pitch(0), + m_pitch(0), + m_pitch_pos(0), + m_stop_after(0), + m_cur_dac(0), + m_cur_bits(0), + m_zero_count(0), + m_dac_index(0) { } @@ -688,4 +688,3 @@ WRITE8_MEMBER( digitalker_device::digitalker_data_w ) { m_data = data; } - diff --git a/src/emu/sound/digitalk.h b/src/emu/sound/digitalk.h index d293fabb9a9..70fc392764c 100644 --- a/src/emu/sound/digitalk.h +++ b/src/emu/sound/digitalk.h @@ -19,7 +19,7 @@ // ======================> digitalker_device class digitalker_device : public device_t, - public device_sound_interface + public device_sound_interface { public: digitalker_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); diff --git a/src/emu/sound/flt_rc.c b/src/emu/sound/flt_rc.c index 7d026a65253..f05cc63883e 100644 --- a/src/emu/sound/flt_rc.c +++ b/src/emu/sound/flt_rc.c @@ -19,11 +19,11 @@ const device_type FILTER_RC = &device_creator<filter_rc_device>; filter_rc_device::filter_rc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : device_t(mconfig, FILTER_RC, "RC Filter", tag, owner, clock), - device_sound_interface(mconfig, *this), - m_stream(NULL), - m_k(0), - m_memory(0), - m_type(0) + device_sound_interface(mconfig, *this), + m_stream(NULL), + m_k(0), + m_memory(0), + m_type(0) { } @@ -119,4 +119,3 @@ void filter_rc_device::filter_rc_set_RC(int type, double R1, double R2, double R m_stream->update(); set_RC_info(type, R1, R2, R3, C); } - diff --git a/src/emu/sound/flt_rc.h b/src/emu/sound/flt_rc.h index aeb18716632..acf5c628baa 100644 --- a/src/emu/sound/flt_rc.h +++ b/src/emu/sound/flt_rc.h @@ -73,13 +73,13 @@ extern const flt_rc_config flt_rc_ac_default; // ======================> filter_rc_device class filter_rc_device : public device_t, - public device_sound_interface + public device_sound_interface { public: filter_rc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); ~filter_rc_device() { } - void filter_rc_set_RC(int type, double R1, double R2, double R3, double C); + void filter_rc_set_RC(int type, double R1, double R2, double R3, double C); protected: // device-level overrides @@ -89,7 +89,7 @@ protected: virtual void sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples); private: - void set_RC_info(int type, double R1, double R2, double R3, double C); + void set_RC_info(int type, double R1, double R2, double R3, double C); private: sound_stream* m_stream; diff --git a/src/emu/sound/flt_vol.c b/src/emu/sound/flt_vol.c index 2532371ecb9..eac2ca7ac7a 100644 --- a/src/emu/sound/flt_vol.c +++ b/src/emu/sound/flt_vol.c @@ -11,9 +11,9 @@ const device_type FILTER_VOLUME = &device_creator<filter_volume_device>; filter_volume_device::filter_volume_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : device_t(mconfig, FILTER_VOLUME, "Volume Filter", tag, owner, clock), - device_sound_interface(mconfig, *this), - m_stream(NULL), - m_gain(0) + device_sound_interface(mconfig, *this), + m_stream(NULL), + m_gain(0) { } @@ -48,4 +48,3 @@ void filter_volume_device::flt_volume_set_volume(float volume) { m_gain = (int)(volume * 256); } - diff --git a/src/emu/sound/flt_vol.h b/src/emu/sound/flt_vol.h index 7836930247c..8440989764a 100644 --- a/src/emu/sound/flt_vol.h +++ b/src/emu/sound/flt_vol.h @@ -22,13 +22,13 @@ // ======================> filter_volume_device class filter_volume_device : public device_t, - public device_sound_interface + public device_sound_interface { public: filter_volume_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); ~filter_volume_device() { } - void flt_volume_set_volume(float volume); + void flt_volume_set_volume(float volume); protected: // device-level overrides diff --git a/src/emu/sound/iremga20.c b/src/emu/sound/iremga20.c index c2e32675731..9314760f57c 100644 --- a/src/emu/sound/iremga20.c +++ b/src/emu/sound/iremga20.c @@ -46,10 +46,10 @@ const device_type IREMGA20 = &device_creator<iremga20_device>; iremga20_device::iremga20_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : device_t(mconfig, IREMGA20, "Irem GA20", tag, owner, clock), - device_sound_interface(mconfig, *this), - m_rom(NULL), - m_rom_size(0), - m_stream(NULL) + device_sound_interface(mconfig, *this), + m_rom(NULL), + m_rom_size(0), + m_stream(NULL) { } diff --git a/src/emu/sound/iremga20.h b/src/emu/sound/iremga20.h index 02a70f5aaa4..f919065e749 100644 --- a/src/emu/sound/iremga20.h +++ b/src/emu/sound/iremga20.h @@ -56,12 +56,12 @@ protected: virtual void sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples); public: - DECLARE_WRITE8_MEMBER( irem_ga20_w ); - DECLARE_READ8_MEMBER( irem_ga20_r ); + DECLARE_WRITE8_MEMBER( irem_ga20_w ); + DECLARE_READ8_MEMBER( irem_ga20_r ); private: void iremga20_reset(); - + private: UINT8 *m_rom; INT32 m_rom_size; diff --git a/src/emu/sound/k005289.c b/src/emu/sound/k005289.c index c3f492e6df2..710f7b4369a 100644 --- a/src/emu/sound/k005289.c +++ b/src/emu/sound/k005289.c @@ -45,11 +45,11 @@ const device_type K005289 = &device_creator<k005289_device>; k005289_device::k005289_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : device_t(mconfig, K005289, "K005289", tag, owner, clock), - device_sound_interface(mconfig, *this), + device_sound_interface(mconfig, *this), m_sound_prom(NULL), m_stream(NULL), m_mclock(0), - m_rate(0), + m_rate(0), m_mixer_table(NULL), m_mixer_lookup(NULL), m_mixer_buffer(NULL), diff --git a/src/emu/sound/k005289.h b/src/emu/sound/k005289.h index cef1781df7c..349bb57281b 100644 --- a/src/emu/sound/k005289.h +++ b/src/emu/sound/k005289.h @@ -30,7 +30,7 @@ struct k005289_sound_channel // ======================> k005289_device class k005289_device : public device_t, - public device_sound_interface + public device_sound_interface { public: k005289_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); @@ -52,8 +52,8 @@ public: DECLARE_WRITE8_MEMBER( k005289_keylatch_B_w ); private: - void make_mixer_table(int voices); - void k005289_recompute(); + void make_mixer_table(int voices); + void k005289_recompute(); private: k005289_sound_channel m_channel_list[2]; @@ -61,7 +61,7 @@ private: const unsigned char *m_sound_prom; sound_stream *m_stream; int m_mclock; - int m_rate; + int m_rate; /* mixer tables and internal buffers */ INT16 *m_mixer_table; diff --git a/src/emu/sound/k056800.c b/src/emu/sound/k056800.c index 1d587d92c18..5623fc20354 100644 --- a/src/emu/sound/k056800.c +++ b/src/emu/sound/k056800.c @@ -198,5 +198,3 @@ void k056800_device::device_reset() { DEVICE_RESET_NAME( k056800 )(this); } - - diff --git a/src/emu/sound/n63701x.c b/src/emu/sound/n63701x.c index 3b4acf8dc61..22ebcc3385b 100644 --- a/src/emu/sound/n63701x.c +++ b/src/emu/sound/n63701x.c @@ -24,16 +24,16 @@ silence compression: '00 nn' must be replaced by nn+1 times '80'. inside 16 bits without overflowing. */ static const int vol_table[4] = { 26, 84, 200, 258 }; - + // device type definition const device_type NAMCO_63701X = &device_creator<namco_63701x_device>; namco_63701x_device::namco_63701x_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : device_t(mconfig, NAMCO_63701X, "Namco 63701X", tag, owner, clock), - device_sound_interface(mconfig, *this), - m_stream(NULL), - m_rom(NULL) + device_sound_interface(mconfig, *this), + m_stream(NULL), + m_rom(NULL) { } @@ -140,4 +140,3 @@ WRITE8_MEMBER( namco_63701x_device::namco_63701x_w ) } } } - diff --git a/src/emu/sound/n63701x.h b/src/emu/sound/n63701x.h index 3493a2a7767..3ea3c60c5ba 100644 --- a/src/emu/sound/n63701x.h +++ b/src/emu/sound/n63701x.h @@ -21,12 +21,12 @@ struct voice_63701x { voice_63701x() : select(0), - playing(0), - base_addr(0), - position(0), - volume(0), - silence_counter(0) {} - + playing(0), + base_addr(0), + position(0), + volume(0), + silence_counter(0) {} + int select; int playing; int base_addr; @@ -58,7 +58,7 @@ public: private: voice_63701x m_voices[2]; sound_stream *m_stream; /* channel assigned by the mixer */ - UINT8 *m_rom; /* pointer to sample ROM */ + UINT8 *m_rom; /* pointer to sample ROM */ }; extern const device_type NAMCO_63701X; diff --git a/src/emu/sound/spu.c b/src/emu/sound/spu.c index 1a0c25cf170..072bd0b0502 100644 --- a/src/emu/sound/spu.c +++ b/src/emu/sound/spu.c @@ -2338,7 +2338,7 @@ void spu_device::key_on(const int v) void spu_device::set_xa_format(const float _freq, const int channels) { // Adjust frequency to compensate for slightly slower/faster frame rate -// float freq=44100.0; //(_freq*get_adjusted_frame_rate())/ps1hw.rcnt->get_vertical_refresh(); +// float freq=44100.0; //(_freq*get_adjusted_frame_rate())/ps1hw.rcnt->get_vertical_refresh(); xa_freq=(unsigned int)((_freq/44100.0)*4096.0f); xa_channels=channels; @@ -2499,7 +2499,7 @@ void spu_device::generate_cdda(void *ptr, const unsigned int sz) if (! cdda_buffer->get_bytes_in()) cdda_playing=false; -// if (n>0) printf("cdda buffer underflow (n=%d cdda_in=%d spf=%d)\n",n,cdda_buffer->get_bytes_in(),cdda_spf); +// if (n>0) printf("cdda buffer underflow (n=%d cdda_in=%d spf=%d)\n",n,cdda_buffer->get_bytes_in(),cdda_spf); } } diff --git a/src/emu/sound/t6721a.h b/src/emu/sound/t6721a.h index 66cc6c593db..9005f596da6 100644 --- a/src/emu/sound/t6721a.h +++ b/src/emu/sound/t6721a.h @@ -62,7 +62,7 @@ // ======================> t6721a_device class t6721a_device : public device_t, - public device_sound_interface + public device_sound_interface { public: t6721a_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); diff --git a/src/emu/sound/tiaintf.c b/src/emu/sound/tiaintf.c index 2b1fe9963a2..ccc9abee31b 100644 --- a/src/emu/sound/tiaintf.c +++ b/src/emu/sound/tiaintf.c @@ -16,9 +16,9 @@ const device_type TIA = &device_creator<tia_device>; tia_device::tia_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : device_t(mconfig, TIA, "TIA", tag, owner, clock), - device_sound_interface(mconfig, *this), - m_channel(NULL), - m_chip(NULL) + device_sound_interface(mconfig, *this), + m_channel(NULL), + m_chip(NULL) { } diff --git a/src/emu/sound/tiaintf.h b/src/emu/sound/tiaintf.h index 89ef8abe527..726ff2df21b 100644 --- a/src/emu/sound/tiaintf.h +++ b/src/emu/sound/tiaintf.h @@ -20,7 +20,7 @@ // ======================> tia_device class tia_device : public device_t, - public device_sound_interface + public device_sound_interface { public: tia_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); @@ -35,7 +35,7 @@ protected: virtual void sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples); public: - DECLARE_WRITE8_MEMBER( tia_sound_w ); + DECLARE_WRITE8_MEMBER( tia_sound_w ); private: sound_stream *m_channel; diff --git a/src/emu/video/ef9340_1.c b/src/emu/video/ef9340_1.c index 25b65a23e7e..3001c5af9b5 100644 --- a/src/emu/video/ef9340_1.c +++ b/src/emu/video/ef9340_1.c @@ -17,7 +17,7 @@ const device_type EF9340_1 = &device_creator<ef9340_1_device>; static const UINT8 bgr2rgb[8] = { - 0x00, 0x04, 0x02, 0x06, 0x01, 0x05, 0x03, 0x07 + 0x00, 0x04, 0x02, 0x06, 0x01, 0x05, 0x03, 0x07 }; @@ -390,4 +390,3 @@ void ef9340_1_device::ef9340_scanline(int vpos) } } } - diff --git a/src/emu/video/ef9340_1.h b/src/emu/video/ef9340_1.h index 7431240f1e1..de91d62b364 100644 --- a/src/emu/video/ef9340_1.h +++ b/src/emu/video/ef9340_1.h @@ -17,14 +17,13 @@ #define MCFG_EF9340_1_ADD(_tag, _clock, _screen_tag) \ MCFG_DEVICE_ADD(_tag, EF9340_1, _clock) \ - ef9340_1_device::set_screen_tag(*device, _screen_tag); \ - + ef9340_1_device::set_screen_tag(*device, _screen_tag); class ef9340_1_device : public device_t { public: - // construction/destruction - ef9340_1_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + // construction/destruction + ef9340_1_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); // static configuration helpers static void set_screen_tag(device_t &device, const char *screen_tag) { downcast<ef9340_1_device &>(device).m_screen_tag = screen_tag; } @@ -82,4 +81,3 @@ protected: extern const device_type EF9340_1; #endif /* __EF9340_1_H__ */ - diff --git a/src/emu/video/i8244.c b/src/emu/video/i8244.c index a4fb9e4c7fb..5320fc066ab 100644 --- a/src/emu/video/i8244.c +++ b/src/emu/video/i8244.c @@ -318,20 +318,20 @@ READ8_MEMBER(i8244_device::read) break; - case 0xa5: - if ((m_vdc.s.control & VDC_CONTROL_REG_STROBE_XY)) + case 0xa5: + if ((m_vdc.s.control & VDC_CONTROL_REG_STROBE_XY)) { - m_x_beam_pos = get_x_beam(); + m_x_beam_pos = get_x_beam(); } - data = m_x_beam_pos; - break; + data = m_x_beam_pos; + break; - default: - data = m_vdc.reg[offset]; + default: + data = m_vdc.reg[offset]; break; - } + } - return data; + return data; } @@ -348,7 +348,7 @@ WRITE8_MEMBER(i8244_device::write) if (offset == 0xa0) { if ( ( m_vdc.s.control & VDC_CONTROL_REG_STROBE_XY ) - && !(data & VDC_CONTROL_REG_STROBE_XY)) + && !(data & VDC_CONTROL_REG_STROBE_XY)) { /* Toggling strobe bit, tuck away values */ m_x_beam_pos = get_x_beam(); @@ -409,7 +409,7 @@ void i8244_device::render_scanline(int vpos) //static const UINT8 COLLISION_EXTERNAL_UNUSED = 0x40; static const UINT8 COLLISION_CHARACTERS = 0x80; - UINT8 collision_map[160]; + UINT8 collision_map[160]; if ( vpos == m_start_vpos ) @@ -501,8 +501,8 @@ void i8244_device::render_scanline(int vpos) /* Regular foreground objects */ for ( int i = 0; i < ARRAY_LENGTH( m_vdc.s.foreground ); i++ ) { - int y = m_vdc.s.foreground[i].y & 0xFE; - int height = 8 - ( ( ( y >> 1 ) + m_vdc.s.foreground[i].ptr ) & 7 ); + int y = m_vdc.s.foreground[i].y & 0xFE; + int height = 8 - ( ( ( y >> 1 ) + m_vdc.s.foreground[i].ptr ) & 7 ); if ( y >= 0x0E && y <= scanline && scanline < y + height * 2 ) { @@ -544,7 +544,7 @@ void i8244_device::render_scanline(int vpos) if ( y <= scanline && scanline < y + height * 2 ) { - int x = m_vdc.s.quad[i].single[0].x; + int x = m_vdc.s.quad[i].single[0].x; // Charaecter height is always determined by the height of the 4th character int char_height = 8 - ( ( ( y >> 1 ) + m_vdc.s.quad[i].single[3].ptr ) & 7 ); @@ -553,7 +553,6 @@ void i8244_device::render_scanline(int vpos) { if ( y <= scanline && scanline < y + char_height * 2 ) { - UINT16 color = 8 + bgr2rgb[ ( ( m_vdc.s.quad[i].single[j].color >> 1 ) & 0x07 ) ]; int offset = ( m_vdc.s.quad[i].single[j].ptr | ( ( m_vdc.s.quad[i].single[j].color & 0x01 ) << 8 ) ) + ( y >> 1 ) + ( ( scanline - y ) >> 1 ); UINT8 chr = c_shape[ offset & 0x1FF ]; @@ -605,7 +604,7 @@ void i8244_device::render_scanline(int vpos) int x = m_vdc.s.sprites[i].x; int x_shift = 0; - switch ( m_vdc.s.sprites[i].color & 0x03 ) + switch ( m_vdc.s.sprites[i].color & 0x03 ) { case 1: // Xg attribute set x_shift = 2; @@ -736,7 +735,7 @@ void i8244_device::sound_stream_update(sound_stream &stream, stream_sample_t **i /* Generate the signal */ old_signal = signal = m_vdc.s.shift3 | (m_vdc.s.shift2 << 8) | (m_vdc.s.shift1 << 16); - if( m_vdc.s.sound & 0x80 ) /* Sound is enabled */ + if( m_vdc.s.sound & 0x80 ) /* Sound is enabled */ { for( ii = 0; ii < samples; ii++, buffer++ ) { @@ -791,5 +790,3 @@ UINT32 i8244_device::screen_update(screen_device &screen, bitmap_ind16 &bitmap, return 0; } - - diff --git a/src/emu/video/i8244.h b/src/emu/video/i8244.h index ed73f86e4b7..76e22a69172 100644 --- a/src/emu/video/i8244.h +++ b/src/emu/video/i8244.h @@ -22,23 +22,18 @@ MCFG_DEVICE_ADD(_tag, I8244, _clock) \ MCFG_I8244_SCREEN_TAG(_screen_tag) \ MCFG_I8244_IRQ_CB(_irq_cb) \ - MCFG_I8244_POSTPROCESS_CB(_postprocess_cb) \ - + MCFG_I8244_POSTPROCESS_CB(_postprocess_cb) #define MCFG_I8244_SCREEN_TAG(_screen_tag) \ - i8244_device::set_screen_tag(*device, _screen_tag); \ - + i8244_device::set_screen_tag(*device, _screen_tag); #define MCFG_I8244_IRQ_CB(_devcb) \ - devcb = &i8244_device::set_irq_cb(*device, DEVCB2_##_devcb); \ - + devcb = &i8244_device::set_irq_cb(*device, DEVCB2_##_devcb); #define MCFG_I8244_POSTPROCESS_CB(_devcb) \ - devcb = &i8244_device::set_postprocess_cb(*device, DEVCB2_##_devcb); \ - + devcb = &i8244_device::set_postprocess_cb(*device, DEVCB2_##_devcb); #define MCFG_I8245_ADD(_tag, _clock, _screen_tag, _irq_cb, _postprocess_cb) \ MCFG_DEVICE_ADD(_tag, I8245, _clock) \ MCFG_I8244_SCREEN_TAG(_screen_tag) \ MCFG_I8244_IRQ_CB(_irq_cb) \ - MCFG_I8244_POSTPROCESS_CB(_postprocess_cb ) \ - + MCFG_I8244_POSTPROCESS_CB(_postprocess_cb ) /*************************************************************************** TYPE DEFINITIONS @@ -48,15 +43,15 @@ union vdc_t { UINT8 reg[0x100]; struct { struct { - UINT8 y,x,color,res; + UINT8 y,x,color,res; } sprites[4]; struct { - UINT8 y,x,ptr,color; + UINT8 y,x,ptr,color; } foreground[12]; struct { - struct { + struct { UINT8 y,x,ptr,color; - } single[4]; + } single[4]; } quad[4]; UINT8 shape[4][8]; UINT8 control; @@ -83,8 +78,8 @@ class i8244_device : public device_t , public device_sound_interface { public: - // construction/destruction - i8244_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + // construction/destruction + i8244_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); i8244_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, int lines); // static configuration helpers @@ -103,7 +98,7 @@ public: inline bitmap_ind16 *get_bitmap() { return &m_tmp_bitmap; } - // Global constants + // Global constants static const int START_ACTIVE_SCAN = 42; static const int BORDER_SIZE = 10; static const int END_ACTIVE_SCAN = 42 + 10 + 320 + 10; @@ -133,8 +128,8 @@ protected: static const device_timer_id TIMER_LINE = 0; static const device_timer_id TIMER_HBLANK = 1; - // callbacks - devcb2_write_line m_irq_func; + // callbacks + devcb2_write_line m_irq_func; devcb2_write16 m_postprocess_func; const char *m_screen_tag; diff --git a/src/emu/video/mc6845.h b/src/emu/video/mc6845.h index c75ee6d5927..0a364b440bc 100644 --- a/src/emu/video/mc6845.h +++ b/src/emu/video/mc6845.h @@ -70,7 +70,7 @@ typedef void (*mc6845_on_update_addr_changed_func)(mc6845_device *device, int ad struct mc6845_interface { const char *m_screen_tag; /* screen we are acting on */ - bool m_show_border_area; /* visible screen area (false) active display (true) active display + blanking */ + bool m_show_border_area; /* visible screen area (false) active display (true) active display + blanking */ int m_hpixels_per_column; /* number of pixels per video memory address */ /* if specified, this gets called before any pixel update, diff --git a/src/emu/video/pc_cga.c b/src/emu/video/pc_cga.c index 34c63d23e49..50a2219baea 100644 --- a/src/emu/video/pc_cga.c +++ b/src/emu/video/pc_cga.c @@ -182,16 +182,16 @@ static VIDEO_START( cga_mc1502 ); static MC6845_INTERFACE( mc6845_cga_intf ) { - CGA_SCREEN_NAME, /* screen number */ - false, /* show border area */ - 8, /* numbers of pixels per video memory address */ - NULL, /* begin_update */ - cga_update_row, /* update_row */ - NULL, /* end_update */ - DEVCB_NULL, /* on_de_changed */ - DEVCB_NULL, /* on_cur_changed */ - DEVCB_LINE(cga_hsync_changed), /* on_hsync_changed */ - DEVCB_LINE(cga_vsync_changed), /* on_vsync_changed */ + CGA_SCREEN_NAME, /* screen number */ + false, /* show border area */ + 8, /* numbers of pixels per video memory address */ + NULL, /* begin_update */ + cga_update_row, /* update_row */ + NULL, /* end_update */ + DEVCB_NULL, /* on_de_changed */ + DEVCB_NULL, /* on_cur_changed */ + DEVCB_LINE(cga_hsync_changed), /* on_hsync_changed */ + DEVCB_LINE(cga_vsync_changed), /* on_vsync_changed */ NULL }; diff --git a/src/emu/video/tlc34076.c b/src/emu/video/tlc34076.c index 03ec2214460..ed812ee8d34 100644 --- a/src/emu/video/tlc34076.c +++ b/src/emu/video/tlc34076.c @@ -40,7 +40,7 @@ const device_type TLC34076 = &device_creator<tlc34076_device>; // tlc34076_device - constructor //------------------------------------------------- tlc34076_device::tlc34076_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) - : device_t(mconfig, TLC34076, "TLC34076", tag, owner, clock), + : device_t(mconfig, TLC34076, "TLC34076", tag, owner, clock), m_dacbits(6) { } diff --git a/src/emu/video/tlc34076.h b/src/emu/video/tlc34076.h index d73967d0a9f..a2aac64aec9 100644 --- a/src/emu/video/tlc34076.h +++ b/src/emu/video/tlc34076.h @@ -38,7 +38,7 @@ public: static void static_set_bits(device_t &device, tlc34076_bits bits); // public interface - const pen_t *get_pens(); + const pen_t *get_pens(); DECLARE_READ8_MEMBER(read); DECLARE_WRITE8_MEMBER(write); |