diff options
author | 2009-05-05 17:06:28 +0000 | |
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committer | 2009-05-05 17:06:28 +0000 | |
commit | c713b0ba1a945cfdbea14e7e37fc9a9b95d6986e (patch) | |
tree | d6ecd928a248815b643d6cc082d319f029c82d0d /src/emu/sound/sn76496.c | |
parent | 38833fa1dc91a55ee79588463d8b6a880146c699 (diff) |
minor update to sn76496.c to make the cycles to ready change made more sane (still not completely right), and document why.
Diffstat (limited to 'src/emu/sound/sn76496.c')
-rw-r--r-- | src/emu/sound/sn76496.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/src/emu/sound/sn76496.c b/src/emu/sound/sn76496.c index 2aea01e5c3d..d356c791771 100644 --- a/src/emu/sound/sn76496.c +++ b/src/emu/sound/sn76496.c @@ -111,8 +111,16 @@ WRITE8_DEVICE_HANDLER( sn76496_w ) /* update the output buffer before changing the registers */ stream_update(R->Channel); - /* set number of cycles until READY is active; this is always one 'sample', i.e. it equals the clock divider exactly; until the clock divider is fully supported, we delay until one sample has played */ - R->CyclestoREADY = 4; + /* set number of cycles until READY is active; this is always one + 'sample', i.e. it equals the clock divider exactly; until the + clock divider is fully supported, we delay until one sample has + played. The fact that this below is '2' and not '1' is because + of a ?race condition? in the mess crvision driver, where after + any sample is played at all, no matter what, the cycles_to_ready + ends up never being not ready, unless this value is greater than + 1. Once the full clock divider stuff is written, this should no + longer be an issue. */ + R->CyclestoREADY = 2; if (data & 0x80) { |