diff options
author | 2007-12-17 15:19:59 +0000 | |
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committer | 2007-12-17 15:19:59 +0000 | |
commit | 7b77f1218624ea26dbb2efd85a19f795f5d4e02e (patch) | |
tree | 19209304095572b4fd61c2a2d6a5aa75c4e471ad /src/emu/sound/okim6295.h | |
parent | 3da7f476068b3ffef713218ba2fc1bd5030f2c38 (diff) |
Initial checkin of MAME 0.121.mame0121
Diffstat (limited to 'src/emu/sound/okim6295.h')
-rw-r--r-- | src/emu/sound/okim6295.h | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/src/emu/sound/okim6295.h b/src/emu/sound/okim6295.h new file mode 100644 index 00000000000..b11a171e44b --- /dev/null +++ b/src/emu/sound/okim6295.h @@ -0,0 +1,65 @@ +#ifndef OKIM6295_H +#define OKIM6295_H + +/* an interface for the OKIM6295 and similar chips */ + +/* + Note about the playback frequency: the external clock is internally divided, + depending on pin 7, by 132 (high) or 165 (low). +*/ +struct OKIM6295interface +{ + int region; /* memory region where the sample ROM lives */ + int pin7; +}; + +extern const struct OKIM6295interface okim6295_interface_region_1_pin7high; +extern const struct OKIM6295interface okim6295_interface_region_2_pin7high; +extern const struct OKIM6295interface okim6295_interface_region_3_pin7high; +extern const struct OKIM6295interface okim6295_interface_region_4_pin7high; + +extern const struct OKIM6295interface okim6295_interface_region_1_pin7low; +extern const struct OKIM6295interface okim6295_interface_region_2_pin7low; +extern const struct OKIM6295interface okim6295_interface_region_3_pin7low; +extern const struct OKIM6295interface okim6295_interface_region_4_pin7low; + + + + + +void OKIM6295_set_bank_base(int which, int base); +void OKIM6295_set_pin7(int which, int pin7); + +READ8_HANDLER( OKIM6295_status_0_r ); +READ8_HANDLER( OKIM6295_status_1_r ); +READ8_HANDLER( OKIM6295_status_2_r ); +READ16_HANDLER( OKIM6295_status_0_lsb_r ); +READ16_HANDLER( OKIM6295_status_1_lsb_r ); +READ16_HANDLER( OKIM6295_status_2_lsb_r ); +READ16_HANDLER( OKIM6295_status_0_msb_r ); +READ16_HANDLER( OKIM6295_status_1_msb_r ); +READ16_HANDLER( OKIM6295_status_2_msb_r ); +WRITE8_HANDLER( OKIM6295_data_0_w ); +WRITE8_HANDLER( OKIM6295_data_1_w ); +WRITE8_HANDLER( OKIM6295_data_2_w ); +WRITE16_HANDLER( OKIM6295_data_0_lsb_w ); +WRITE16_HANDLER( OKIM6295_data_1_lsb_w ); +WRITE16_HANDLER( OKIM6295_data_2_lsb_w ); +WRITE16_HANDLER( OKIM6295_data_0_msb_w ); +WRITE16_HANDLER( OKIM6295_data_1_msb_w ); +WRITE16_HANDLER( OKIM6295_data_2_msb_w ); + +/* + To help the various custom ADPCM generators out there, + the following routines may be used. +*/ +struct adpcm_state +{ + INT32 signal; + INT32 step; +}; +void reset_adpcm(struct adpcm_state *state); +INT16 clock_adpcm(struct adpcm_state *state, UINT8 nibble); + + +#endif |