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author Zoë Blade <zoe@bytenoise.co.uk>2015-04-10 23:35:33 +0100
committer Zoë Blade <zoe@bytenoise.co.uk>2015-04-11 00:52:26 +0100
commit90f110f261b74f7cb49e537e573f34b6d6d453c1 (patch)
tree734d0e7870eab46688a49e98bf38ee0df6e94f54 /src/emu/cpu
parentac614bf9e4018fedd07df5e097d1b91b75654b15 (diff)
Fix various typos and spelling mistakes
I'm purposefully leaving /src/emu/bus/cbmiec/c1541.c's kernal.bin as it is, as this particular spelling mistake was originally made by Robert Russell, therefore is canon. See http://en.wikipedia.org/wiki/KERNAL for details. I'm also leaving /src/emu/machine/nscsi_bus.c's RECIEVE as I don't want to break anything, but it's worth someone looking into. I renamed some variables in /src/mame/drivers/sfbonus.c, /src/mame/video/tia.c and /src/mame/video/tia.h, so if anyone wants to verify I didn't break anything, that would be nice.
Diffstat (limited to 'src/emu/cpu')
-rw-r--r--src/emu/cpu/alto2/a2ether.c4
-rw-r--r--src/emu/cpu/alto2/a2mem.c8
-rw-r--r--src/emu/cpu/apexc/apexcdsm.c4
-rw-r--r--src/emu/cpu/dsp16/dsp16.h4
-rw-r--r--src/emu/cpu/m68000/m68kcpu.h2
-rw-r--r--src/emu/cpu/mcs51/mcs51.c2
-rw-r--r--src/emu/cpu/mn10200/mn10200.c2
-rw-r--r--src/emu/cpu/pdp1/pdp1.c32
-rw-r--r--src/emu/cpu/pps4/pps4.c6
-rw-r--r--src/emu/cpu/tms32025/tms32025.c2
-rw-r--r--src/emu/cpu/tms9900/99xxcore.h14
-rw-r--r--src/emu/cpu/tms9900/tms9995.c2
12 files changed, 41 insertions, 41 deletions
diff --git a/src/emu/cpu/alto2/a2ether.c b/src/emu/cpu/alto2/a2ether.c
index 94bd5e26603..7de3a30aa4b 100644
--- a/src/emu/cpu/alto2/a2ether.c
+++ b/src/emu/cpu/alto2/a2ether.c
@@ -435,9 +435,9 @@ void alto2_cpu_device::eth_wakeup()
* 'F401 is not in the data path, but only monitors the message. The
* Error output becomes valid after the last check bit has been entered
* into the 'F401 by a HIGH-to-LOW transition of CP'. If no detectable
- * errors have occured during the transmission, the resultant internal
+ * errors have occurred during the transmission, the resultant internal
* register bits are all LOW and the Error Output (ER) is LOW.
- * If a detectable error has occured, ER is HIGH.
+ * If a detectable error has occurred, ER is HIGH.
*
* A HIGH on the Master Reset input (MR) asynchronously clears the
* register. A LOW on the Preset input (P') asynchronously sets the
diff --git a/src/emu/cpu/alto2/a2mem.c b/src/emu/cpu/alto2/a2mem.c
index e0ae8563821..c878f09040b 100644
--- a/src/emu/cpu/alto2/a2mem.c
+++ b/src/emu/cpu/alto2/a2mem.c
@@ -487,7 +487,7 @@ UINT32 alto2_cpu_device::hamming_code(int write, UINT32 dw_addr, UINT32 dw_data)
*
* This register is a 'shadow MAR'; it holds the address of the
* first error since the error status was last reset. If no error
- * has occured, MEAR reports the address of the most recent
+ * has occurred, MEAR reports the address of the most recent
* memory access. Note that MEAR is set whenever an error of
* _any kind_ (single-bit or double-bit) is detected.
*/
@@ -504,7 +504,7 @@ READ16_MEMBER( alto2_cpu_device::mear_r )
* @brief memory error status register read
*
* This register reports specifics of the first error that
- * occured since MESR was last reset. Storing anything into
+ * occurred since MESR was last reset. Storing anything into
* this register resets the error logic and enables it to
* detect a new error. Bits are "low true", i.e. if the bit
* is 0, the conidition is true.
@@ -513,7 +513,7 @@ READ16_MEMBER( alto2_cpu_device::mear_r )
* MESR[6] Parity error
* MESR[7] Memory parity bit
* MESR[8-13] Syndrome bits
- * MESR[14-15] Bank number in which error occured
+ * MESR[14-15] Bank number in which error occurred
* </PRE>
*/
READ16_MEMBER( alto2_cpu_device::mesr_r )
@@ -551,7 +551,7 @@ WRITE16_MEMBER( alto2_cpu_device::mesr_w )
* the memory error logic. This register is set to all ones
* (disable all interrupts) when the alto is bootstrapped
* and when the parity error task first detects an error.
- * When an error has occured, MEAR and MESR should be read
+ * When an error has occurred, MEAR and MESR should be read
* before setting MECR. Bits are "low true", i.e. a 0 bit
* enables the condition.
*
diff --git a/src/emu/cpu/apexc/apexcdsm.c b/src/emu/cpu/apexc/apexcdsm.c
index e7ea37d08e8..276e0531e1e 100644
--- a/src/emu/cpu/apexc/apexcdsm.c
+++ b/src/emu/cpu/apexc/apexcdsm.c
@@ -86,7 +86,7 @@ CPU_DISASSEMBLE( apexc )
UINT32 instruction; /* 32-bit machine instruction */
int x, y, function, c6, vector; /* instruction fields */
int n; /* 'friendly', instruction-dependant interpretation of C6 */
- const instr_desc *the_desc; /* pointer to the revelant entry in the instructions array */
+ const instr_desc *the_desc; /* pointer to the relevant entry in the instructions array */
char mnemonic[9]; /* storage for generated mnemonic */
/* read the instruction to disassemble */
@@ -99,7 +99,7 @@ CPU_DISASSEMBLE( apexc )
c6 = (instruction >> 1) & 0x3F;
vector = instruction & 1;
- /* get the revelant entry in instructions */
+ /* get the relevant entry in instructions */
the_desc = & instructions[function >> 1];
/* generate mnemonic : append a 'v' to the basic mnemonic if it is a vector instruction */
diff --git a/src/emu/cpu/dsp16/dsp16.h b/src/emu/cpu/dsp16/dsp16.h
index db8cb49b3c8..ccb337d9865 100644
--- a/src/emu/cpu/dsp16/dsp16.h
+++ b/src/emu/cpu/dsp16/dsp16.h
@@ -91,12 +91,12 @@ protected:
UINT16 m_sdx;
UINT16 m_pioc;
UINT16 m_pdx0; // pdx0 & pdx1 refer to the same physical register (page 6-1)
- UINT16 m_pdx1; // but we keep them seperate for logic's sake.
+ UINT16 m_pdx1; // but we keep them separate for logic's sake.
// internal stuff
UINT16 m_ppc;
- // This CPU core handles the cache as more of a loop than 15 seperate memory elements.
+ // This CPU core handles the cache as more of a loop than 15 separate memory elements.
// It's a bit of a hack, but it's easier this way (for now).
UINT16 m_cacheStart;
UINT16 m_cacheEnd;
diff --git a/src/emu/cpu/m68000/m68kcpu.h b/src/emu/cpu/m68000/m68kcpu.h
index 8fef90d8896..460a5c42f66 100644
--- a/src/emu/cpu/m68000/m68kcpu.h
+++ b/src/emu/cpu/m68000/m68kcpu.h
@@ -698,7 +698,7 @@ INLINE UINT32 m68ki_ic_readimm16(m68000_base_device *m68k, UINT32 address)
// printf("m68k: doing cache fill at %08x (tag %08x idx %d)\n", address, tag, idx);
- // if no buserror occured, validate the tag
+ // if no buserror occurred, validate the tag
if (!m68k->mmu_tmp_buserror_occurred)
{
m68k->ic_address[idx] = tag;
diff --git a/src/emu/cpu/mcs51/mcs51.c b/src/emu/cpu/mcs51/mcs51.c
index 4cc92af071c..c212047e739 100644
--- a/src/emu/cpu/mcs51/mcs51.c
+++ b/src/emu/cpu/mcs51/mcs51.c
@@ -124,7 +124,7 @@
* - Fix limenko.c videopkr.c : Issue with core allocation of ram (duplicate savestate)
* - Handle internal ram better (debugger visible)
* - Fixed port reading
- * - Rewrote Macros for better readibility
+ * - Rewrote Macros for better readability
* - Fixed and rewrote Interrupt handling
* - Now returns INTERNAL_DIVIDER, adjusted cycle counts
* - Remove unnecessary and duplicated code
diff --git a/src/emu/cpu/mn10200/mn10200.c b/src/emu/cpu/mn10200/mn10200.c
index dbde9e1c927..e7c44761eef 100644
--- a/src/emu/cpu/mn10200/mn10200.c
+++ b/src/emu/cpu/mn10200/mn10200.c
@@ -394,7 +394,7 @@ TIMER_CALLBACK_MEMBER( mn10200_device::simple_timer_cb )
// handle our expiring and also tick our cascaded children
if (timer_tick_simple(tmr) == 2)
- m_simple_timer[tmr].cur = 0xff; // cascaded and no underflow occured
+ m_simple_timer[tmr].cur = 0xff; // cascaded and no underflow occurred
else
m_simple_timer[tmr].cur = m_simple_timer[tmr].base;
diff --git a/src/emu/cpu/pdp1/pdp1.c b/src/emu/cpu/pdp1/pdp1.c
index a7c280059d5..97ea4a4b753 100644
--- a/src/emu/cpu/pdp1/pdp1.c
+++ b/src/emu/cpu/pdp1/pdp1.c
@@ -441,7 +441,7 @@ void pdp1_device::field_interrupt()
/* current_irq: 1 bit for each active pending interrupt request
Pending interrupts are in b3 (simulated by (m_irq_state & m_b1) | m_b2)), but they
are only honored if no higher priority interrupt routine is in execution (one bit set in b4
- for each routine in execution). The revelant mask is created with (m_b4 | (- m_b4)),
+ for each routine in execution). The relevant mask is created with (m_b4 | (- m_b4)),
as the carry chain (remember that -b4 = (~ b4) + 1) does precisely what we want.
b4: 0001001001000
-b4: 1110110111000
@@ -833,7 +833,7 @@ void pdp1_device::execute_run()
else if ((IR == DIO) || (IR == DAC)) /* dio or dac instruction ? */
{ /* there is a discrepancy: the pdp1 handbook tells that only dio should be used,
but the lisp tape uses the dac instruction instead */
- /* Yet maintainance manual p. 6-25 states clearly that the data is located
+ /* Yet maintenance manual p. 6-25 states clearly that the data is located
in IO and transfered to MB, so DAC is likely to be a mistake. */
m_rim_step = 2;
}
@@ -881,7 +881,7 @@ void pdp1_device::execute_run()
/* yes, interrupt can occur in the midst of an instruction (impressing, huh?) */
/* Note that break cannot occur during a one-cycle jump that is deferred only once,
or another break cycle. Also, it cannot interrupt the long cycle 1 of automatic
- multiply/divide. (maintainance manual 6-19) */
+ multiply/divide. (maintenance manual 6-19) */
if (m_sbs_request && (! m_no_sequence_break) && (! m_brk_ctr))
{ /* begin sequence break */
m_brk_ctr = 1;
@@ -900,7 +900,7 @@ void pdp1_device::execute_run()
MA = m_sbs_level << 2; /* always 0 with standard sequence break system */
MB = AC; /* save AC to MB */
AC = (OV << 17) | (EXD << 16) | PC; /* save OV/EXD/PC to AC */
- EXD = OV = 0; /* according to maintainance manual p. 8-17 and ?-?? */
+ EXD = OV = 0; /* according to maintenance manual p. 8-17 and ?-?? */
m_cycle = m_defer = m_exc = 0; /* mere guess */
WRITE_PDP_18BIT(MA, MB); /* save former AC to memory */
INCREMENT_MA;
@@ -954,7 +954,7 @@ void pdp1_device::execute_run()
m_b4 &= ~(1 << level);
field_interrupt();
if (m_extend_support)
- EXD = 1; /* according to maintainance manual p. 6-33 */
+ EXD = 1; /* according to maintenance manual p. 6-33 */
m_sbs_restore = 1;
}
}
@@ -990,7 +990,7 @@ void pdp1_device::execute_run()
m_exc = 0;
if (m_sbs_restore)
- { /* interrupt return: according to maintainance manual p. 6-33 */
+ { /* interrupt return: according to maintenance manual p. 6-33 */
if (m_extend_support)
EXD = (MB >> 16) & 1;
OV = (MB >> 17) & 1;
@@ -1119,7 +1119,7 @@ void pdp1_device::execute_instruction()
break;
}
case SUB: /* Subtract */
- { /* maintainance manual 7-14 seems to imply that substract does not test for -0.
+ { /* maintenance manual 7-14 seems to imply that substract does not test for -0.
The sim 2.3 source says so explicitely, though they do not give a reference.
It sounds a bit weird, but the reason is probably that doing so would
require additionnal logic that does not exist. */
@@ -1230,7 +1230,7 @@ void pdp1_device::execute_instruction()
}
else
{ /* MUS */
- /* should we check for -0??? (Maintainance manual 7-14 seems to imply we should not:
+ /* should we check for -0??? (Maintenance manual 7-14 seems to imply we should not:
as a matter of fact, since the MUS instruction is supposed to have positive operands,
there is no need to check for -0, therefore such a simplification does not sound
absurd.) */
@@ -1777,8 +1777,8 @@ void pdp1_device::pdp1_type_20_sbs_iot(int op2, int nac, int mb, int *io, int ac
void pdp1_device::pulse_start_clear()
{
/* processor registers */
- PC = 0; /* according to maintainance manual p. 6-17 */
- IR = 0; /* according to maintainance manual p. 6-13 */
+ PC = 0; /* according to maintenance manual p. 6-17 */
+ IR = 0; /* according to maintenance manual p. 6-13 */
/*MB = 0;*/ /* ??? */
/*MA = 0;*/ /* ??? */
/*AC = 0;*/ /* ??? */
@@ -1790,14 +1790,14 @@ void pdp1_device::pulse_start_clear()
m_cycle = 0; /* mere guess */
m_defer = 0; /* mere guess */
m_brk_ctr = 0; /* mere guess */
- m_ov = 0; /* according to maintainance manual p. 7-18 */
+ m_ov = 0; /* according to maintenance manual p. 7-18 */
m_rim = 0; /* ??? */
m_sbm = 0; /* ??? */
- EXD = 0; /* according to maintainance manual p. 8-16 */
- m_exc = 0; /* according to maintainance manual p. 8-16 */
- m_ioc = 1; /* according to maintainance manual p. 6-10 */
- m_ioh = 0; /* according to maintainance manual p. 6-10 */
- m_ios = 0; /* according to maintainance manual p. 6-10 */
+ EXD = 0; /* according to maintenance manual p. 8-16 */
+ m_exc = 0; /* according to maintenance manual p. 8-16 */
+ m_ioc = 1; /* according to maintenance manual p. 6-10 */
+ m_ioh = 0; /* according to maintenance manual p. 6-10 */
+ m_ios = 0; /* according to maintenance manual p. 6-10 */
m_b1 = m_type_20_sbs ? 0 : 1; /* mere guess */
m_b2 = 0; /* mere guess */
diff --git a/src/emu/cpu/pps4/pps4.c b/src/emu/cpu/pps4/pps4.c
index af3b1290c5e..d1ee54e6e64 100644
--- a/src/emu/cpu/pps4/pps4.c
+++ b/src/emu/cpu/pps4/pps4.c
@@ -571,7 +571,7 @@ void pps4_device::iEXD()
* The 4-bit contents, immediate field I(4:1),
* of the instruction are placed in the accumulator.
*
- * Note: Only the first occurence of an LDI in a consecutive
+ * Note: Only the first occurrence of an LDI in a consecutive
* string of LDIs will be executed. The program will ignore
* remaining LDIs and execute next valid instruction.
*
@@ -815,7 +815,7 @@ void pps4_device::iCYS()
* This instruction takes two cycles to execute but occupies
* only one ROM word. (Automatic return)
*
- * Only the first occurence of an LB or LBL instruction in a
+ * Only the first occurrence of an LB or LBL instruction in a
* consecutive string of LB or LBL will be executed. The
* program will ignore the remaining LB or LBL and execute
* the next valid instruction. Within subroutines the LB
@@ -858,7 +858,7 @@ void pps4_device::iLB()
* bits of the B register. The four most significant bits
* of B (BU) will be loaded with zeroes.
*
- * Only the first occurence of an LB or LBL instruction in a
+ * Only the first occurrence of an LB or LBL instruction in a
* consecutive string of LB or LBL will be executed. The
* program will ignore the remaining LB or LBL and execute
* the next valid instruction.
diff --git a/src/emu/cpu/tms32025/tms32025.c b/src/emu/cpu/tms32025/tms32025.c
index 55f9e2684c8..ded22a8de6c 100644
--- a/src/emu/cpu/tms32025/tms32025.c
+++ b/src/emu/cpu/tms32025/tms32025.c
@@ -1102,7 +1102,7 @@ void tms32025_device::macd() /** RAM blocks B0,B1,B2 may be important !
CALCULATE_ADD_OVERFLOW(m_ALU.d);
CALCULATE_ADD_CARRY();
GETDATA(0, 0);
- if ( (m_opcode.b.l & 0x80) || m_init_load_addr ) { /* No writing during repitition, or DMA mode */
+ if ( (m_opcode.b.l & 0x80) || m_init_load_addr ) { /* No writing during repetition, or DMA mode */
M_WRTRAM((m_memaccess+1), m_ALU.w.l);
}
m_Treg = m_ALU.w.l;
diff --git a/src/emu/cpu/tms9900/99xxcore.h b/src/emu/cpu/tms9900/99xxcore.h
index feaf001f680..2eda0842840 100644
--- a/src/emu/cpu/tms9900/99xxcore.h
+++ b/src/emu/cpu/tms9900/99xxcore.h
@@ -787,7 +787,7 @@ WRITE8_HANDLER(tms9995_internal2_w)
#elif (TMS99XX_MODEL == TMS9900_ID) || (TMS99XX_MODEL == TMS9940_ID)
/*16-bit data bus, 16-bit address bus (internal bus in the case of TMS9940)*/
/*Note that tms9900 actually never accesses a single byte : when performing byte operations,
- it reads a 16-bit word, changes the revelant byte, then write a complete word. You should
+ it reads a 16-bit word, changes the relevant byte, then write a complete word. You should
remember this when writing memory handlers.*/
/*This does not apply to tms9995 and tms99xxx, but does apply to tms9980 (see below).*/
@@ -2342,7 +2342,7 @@ static void tms99xx_set_irq_line(tms99xx_state *cpustate, int irqline, int state
/*
* field_interrupt
*
- * Determines whether if an interrupt is pending, and sets the revelant flag.
+ * Determines whether if an interrupt is pending, and sets the relevant flag.
*
* Called when an interrupt pin (LOAD*, INTREQ*, IC0-IC3) is changed, and when the interrupt mask
* is modified.
@@ -2959,9 +2959,9 @@ static void contextswitch(tms99xx_state *cpustate, UINT16 addr)
#if HAS_MAPPING || HAS_PRIVILEGE
-/* priviledged context switch, that occurs after a reset, interrupt or XOP:
-we enter priviledged mode and select map file 0 before doing the context switch */
-/* For CPU that have no priviledge support, contextswitchX would behave
+/* privileged context switch, that occurs after a reset, interrupt or XOP:
+we enter privileged mode and select map file 0 before doing the context switch */
+/* For CPU that have no privilege support, contextswitchX would behave
identically to contextswitch, so we can call contextswitch in all cases. */
static void contextswitchX(tms99xx_state *cpustate, UINT16 addr)
{
@@ -2973,7 +2973,7 @@ static void contextswitchX(tms99xx_state *cpustate, UINT16 addr)
setstat(cpustate);
oldST = cpustate->STATUS;
- /* enter priviledged mode and select map file 0 */
+ /* enter privileged mode and select map file 0 */
#if HAS_PRIVILEGE
cpustate->STATUS &= ~ ST_PR;
#endif
@@ -4951,7 +4951,7 @@ static void h4000b(tms99xx_state *cpustate, UINT16 opcode)
setst_byte_laep(cpustate, value);
#if (TMS99XX_MODEL <= TMS9985_ID)
/* On ti990/10 and tms9900, MOVB needs to read destination, because it cannot actually
- read one single byte. It reads a word, replaces the revelant byte, then write
+ read one single byte. It reads a word, replaces the relevant byte, then write
the result. A tms9980 should not need to do so, but still does, because it is just
a tms9900 with a 16 to 8 bit multiplexer (instead of a new chip design, like tms9995). */
(void)readbyteX(cpustate, dest, dst_map);
diff --git a/src/emu/cpu/tms9900/tms9995.c b/src/emu/cpu/tms9900/tms9995.c
index 2721958075a..ef42dea1252 100644
--- a/src/emu/cpu/tms9900/tms9995.c
+++ b/src/emu/cpu/tms9900/tms9995.c
@@ -1467,7 +1467,7 @@ void tms9995_device::int_prefetch_and_decode()
if (m_idle_state)
{
m_idle_state = false;
- if (TRACE_INT) logerror("tms9995: Interrupt occured, terminate IDLE state\n");
+ if (TRACE_INT) logerror("tms9995: Interrupt occurred, terminate IDLE state\n");
}
PC = PC + 2; // PC must be advanced (see flow chart), but no prefetch
if (TRACE_INT) logerror("tms9995: Interrupts pending; no prefetch; advance PC to %04x\n", PC);