diff options
| author | 2012-11-19 08:40:08 +0000 | |
|---|---|---|
| committer | 2012-11-19 08:40:08 +0000 | |
| commit | 8813fb6bcd7f44f308e0c4350231d536ccd032d6 (patch) | |
| tree | bf50f0b04ee4e4c617773687fa1195981f9dc216 /src/emu/cpu | |
| parent | d60236970a2d1ac8e78e1b108100d9a4ccb33b8c (diff) | |
Cleanups and version bump (nw)mame0147u3
Diffstat (limited to 'src/emu/cpu')
| -rw-r--r-- | src/emu/cpu/avr8/avr8.c | 48 | ||||
| -rw-r--r-- | src/emu/cpu/avr8/avr8.h | 38 | ||||
| -rw-r--r-- | src/emu/cpu/i386/i386.c | 4 | ||||
| -rw-r--r-- | src/emu/cpu/m6502/m4510.c | 2 | ||||
| -rw-r--r-- | src/emu/cpu/m6502/m6502make.c | 2 | ||||
| -rw-r--r-- | src/emu/cpu/m6502/m6510.c | 2 | ||||
| -rw-r--r-- | src/emu/cpu/m6502/om6502.lst | 2 | ||||
| -rw-r--r-- | src/emu/cpu/m6502/om65c02.lst | 8 | ||||
| -rw-r--r-- | src/emu/cpu/m6502/om65ce02.lst | 8 | ||||
| -rw-r--r-- | src/emu/cpu/z8000/z8000ops.c | 32 |
10 files changed, 73 insertions, 73 deletions
diff --git a/src/emu/cpu/avr8/avr8.c b/src/emu/cpu/avr8/avr8.c index df1d88a35f6..71c8c1936a8 100644 --- a/src/emu/cpu/avr8/avr8.c +++ b/src/emu/cpu/avr8/avr8.c @@ -9,25 +9,25 @@ the existing opcodes has been shown to wildly corrupt the video output in Craft, so one can assume that the existing timing is 100% correct. - Unimplemented opcodes: CPSR, LD Z+, ST -Z/-Y/-X, ELPM, SPM, SPM Z+, EIJMP, SLEEP, BREAK, WDR, ICALL, EICALL, - JMP, CALL - - - Changelist - - 30 Oct. 2012 - - Added FMUL, FMULS, FMULSU opcodes [MooglyGuy] - - Fixed incorrect flag calculation in ROR opcode [MooglyGuy] - - Fixed incorrect bit testing in SBIC/SBIS opcodes [MooglyGuy] - - 25 Oct. 2012 - - Added MULS, ANDI, STI Z+, LD -Z, LD -Y, LD -X, LD Y+q, LD Z+q, SWAP, ASR, ROR and SBIS opcodes [MooglyGuy] - - Corrected cycle counts for LD and ST opcodes [MooglyGuy] - - Moved opcycles init into inner while loop, fixes 2-cycle and 3-cycle opcodes effectively forcing - all subsequent 1-cycle opcodes to be 2 or 3 cycles [MooglyGuy] - - Fixed register behavior in MULSU, LD -Z, and LD -Y opcodes [MooglyGuy] - - 18 Oct. 2012 - - Added OR, SBCI, ORI, ST Y+, ADIQ opcodes [MooglyGuy] - - Fixed COM, NEG, LSR opcodes [MooglyGuy] + Unimplemented opcodes: CPSR, LD Z+, ST -Z/-Y/-X, ELPM, SPM, SPM Z+, EIJMP, SLEEP, BREAK, WDR, ICALL, EICALL, + JMP, CALL + + - Changelist - + 30 Oct. 2012 + - Added FMUL, FMULS, FMULSU opcodes [MooglyGuy] + - Fixed incorrect flag calculation in ROR opcode [MooglyGuy] + - Fixed incorrect bit testing in SBIC/SBIS opcodes [MooglyGuy] + + 25 Oct. 2012 + - Added MULS, ANDI, STI Z+, LD -Z, LD -Y, LD -X, LD Y+q, LD Z+q, SWAP, ASR, ROR and SBIS opcodes [MooglyGuy] + - Corrected cycle counts for LD and ST opcodes [MooglyGuy] + - Moved opcycles init into inner while loop, fixes 2-cycle and 3-cycle opcodes effectively forcing + all subsequent 1-cycle opcodes to be 2 or 3 cycles [MooglyGuy] + - Fixed register behavior in MULSU, LD -Z, and LD -Y opcodes [MooglyGuy] + + 18 Oct. 2012 + - Added OR, SBCI, ORI, ST Y+, ADIQ opcodes [MooglyGuy] + - Fixed COM, NEG, LSR opcodes [MooglyGuy] */ @@ -783,7 +783,7 @@ void avr8_device::timer0_tick() //UINT8 compare_mode[2] = { (m_r[AVR8_REGIDX_TCCR0A] & AVR8_TCCR0A_COM0A_MASK) >> AVR8_TCCR0A_COM0A_SHIFT, //(m_r[AVR8_REGIDX_TCCR0A] & AVR8_TCCR0A_COM0B_MASK) >> AVR8_TCCR0A_COM0B_SHIFT }; UINT8 ocr0[2] = { m_r[AVR8_REGIDX_OCR0A], m_r[AVR8_REGIDX_OCR0B] }; - UINT8 ocf0[2] = { (1 << AVR8_TIFR0_OCF0A_SHIFT), (1 << AVR8_TIFR0_OCF0B_SHIFT) }; + UINT8 ocf0[2] = { (1 << AVR8_TIFR0_OCF0A_SHIFT), (1 << AVR8_TIFR0_OCF0B_SHIFT) }; INT32 increment = m_timer0_increment; for(INT32 reg = AVR8_REG_A; reg <= AVR8_REG_B; reg++) @@ -854,9 +854,9 @@ void avr8_device::timer0_tick() m_r[AVR8_REGIDX_TCNT0] = count + increment; - update_interrupt(AVR8_INTIDX_OCF0A); - update_interrupt(AVR8_INTIDX_OCF0B); - update_interrupt(AVR8_INTIDX_TOV0); + update_interrupt(AVR8_INTIDX_OCF0A); + update_interrupt(AVR8_INTIDX_OCF0B); + update_interrupt(AVR8_INTIDX_TOV0); */ } @@ -1054,7 +1054,7 @@ void avr8_device::timer1_tick() break; default: - verboselog(m_pc, 0, "update_timer1_compare_mode: Unknown waveform generation mode: %02x\n", wgm1); + verboselog(m_pc, 0, "update_timer1_compare_mode: Unknown waveform generation mode: %02x\n", wgm1); break; } /* diff --git a/src/emu/cpu/avr8/avr8.h b/src/emu/cpu/avr8/avr8.h index df33de0715e..a1509641d37 100644 --- a/src/emu/cpu/avr8/avr8.h +++ b/src/emu/cpu/avr8/avr8.h @@ -9,25 +9,25 @@ the existing opcodes has been shown to wildly corrupt the video output in Craft, so one can assume that the existing timing is 100% correct. - Unimplemented opcodes: CPSR, LD Z+, ST Z+, ST -Z/-Y/-X, ELPM, SPM, SPM Z+, EIJMP, SLEEP, BREAK, WDR, ICALL, - EICALL, JMP, CALL, SBIW - - - Changelist - - 30 Oct. 2012 - - Added FMUL, FMULS, FMULSU opcodes [MooglyGuy] - - Fixed incorrect flag calculation in ROR opcode [MooglyGuy] - - Fixed incorrect bit testing in SBIC/SBIS opcodes [MooglyGuy] - - 25 Oct. 2012 - - Added MULS, ANDI, STI Z+, LD -Z, LD -Y, LD -X, LD Y+q, LD Z+q, SWAP, ASR, ROR and SBIS opcodes [MooglyGuy] - - Corrected cycle counts for LD and ST opcodes [MooglyGuy] - - Moved opcycles init into inner while loop, fixes 2-cycle and 3-cycle opcodes effectively forcing - all subsequent 1-cycle opcodes to be 2 or 3 cycles [MooglyGuy] - - Fixed register behavior in MULSU, LD -Z, and LD -Y opcodes [MooglyGuy] - - 18 Oct. 2012 - - Added OR, SBCI, ORI, ST Y+, ADIQ opcodes [MooglyGuy] - - Fixed COM, NEG, LSR opcodes [MooglyGuy] + Unimplemented opcodes: CPSR, LD Z+, ST Z+, ST -Z/-Y/-X, ELPM, SPM, SPM Z+, EIJMP, SLEEP, BREAK, WDR, ICALL, + EICALL, JMP, CALL, SBIW + + - Changelist - + 30 Oct. 2012 + - Added FMUL, FMULS, FMULSU opcodes [MooglyGuy] + - Fixed incorrect flag calculation in ROR opcode [MooglyGuy] + - Fixed incorrect bit testing in SBIC/SBIS opcodes [MooglyGuy] + + 25 Oct. 2012 + - Added MULS, ANDI, STI Z+, LD -Z, LD -Y, LD -X, LD Y+q, LD Z+q, SWAP, ASR, ROR and SBIS opcodes [MooglyGuy] + - Corrected cycle counts for LD and ST opcodes [MooglyGuy] + - Moved opcycles init into inner while loop, fixes 2-cycle and 3-cycle opcodes effectively forcing + all subsequent 1-cycle opcodes to be 2 or 3 cycles [MooglyGuy] + - Fixed register behavior in MULSU, LD -Z, and LD -Y opcodes [MooglyGuy] + + 18 Oct. 2012 + - Added OR, SBCI, ORI, ST Y+, ADIQ opcodes [MooglyGuy] + - Fixed COM, NEG, LSR opcodes [MooglyGuy] */ diff --git a/src/emu/cpu/i386/i386.c b/src/emu/cpu/i386/i386.c index 2e424362551..77487b61f9a 100644 --- a/src/emu/cpu/i386/i386.c +++ b/src/emu/cpu/i386/i386.c @@ -2831,7 +2831,7 @@ static UINT32 i386_get_debug_desc(i386_state *cpustate, I386_SREG *seg) entry = seg->selector & ~0x7; if (limit == 0 || entry + 7 > limit) return 0; - + address = entry + base; // todo: bigendian @@ -2910,7 +2910,7 @@ static UINT64 i386_debug_segofftovirt(symbol_table &table, void *ref, int params if(param[0] > 65535) return 0; - + if (PROTECTED_MODE && !V8086_MODE) { memset(&seg, 0, sizeof(seg)); diff --git a/src/emu/cpu/m6502/m4510.c b/src/emu/cpu/m6502/m4510.c index 96a2603fffc..c9b7bda9bd1 100644 --- a/src/emu/cpu/m6502/m4510.c +++ b/src/emu/cpu/m6502/m4510.c @@ -57,7 +57,7 @@ offs_t m4510_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *op void m4510_device::device_start() { - if(direct_disabled) + if(direct_disabled) mintf = new mi_4510_nd(this); else mintf = new mi_4510_normal(this); diff --git a/src/emu/cpu/m6502/m6502make.c b/src/emu/cpu/m6502/m6502make.c index 8e71e0b1181..918c98518af 100644 --- a/src/emu/cpu/m6502/m6502make.c +++ b/src/emu/cpu/m6502/m6502make.c @@ -211,7 +211,7 @@ static void save_tables(FILE *f) opc = string(opcode.begin(), k); fullopc = string(opcode.begin(), ke-1); mode = string(ke, opcode.end()); - + bool step_over = opc == "jsr" || opc == "bsr"; bool step_out = opc == "rts" || opc == "rti" || opc == "rtn"; fprintf(f, "\t{ \"%s\", DASM_%s, %s },\n", diff --git a/src/emu/cpu/m6502/m6510.c b/src/emu/cpu/m6502/m6510.c index 1121392e61b..cb28946e3f6 100644 --- a/src/emu/cpu/m6502/m6510.c +++ b/src/emu/cpu/m6502/m6510.c @@ -76,7 +76,7 @@ void m6510_device::device_start() read_port.resolve_safe(0); write_port.resolve_safe(); - if(direct_disabled) + if(direct_disabled) mintf = new mi_6510_nd(this); else mintf = new mi_6510_normal(this); diff --git a/src/emu/cpu/m6502/om6502.lst b/src/emu/cpu/m6502/om6502.lst index a40800d42c6..b8143a5279f 100644 --- a/src/emu/cpu/m6502/om6502.lst +++ b/src/emu/cpu/m6502/om6502.lst @@ -1962,4 +1962,4 @@ kil_non read(0xfffe); for(;;) { read(0xffff); - } + } diff --git a/src/emu/cpu/m6502/om65c02.lst b/src/emu/cpu/m6502/om65c02.lst index e1292eadfec..700b529624e 100644 --- a/src/emu/cpu/m6502/om65c02.lst +++ b/src/emu/cpu/m6502/om65c02.lst @@ -533,7 +533,7 @@ trb_aba if(A & TMP2) P &= ~F_Z; else - P |= F_Z; + P |= F_Z; TMP2 &= ~A; write(TMP, TMP2); prefetch(); @@ -545,7 +545,7 @@ trb_zpg if(A & TMP2) P &= ~F_Z; else - P |= F_Z; + P |= F_Z; TMP2 &= ~A; write(TMP, TMP2); prefetch(); @@ -558,7 +558,7 @@ tsb_aba if(A & TMP2) P &= ~F_Z; else - P |= F_Z; + P |= F_Z; TMP2 |= A; write(TMP, TMP2); prefetch(); @@ -570,7 +570,7 @@ tsb_zpg if(A & TMP2) P &= ~F_Z; else - P |= F_Z; + P |= F_Z; TMP2 |= A; write(TMP, TMP2); prefetch(); diff --git a/src/emu/cpu/m6502/om65ce02.lst b/src/emu/cpu/m6502/om65ce02.lst index 2c59ffb01dc..742f4fb0ede 100644 --- a/src/emu/cpu/m6502/om65ce02.lst +++ b/src/emu/cpu/m6502/om65ce02.lst @@ -1459,7 +1459,7 @@ trb_ce_aba if(A & TMP2) P &= ~F_Z; else - P |= F_Z; + P |= F_Z; TMP2 &= ~A; write(TMP, TMP2); prefetch(); @@ -1470,7 +1470,7 @@ trb_ce_zpg if(A & TMP2) P &= ~F_Z; else - P |= F_Z; + P |= F_Z; TMP2 &= ~A; write(TMP, TMP2); prefetch(); @@ -1482,7 +1482,7 @@ tsb_ce_aba if(A & TMP2) P &= ~F_Z; else - P |= F_Z; + P |= F_Z; TMP2 |= A; write(TMP, TMP2); prefetch(); @@ -1493,7 +1493,7 @@ tsb_ce_zpg if(A & TMP2) P &= ~F_Z; else - P |= F_Z; + P |= F_Z; TMP2 |= A; write(TMP, TMP2); prefetch(); diff --git a/src/emu/cpu/z8000/z8000ops.c b/src/emu/cpu/z8000/z8000ops.c index 25561e5abc4..da5858d5a96 100644 --- a/src/emu/cpu/z8000/z8000ops.c +++ b/src/emu/cpu/z8000/z8000ops.c @@ -5829,8 +5829,8 @@ static void ZB7_ssss_dddd(z8000_state *cpustate) } /****************************************** - trtib @rd,@rs,rr - flags: -ZSV-- + trtib @rd,@rs,rr + flags: -ZSV-- ******************************************/ static void ZB8_ddN0_0010_0000_rrrr_ssN0_0000(z8000_state *cpustate) { @@ -5845,8 +5845,8 @@ static void ZB8_ddN0_0010_0000_rrrr_ssN0_0000(z8000_state *cpustate) } /****************************************** - trtirb @rd,@rs,rbr - flags: -ZSV-- + trtirb @rd,@rs,rbr + flags: -ZSV-- ******************************************/ static void ZB8_ddN0_0110_0000_rrrr_ssN0_1110(z8000_state *cpustate) { @@ -5866,8 +5866,8 @@ static void ZB8_ddN0_0110_0000_rrrr_ssN0_1110(z8000_state *cpustate) } /****************************************** - trtdb @rd,@rs,rbr - flags: -ZSV-- + trtdb @rd,@rs,rbr + flags: -ZSV-- ******************************************/ static void ZB8_ddN0_1010_0000_rrrr_ssN0_0000(z8000_state *cpustate) { @@ -5882,8 +5882,8 @@ static void ZB8_ddN0_1010_0000_rrrr_ssN0_0000(z8000_state *cpustate) } /****************************************** - trtdrb @rd,@rs,rbr - flags: -ZSV-- + trtdrb @rd,@rs,rbr + flags: -ZSV-- ******************************************/ static void ZB8_ddN0_1110_0000_rrrr_ssN0_1110(z8000_state *cpustate) { @@ -5903,8 +5903,8 @@ static void ZB8_ddN0_1110_0000_rrrr_ssN0_1110(z8000_state *cpustate) } /****************************************** - trib @rd,@rs,rbr - flags: -ZSV-- + trib @rd,@rs,rbr + flags: -ZSV-- ******************************************/ static void ZB8_ddN0_0000_0000_rrrr_ssN0_0000(z8000_state *cpustate) { @@ -5919,8 +5919,8 @@ static void ZB8_ddN0_0000_0000_rrrr_ssN0_0000(z8000_state *cpustate) } /****************************************** - trirb @rd,@rs,rbr - flags: -ZSV-- + trirb @rd,@rs,rbr + flags: -ZSV-- ******************************************/ static void ZB8_ddN0_0100_0000_rrrr_ssN0_0000(z8000_state *cpustate) { @@ -5935,8 +5935,8 @@ static void ZB8_ddN0_0100_0000_rrrr_ssN0_0000(z8000_state *cpustate) } /****************************************** - trdb @rd,@rs,rbr - flags: -ZSV-- + trdb @rd,@rs,rbr + flags: -ZSV-- ******************************************/ static void ZB8_ddN0_1000_0000_rrrr_ssN0_0000(z8000_state *cpustate) { @@ -5951,8 +5951,8 @@ static void ZB8_ddN0_1000_0000_rrrr_ssN0_0000(z8000_state *cpustate) } /****************************************** - trdrb @rd,@rs,rbr - flags: -ZSV-- + trdrb @rd,@rs,rbr + flags: -ZSV-- ******************************************/ static void ZB8_ddN0_1100_0000_rrrr_ssN0_0000(z8000_state *cpustate) { |
