diff options
author | 2009-01-14 06:10:30 +0000 | |
---|---|---|
committer | 2009-01-14 06:10:30 +0000 | |
commit | 2a780fc07d40ec3cded1f4320e4daca5d9d37b24 (patch) | |
tree | 801f20a62affe3e5aad1aed4c4db62a7f4aa1de4 /src/emu/cpu | |
parent | 62bddb4fe6de8a4b8a14c247aaa2689dba25b6f4 (diff) |
From: Oliver Stoeneberg [mailto:oliverst@online.de]
Sent: Sunday, January 11, 2009 5:52 AM
To: submit@mamedev.org
Subject: unreachable code cleanup
This patch cleans up the usage of unreachable code (mostly
unnecessary breaks after returns in switch - case). A few case of
really unused code were also discovered. I marked thos with FIXME
comments.
I based this cleanup on teh output of cppcheck. It does still missing
a few cases of unreachable code, so there might be future patches to
address more cases.
Diffstat (limited to 'src/emu/cpu')
-rw-r--r-- | src/emu/cpu/arm/arm.c | 1 | ||||
-rw-r--r-- | src/emu/cpu/dsp56k/dsp56dsm.c | 6 | ||||
-rw-r--r-- | src/emu/cpu/dsp56k/dsp56mem.c | 5 | ||||
-rw-r--r-- | src/emu/cpu/dsp56k/dsp56ops.c | 4 | ||||
-rw-r--r-- | src/emu/cpu/h6280/h6280.c | 4 | ||||
-rw-r--r-- | src/emu/cpu/hd6309/6309ops.c | 16 | ||||
-rw-r--r-- | src/emu/cpu/m37710/m37710.c | 38 | ||||
-rw-r--r-- | src/emu/cpu/m37710/m37710op.h | 1 | ||||
-rw-r--r-- | src/emu/cpu/mb86233/mb86233.c | 19 | ||||
-rw-r--r-- | src/emu/cpu/se3208/se3208.c | 1 | ||||
-rw-r--r-- | src/emu/cpu/se3208/se3208dis.c | 1 | ||||
-rw-r--r-- | src/emu/cpu/sh2/sh2drc.c | 147 | ||||
-rw-r--r-- | src/emu/cpu/sh2/sh2fe.c | 94 | ||||
-rw-r--r-- | src/emu/cpu/tms9900/9900dasm.c | 3 | ||||
-rw-r--r-- | src/emu/cpu/v60/am1.c | 3 |
15 files changed, 16 insertions, 327 deletions
diff --git a/src/emu/cpu/arm/arm.c b/src/emu/cpu/arm/arm.c index f9bce799cc5..6246f8db31c 100644 --- a/src/emu/cpu/arm/arm.c +++ b/src/emu/cpu/arm/arm.c @@ -1200,7 +1200,6 @@ static UINT32 decodeShift( ARM_REGS* cpustate, UINT32 insn, UINT32 *pCarry) *pCarry = k ? (rm & (1 << (32 - k))) : (R15 & C_MASK); } return k ? LSL(rm, k) : rm; - break; case 1: /* LSR */ if (k == 0 || k == 32) diff --git a/src/emu/cpu/dsp56k/dsp56dsm.c b/src/emu/cpu/dsp56k/dsp56dsm.c index 6ba798a8e3f..7173b517acf 100644 --- a/src/emu/cpu/dsp56k/dsp56dsm.c +++ b/src/emu/cpu/dsp56k/dsp56dsm.c @@ -2659,9 +2659,9 @@ static int decode_BBB_table(UINT16 BBB) { switch(BBB) { - case 0x4: return BBB_UPPER ; break; - case 0x2: return BBB_MIDDLE; break; - case 0x1: return BBB_LOWER ; break; + case 0x4: return BBB_UPPER; + case 0x2: return BBB_MIDDLE; + case 0x1: return BBB_LOWER; } return BBB_LOWER; /* Not really safe... */ diff --git a/src/emu/cpu/dsp56k/dsp56mem.c b/src/emu/cpu/dsp56k/dsp56mem.c index 695dc7149bb..b3375aaaf06 100644 --- a/src/emu/cpu/dsp56k/dsp56mem.c +++ b/src/emu/cpu/dsp56k/dsp56mem.c @@ -721,27 +721,22 @@ UINT8 dsp56k_host_interface_read(device_config* device, UINT8 offset) // Interrupt Control Register (ICR) case 0x00: return ICR; - break; // Command Vector Register (CVR) case 0x01: return CVR; - break; // Interrupt status register (ISR) case 0x02: return ISR; - break; // Interrupt vector register (IVR) case 0x03: return IVR; - break; // Read zeroes case 0x04: return 0x00; - break; // Reserved case 0x05: diff --git a/src/emu/cpu/dsp56k/dsp56ops.c b/src/emu/cpu/dsp56k/dsp56ops.c index 167f8f287fe..fd8d25abdcd 100644 --- a/src/emu/cpu/dsp56k/dsp56ops.c +++ b/src/emu/cpu/dsp56k/dsp56ops.c @@ -4345,8 +4345,8 @@ static UINT16 execute_q_table(dsp56k_core* cpustate, int RR, UINT16 q) switch(q) { - case 0x0: /* No permanent changes */ ; return (*rX)+(*nX); break; - case 0x1: (*rX)--; return (*rX); break; // This one is special - it's a *PRE-decrement*! + case 0x0: /* No permanent changes */ ; return (*rX)+(*nX); + case 0x1: (*rX)--; return (*rX); // This one is special - it's a *PRE-decrement*! } /* Should not get here */ diff --git a/src/emu/cpu/h6280/h6280.c b/src/emu/cpu/h6280/h6280.c index 4cb2af5db97..57a7ca0a867 100644 --- a/src/emu/cpu/h6280/h6280.c +++ b/src/emu/cpu/h6280/h6280.c @@ -289,7 +289,7 @@ READ8_HANDLER( h6280_irq_status_r ) switch (offset&3) { - default: return cpustate->io_buffer; break; + default: return cpustate->io_buffer; case 3: { status=0; @@ -298,7 +298,7 @@ READ8_HANDLER( h6280_irq_status_r ) if(cpustate->irq_state[2]!=CLEAR_LINE) status|=4; /* TIMER */ return status|(cpustate->io_buffer&(~H6280_IRQ_MASK)); } - case 2: return cpustate->irq_mask|(cpustate->io_buffer&(~H6280_IRQ_MASK));break; + case 2: return cpustate->irq_mask|(cpustate->io_buffer&(~H6280_IRQ_MASK)); } } diff --git a/src/emu/cpu/hd6309/6309ops.c b/src/emu/cpu/hd6309/6309ops.c index 5cd2c921099..85b336159ca 100644 --- a/src/emu/cpu/hd6309/6309ops.c +++ b/src/emu/cpu/hd6309/6309ops.c @@ -945,7 +945,7 @@ OP_HANDLER( tfmpp ) case 2: srcValue = RM(Y++); break; case 3: srcValue = RM(U++); break; case 4: srcValue = RM(S++); break; - default: IIError(m68_state); return; break; /* reg PC thru F */ + default: IIError(m68_state); return; /* reg PC thru F */ } switch(tb&15) { @@ -954,7 +954,7 @@ OP_HANDLER( tfmpp ) case 2: WM(Y++, srcValue); break; case 3: WM(U++, srcValue); break; case 4: WM(S++, srcValue); break; - default: IIError(m68_state); return; break; /* reg PC thru F */ + default: IIError(m68_state); return; /* reg PC thru F */ } PCD = PCD - 3; @@ -979,7 +979,7 @@ OP_HANDLER( tfmmm ) case 2: srcValue = RM(Y--); break; case 3: srcValue = RM(U--); break; case 4: srcValue = RM(S--); break; - default: IIError(m68_state); return; break; /* reg PC thru F */ + default: IIError(m68_state); return; /* reg PC thru F */ } switch(tb&15) { @@ -988,7 +988,7 @@ OP_HANDLER( tfmmm ) case 2: WM(Y--, srcValue); break; case 3: WM(U--, srcValue); break; case 4: WM(S--, srcValue); break; - default: IIError(m68_state); return; break; /* reg PC thru F */ + default: IIError(m68_state); return; /* reg PC thru F */ } PCD = PCD - 3; @@ -1013,7 +1013,7 @@ OP_HANDLER( tfmpc ) case 2: srcValue = RM(Y++); break; case 3: srcValue = RM(U++); break; case 4: srcValue = RM(S++); break; - default: IIError(m68_state); return; break; /* reg PC thru F */ + default: IIError(m68_state); return; /* reg PC thru F */ } switch(tb&15) { @@ -1022,7 +1022,7 @@ OP_HANDLER( tfmpc ) case 2: WM(Y, srcValue); break; case 3: WM(U, srcValue); break; case 4: WM(S, srcValue); break; - default: IIError(m68_state); return; break; /* reg PC thru F */ + default: IIError(m68_state); return; /* reg PC thru F */ } PCD = PCD - 3; @@ -1047,7 +1047,7 @@ OP_HANDLER( tfmcp ) case 2: srcValue = RM(Y); break; case 3: srcValue = RM(U); break; case 4: srcValue = RM(S); break; - default: IIError(m68_state); return; break; /* reg PC thru F */ + default: IIError(m68_state); return; /* reg PC thru F */ } switch(tb&15) { @@ -1056,7 +1056,7 @@ OP_HANDLER( tfmcp ) case 2: WM(Y++, srcValue); break; case 3: WM(U++, srcValue); break; case 4: WM(S++, srcValue); break; - default: IIError(m68_state); return; break; /* reg PC thru F */ + default: IIError(m68_state); return; /* reg PC thru F */ } PCD = PCD - 3; diff --git a/src/emu/cpu/m37710/m37710.c b/src/emu/cpu/m37710/m37710.c index 012289ce5c2..67e3f4e44d9 100644 --- a/src/emu/cpu/m37710/m37710.c +++ b/src/emu/cpu/m37710/m37710.c @@ -404,87 +404,60 @@ static UINT8 m37710_internal_r(m37710i_cpu_struct *cpustate, int offset) { case 2: // p0 return memory_read_byte_8le(cpustate->io, M37710_PORT0); - break; case 3: // p1 return memory_read_byte_8le(cpustate->io, M37710_PORT1); - break; case 6: // p2 return memory_read_byte_8le(cpustate->io, M37710_PORT2); - break; case 7: // p3 return memory_read_byte_8le(cpustate->io, M37710_PORT3); - break; case 0xa: // p4 return memory_read_byte_8le(cpustate->io, M37710_PORT4); - break; case 0xb: // p5 return memory_read_byte_8le(cpustate->io, M37710_PORT5); - break; case 0xe: // p6 return memory_read_byte_8le(cpustate->io, M37710_PORT6); - break; case 0xf: // p7 return memory_read_byte_8le(cpustate->io, M37710_PORT7); - break; case 0x12: // p8 return memory_read_byte_8le(cpustate->io, M37710_PORT8); - break; case 0x20: return memory_read_byte_8le(cpustate->io, M37710_ADC0_L); - break; case 0x21: return memory_read_byte_8le(cpustate->io, M37710_ADC0_H); - break; case 0x22: return memory_read_byte_8le(cpustate->io, M37710_ADC1_L); - break; case 0x23: return memory_read_byte_8le(cpustate->io, M37710_ADC1_H); - break; case 0x24: return memory_read_byte_8le(cpustate->io, M37710_ADC2_L); - break; case 0x25: return memory_read_byte_8le(cpustate->io, M37710_ADC2_H); - break; case 0x26: return memory_read_byte_8le(cpustate->io, M37710_ADC3_L); - break; case 0x27: return memory_read_byte_8le(cpustate->io, M37710_ADC3_H); - break; case 0x28: return memory_read_byte_8le(cpustate->io, M37710_ADC4_L); - break; case 0x29: return memory_read_byte_8le(cpustate->io, M37710_ADC4_H); - break; case 0x2a: return memory_read_byte_8le(cpustate->io, M37710_ADC5_L); - break; case 0x2b: return memory_read_byte_8le(cpustate->io, M37710_ADC5_H); - break; case 0x2c: return memory_read_byte_8le(cpustate->io, M37710_ADC6_L); - break; case 0x2d: return memory_read_byte_8le(cpustate->io, M37710_ADC6_H); - break; case 0x2e: return memory_read_byte_8le(cpustate->io, M37710_ADC7_L); - break; case 0x2f: return memory_read_byte_8le(cpustate->io, M37710_ADC7_H); - break; case 0x35: return 0xff; // UART control - break; case 0x70: // A/D IRQ control return cpustate->m37710_regs[offset] | 8; - break; } return cpustate->m37710_regs[offset]; @@ -499,39 +472,30 @@ static void m37710_internal_w(m37710i_cpu_struct *cpustate, int offset, UINT8 da case 2: // p0 memory_write_byte_8le(cpustate->io, M37710_PORT0, data); return; - break; case 3: // p1 memory_write_byte_8le(cpustate->io, M37710_PORT1, data); return; - break; case 6: // p2 memory_write_byte_8le(cpustate->io, M37710_PORT2, data); return; - break; case 7: // p3 memory_write_byte_8le(cpustate->io, M37710_PORT3, data); return; - break; case 0xa: // p4 memory_write_byte_8le(cpustate->io, M37710_PORT4, data); return; - break; case 0xb: // p5 memory_write_byte_8le(cpustate->io, M37710_PORT5, data); return; - break; case 0xe: // p6 memory_write_byte_8le(cpustate->io, M37710_PORT6, data); return; - break; case 0xf: // p7 memory_write_byte_8le(cpustate->io, M37710_PORT7, data); return; - break; case 0x12: // p8 memory_write_byte_8le(cpustate->io, M37710_PORT8, data); return; - break; case 0x40: // count start for (i = 0; i < 8; i++) @@ -546,11 +510,9 @@ static void m37710_internal_w(m37710i_cpu_struct *cpustate, int offset, UINT8 da cpustate->m37710_regs[offset] = data; return; - break; case 0x60: // watchdog reset return; - break; } cpustate->m37710_regs[offset] = data; diff --git a/src/emu/cpu/m37710/m37710op.h b/src/emu/cpu/m37710/m37710op.h index 5e84c6ceba6..22d901c557e 100644 --- a/src/emu/cpu/m37710/m37710op.h +++ b/src/emu/cpu/m37710/m37710op.h @@ -2862,7 +2862,6 @@ TABLE_FUNCTION(void, set_line, (m37710i_cpu_struct *cpustate, int line, int stat cpustate->m37710_regs[m37710_irq_levels[line]] |= 8; } return; - break; case ASSERT_LINE: case PULSE_LINE: case HOLD_LINE: diff --git a/src/emu/cpu/mb86233/mb86233.c b/src/emu/cpu/mb86233/mb86233.c index abe4e2bf65a..102df4b1434 100644 --- a/src/emu/cpu/mb86233/mb86233.c +++ b/src/emu/cpu/mb86233/mb86233.c @@ -204,7 +204,6 @@ static int COND( mb86233_state *cpustate, UINT32 cond ) case 0x16: /* always */ return 1; - break; default: logerror( "TGP: Unknown condition code (cc=%d) at PC:%x\n", cond, GETPC()); @@ -594,60 +593,46 @@ static UINT32 GETREGS( mb86233_state *cpustate, UINT32 reg, int source ) { case 0x10: /* A */ return GETA().u; - break; case 0x11: /* A.e */ return (GETA().u >> 23) & 0xff; - break; case 0x12: /* A.m */ return (GETA().u & 0x7fffff) | ((GETA().u&0x80000000) >> 8); - break; case 0x13: /* B */ return GETB().u; - break; case 0x14: /* B.e */ return (GETB().u >> 23) & 0xff; - break; case 0x15: /* B.m */ return (GETB().u & 0x7fffff) | ((GETB().u&0x80000000) >> 8); - break; case 0x19: /* D */ return GETD().u; - break; case 0x1A: /* D.e */ return (GETD().u >> 23) & 0xff; - break; case 0x1B: /* D.m */ return (GETD().u & 0x7fffff) | ((GETD().u&0x80000000) >> 8); - break; case 0x1C: /* P */ return GETP().u; - break; case 0x1D: /* P.e */ return (GETP().u >> 23) & 0xff; - break; case 0x1E: /* P.m */ return (GETP().u & 0x7fffff) | ((GETP().u&0x80000000) >> 8); - break; case 0x1F: /* Shift */ return GETSHIFT(); - break; case 0x20: /* Parallel Port */ logerror( "TGP: Parallel port read at PC:%04x\n", GETPC() ); return 0; - break; case 0x21: /* FIn */ { @@ -664,19 +649,15 @@ static UINT32 GETREGS( mb86233_state *cpustate, UINT32 reg, int source ) GETFIFOWAIT() = 1; return 0; } - break; case 0x22: /* FOut */ return 0; - break; case 0x23: /* EB */ return GETEB(); - break; case 0x34: return GETREPCNT(); - break; default: logerror( "TGP: Unknown GETREG (%d) at PC=%04x\n", reg, GETPC() ); diff --git a/src/emu/cpu/se3208/se3208.c b/src/emu/cpu/se3208/se3208.c index c9f5cc23a5b..d033df93958 100644 --- a/src/emu/cpu/se3208/se3208.c +++ b/src/emu/cpu/se3208/se3208.c @@ -1464,7 +1464,6 @@ static _OP DecodeOp(UINT16 Opcode) break; case 0x1: return LERI; - break; case 0x2: { switch(EXTRACT(Opcode,11,13)) diff --git a/src/emu/cpu/se3208/se3208dis.c b/src/emu/cpu/se3208/se3208dis.c index 8bff0d59470..66563ffcf5a 100644 --- a/src/emu/cpu/se3208/se3208dis.c +++ b/src/emu/cpu/se3208/se3208dis.c @@ -1171,7 +1171,6 @@ static _OP DecodeOp(UINT16 Opcode) break; case 0x1: return LERI; - break; case 0x2: { switch(EXTRACT(Opcode,11,13)) diff --git a/src/emu/cpu/sh2/sh2drc.c b/src/emu/cpu/sh2/sh2drc.c index 386399d92a5..5b4b1f022c6 100644 --- a/src/emu/cpu/sh2/sh2drc.c +++ b/src/emu/cpu/sh2/sh2drc.c @@ -1661,7 +1661,6 @@ static int generate_opcode(SH2 *sh2, drcuml_block *block, compiler_state *compil { case 0: return generate_group_0(sh2, block, compiler, desc, opcode, in_delay_slot); - break; case 1: // MOVLS4 scratch = (opcode & 0x0f) * 4; @@ -1673,17 +1672,13 @@ static int generate_opcode(SH2 *sh2, drcuml_block *block, compiler_state *compil if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 2: return generate_group_2(sh2, block, compiler, desc, opcode, in_delay_slot); - break; case 3: return generate_group_3(sh2, block, compiler, desc, opcode); - break; case 4: return generate_group_4(sh2, block, compiler, desc, opcode, in_delay_slot); - break; case 5: // MOVLL4 scratch = (opcode & 0x0f) * 4; @@ -1695,22 +1690,18 @@ static int generate_opcode(SH2 *sh2, drcuml_block *block, compiler_state *compil if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 6: return generate_group_6(sh2, block, compiler, desc, opcode, in_delay_slot); - break; case 7: // ADDI scratch = opcode & 0xff; scratch2 = (UINT32)(INT32)(INT16)(INT8)scratch; UML_ADD(block, R32(Rn), R32(Rn), IMM(scratch2)); // add Rn, Rn, scratch2 return TRUE; - break; case 8: return generate_group_8(sh2, block, compiler, desc, opcode, in_delay_slot); - break; case 9: // MOVWI scratch = (desc->pc + 2) + ((opcode & 0xff) * 2) + 2; @@ -1731,7 +1722,6 @@ static int generate_opcode(SH2 *sh2, drcuml_block *block, compiler_state *compil if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 10: // BRA generate_delay_slot(sh2, block, compiler, desc); @@ -1743,7 +1733,6 @@ static int generate_opcode(SH2 *sh2, drcuml_block *block, compiler_state *compil generate_update_cycles(sh2, block, compiler, IMM(sh2->ea), TRUE); // <subtract cycles> UML_HASHJMP(block, IMM(0), IMM(sh2->ea), sh2->nocode); // hashjmp sh2->ea return TRUE; - break; case 11: // BSR // panicstr @ 403da22 relies on the delay slot clobbering the PR set by a BSR, so @@ -1758,11 +1747,9 @@ static int generate_opcode(SH2 *sh2, drcuml_block *block, compiler_state *compil generate_update_cycles(sh2, block, compiler, IMM(sh2->ea), TRUE); // <subtract cycles> UML_HASHJMP(block, IMM(0), IMM(sh2->ea), sh2->nocode); // hashjmp sh2->ea return TRUE; - break; case 12: return generate_group_12(sh2, block, compiler, desc, opcode, in_delay_slot); - break; case 13: // MOVLI scratch = ((desc->pc + 4) & ~3) + ((opcode & 0xff) * 4); @@ -1782,18 +1769,15 @@ static int generate_opcode(SH2 *sh2, drcuml_block *block, compiler_state *compil if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 14: // MOVI scratch = opcode & 0xff; scratch2 = (UINT32)(INT32)(INT16)(INT8)scratch; UML_MOV(block, R32(Rn), IMM(scratch2)); return TRUE; - break; case 15: // NOP return TRUE; - break; } return FALSE; @@ -1820,12 +1804,10 @@ static int generate_group_0(SH2 *sh2, drcuml_block *block, compiler_state *compi case 0x3a: // NOP(); case 0x3b: // NOP(); return TRUE; - break; case 0x02: // STCSR(Rn); UML_MOV(block, R32(Rn), MEM(&sh2->sr)); return TRUE; - break; case 0x03: // BSRF(Rn); if (sh2->cpu_type > CPU_TYPE_SH1) @@ -1855,7 +1837,6 @@ static int generate_group_0(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x05: // MOVWS0(Rm, Rn); case 0x15: // MOVWS0(Rm, Rn); @@ -1869,7 +1850,6 @@ static int generate_group_0(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x06: // MOVLS0(Rm, Rn); case 0x16: // MOVLS0(Rm, Rn); @@ -1882,7 +1862,6 @@ static int generate_group_0(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x07: // MULL(Rm, Rn); case 0x17: // MULL(Rm, Rn); @@ -1898,12 +1877,10 @@ static int generate_group_0(SH2 *sh2, drcuml_block *block, compiler_state *compi case 0x08: // CLRT(); UML_AND(block, MEM(&sh2->sr), MEM(&sh2->sr), IMM(~T)); // and r0, sr, ~T (clear the T bit) return TRUE; - break; case 0x0a: // STSMACH(Rn); UML_MOV(block, R32(Rn), MEM(&sh2->mach)); // mov Rn, mach return TRUE; - break; case 0x0b: // RTS(); UML_MOV(block, MEM(&sh2->target), MEM(&sh2->pr)); // mov target, pr (in case of d-slot shenanigans) @@ -1913,7 +1890,6 @@ static int generate_group_0(SH2 *sh2, drcuml_block *block, compiler_state *compi generate_update_cycles(sh2, block, compiler, MEM(&sh2->target), TRUE); // <subtract cycles> UML_HASHJMP(block, IMM(0), MEM(&sh2->target), sh2->nocode); return TRUE; - break; case 0x0c: // MOVBL0(Rm, Rn); case 0x1c: // MOVBL0(Rm, Rn); @@ -1926,7 +1902,6 @@ static int generate_group_0(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x0d: // MOVWL0(Rm, Rn); case 0x1d: // MOVWL0(Rm, Rn); @@ -1939,7 +1914,6 @@ static int generate_group_0(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x0e: // MOVLL0(Rm, Rn); case 0x1e: // MOVLL0(Rm, Rn); @@ -1952,7 +1926,6 @@ static int generate_group_0(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x0f: // MAC_L(Rm, Rn); case 0x1f: // MAC_L(Rm, Rn); @@ -1971,22 +1944,18 @@ static int generate_group_0(SH2 *sh2, drcuml_block *block, compiler_state *compi case 0x12: // STCGBR(Rn); UML_MOV(block, R32(Rn), MEM(&sh2->gbr)); // mov Rn, gbr return TRUE; - break; case 0x18: // SETT(); UML_OR(block, MEM(&sh2->sr), MEM(&sh2->sr), IMM(T)); // or sr, sr, T return TRUE; - break; case 0x19: // DIV0U(); UML_AND(block, MEM(&sh2->sr), MEM(&sh2->sr), IMM(~(M|Q|T))); // and sr, sr, ~(M|Q|T) return TRUE; - break; case 0x1a: // STSMACL(Rn); UML_MOV(block, R32(Rn), MEM(&sh2->macl)); // mov Rn, macl return TRUE; - break; case 0x1b: // SLEEP(); // inlined special version of generate_update_cycles here @@ -2024,12 +1993,10 @@ static int generate_group_0(SH2 *sh2, drcuml_block *block, compiler_state *compi } return TRUE; - break; case 0x22: // STCVBR(Rn); UML_MOV(block, R32(Rn), MEM(&sh2->vbr)); // mov Rn, vbr return TRUE; - break; case 0x23: // BRAF(Rn); if (sh2->cpu_type > CPU_TYPE_SH1) @@ -2048,17 +2015,14 @@ static int generate_group_0(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_MOV(block, MEM(&sh2->macl), IMM(0)); // mov macl, #0 UML_MOV(block, MEM(&sh2->mach), IMM(0)); // mov mach, #0 return TRUE; - break; case 0x29: // MOVT(Rn); UML_AND(block, R32(Rn), MEM(&sh2->sr), IMM(T)); // and Rn, sr, T return TRUE; - break; case 0x2a: // STSPR(Rn); UML_MOV(block, R32(Rn), MEM(&sh2->pr)); // mov Rn, pr return TRUE; - break; case 0x2b: // RTE(); generate_delay_slot(sh2, block, compiler, desc); @@ -2079,7 +2043,6 @@ static int generate_group_0(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_HASHJMP(block, IMM(0), MEM(&sh2->pc), sh2->nocode); // and jump to the "resume PC" return TRUE; - break; } return FALSE; @@ -2098,7 +2061,6 @@ static int generate_group_2(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 1: // MOVWS(Rm, Rn); UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn @@ -2109,7 +2071,6 @@ static int generate_group_2(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 2: // MOVLS(Rm, Rn); UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn @@ -2119,11 +2080,9 @@ static int generate_group_2(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 3: // NOP(); return TRUE; - break; case 4: // MOVBM(Rm, Rn); UML_MOV(block, IREG(1), R32(Rm)); // mov r1, Rm @@ -2134,7 +2093,6 @@ static int generate_group_2(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 5: // MOVWM(Rm, Rn); UML_MOV(block, IREG(1), R32(Rm)); // mov r1, Rm @@ -2145,7 +2103,6 @@ static int generate_group_2(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 6: // MOVLM(Rm, Rn); UML_MOV(block, IREG(1), R32(Rm)); // mov r1, Rm @@ -2156,7 +2113,6 @@ static int generate_group_2(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 13: // XTRCT(Rm, Rn); UML_SHL(block, IREG(0), R32(Rm), IMM(16)); // shl r0, Rm, #16 @@ -2167,7 +2123,6 @@ static int generate_group_2(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_OR(block, R32(Rn), IREG(0), IREG(1)); // or Rn, r0, r1 return TRUE; - break; case 7: // DIV0S(Rm, Rn); UML_MOV(block, IREG(0), MEM(&sh2->sr)); // move r0, sr @@ -2193,7 +2148,6 @@ static int generate_group_2(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_LABEL(block, compiler->labelnum++); // labelnum: UML_MOV(block, MEM(&sh2->sr), IREG(0)); // mov sr, r0 return TRUE; - break; case 8: // TST(Rm, Rn); UML_AND(block, IREG(0), MEM(&sh2->sr), IMM(~T)); // and r0, sr, ~T (clear the T bit) @@ -2205,7 +2159,6 @@ static int generate_group_2(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_MOV(block, MEM(&sh2->sr), IREG(0)); // mov sh2->sr, r0 return TRUE; - break; case 12: // CMPSTR(Rm, Rn); UML_XOR(block, IREG(0), R32(Rn), R32(Rm)); // xor r0, Rn, Rm (temp) @@ -2237,36 +2190,30 @@ static int generate_group_2(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_LABEL(block, compiler->labelnum++); // labelnum+1: return TRUE; - break; case 9: // AND(Rm, Rn); UML_AND(block, R32(Rn), R32(Rn), R32(Rm)); // and Rn, Rn, Rm return TRUE; - break; case 10: // XOR(Rm, Rn); UML_XOR(block, R32(Rn), R32(Rn), R32(Rm)); // xor Rn, Rn, Rm return TRUE; - break; case 11: // OR(Rm, Rn); UML_OR(block, R32(Rn), R32(Rn), R32(Rm)); // or Rn, Rn, Rm return TRUE; - break; case 14: // MULU(Rm, Rn); UML_AND(block, IREG(0), R32(Rm), IMM(0xffff)); // and r0, Rm, 0xffff UML_AND(block, IREG(1), R32(Rn), IMM(0xffff)); // and r1, Rn, 0xffff UML_MULU(block, MEM(&sh2->macl), MEM(&sh2->ea), IREG(0), IREG(1)); // mulu macl, ea, r0, r1 return TRUE; - break; case 15: // MULS(Rm, Rn); UML_SEXT(block, IREG(0), R32(Rm), WORD); // sext r0, Rm UML_SEXT(block, IREG(1), R32(Rn), WORD); // sext r1, Rn UML_MULS(block, MEM(&sh2->macl), MEM(&sh2->ea), IREG(0), IREG(1)); // muls macl, ea, r0, r1 return TRUE; - break; } return FALSE; @@ -2281,40 +2228,34 @@ static int generate_group_3(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_SETc(block, IF_E, IREG(0)); // set E, r0 UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(1)); // rolins sr, r0, 0, 1 return TRUE; - break; case 2: // CMPHS(Rm, Rn); (unsigned greater than or equal) UML_CMP(block, R32(Rn), R32(Rm)); // cmp Rn, Rm UML_SETc(block, IF_AE, IREG(0)); // set AE, r0 UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(1)); // rolins sr, r0, 0, 1 return TRUE; - break; case 3: // CMPGE(Rm, Rn); (signed greater than or equal) UML_CMP(block, R32(Rn), R32(Rm)); // cmp Rn, Rm UML_SETc(block, IF_GE, IREG(0)); // set GE, r0 UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(1)); // rolins sr, r0, 0, 1 return TRUE; - break; case 6: // CMPHI(Rm, Rn); (unsigned greater than) UML_CMP(block, R32(Rn), R32(Rm)); // cmp Rn, Rm UML_SETc(block, IF_A, IREG(0)); // set A, r0 UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(1)); // rolins sr, r0, 0, 1 return TRUE; - break; case 7: // CMPGT(Rm, Rn); (signed greater than) UML_CMP(block, R32(Rn), R32(Rm)); // cmp Rn, Rm UML_SETc(block, IF_G, IREG(0)); // set G, r0 UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(1)); // rolins sr, r0, 0, 1 return TRUE; - break; case 1: // NOP(); case 9: // NOP(); return TRUE; - break; case 4: // DIV1(Rm, Rn); save_fast_iregs(sh2, block); @@ -2322,7 +2263,6 @@ static int generate_group_3(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_CALLC(block, cfunc_DIV1, sh2); load_fast_iregs(sh2, block); return TRUE; - break; case 5: // DMULU(Rm, Rn); if (sh2->cpu_type > CPU_TYPE_SH1) @@ -2343,12 +2283,10 @@ static int generate_group_3(SH2 *sh2, drcuml_block *block, compiler_state *compi case 8: // SUB(Rm, Rn); UML_SUB(block, R32(Rn), R32(Rn), R32(Rm)); // sub Rn, Rn, Rm return TRUE; - break; case 12: // ADD(Rm, Rn); UML_ADD(block, R32(Rn), R32(Rn), R32(Rm)); // add Rn, Rn, Rm return TRUE; - break; case 10: // SUBC(Rm, Rn); UML_CARRY(block, MEM(&sh2->sr), IMM(0)); // carry = T (T is bit 0 of SR) @@ -2356,7 +2294,6 @@ static int generate_group_3(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_SETc(block, IF_C, IREG(0)); // setc i0, C UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(T)); // rolins sr,i0,0,T return TRUE; - break; case 11: // SUBV(Rm, Rn); #if ADDSUBV_DIRECT @@ -2370,7 +2307,6 @@ static int generate_group_3(SH2 *sh2, drcuml_block *block, compiler_state *compi load_fast_iregs(sh2, block); #endif return TRUE; - break; case 14: // ADDC(Rm, Rn); UML_CARRY(block, MEM(&sh2->sr), IMM(0)); // carry = T (T is bit 0 of SR) @@ -2378,7 +2314,6 @@ static int generate_group_3(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_SETc(block, IF_C, IREG(0)); // setc i0, C UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(T)); // rolins sr,i0,0,T return TRUE; - break; case 15: // ADDV(Rm, Rn); #if ADDSUBV_DIRECT @@ -2392,7 +2327,6 @@ static int generate_group_3(SH2 *sh2, drcuml_block *block, compiler_state *compi load_fast_iregs(sh2, block); #endif return TRUE; - break; } return FALSE; } @@ -2406,28 +2340,24 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_SETc(block, IF_C, IREG(0)); // set i0,C UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(T)); // rolins [sr],i0,0,T return TRUE; - break; case 0x01: // SHLR(Rn); UML_SHR(block, R32(Rn), R32(Rn), IMM(1)); // shr Rn, Rn, 1 UML_SETc(block, IF_C, IREG(0)); // set i0,C UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(T)); // rolins [sr],i0,0,T return TRUE; - break; case 0x04: // ROTL(Rn); UML_ROL(block, R32(Rn), R32(Rn), IMM(1)); // rol Rn, Rn, 1 UML_SETc(block, IF_C, IREG(0)); // set i0,C UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(T)); // rolins [sr],i0,0,T return TRUE; - break; case 0x05: // ROTR(Rn); UML_ROR(block, R32(Rn), R32(Rn), IMM(1)); // ror Rn, Rn, 1 UML_SETc(block, IF_C, IREG(0)); // set i0,C UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(T)); // rolins [sr],i0,0,T return TRUE; - break; case 0x02: // STSMMACH(Rn); UML_SUB(block, R32(Rn), R32(Rn), IMM(4)); // sub Rn, Rn, #4 @@ -2439,7 +2369,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x03: // STCMSR(Rn); UML_SUB(block, R32(Rn), R32(Rn), IMM(4)); // sub Rn, Rn, #4 @@ -2451,7 +2380,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x06: // LDSMMACH(Rn); UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn @@ -2463,7 +2391,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x07: // LDCMSR(Rn); UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn @@ -2476,42 +2403,35 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; + case 0x08: // SHLL2(Rn); UML_SHL(block, R32(Rn), R32(Rn), IMM(2)); return TRUE; - break; case 0x09: // SHLR2(Rn); UML_SHR(block, R32(Rn), R32(Rn), IMM(2)); return TRUE; - break; case 0x18: // SHLL8(Rn); UML_SHL(block, R32(Rn), R32(Rn), IMM(8)); return TRUE; - break; case 0x19: // SHLR8(Rn); UML_SHR(block, R32(Rn), R32(Rn), IMM(8)); return TRUE; - break; case 0x28: // SHLL16(Rn); UML_SHL(block, R32(Rn), R32(Rn), IMM(16)); return TRUE; - break; case 0x29: // SHLR16(Rn); UML_SHR(block, R32(Rn), R32(Rn), IMM(16)); return TRUE; - break; case 0x0a: // LDSMACH(Rn); UML_MOV(block, MEM(&sh2->mach), R32(Rn)); // mov mach, Rn return TRUE; - break; case 0x0b: // JSR(Rn); UML_MOV(block, MEM(&sh2->target), R32(Rn)); // mov target, Rn @@ -2523,7 +2443,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi generate_update_cycles(sh2, block, compiler, MEM(&sh2->target), TRUE); // <subtract cycles> UML_HASHJMP(block, IMM(0), MEM(&sh2->target), sh2->nocode); // and do the jump return TRUE; - break; case 0x0e: // LDCSR(Rn); UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn @@ -2532,7 +2451,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi compiler->checkints = TRUE; return TRUE; - break; case 0x0f: // MAC_W(Rm, Rn); case 0x1f: // MAC_W(Rm, Rn); @@ -2543,7 +2461,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_CALLC(block, cfunc_MAC_W, sh2); load_fast_iregs(sh2, block); return TRUE; - break; case 0x10: // DT(Rn); if (sh2->cpu_type > CPU_TYPE_SH1) @@ -2571,7 +2488,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_MOV(block, MEM(&sh2->sr), IREG(0)); // mov sh2->sr, r0 return TRUE; - break; case 0x15: // CMPPL(Rn); UML_AND(block, IREG(0), MEM(&sh2->sr), IMM(~T)); // and r0, sr, ~T (clear the T bit) @@ -2586,7 +2502,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_LABEL(block, compiler->labelnum++); // desc->pc: UML_MOV(block, MEM(&sh2->sr), IREG(0)); // mov sh2->sr, r0 return TRUE; - break; case 0x12: // STSMMACL(Rn); UML_SUB(block, R32(Rn), R32(Rn), IMM(4)); // sub Rn, Rn, #4 @@ -2598,7 +2513,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x13: // STCMGBR(Rn); UML_SUB(block, R32(Rn), R32(Rn), IMM(4)); // sub Rn, Rn, #4 @@ -2610,7 +2524,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x16: // LDSMMACL(Rn); UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn @@ -2622,7 +2535,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x17: // LDCMGBR(Rn); UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn @@ -2634,12 +2546,10 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x1a: // LDSMACL(Rn); UML_MOV(block, MEM(&sh2->macl), R32(Rn)); // mov macl, Rn return TRUE; - break; case 0x1b: // TAS(Rn); UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn @@ -2663,12 +2573,10 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x1e: // LDCGBR(Rn); UML_MOV(block, MEM(&sh2->gbr), R32(Rn)); // mov gbr, Rn return TRUE; - break; case 0x20: // SHAL(Rn); UML_AND(block, MEM(&sh2->sr), MEM(&sh2->sr), IMM(~T)); // and sr, sr, ~T @@ -2677,7 +2585,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_OR(block, MEM(&sh2->sr), MEM(&sh2->sr), IREG(0)); // or sr, sr, r0 UML_SHL(block, R32(Rn), R32(Rn), IMM(1)); // shl Rn, Rn, 1 return TRUE; - break; case 0x21: // SHAR(Rn); UML_AND(block, MEM(&sh2->sr), MEM(&sh2->sr), IMM(~T)); // and sr, sr, ~T @@ -2685,7 +2592,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_OR(block, MEM(&sh2->sr), MEM(&sh2->sr), IREG(0)); // or sr, sr, r0 UML_SAR(block, R32(Rn), R32(Rn), IMM(1)); // sar Rn, Rn, 1 return TRUE; - break; case 0x22: // STSMPR(Rn); UML_SUB(block, R32(Rn), R32(Rn), IMM(4)); // sub Rn, Rn, 4 @@ -2697,7 +2603,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x23: // STCMVBR(Rn); UML_SUB(block, R32(Rn), R32(Rn), IMM(4)); // sub Rn, Rn, 4 @@ -2709,7 +2614,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x24: // ROTCL(Rn); UML_CARRY(block, MEM(&sh2->sr), IMM(0)); // carry sr,0 @@ -2717,7 +2621,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_SETc(block, IF_C, IREG(0)); // set i0,C UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(T)); // rolins sr,i0,0,T return TRUE; - break; case 0x25: // ROTCR(Rn); UML_CARRY(block, MEM(&sh2->sr), IMM(0)); // carry sr,0 @@ -2725,7 +2628,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_SETc(block, IF_C, IREG(0)); // set i0,C UML_ROLINS(block, MEM(&sh2->sr), IREG(0), IMM(0), IMM(T)); // rolins sr,i0,0,T return TRUE; - break; case 0x26: // LDSMPR(Rn); UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn @@ -2737,7 +2639,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x27: // LDCMVBR(Rn); UML_MOV(block, IREG(0), R32(Rn)); // mov r0, Rn @@ -2749,12 +2650,10 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 0x2a: // LDSPR(Rn); UML_MOV(block, MEM(&sh2->pr), R32(Rn)); // mov sh2->pr, Rn return TRUE; - break; case 0x2b: // JMP(Rn); UML_MOV(block, MEM(&sh2->target), R32(Rn)); // mov target, Rn @@ -2764,12 +2663,10 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi generate_update_cycles(sh2, block, compiler, MEM(&sh2->target), TRUE); // <subtract cycles> UML_HASHJMP(block, IMM(0), MEM(&sh2->target), sh2->nocode); // jmp (target) return TRUE; - break; case 0x2e: // LDCVBR(Rn); UML_MOV(block, MEM(&sh2->vbr), R32(Rn)); // mov vbr, Rn return TRUE; - break; case 0x0c: // NOP(); case 0x0d: // NOP(); @@ -2794,8 +2691,6 @@ static int generate_group_4(SH2 *sh2, drcuml_block *block, compiler_state *compi case 0x3d: // NOP(); case 0x3e: // NOP(); return TRUE; - break; - } return FALSE; @@ -2814,7 +2709,6 @@ static int generate_group_6(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 1: // MOVWL(Rm, Rn); UML_MOV(block, IREG(0), R32(Rm)); // mov r0, Rm @@ -2825,7 +2719,6 @@ static int generate_group_6(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 2: // MOVLL(Rm, Rn); UML_MOV(block, IREG(0), R32(Rm)); // mov r0, Rm @@ -2836,47 +2729,38 @@ static int generate_group_6(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 3: // MOV(Rm, Rn); UML_MOV(block, R32(Rn), R32(Rm)); // mov Rn, Rm return TRUE; - break; case 7: // NOT(Rm, Rn); UML_XOR(block, R32(Rn), R32(Rm), IMM(0xffffffff)); // xor Rn, Rm, 0xffffffff return TRUE; - break; case 9: // SWAPW(Rm, Rn); UML_ROL(block, R32(Rn), R32(Rm), IMM(16)); // rol Rn, Rm, 16 return TRUE; - break; case 11: // NEG(Rm, Rn); UML_SUB(block, R32(Rn), IMM(0), R32(Rm)); // sub Rn, 0, Rm return TRUE; - break; case 12: // EXTUB(Rm, Rn); UML_AND(block, R32(Rn), R32(Rm), IMM(0x000000ff)); // and Rn, Rm, 0xff return TRUE; - break; case 13: // EXTUW(Rm, Rn); UML_AND(block, R32(Rn), R32(Rm), IMM(0x0000ffff)); // and Rn, Rm, 0xffff return TRUE; - break; case 14: // EXTSB(Rm, Rn); UML_SEXT(block, R32(Rn), R32(Rm), BYTE); // sext Rn, Rm, BYTE return TRUE; - break; case 15: // EXTSW(Rm, Rn); UML_SEXT(block, R32(Rn), R32(Rm), WORD); // sext Rn, Rm, WORD return TRUE; - break; case 4: // MOVBP(Rm, Rn); UML_MOV(block, IREG(0), R32(Rm)); // mov r0, Rm @@ -2893,7 +2777,6 @@ static int generate_group_6(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 5: // MOVWP(Rm, Rn); UML_MOV(block, IREG(0), R32(Rm)); // mov r0, Rm @@ -2910,7 +2793,6 @@ static int generate_group_6(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 6: // MOVLP(Rm, Rn); UML_MOV(block, IREG(0), R32(Rm)); // mov r0, Rm @@ -2927,7 +2809,6 @@ static int generate_group_6(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 8: // SWAPB(Rm, Rn); UML_AND(block, IREG(0), R32(Rm), IMM(0xffff0000)); // and r0, Rm, #0xffff0000 @@ -2938,7 +2819,6 @@ static int generate_group_6(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_OR(block, IREG(0), IREG(0), IREG(1)); // or r0, r0, r1 UML_OR(block, R32(Rn), IREG(0), IREG(2)); // or Rn, r0, r2 return TRUE; - break; case 10: // NEGC(Rm, Rn); UML_MOV(block, IREG(0), MEM(&sh2->sr)); // mov r0, sr (save SR) @@ -2953,7 +2833,6 @@ static int generate_group_6(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_LABEL(block, compiler->labelnum++); // labelnum: return TRUE; - break; } return FALSE; @@ -2976,7 +2855,6 @@ static int generate_group_8(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 1 << 8: // MOVWS4(opcode & 0x0f, Rm); udisp = (opcode & 0x0f) * 2; @@ -2987,7 +2865,6 @@ static int generate_group_8(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 2<< 8: // NOP(); case 3<< 8: // NOP(); @@ -2997,7 +2874,6 @@ static int generate_group_8(SH2 *sh2, drcuml_block *block, compiler_state *compi case 12<< 8: // NOP(); case 14<< 8: // NOP(); return TRUE; - break; case 4<< 8: // MOVBL4(Rm, opcode & 0x0f); udisp = opcode & 0x0f; @@ -3009,7 +2885,6 @@ static int generate_group_8(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 5<< 8: // MOVWL4(Rm, opcode & 0x0f); udisp = (opcode & 0x0f)*2; @@ -3021,7 +2896,6 @@ static int generate_group_8(SH2 *sh2, drcuml_block *block, compiler_state *compi if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 8<< 8: // CMPIM(opcode & 0xff); UML_AND(block, IREG(0), MEM(&sh2->sr), IMM(~T)); // and r0, sr, ~T (clear the T bit) @@ -3035,7 +2909,6 @@ static int generate_group_8(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_LABEL(block, compiler->labelnum++); // labelnum: UML_MOV(block, MEM(&sh2->sr), IREG(0)); // mov sh2->sr, r0 return TRUE; - break; case 9<< 8: // BT(opcode & 0xff); UML_TEST(block, MEM(&sh2->sr), IMM(T)); // test sh2->sr, T @@ -3049,7 +2922,6 @@ static int generate_group_8(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_LABEL(block, compiler->labelnum++); // labelnum: return TRUE; - break; case 11<< 8: // BF(opcode & 0xff); UML_TEST(block, MEM(&sh2->sr), IMM(T)); // test sh2->sr, T @@ -3063,7 +2935,6 @@ static int generate_group_8(SH2 *sh2, drcuml_block *block, compiler_state *compi UML_LABEL(block, compiler->labelnum++); // labelnum: return TRUE; - break; case 13<< 8: // BTS(opcode & 0xff); if (sh2->cpu_type > CPU_TYPE_SH1) @@ -3126,7 +2997,6 @@ static int generate_group_12(SH2 *sh2, drcuml_block *block, compiler_state *comp if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 1<<8: // MOVWSG(opcode & 0xff); scratch = (opcode & 0xff) * 2; @@ -3137,7 +3007,6 @@ static int generate_group_12(SH2 *sh2, drcuml_block *block, compiler_state *comp if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 2<<8: // MOVLSG(opcode & 0xff); scratch = (opcode & 0xff) * 4; @@ -3148,7 +3017,6 @@ static int generate_group_12(SH2 *sh2, drcuml_block *block, compiler_state *comp if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 3<<8: // TRAPA(opcode & 0xff); scratch = (opcode & 0xff) * 4; @@ -3169,7 +3037,6 @@ static int generate_group_12(SH2 *sh2, drcuml_block *block, compiler_state *comp UML_HASHJMP(block, IMM(0), IREG(0), sh2->nocode); // jmp (r0) return TRUE; - break; case 4<<8: // MOVBLG(opcode & 0xff); scratch = (opcode & 0xff); @@ -3180,7 +3047,6 @@ static int generate_group_12(SH2 *sh2, drcuml_block *block, compiler_state *comp if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 5<<8: // MOVWLG(opcode & 0xff); scratch = (opcode & 0xff) * 2; @@ -3191,7 +3057,6 @@ static int generate_group_12(SH2 *sh2, drcuml_block *block, compiler_state *comp if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 6<<8: // MOVLLG(opcode & 0xff); scratch = (opcode & 0xff) * 4; @@ -3202,7 +3067,6 @@ static int generate_group_12(SH2 *sh2, drcuml_block *block, compiler_state *comp if (!in_delay_slot) generate_update_cycles(sh2, block, compiler, IMM(desc->pc + 2), TRUE); return TRUE; - break; case 7<<8: // MOVA(opcode & 0xff); scratch = (opcode & 0xff) * 4; @@ -3210,7 +3074,6 @@ static int generate_group_12(SH2 *sh2, drcuml_block *block, compiler_state *comp UML_MOV(block, R32(0), IMM(scratch)); // mov R0, scratch return TRUE; - break; case 8<<8: // TSTI(opcode & 0xff); scratch = opcode & 0xff; @@ -3224,22 +3087,18 @@ static int generate_group_12(SH2 *sh2, drcuml_block *block, compiler_state *comp UML_LABEL(block, compiler->labelnum++); // labelnum: return TRUE; - break; case 9<<8: // ANDI(opcode & 0xff); UML_AND(block, R32(0), R32(0), IMM(opcode & 0xff)); // and r0, r0, opcode & 0xff return TRUE; - break; case 10<<8: // XORI(opcode & 0xff); UML_XOR(block, R32(0), R32(0), IMM(opcode & 0xff)); // xor r0, r0, opcode & 0xff return TRUE; - break; case 11<<8: // ORI(opcode & 0xff); UML_OR(block, R32(0), R32(0), IMM(opcode & 0xff)); // or r0, r0, opcode & 0xff return TRUE; - break; case 12<<8: // TSTM(opcode & 0xff); UML_AND(block, MEM(&sh2->sr), MEM(&sh2->sr), IMM(~T)); // and sr, sr, ~T (clear the T bit) @@ -3253,7 +3112,6 @@ static int generate_group_12(SH2 *sh2, drcuml_block *block, compiler_state *comp UML_LABEL(block, compiler->labelnum++); // labelnum: return TRUE; - break; case 13<<8: // ANDM(opcode & 0xff); UML_ADD(block, IREG(0), R32(0), MEM(&sh2->gbr)); // add r0, R0, gbr @@ -3264,7 +3122,6 @@ static int generate_group_12(SH2 *sh2, drcuml_block *block, compiler_state *comp SETEA(0); UML_CALLH(block, sh2->write8); // write8 return TRUE; - break; case 14<<8: // XORM(opcode & 0xff); UML_ADD(block, IREG(0), R32(0), MEM(&sh2->gbr)); // add r0, R0, gbr @@ -3275,7 +3132,6 @@ static int generate_group_12(SH2 *sh2, drcuml_block *block, compiler_state *comp SETEA(0); UML_CALLH(block, sh2->write8); // write8 return TRUE; - break; case 15<<8: // ORM(opcode & 0xff); UML_ADD(block, IREG(0), R32(0), MEM(&sh2->gbr)); // add r0, R0, gbr @@ -3286,7 +3142,6 @@ static int generate_group_12(SH2 *sh2, drcuml_block *block, compiler_state *comp SETEA(0); UML_CALLH(block, sh2->write8); // write8 return TRUE; - break; } return FALSE; diff --git a/src/emu/cpu/sh2/sh2fe.c b/src/emu/cpu/sh2/sh2fe.c index 22fc9c2c47b..402c13dae26 100644 --- a/src/emu/cpu/sh2/sh2fe.c +++ b/src/emu/cpu/sh2/sh2fe.c @@ -48,52 +48,42 @@ int sh2_describe(void *param, opcode_desc *desc, const opcode_desc *prev) { case 0: return describe_group_0(context, desc, prev, opcode); - break; case 1: // MOVLS4 desc->regin[0] |= REGFLAG_R(Rn) | REGFLAG_R(Rm); desc->flags |= OPFLAG_WRITES_MEMORY; return TRUE; - break; case 2: return describe_group_2(context, desc, prev, opcode); - break; case 3: return describe_group_3(context, desc, prev, opcode); - break; case 4: return describe_group_4(context, desc, prev, opcode); - break; case 5: // MOVLL4 desc->regin[0] |= REGFLAG_R(Rm); desc->regout[0] |= REGFLAG_R(Rn); desc->flags |= OPFLAG_READS_MEMORY; return TRUE; - break; case 6: return describe_group_6(context, desc, prev, opcode); - break; case 7: // ADDI desc->regin[0] |= REGFLAG_R(Rn); desc->regout[0] |= REGFLAG_R(Rn); return TRUE; - break; case 8: return describe_group_8(context, desc, prev, opcode); - break; case 9: // MOVWI desc->regout[0] |= REGFLAG_R(Rn); desc->flags |= OPFLAG_READS_MEMORY; return TRUE; - break; case 11: // BSR desc->regout[1] |= REGFLAG_PR; @@ -108,26 +98,21 @@ int sh2_describe(void *param, opcode_desc *desc, const opcode_desc *prev) desc->cycles = 2; return TRUE; } - break; case 12: return describe_group_12(context, desc, prev, opcode); - break; case 13: // MOVLI desc->regout[0] |= REGFLAG_R(Rn); desc->flags |= OPFLAG_READS_MEMORY; return TRUE; - break; case 14: // MOVI desc->regout[0] |= REGFLAG_R(Rn); return TRUE; - break; case 15: // NOP return TRUE; - break; } return FALSE; @@ -154,12 +139,10 @@ static int describe_group_0(SH2 *context, opcode_desc *desc, const opcode_desc * case 0x3a: // NOP(); case 0x3b: // NOP(); return TRUE; - break; case 0x02: // STCSR(Rn); desc->regout[0] |= REGFLAG_R(Rn); return TRUE; - break; case 0x03: // BSRF(Rn); desc->regout[1] |= REGFLAG_PR; @@ -169,7 +152,6 @@ static int describe_group_0(SH2 *context, opcode_desc *desc, const opcode_desc * desc->delayslots = 1; return TRUE; - break; case 0x04: // MOVBS0(Rm, Rn); case 0x05: // MOVWS0(Rm, Rn); @@ -186,7 +168,6 @@ static int describe_group_0(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn) | REGFLAG_R(0); desc->flags |= OPFLAG_READS_MEMORY; return TRUE; - break; case 0x07: // MULL(Rm, Rn); case 0x17: // MULL(Rm, Rn); @@ -196,18 +177,15 @@ static int describe_group_0(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[1] |= REGFLAG_MACL; desc->cycles = 2; return TRUE; - break; case 0x08: // CLRT(); desc->regout[1] |= REGFLAG_SR; return TRUE; - break; case 0x0a: // STSMACH(Rn); desc->regout[0] |= REGFLAG_R(Rn); desc->regout[1] |= REGFLAG_MACH; return TRUE; - break; case 0x0b: // RTS(); desc->regin[1] |= REGFLAG_PR; @@ -218,7 +196,6 @@ static int describe_group_0(SH2 *context, opcode_desc *desc, const opcode_desc * desc->cycles = 2; return TRUE; - break; case 0x0c: // MOVBL0(Rm, Rn); case 0x0d: // MOVWL0(Rm, Rn); @@ -236,7 +213,6 @@ static int describe_group_0(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[0] |= REGFLAG_R(Rn); desc->flags |= OPFLAG_READS_MEMORY; return TRUE; - break; case 0x0f: // MAC_L(Rm, Rn); case 0x1f: // MAC_L(Rm, Rn); @@ -246,40 +222,33 @@ static int describe_group_0(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[1] |= REGFLAG_MACL | REGFLAG_MACH; desc->cycles = 3; return TRUE; - break; case 0x12: // STCGBR(Rn); desc->regout[0] |= REGFLAG_R(Rn); desc->regin[1] |= REGFLAG_GBR; return TRUE; - break; case 0x18: // SETT(); desc->regout[1] |= REGFLAG_SR; return TRUE; - break; case 0x19: // DIV0U(); desc->regout[1] |= REGFLAG_SR; return TRUE; - break; case 0x1a: // STSMACL(Rn); desc->regin[1] |= REGFLAG_MACL; desc->regout[0] |= REGFLAG_R(Rn); return TRUE; - break; case 0x1b: // SLEEP(); desc->cycles = 3; return TRUE; - break; case 0x22: // STCVBR(Rn); desc->regin[0] |= REGFLAG_R(Rn); desc->regout[1] |= REGFLAG_VBR; return TRUE; - break; case 0x23: // BRAF(Rn); desc->regin[0] |= REGFLAG_R(Rm); @@ -288,24 +257,20 @@ static int describe_group_0(SH2 *context, opcode_desc *desc, const opcode_desc * desc->delayslots = 1; desc->cycles = 2; return TRUE; - break; case 0x28: // CLRMAC(); desc->regout[1] |= REGFLAG_MACL | REGFLAG_MACH; return TRUE; - break; case 0x29: // MOVT(Rn); desc->regin[1] |= REGFLAG_SR; desc->regout[0] |= REGFLAG_R(Rn); return TRUE; - break; case 0x2a: // STSPR(Rn); desc->regin[1] |= REGFLAG_PR; desc->regout[0] |= REGFLAG_R(Rn); return TRUE; - break; case 0x2b: // RTE(); desc->regin[0] |= REGFLAG_R(15); @@ -317,7 +282,6 @@ static int describe_group_0(SH2 *context, opcode_desc *desc, const opcode_desc * desc->cycles = 4; return TRUE; - break; } return FALSE; @@ -333,11 +297,9 @@ static int describe_group_2(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn); desc->flags |= OPFLAG_WRITES_MEMORY; return TRUE; - break; case 3: // NOP(); return TRUE; - break; case 4: // MOVBM(Rm, Rn); case 5: // MOVWM(Rm, Rn); @@ -347,7 +309,6 @@ static int describe_group_2(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[0] |= REGFLAG_R(Rn); desc->flags |= OPFLAG_WRITES_MEMORY; return TRUE; - break; case 7: // DIV0S(Rm, Rn); case 8: // TST(Rm, Rn); @@ -355,7 +316,6 @@ static int describe_group_2(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn); desc->regout[1] |= REGFLAG_SR; return TRUE; - break; case 9: // AND(Rm, Rn); case 10: // XOR(Rm, Rn); @@ -363,7 +323,6 @@ static int describe_group_2(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn); desc->regout[0] |= REGFLAG_R(Rn); return TRUE; - break; case 14: // MULU(Rm, Rn); case 15: // MULS(Rm, Rn); @@ -371,7 +330,6 @@ static int describe_group_2(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[1] |= REGFLAG_MACL | REGFLAG_MACH; desc->cycles = 2; return TRUE; - break; } return FALSE; @@ -389,19 +347,16 @@ static int describe_group_3(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn); desc->regout[1] |= REGFLAG_SR; return TRUE; - break; case 1: // NOP(); case 9: // NOP(); return TRUE; - break; case 4: // DIV1(Rm, Rn); desc->regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn); desc->regout[0] |= REGFLAG_R(Rn); desc->regout[1] |= REGFLAG_SR; return TRUE; - break; case 5: // DMULU(Rm, Rn); case 13: // DMULS(Rm, Rn); @@ -409,14 +364,12 @@ static int describe_group_3(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[1] |= REGFLAG_MACL | REGFLAG_MACH; desc->cycles = 2; return TRUE; - break; case 8: // SUB(Rm, Rn); case 12: // ADD(Rm, Rn); desc->regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn); desc->regout[0] |= REGFLAG_R(Rn); return TRUE; - break; case 10: // SUBC(Rm, Rn); case 11: // SUBV(Rm, Rn); @@ -427,7 +380,6 @@ static int describe_group_3(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[0] |= REGFLAG_R(Rn); desc->regout[1] |= REGFLAG_SR; return TRUE; - break; } return FALSE; } @@ -444,7 +396,6 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[0] |= REGFLAG_R(Rn); desc->regout[1] |= REGFLAG_SR; return TRUE; - break; case 0x02: // STSMMACH(Rn); desc->regin[0] |= REGFLAG_R(Rn); @@ -452,7 +403,6 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[0] |= REGFLAG_R(Rn); desc->flags |= OPFLAG_WRITES_MEMORY; return TRUE; - break; case 0x03: // STCMSR(Rn); desc->regin[0] |= REGFLAG_R(Rn); @@ -460,7 +410,6 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->cycles = 2; desc->flags |= OPFLAG_WRITES_MEMORY; return TRUE; - break; case 0x06: // LDSMMACH(Rn); desc->regin[0] |= REGFLAG_R(Rn); @@ -468,7 +417,6 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[1] |= REGFLAG_MACH; desc->flags |= OPFLAG_READS_MEMORY; return TRUE; - break; case 0x07: // LDCMSR(Rn); desc->regin[0] |= REGFLAG_R(Rn); @@ -477,7 +425,6 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->cycles = 3; desc->flags |= OPFLAG_READS_MEMORY | OPFLAG_CAN_EXPOSE_EXTERNAL_INT | OPFLAG_END_SEQUENCE; return TRUE; - break; case 0x08: // SHLL2(Rn); case 0x09: // SHLR2(Rn); @@ -488,13 +435,11 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regin[0] |= REGFLAG_R(Rn); desc->regout[0] |= REGFLAG_R(Rn); return TRUE; - break; case 0x0a: // LDSMACH(Rn); desc->regin[0] |= REGFLAG_R(Rn); desc->regout[1] |= REGFLAG_MACH; return TRUE; - break; case 0x0b: // JSR(Rn); desc->regin[0] |= REGFLAG_R(Rn); @@ -503,14 +448,12 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->targetpc = BRANCH_TARGET_DYNAMIC; desc->delayslots = 1; return TRUE; - break; case 0x0e: // LDCSR(Rn); desc->regin[0] |= REGFLAG_R(Rn); desc->regout[1] |= REGFLAG_SR; desc->flags |= OPFLAG_CAN_EXPOSE_EXTERNAL_INT | OPFLAG_END_SEQUENCE; return TRUE; - break; case 0x0f: // MAC_W(Rm, Rn); case 0x1f: // MAC_W(Rm, Rn); @@ -522,7 +465,6 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[1] |= REGFLAG_MACL | REGFLAG_MACH; desc->cycles = 3; return TRUE; - break; case 0x10: // DT(Rn); desc->regin[0] |= REGFLAG_R(Rn); @@ -530,7 +472,6 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[0] |= REGFLAG_R(Rn); desc->regout[1] |= REGFLAG_SR; return TRUE; - break; case 0x11: // CMPPZ(Rn); case 0x15: // CMPPL(Rn); @@ -538,7 +479,6 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regin[1] |= REGFLAG_SR; desc->regout[1] |= REGFLAG_SR; return TRUE; - break; case 0x12: // STSMMACL(Rn); desc->regin[0] |= REGFLAG_R(Rn); @@ -546,7 +486,6 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[0] |= REGFLAG_R(Rn); desc->flags |= OPFLAG_WRITES_MEMORY; return TRUE; - break; case 0x13: // STCMGBR(Rn); desc->regin[0] |= REGFLAG_R(Rn); @@ -554,7 +493,6 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[0] |= REGFLAG_R(Rn); desc->flags |= OPFLAG_WRITES_MEMORY; return TRUE; - break; case 0x16: // LDSMMACL(Rn); desc->regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn); @@ -562,7 +500,6 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[1] |= REGFLAG_MACL; desc->flags |= OPFLAG_READS_MEMORY; return TRUE; - break; case 0x17: // LDCMGBR(Rn); desc->regin[0] |= REGFLAG_R(Rn); @@ -570,13 +507,11 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[1] |= REGFLAG_GBR; desc->flags |= OPFLAG_READS_MEMORY; return TRUE; - break; case 0x1a: // LDSMACL(Rn); desc->regin[0] |= REGFLAG_R(Rn); desc->regout[1] |= REGFLAG_MACL; return TRUE; - break; case 0x1b: // TAS(Rn); desc->regin[0] |= REGFLAG_R(Rn); @@ -585,13 +520,11 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->cycles = 4; desc->flags |= OPFLAG_READS_MEMORY | OPFLAG_WRITES_MEMORY; return TRUE; - break; case 0x1e: // LDCGBR(Rn); desc->regin[0] |= REGFLAG_R(Rn); desc->regout[1] |= REGFLAG_GBR; return TRUE; - break; case 0x20: // SHAL(Rn); case 0x21: // SHAR(Rn); @@ -599,7 +532,6 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[0] |= REGFLAG_R(Rn); desc->regout[1] |= REGFLAG_SR; return TRUE; - break; case 0x22: // STSMPR(Rn); desc->regin[0] |= REGFLAG_R(Rn); @@ -607,7 +539,6 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[0] |= REGFLAG_R(Rn); desc->flags |= OPFLAG_WRITES_MEMORY; return TRUE; - break; case 0x23: // STCMVBR(Rn); desc->regin[0] |= REGFLAG_R(Rn); @@ -615,7 +546,6 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[0] |= REGFLAG_R(Rn); desc->flags |= OPFLAG_WRITES_MEMORY; return TRUE; - break; case 0x24: // ROTCL(Rn); case 0x25: // ROTCR(Rn); @@ -624,7 +554,6 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[0] |= REGFLAG_R(Rn); desc->regout[1] |= REGFLAG_SR; return TRUE; - break; case 0x26: // LDSMPR(Rn); desc->regin[0] |= REGFLAG_R(Rn); @@ -632,7 +561,6 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[1] |= REGFLAG_PR; desc->flags |= OPFLAG_READS_MEMORY; return TRUE; - break; case 0x27: // LDCMVBR(Rn); desc->regin[0] |= REGFLAG_R(Rn); @@ -640,13 +568,11 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[1] |= REGFLAG_VBR; desc->flags |= OPFLAG_READS_MEMORY; return TRUE; - break; case 0x2a: // LDSPR(Rn); desc->regin[0] |= REGFLAG_R(Rn); desc->regout[1] |= REGFLAG_PR; return TRUE; - break; case 0x2b: // JMP(Rm); desc->regin[0] |= REGFLAG_R(Rm); @@ -654,13 +580,11 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * desc->targetpc = BRANCH_TARGET_DYNAMIC; desc->delayslots = 1; return TRUE; - break; case 0x2e: // LDCVBR(Rn); desc->regin[0] |= REGFLAG_R(Rn); desc->regout[1] |= REGFLAG_VBR; return TRUE; - break; case 0x0c: // NOP(); case 0x0d: // NOP(); @@ -685,8 +609,6 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc * case 0x3d: // NOP(); case 0x3e: // NOP(); return TRUE; - break; - } return FALSE; @@ -710,7 +632,6 @@ static int describe_group_6(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regin[0] |= REGFLAG_R(Rm); desc->regout[0] |= REGFLAG_R(Rn); return TRUE; - break; case 4: // MOVBP(Rm, Rn); case 5: // MOVWP(Rm, Rn); @@ -719,20 +640,17 @@ static int describe_group_6(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[0] |= REGFLAG_R(Rn); desc->flags |= OPFLAG_READS_MEMORY; return TRUE; - break; case 8: // SWAPB(Rm, Rn); desc->regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn); desc->regout[0] |= REGFLAG_R(Rn); return TRUE; - break; case 10: // NEGC(Rm, Rn); desc->regin[0] |= REGFLAG_R(Rm); desc->regout[0] |= REGFLAG_R(Rn); desc->regout[1] |= REGFLAG_SR; return TRUE; - break; } return FALSE; } @@ -748,7 +666,6 @@ static int describe_group_8(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(0); desc->flags |= OPFLAG_WRITES_MEMORY; return TRUE; - break; case 2<< 8: // NOP(); case 3<< 8: // NOP(); @@ -758,7 +675,6 @@ static int describe_group_8(SH2 *context, opcode_desc *desc, const opcode_desc * case 12<< 8: // NOP(); case 14<< 8: // NOP(); return TRUE; - break; case 4<< 8: // MOVBL4(Rm, opcode & 0x0f); case 5<< 8: // MOVWL4(Rm, opcode & 0x0f); @@ -766,14 +682,12 @@ static int describe_group_8(SH2 *context, opcode_desc *desc, const opcode_desc * desc->regout[0] |= REGFLAG_R(0); desc->flags |= OPFLAG_READS_MEMORY; return TRUE; - break; case 8<< 8: // CMPIM(opcode & 0xff); desc->regin[0] |= REGFLAG_R(Rm); desc->regin[1] |= REGFLAG_SR; desc->regout[1] |= REGFLAG_SR; return TRUE; - break; case 9<< 8: // BT(opcode & 0xff); case 11<< 8: // BF(opcode & 0xff); @@ -782,7 +696,6 @@ static int describe_group_8(SH2 *context, opcode_desc *desc, const opcode_desc * disp = ((INT32)opcode << 24) >> 24; desc->targetpc = (desc->pc + 2) + disp * 2 + 2; return TRUE; - break; case 13<< 8: // BTS(opcode & 0xff); case 15<< 8: // BFS(opcode & 0xff); @@ -792,7 +705,6 @@ static int describe_group_8(SH2 *context, opcode_desc *desc, const opcode_desc * desc->targetpc = (desc->pc + 2) + disp * 2 + 2; desc->delayslots = 1; return TRUE; - break; } return FALSE; @@ -808,7 +720,6 @@ static int describe_group_12(SH2 *context, opcode_desc *desc, const opcode_desc desc->regin[0] |= REGFLAG_R(0); desc->flags |= OPFLAG_WRITES_MEMORY; return TRUE; - break; case 3<<8: // TRAPA(opcode & 0xff); desc->regin[0] |= REGFLAG_R(15); @@ -818,7 +729,6 @@ static int describe_group_12(SH2 *context, opcode_desc *desc, const opcode_desc desc->targetpc = BRANCH_TARGET_DYNAMIC; desc->flags |= OPFLAG_READS_MEMORY | OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE; return TRUE; - break; case 4<<8: // MOVBLG(opcode & 0xff); case 5<<8: // MOVWLG(opcode & 0xff); @@ -827,14 +737,12 @@ static int describe_group_12(SH2 *context, opcode_desc *desc, const opcode_desc desc->regout[0] |= REGFLAG_R(0); desc->flags |= OPFLAG_READS_MEMORY; return TRUE; - break; case 8<<8: // TSTI(opcode & 0xff); desc->regin[0] |= REGFLAG_R(0); desc->regin[1] |= REGFLAG_SR; desc->regout[1] |= REGFLAG_SR; return TRUE; - break; case 9<<8: // ANDI(opcode & 0xff); case 10<<8: // XORI(opcode & 0xff); @@ -842,7 +750,6 @@ static int describe_group_12(SH2 *context, opcode_desc *desc, const opcode_desc desc->regin[0] |= REGFLAG_R(0); desc->regout[0] |= REGFLAG_R(0); return TRUE; - break; case 12<<8: // TSTM(opcode & 0xff); case 13<<8: // ANDM(opcode & 0xff); @@ -853,7 +760,6 @@ static int describe_group_12(SH2 *context, opcode_desc *desc, const opcode_desc desc->regout[1] |= REGFLAG_SR; desc->flags |= OPFLAG_READS_MEMORY; return TRUE; - break; } return FALSE; diff --git a/src/emu/cpu/tms9900/9900dasm.c b/src/emu/cpu/tms9900/9900dasm.c index 3c7b787d3c9..c4dc1d1d2d1 100644 --- a/src/emu/cpu/tms9900/9900dasm.c +++ b/src/emu/cpu/tms9900/9900dasm.c @@ -325,10 +325,8 @@ static int print_arg (char *dest, int mode, int arg, const UINT8 *opram, unsigne { case 0x0: /* workspace register */ return sprintf (dest, "R%d", arg); - break; case 0x1: /* workspace register indirect */ return sprintf (dest, "*R%d", arg); - break; case 0x2: /* symbolic|indexed */ base = readop_arg(opram, pc); if (arg) /* indexed */ @@ -338,7 +336,6 @@ static int print_arg (char *dest, int mode, int arg, const UINT8 *opram, unsigne break; case 0x3: /* workspace register indirect auto increment */ return sprintf (dest, "*R%d+", arg); - break; } return 0; diff --git a/src/emu/cpu/v60/am1.c b/src/emu/cpu/v60/am1.c index 77fb8137dec..de69fd9779b 100644 --- a/src/emu/cpu/v60/am1.c +++ b/src/emu/cpu/v60/am1.c @@ -1058,17 +1058,14 @@ static UINT32 am1Immediate(v60_state *cpustate) case 0: cpustate->amout = OpRead8(cpustate->program, cpustate->modadd + 1); return 2; - break; case 1: cpustate->amout = OpRead16(cpustate->program, cpustate->modadd + 1); return 3; - break; case 2: cpustate->amout = OpRead32(cpustate->program, cpustate->modadd + 1); return 5; - break; } // It should not be here! Written to avoid warning |