diff options
author | 2013-01-11 07:32:46 +0000 | |
---|---|---|
committer | 2013-01-11 07:32:46 +0000 | |
commit | 0e19f641d3186cdbf51f8ca857e2b07ab95779c2 (patch) | |
tree | 234109de1123b13f217494af4b3f8efad346d5cc /src/emu/cpu/v60 | |
parent | 111157ca09a9ff60fe4a9ba49173c315e94314fa (diff) |
Cleanups and version bumpmame0148
Diffstat (limited to 'src/emu/cpu/v60')
-rw-r--r-- | src/emu/cpu/v60/am.c | 2 | ||||
-rw-r--r-- | src/emu/cpu/v60/am1.c | 24 | ||||
-rw-r--r-- | src/emu/cpu/v60/am2.c | 4 | ||||
-rw-r--r-- | src/emu/cpu/v60/am3.c | 13 | ||||
-rw-r--r-- | src/emu/cpu/v60/op12.c | 98 | ||||
-rw-r--r-- | src/emu/cpu/v60/op2.c | 16 | ||||
-rw-r--r-- | src/emu/cpu/v60/op3.c | 2 | ||||
-rw-r--r-- | src/emu/cpu/v60/op4.c | 1 | ||||
-rw-r--r-- | src/emu/cpu/v60/op5.c | 7 | ||||
-rw-r--r-- | src/emu/cpu/v60/op6.c | 1 | ||||
-rw-r--r-- | src/emu/cpu/v60/op7a.c | 20 | ||||
-rw-r--r-- | src/emu/cpu/v60/v60.c | 762 | ||||
-rw-r--r-- | src/emu/cpu/v60/v60d.c | 4 |
13 files changed, 466 insertions, 488 deletions
diff --git a/src/emu/cpu/v60/am.c b/src/emu/cpu/v60/am.c index 3d5c17171eb..f237844f8e6 100644 --- a/src/emu/cpu/v60/am.c +++ b/src/emu/cpu/v60/am.c @@ -80,5 +80,3 @@ static UINT32 WriteAM(v60_state *cpustate) cpustate->modval = OpRead8(cpustate, cpustate->modadd); return AMTable3[cpustate->modm][cpustate->modval >> 5](cpustate); } - - diff --git a/src/emu/cpu/v60/am1.c b/src/emu/cpu/v60/am1.c index 40548d70835..6969b46820f 100644 --- a/src/emu/cpu/v60/am1.c +++ b/src/emu/cpu/v60/am1.c @@ -1231,19 +1231,19 @@ static UINT32 (*const AMTable1_G7[32])(v60_state *) = am1PCDisplacement8, am1PCDisplacement16, am1PCDisplacement32, - am1DirectAddress, + am1DirectAddress, am1Immediate, am1Error2, am1Error2, am1Error2, - am1PCDisplacementIndirect8, - am1PCDisplacementIndirect16, - am1PCDisplacementIndirect32, + am1PCDisplacementIndirect8, + am1PCDisplacementIndirect16, + am1PCDisplacementIndirect32, am1DirectAddressDeferred, am1PCDoubleDisplacement8, am1PCDoubleDisplacement16, am1PCDoubleDisplacement32, - am1Error2 + am1Error2 }; static UINT32 (*const BAMTable1_G7[32])(v60_state *) = @@ -1267,19 +1267,19 @@ static UINT32 (*const BAMTable1_G7[32])(v60_state *) = bam1PCDisplacement8, bam1PCDisplacement16, bam1PCDisplacement32, - bam1DirectAddress, + bam1DirectAddress, bam1Error6, bam1Error2, bam1Error2, bam1Error2, - bam1PCDisplacementIndirect8, - bam1PCDisplacementIndirect16, - bam1PCDisplacementIndirect32, + bam1PCDisplacementIndirect8, + bam1PCDisplacementIndirect16, + bam1PCDisplacementIndirect32, bam1DirectAddressDeferred, bam1PCDoubleDisplacement8, bam1PCDoubleDisplacement16, bam1PCDoubleDisplacement32, - bam1Error2 + bam1Error2 }; @@ -1382,7 +1382,3 @@ static UINT32 (*const BAMTable1[2][8])(v60_state *) = bam1Error1 } }; - - - - diff --git a/src/emu/cpu/v60/am2.c b/src/emu/cpu/v60/am2.c index 3524b559402..c682a42df49 100644 --- a/src/emu/cpu/v60/am2.c +++ b/src/emu/cpu/v60/am2.c @@ -1251,7 +1251,3 @@ static UINT32 (*const BAMTable2[2][8])(v60_state *) = bam2Error1 } }; - - - - diff --git a/src/emu/cpu/v60/am3.c b/src/emu/cpu/v60/am3.c index 84c7ec6a958..3857bb3bb4a 100644 --- a/src/emu/cpu/v60/am3.c +++ b/src/emu/cpu/v60/am3.c @@ -814,19 +814,19 @@ static UINT32 (*const AMTable3_G7[32])(v60_state *) = am3PCDisplacement8, am3PCDisplacement16, am3PCDisplacement32, - am3DirectAddress, + am3DirectAddress, am3Immediate, am3Error2, am3Error2, am3Error2, - am3PCDisplacementIndirect8, - am3PCDisplacementIndirect16, - am3PCDisplacementIndirect32, + am3PCDisplacementIndirect8, + am3PCDisplacementIndirect16, + am3PCDisplacementIndirect32, am3DirectAddressDeferred, am3PCDoubleDisplacement8, am3PCDoubleDisplacement16, am3PCDoubleDisplacement32, - am3Error2 + am3Error2 }; static UINT32 (*const AMTable3_G6[8])(v60_state *) = @@ -882,6 +882,3 @@ static UINT32 (*const AMTable3[2][8])(v60_state *) = am3Error1 } }; - - - diff --git a/src/emu/cpu/v60/op12.c b/src/emu/cpu/v60/op12.c index f8e999cd4e1..cfae254d48b 100644 --- a/src/emu/cpu/v60/op12.c +++ b/src/emu/cpu/v60/op12.c @@ -16,40 +16,40 @@ * Macro to access data in operands decoded with ReadAMAddress(cpustate) */ -#define F12LOADOPBYTE(cs, num) \ - if ((cs)->flag##num) \ - appb = (UINT8)(cs)->reg[(cs)->op##num]; \ - else \ +#define F12LOADOPBYTE(cs, num) \ + if ((cs)->flag##num) \ + appb = (UINT8)(cs)->reg[(cs)->op##num]; \ + else \ appb = (cs)->program->read_byte((cs)->op##num); -#define F12LOADOPHALF(cs, num) \ - if ((cs)->flag##num) \ - apph = (UINT16)(cs)->reg[(cs)->op##num]; \ - else \ +#define F12LOADOPHALF(cs, num) \ + if ((cs)->flag##num) \ + apph = (UINT16)(cs)->reg[(cs)->op##num]; \ + else \ apph = (cs)->program->read_word_unaligned((cs)->op##num); -#define F12LOADOPWORD(cs, num) \ - if ((cs)->flag##num) \ - appw = (cs)->reg[(cs)->op##num]; \ - else \ +#define F12LOADOPWORD(cs, num) \ + if ((cs)->flag##num) \ + appw = (cs)->reg[(cs)->op##num]; \ + else \ appw = (cs)->program->read_dword_unaligned((cs)->op##num); -#define F12STOREOPBYTE(cs, num) \ - if ((cs)->flag##num) \ - SETREG8((cs)->reg[(cs)->op##num], appb); \ - else \ +#define F12STOREOPBYTE(cs, num) \ + if ((cs)->flag##num) \ + SETREG8((cs)->reg[(cs)->op##num], appb); \ + else \ (cs)->program->write_byte((cs)->op##num, appb); -#define F12STOREOPHALF(cs, num) \ - if ((cs)->flag##num) \ - SETREG16((cs)->reg[(cs)->op##num], apph); \ - else \ +#define F12STOREOPHALF(cs, num) \ + if ((cs)->flag##num) \ + SETREG16((cs)->reg[(cs)->op##num], apph); \ + else \ (cs)->program->write_word_unaligned((cs)->op##num, apph); -#define F12STOREOPWORD(cs, num) \ - if ((cs)->flag##num) \ - (cs)->reg[(cs)->op##num] = appw; \ - else \ +#define F12STOREOPWORD(cs, num) \ + if ((cs)->flag##num) \ + (cs)->reg[(cs)->op##num] = appw; \ + else \ (cs)->program->write_dword_unaligned((cs)->op##num, appw); #define F12LOADOP1BYTE(cs) F12LOADOPBYTE(cs, 1) @@ -68,7 +68,7 @@ #define F12STOREOP2HALF(cs) F12STOREOPHALF(cs, 2) #define F12STOREOP2WORD(cs) F12STOREOPWORD(cs, 2) -#define F12END(cs) \ +#define F12END(cs) \ return (cs)->amlength1 + (cs)->amlength2 + 2; @@ -665,7 +665,7 @@ static UINT32 opDIVUB(v60_state *cpustate) /* TRUSTED */ F12LOADOP2BYTE(cpustate); cpustate->_OV = 0; - if (cpustate->op1) appb /= (UINT8)cpustate->op1; + if (cpustate->op1) appb /= (UINT8)cpustate->op1; cpustate->_Z = (appb == 0); cpustate->_S = ((appb & 0x80) != 0); @@ -681,7 +681,7 @@ static UINT32 opDIVUH(v60_state *cpustate) /* TRUSTED */ F12LOADOP2HALF(cpustate); cpustate->_OV = 0; - if (cpustate->op1) apph /= (UINT16)cpustate->op1; + if (cpustate->op1) apph /= (UINT16)cpustate->op1; cpustate->_Z = (apph == 0); cpustate->_S = ((apph & 0x8000) != 0); @@ -697,7 +697,7 @@ static UINT32 opDIVUW(v60_state *cpustate) /* TRUSTED */ F12LOADOP2WORD(cpustate); cpustate->_OV = 0; - if (cpustate->op1) appw /= cpustate->op1; + if (cpustate->op1) appw /= cpustate->op1; cpustate->_Z = (appw == 0); cpustate->_S = ((appw & 0x80000000) != 0); @@ -755,7 +755,7 @@ static UINT32 opLDPR(v60_state *cpustate) F12DecodeOperands(cpustate, ReadAMAddress, 2,ReadAM, 2); if (cpustate->op2 <= 28) { - if (cpustate->flag1 &&(!(OpRead8(cpustate, cpustate->PC + 1)&0x80 && OpRead8(cpustate, cpustate->PC + 2) == 0xf4 ) )) + if (cpustate->flag1 &&(!(OpRead8(cpustate, cpustate->PC + 1)&0x80 && OpRead8(cpustate, cpustate->PC + 2) == 0xf4 ) )) cpustate->reg[cpustate->op2 + 36] = cpustate->reg[cpustate->op1]; else cpustate->reg[cpustate->op2 + 36] = cpustate->op1; @@ -920,7 +920,7 @@ static UINT32 opMOVTHB(v60_state *cpustate) // Check for overflow: the truncated bits must match the sign // of the result, otherwise overflow if (((cpustate->modwritevalb & 0x80) == 0x80 && ((cpustate->op1 & 0xFF00) == 0xFF00)) || - ((cpustate->modwritevalb & 0x80) == 0 && ((cpustate->op1 & 0xFF00) == 0x0000))) + ((cpustate->modwritevalb & 0x80) == 0 && ((cpustate->op1 & 0xFF00) == 0x0000))) cpustate->_OV = 0; else cpustate->_OV = 1; @@ -937,7 +937,7 @@ static UINT32 opMOVTWB(v60_state *cpustate) // Check for overflow: the truncated bits must match the sign // of the result, otherwise overflow if (((cpustate->modwritevalb & 0x80) == 0x80 && ((cpustate->op1 & 0xFFFFFF00) == 0xFFFFFF00)) || - ((cpustate->modwritevalb & 0x80) == 0 && ((cpustate->op1 & 0xFFFFFF00) == 0x00000000))) + ((cpustate->modwritevalb & 0x80) == 0 && ((cpustate->op1 & 0xFFFFFF00) == 0x00000000))) cpustate->_OV = 0; else cpustate->_OV = 1; @@ -954,7 +954,7 @@ static UINT32 opMOVTWH(v60_state *cpustate) // Check for overflow: the truncated bits must match the sign // of the result, otherwise overflow if (((cpustate->modwritevalh & 0x8000) == 0x8000 && ((cpustate->op1 & 0xFFFF0000) == 0xFFFF0000)) || - ((cpustate->modwritevalh & 0x8000) == 0 && ((cpustate->op1 & 0xFFFF0000) == 0x00000000))) + ((cpustate->modwritevalh & 0x8000) == 0 && ((cpustate->op1 & 0xFFFF0000) == 0x00000000))) cpustate->_OV = 0; else cpustate->_OV = 1; @@ -1592,13 +1592,13 @@ static UINT32 opRVBIT(v60_state *cpustate) cpustate->modwritevalb =(UINT8) (((cpustate->op1 & (1 << 0)) << 7) | - ((cpustate->op1 & (1 << 1)) << 5) | - ((cpustate->op1 & (1 << 2)) << 3) | - ((cpustate->op1 & (1 << 3)) << 1) | - ((cpustate->op1 & (1 << 4)) >> 1) | - ((cpustate->op1 & (1 << 5)) >> 3) | - ((cpustate->op1 & (1 << 6)) >> 5) | - ((cpustate->op1 & (1 << 7)) >> 7)); + ((cpustate->op1 & (1 << 1)) << 5) | + ((cpustate->op1 & (1 << 2)) << 3) | + ((cpustate->op1 & (1 << 3)) << 1) | + ((cpustate->op1 & (1 << 4)) >> 1) | + ((cpustate->op1 & (1 << 5)) >> 3) | + ((cpustate->op1 & (1 << 6)) >> 5) | + ((cpustate->op1 & (1 << 7)) >> 7)); F12WriteSecondOperand(cpustate, 0); F12END(cpustate); @@ -1609,9 +1609,9 @@ static UINT32 opRVBYT(v60_state *cpustate) /* TRUSTED */ F12DecodeFirstOperand(cpustate, ReadAM, 2); cpustate->modwritevalw = ((cpustate->op1 & 0x000000FF) << 24) | - ((cpustate->op1 & 0x0000FF00) << 8) | - ((cpustate->op1 & 0x00FF0000) >> 8) | - ((cpustate->op1 & 0xFF000000) >> 24); + ((cpustate->op1 & 0x0000FF00) << 8) | + ((cpustate->op1 & 0x00FF0000) >> 8) | + ((cpustate->op1 & 0xFF000000) >> 24); F12WriteSecondOperand(cpustate, 2); F12END(cpustate); @@ -1932,12 +1932,12 @@ static UINT32 opSHLB(v60_state *cpustate) /* TRUSTED */ // carry gets the last bit shifted out, // overflow is always CLEARed - cpustate->_OV = 0; // default to no overflow + cpustate->_OV = 0; // default to no overflow // now handle carry tmp = appb & 0xff; tmp <<= count; - SetCFB(tmp); // set carry properly + SetCFB(tmp); // set carry properly // do the actual shift... appb <<= count; @@ -1951,7 +1951,7 @@ static UINT32 opSHLB(v60_state *cpustate) /* TRUSTED */ { // special case: clear carry and overflow, do nothing else cpustate->_CY = cpustate->_OV = 0; - SetSZPF_Byte(appb); // doc. is unclear if this is true... + SetSZPF_Byte(appb); // doc. is unclear if this is true... } else { @@ -1997,7 +1997,7 @@ static UINT32 opSHLH(v60_state *cpustate) /* TRUSTED */ // now handle carry tmp = apph & 0xffff; tmp <<= count; - SetCFW(tmp); // set carry properly + SetCFW(tmp); // set carry properly // do the actual shift... apph <<= count; @@ -2011,7 +2011,7 @@ static UINT32 opSHLH(v60_state *cpustate) /* TRUSTED */ { // special case: clear carry and overflow, do nothing else cpustate->_CY = cpustate->_OV = 0; - SetSZPF_Word(apph); // doc. is unclear if this is true... + SetSZPF_Word(apph); // doc. is unclear if this is true... } else { @@ -2056,7 +2056,7 @@ static UINT32 opSHLW(v60_state *cpustate) /* TRUSTED */ // now handle carry tmp = appw & 0xffffffff; tmp <<= count; - SetCFL(tmp); // set carry properly + SetCFL(tmp); // set carry properly // do the actual shift... appw <<= count; @@ -2070,7 +2070,7 @@ static UINT32 opSHLW(v60_state *cpustate) /* TRUSTED */ { // special case: clear carry and overflow, do nothing else cpustate->_CY = cpustate->_OV = 0; - SetSZPF_Long(appw); // doc. is unclear if this is true... + SetSZPF_Long(appw); // doc. is unclear if this is true... } else { diff --git a/src/emu/cpu/v60/op2.c b/src/emu/cpu/v60/op2.c index b1c7b58d9c1..defb328e425 100644 --- a/src/emu/cpu/v60/op2.c +++ b/src/emu/cpu/v60/op2.c @@ -3,16 +3,16 @@ #define F2END(cs) \ return 2 + (cs)->amlength1 + (cs)->amlength2; -#define F2LOADOPFLOAT(cs, num) \ - if ((cs)->flag##num) \ - appf = u2f((cs)->reg[(cs)->op##num]); \ - else \ +#define F2LOADOPFLOAT(cs, num) \ + if ((cs)->flag##num) \ + appf = u2f((cs)->reg[(cs)->op##num]); \ + else \ appf = u2f((cs)->program->read_dword_unaligned((cs)->op##num)); -#define F2STOREOPFLOAT(cs,num) \ - if ((cs)->flag##num) \ - (cs)->reg[(cs)->op##num] = f2u(appf); \ - else \ +#define F2STOREOPFLOAT(cs,num) \ + if ((cs)->flag##num) \ + (cs)->reg[(cs)->op##num] = f2u(appf); \ + else \ (cs)->program->write_dword_unaligned((cs)->op##num, f2u(appf)); static void F2DecodeFirstOperand(v60_state *cpustate, UINT32 (*DecodeOp1)(v60_state *), UINT8 dim1) diff --git a/src/emu/cpu/v60/op3.c b/src/emu/cpu/v60/op3.c index f7e5f674237..722dc81ab81 100644 --- a/src/emu/cpu/v60/op3.c +++ b/src/emu/cpu/v60/op3.c @@ -174,7 +174,7 @@ static UINT32 opJSR(v60_state *cpustate) /* TRUSTED */ return 0; } -static UINT32 opPREPARE(v60_state *cpustate) /* somewhat TRUSTED */ +static UINT32 opPREPARE(v60_state *cpustate) /* somewhat TRUSTED */ { cpustate->modadd = cpustate->PC + 1; cpustate->moddim = 2; diff --git a/src/emu/cpu/v60/op4.c b/src/emu/cpu/v60/op4.c index dd83915c1c9..6332052354e 100644 --- a/src/emu/cpu/v60/op4.c +++ b/src/emu/cpu/v60/op4.c @@ -351,4 +351,3 @@ static UINT32 opBSR(v60_state *cpustate) /* TRUSTED */ cpustate->PC += (INT16)OpRead16(cpustate, cpustate->PC + 1); return 0; } - diff --git a/src/emu/cpu/v60/op5.c b/src/emu/cpu/v60/op5.c index 8c6808c6285..6373a3ce8e1 100644 --- a/src/emu/cpu/v60/op5.c +++ b/src/emu/cpu/v60/op5.c @@ -84,10 +84,3 @@ static UINT32 opTRAPFL(v60_state *cpustate) return 1; } - - - - - - - diff --git a/src/emu/cpu/v60/op6.c b/src/emu/cpu/v60/op6.c index 0441c83bb87..af9fa875700 100644 --- a/src/emu/cpu/v60/op6.c +++ b/src/emu/cpu/v60/op6.c @@ -251,4 +251,3 @@ static UINT32 opC7(v60_state *cpustate) /* TRUSTED */ UINT8 appb = OpRead8(cpustate, cpustate->PC + 1); return OpC7Table[appb >> 5](cpustate, appb & 0x1f); } - diff --git a/src/emu/cpu/v60/op7a.c b/src/emu/cpu/v60/op7a.c index 08303c3eb8b..071681cb543 100644 --- a/src/emu/cpu/v60/op7a.c +++ b/src/emu/cpu/v60/op7a.c @@ -12,19 +12,19 @@ * they do the opposite (set if not found, reset if found) */ -#define F7AEND(cs) \ +#define F7AEND(cs) \ return (cs)->amlength1 + (cs)->amlength2 + 4; -#define F7BEND(cs) \ +#define F7BEND(cs) \ return (cs)->amlength1 + (cs)->amlength2 + 3; -#define F7CEND(cs) \ +#define F7CEND(cs) \ return (cs)->amlength1 + (cs)->amlength2 + 3; -#define F7BCREATEBITMASK(x) \ +#define F7BCREATEBITMASK(x) \ x = ((1 << (x)) - 1) -#define F7CCREATEBITMASK(x) \ +#define F7CCREATEBITMASK(x) \ x = ((1 << (x)) - 1) static void F7aDecodeOperands(v60_state *cpustate, UINT32 (*DecodeOp1)(v60_state *), UINT8 dim1, UINT32 (*DecodeOp2)(v60_state *), UINT8 dim2) @@ -193,11 +193,11 @@ static UINT32 opCMPSTRB(v60_state *cpustate, UINT8 bFill, UINT8 bStop) if (c1 > c2) { - cpustate->_S = 1; break; + cpustate->_S = 1; break; } else if (c2 > c1) { - cpustate->_S = 0; break; + cpustate->_S = 0; break; } if (bStop) @@ -259,11 +259,11 @@ static UINT32 opCMPSTRH(v60_state *cpustate, UINT8 bFill, UINT8 bStop) if (c1 > c2) { - cpustate->_S = 1; break; + cpustate->_S = 1; break; } else if (c2 > c1) { - cpustate->_S = 0; break; + cpustate->_S = 0; break; } if (bStop) @@ -1035,7 +1035,7 @@ static UINT32 (*const Op5BTable[32])(v60_state *) = opSCH0BSU, op5BUNHANDLED, opSCH1BSU, - op5BUNHANDLED, + op5BUNHANDLED, op5BUNHANDLED, op5BUNHANDLED, op5BUNHANDLED, diff --git a/src/emu/cpu/v60/v60.c b/src/emu/cpu/v60/v60.c index 9d3eeae0379..f910deb802e 100644 --- a/src/emu/cpu/v60/v60.c +++ b/src/emu/cpu/v60/v60.c @@ -9,17 +9,17 @@ // memory accessors #if defined(LSB_FIRST) && !defined(ALIGN_INTS) -#define OpRead8(s, a) ((s)->direct->read_decrypted_byte(a)) -#define OpRead16(s, a) ((s)->direct->read_decrypted_word(a)) -#define OpRead32(s, a) ((s)->direct->read_decrypted_dword(a)) +#define OpRead8(s, a) ((s)->direct->read_decrypted_byte(a)) +#define OpRead16(s, a) ((s)->direct->read_decrypted_word(a)) +#define OpRead32(s, a) ((s)->direct->read_decrypted_dword(a)) #else #define OpRead8(s, a) ((s)->direct->read_decrypted_byte((a), (s)->fetch_xor)) -#define OpRead16(s, a) (((s)->direct->read_decrypted_byte(((a)+0), (s)->fetch_xor) << 0) | \ - ((s)->direct->read_decrypted_byte(((a)+1), (s)->fetch_xor) << 8)) -#define OpRead32(s, a) (((s)->direct->read_decrypted_byte(((a)+0), (s)->fetch_xor) << 0) | \ - ((s)->direct->read_decrypted_byte(((a)+1), (s)->fetch_xor) << 8) | \ - ((s)->direct->read_decrypted_byte(((a)+2), (s)->fetch_xor) << 16) | \ - ((s)->direct->read_decrypted_byte(((a)+3), (s)->fetch_xor) << 24)) +#define OpRead16(s, a) (((s)->direct->read_decrypted_byte(((a)+0), (s)->fetch_xor) << 0) | \ + ((s)->direct->read_decrypted_byte(((a)+1), (s)->fetch_xor) << 8)) +#define OpRead32(s, a) (((s)->direct->read_decrypted_byte(((a)+0), (s)->fetch_xor) << 0) | \ + ((s)->direct->read_decrypted_byte(((a)+1), (s)->fetch_xor) << 8) | \ + ((s)->direct->read_decrypted_byte(((a)+2), (s)->fetch_xor) << 16) | \ + ((s)->direct->read_decrypted_byte(((a)+3), (s)->fetch_xor) << 24)) #endif @@ -29,47 +29,47 @@ // parameter x = result, y = source 1, z = source 2 -#define SetOFL_Add(x, y,z) (cpustate->_OV = (((x) ^ (y)) & ((x) ^ (z)) & 0x80000000) ? 1: 0) -#define SetOFW_Add(x, y,z) (cpustate->_OV = (((x) ^ (y)) & ((x) ^ (z)) & 0x8000) ? 1 : 0) -#define SetOFB_Add(x, y,z) (cpustate->_OV = (((x) ^ (y)) & ((x) ^ (z)) & 0x80) ? 1 : 0) +#define SetOFL_Add(x, y,z) (cpustate->_OV = (((x) ^ (y)) & ((x) ^ (z)) & 0x80000000) ? 1: 0) +#define SetOFW_Add(x, y,z) (cpustate->_OV = (((x) ^ (y)) & ((x) ^ (z)) & 0x8000) ? 1 : 0) +#define SetOFB_Add(x, y,z) (cpustate->_OV = (((x) ^ (y)) & ((x) ^ (z)) & 0x80) ? 1 : 0) -#define SetOFL_Sub(x, y,z) (cpustate->_OV = (((z) ^ (y)) & ((z) ^ (x)) & 0x80000000) ? 1 : 0) -#define SetOFW_Sub(x, y,z) (cpustate->_OV = (((z) ^ (y)) & ((z) ^ (x)) & 0x8000) ? 1 : 0) -#define SetOFB_Sub(x, y,z) (cpustate->_OV = (((z) ^ (y)) & ((z) ^ (x)) & 0x80) ? 1 : 0) +#define SetOFL_Sub(x, y,z) (cpustate->_OV = (((z) ^ (y)) & ((z) ^ (x)) & 0x80000000) ? 1 : 0) +#define SetOFW_Sub(x, y,z) (cpustate->_OV = (((z) ^ (y)) & ((z) ^ (x)) & 0x8000) ? 1 : 0) +#define SetOFB_Sub(x, y,z) (cpustate->_OV = (((z) ^ (y)) & ((z) ^ (x)) & 0x80) ? 1 : 0) -#define SetCFB(x) {cpustate->_CY = ((x) & 0x100) ? 1 : 0; } -#define SetCFW(x) {cpustate->_CY = ((x) & 0x10000) ? 1 : 0; } -#define SetCFL(x) {cpustate->_CY = ((x) & (((UINT64)1) << 32)) ? 1 : 0; } +#define SetCFB(x) {cpustate->_CY = ((x) & 0x100) ? 1 : 0; } +#define SetCFW(x) {cpustate->_CY = ((x) & 0x10000) ? 1 : 0; } +#define SetCFL(x) {cpustate->_CY = ((x) & (((UINT64)1) << 32)) ? 1 : 0; } -#define SetSF(x) (cpustate->_S = (x)) -#define SetZF(x) (cpustate->_Z = (x)) +#define SetSF(x) (cpustate->_S = (x)) +#define SetZF(x) (cpustate->_Z = (x)) -#define SetSZPF_Byte(x) {cpustate->_Z = ((UINT8)(x) == 0); cpustate->_S = ((x)&0x80) ? 1 : 0; } -#define SetSZPF_Word(x) {cpustate->_Z = ((UINT16)(x) == 0); cpustate->_S = ((x)&0x8000) ? 1 : 0; } -#define SetSZPF_Long(x) {cpustate->_Z = ((UINT32)(x) == 0); cpustate->_S = ((x)&0x80000000) ? 1 : 0; } +#define SetSZPF_Byte(x) {cpustate->_Z = ((UINT8)(x) == 0); cpustate->_S = ((x)&0x80) ? 1 : 0; } +#define SetSZPF_Word(x) {cpustate->_Z = ((UINT16)(x) == 0); cpustate->_S = ((x)&0x8000) ? 1 : 0; } +#define SetSZPF_Long(x) {cpustate->_Z = ((UINT32)(x) == 0); cpustate->_S = ((x)&0x80000000) ? 1 : 0; } -#define ORB(dst, src) { (dst) |= (src); cpustate->_CY = cpustate->_OV = 0; SetSZPF_Byte(dst); } -#define ORW(dst, src) { (dst) |= (src); cpustate->_CY = cpustate->_OV = 0; SetSZPF_Word(dst); } -#define ORL(dst, src) { (dst) |= (src); cpustate->_CY = cpustate->_OV = 0; SetSZPF_Long(dst); } +#define ORB(dst, src) { (dst) |= (src); cpustate->_CY = cpustate->_OV = 0; SetSZPF_Byte(dst); } +#define ORW(dst, src) { (dst) |= (src); cpustate->_CY = cpustate->_OV = 0; SetSZPF_Word(dst); } +#define ORL(dst, src) { (dst) |= (src); cpustate->_CY = cpustate->_OV = 0; SetSZPF_Long(dst); } -#define ANDB(dst, src) { (dst) &= (src); cpustate->_CY = cpustate->_OV = 0; SetSZPF_Byte(dst); } -#define ANDW(dst, src) { (dst) &= (src); cpustate->_CY = cpustate->_OV = 0; SetSZPF_Word(dst); } -#define ANDL(dst, src) { (dst) &= (src); cpustate->_CY = cpustate->_OV = 0; SetSZPF_Long(dst); } +#define ANDB(dst, src) { (dst) &= (src); cpustate->_CY = cpustate->_OV = 0; SetSZPF_Byte(dst); } +#define ANDW(dst, src) { (dst) &= (src); cpustate->_CY = cpustate->_OV = 0; SetSZPF_Word(dst); } +#define ANDL(dst, src) { (dst) &= (src); cpustate->_CY = cpustate->_OV = 0; SetSZPF_Long(dst); } -#define XORB(dst, src) { (dst) ^= (src); cpustate->_CY = cpustate->_OV = 0; SetSZPF_Byte(dst); } -#define XORW(dst, src) { (dst) ^= (src); cpustate->_CY = cpustate->_OV = 0; SetSZPF_Word(dst); } -#define XORL(dst, src) { (dst) ^= (src); cpustate->_CY = cpustate->_OV = 0; SetSZPF_Long(dst); } +#define XORB(dst, src) { (dst) ^= (src); cpustate->_CY = cpustate->_OV = 0; SetSZPF_Byte(dst); } +#define XORW(dst, src) { (dst) ^= (src); cpustate->_CY = cpustate->_OV = 0; SetSZPF_Word(dst); } +#define XORL(dst, src) { (dst) ^= (src); cpustate->_CY = cpustate->_OV = 0; SetSZPF_Long(dst); } -#define SUBB(dst, src) { unsigned res = (dst) - (src); SetCFB(res); SetOFB_Sub(res, src, dst); SetSZPF_Byte(res); dst = (UINT8)res; } -#define SUBW(dst, src) { unsigned res = (dst) - (src); SetCFW(res); SetOFW_Sub(res, src, dst); SetSZPF_Word(res); dst = (UINT16)res; } -#define SUBL(dst, src) { UINT64 res = (UINT64)(dst) - (INT64)(src); SetCFL(res); SetOFL_Sub(res, src, dst); SetSZPF_Long(res); dst = (UINT32)res; } +#define SUBB(dst, src) { unsigned res = (dst) - (src); SetCFB(res); SetOFB_Sub(res, src, dst); SetSZPF_Byte(res); dst = (UINT8)res; } +#define SUBW(dst, src) { unsigned res = (dst) - (src); SetCFW(res); SetOFW_Sub(res, src, dst); SetSZPF_Word(res); dst = (UINT16)res; } +#define SUBL(dst, src) { UINT64 res = (UINT64)(dst) - (INT64)(src); SetCFL(res); SetOFL_Sub(res, src, dst); SetSZPF_Long(res); dst = (UINT32)res; } -#define ADDB(dst, src) { unsigned res = (dst) + (src); SetCFB(res); SetOFB_Add(res, src, dst); SetSZPF_Byte(res); dst = (UINT8)res; } -#define ADDW(dst, src) { unsigned res = (dst) + (src); SetCFW(res); SetOFW_Add(res, src, dst); SetSZPF_Word(res); dst = (UINT16)res; } -#define ADDL(dst, src) { UINT64 res = (UINT64)(dst) + (UINT64)(src); SetCFL(res); SetOFL_Add(res, src, dst); SetSZPF_Long(res); dst = (UINT32)res; } +#define ADDB(dst, src) { unsigned res = (dst) + (src); SetCFB(res); SetOFB_Add(res, src, dst); SetSZPF_Byte(res); dst = (UINT8)res; } +#define ADDW(dst, src) { unsigned res = (dst) + (src); SetCFW(res); SetOFW_Add(res, src, dst); SetSZPF_Word(res); dst = (UINT16)res; } +#define ADDL(dst, src) { UINT64 res = (UINT64)(dst) + (UINT64)(src); SetCFL(res); SetOFL_Add(res, src, dst); SetSZPF_Long(res); dst = (UINT32)res; } -#define SETREG8(a, b) (a) = ((a) & ~0xff) | ((b) & 0xff) -#define SETREG16(a, b) (a) = ((a) & ~0xffff) | ((b) & 0xffff) +#define SETREG8(a, b) (a) = ((a) & ~0xff) | ((b) & 0xff) +#define SETREG16(a, b) (a) = ((a) & ~0xffff) | ((b) & 0xffff) struct v60_flags { @@ -82,52 +82,52 @@ struct v60_flags // v60 Register Inside (Hm... It's not a pentium inside :-))) ) struct v60_state { - offs_t fetch_xor; - offs_t start_pc; - UINT32 reg[68]; - v60_flags flags; - UINT8 irq_line; - UINT8 nmi_line; - device_irq_acknowledge_callback irq_cb; - legacy_cpu_device * device; + offs_t fetch_xor; + offs_t start_pc; + UINT32 reg[68]; + v60_flags flags; + UINT8 irq_line; + UINT8 nmi_line; + device_irq_acknowledge_callback irq_cb; + legacy_cpu_device * device; address_space *program; - direct_read_data * direct; + direct_read_data * direct; address_space *io; - UINT32 PPC; - int icount; - int stall_io; + UINT32 PPC; + int icount; + int stall_io; - UINT32 op1, op2; - UINT8 flag1, flag2; - UINT8 instflags; - UINT32 lenop1, lenop2; - UINT8 subop; - UINT32 bamoffset1, bamoffset2; + UINT32 op1, op2; + UINT8 flag1, flag2; + UINT8 instflags; + UINT32 lenop1, lenop2; + UINT8 subop; + UINT32 bamoffset1, bamoffset2; // Output variables for ReadAMAddress(cpustate) - UINT8 amflag; - UINT32 amout; - UINT32 bamoffset; + UINT8 amflag; + UINT32 amout; + UINT32 bamoffset; // Appo temp var - UINT32 amlength1, amlength2; + UINT32 amlength1, amlength2; // Global vars used by AM functions - UINT32 modadd; - UINT8 modm; - UINT8 modval; - UINT8 modval2; - UINT8 modwritevalb; - UINT16 modwritevalh; - UINT32 modwritevalw; - UINT8 moddim; + UINT32 modadd; + UINT8 modm; + UINT8 modval; + UINT8 modval2; + UINT8 modwritevalb; + UINT16 modwritevalh; + UINT32 modwritevalw; + UINT8 moddim; }; INLINE v60_state *get_safe_token(device_t *device) { assert(device != NULL); assert(device->type() == V60 || - device->type() == V70); + device->type() == V70); return (v60_state *)downcast<legacy_cpu_device *>(device)->token(); } @@ -139,84 +139,84 @@ INLINE v60_state *get_safe_token(device_t *device) */ #undef _S -#define _CY flags.CY -#define _OV flags.OV -#define _S flags.S -#define _Z flags.Z +#define _CY flags.CY +#define _OV flags.OV +#define _S flags.S +#define _Z flags.Z // Defines of all v60 register... -#define R0 reg[0] -#define R1 reg[1] -#define R2 reg[2] -#define R3 reg[3] -#define R4 reg[4] -#define R5 reg[5] -#define R6 reg[6] -#define R7 reg[7] -#define R8 reg[8] -#define R9 reg[9] -#define R10 reg[10] -#define R11 reg[11] -#define R12 reg[12] -#define R13 reg[13] -#define R14 reg[14] -#define R15 reg[15] -#define R16 reg[16] -#define R17 reg[17] -#define R18 reg[18] -#define R19 reg[19] -#define R20 reg[20] -#define R21 reg[21] -#define R22 reg[22] -#define R23 reg[23] -#define R24 reg[24] -#define R25 reg[25] -#define R26 reg[26] -#define R27 reg[27] -#define R28 reg[28] -#define AP reg[29] -#define FP reg[30] -#define SP reg[31] - -#define PC reg[32] -#define PSW reg[33] +#define R0 reg[0] +#define R1 reg[1] +#define R2 reg[2] +#define R3 reg[3] +#define R4 reg[4] +#define R5 reg[5] +#define R6 reg[6] +#define R7 reg[7] +#define R8 reg[8] +#define R9 reg[9] +#define R10 reg[10] +#define R11 reg[11] +#define R12 reg[12] +#define R13 reg[13] +#define R14 reg[14] +#define R15 reg[15] +#define R16 reg[16] +#define R17 reg[17] +#define R18 reg[18] +#define R19 reg[19] +#define R20 reg[20] +#define R21 reg[21] +#define R22 reg[22] +#define R23 reg[23] +#define R24 reg[24] +#define R25 reg[25] +#define R26 reg[26] +#define R27 reg[27] +#define R28 reg[28] +#define AP reg[29] +#define FP reg[30] +#define SP reg[31] + +#define PC reg[32] +#define PSW reg[33] // Privileged registers -#define ISP reg[36] -#define L0SP reg[37] -#define L1SP reg[38] -#define L2SP reg[39] -#define L3SP reg[40] -#define SBR reg[41] -#define TR reg[42] -#define SYCW reg[43] -#define TKCW reg[44] -#define PIR reg[45] +#define ISP reg[36] +#define L0SP reg[37] +#define L1SP reg[38] +#define L2SP reg[39] +#define L3SP reg[40] +#define SBR reg[41] +#define TR reg[42] +#define SYCW reg[43] +#define TKCW reg[44] +#define PIR reg[45] //10-14 reserved -#define PSW2 reg[51] -#define ATBR0 reg[52] -#define ATLR0 reg[53] -#define ATBR1 reg[54] -#define ATLR1 reg[55] -#define ATBR2 reg[56] -#define ATLR2 reg[57] -#define ATBR3 reg[58] -#define ATLR3 reg[59] -#define TRMODE reg[60] -#define ADTR0 reg[61] -#define ADTR1 reg[62] -#define ADTMR0 reg[63] -#define ADTMR1 reg[64] +#define PSW2 reg[51] +#define ATBR0 reg[52] +#define ATLR0 reg[53] +#define ATBR1 reg[54] +#define ATLR1 reg[55] +#define ATBR2 reg[56] +#define ATLR2 reg[57] +#define ATBR3 reg[58] +#define ATLR3 reg[59] +#define TRMODE reg[60] +#define ADTR0 reg[61] +#define ADTR1 reg[62] +#define ADTMR0 reg[63] +#define ADTMR1 reg[64] //29-31 reserved // Defines... #define NORMALIZEFLAGS(cs) \ { \ - (cs)->_S = (cs)->_S ? 1 : 0; \ - (cs)->_OV = (cs)->_OV ? 1 : 0; \ - (cs)->_Z = (cs)->_Z ? 1 : 0; \ - (cs)->_CY = (cs)->_CY ? 1 : 0; \ + (cs)->_S = (cs)->_S ? 1 : 0; \ + (cs)->_OV = (cs)->_OV ? 1 : 0; \ + (cs)->_Z = (cs)->_Z ? 1 : 0; \ + (cs)->_CY = (cs)->_CY ? 1 : 0; \ } static void v60_try_irq(v60_state *cpustate); @@ -297,8 +297,8 @@ INLINE UINT32 v60_update_psw_for_exception(v60_state *cpustate, int is_interrupt } -#define GETINTVECT(cs, nint) (cs)->program->read_dword(((cs)->SBR & ~0xfff) + (nint) * 4) -#define EXCEPTION_CODE_AND_SIZE(code, size) (((code) << 16) | (size)) +#define GETINTVECT(cs, nint) (cs)->program->read_dword(((cs)->SBR & ~0xfff) + (nint) * 4) +#define EXCEPTION_CODE_AND_SIZE(code, size) (((code) << 16) | (size)) // Addressing mode decoding functions @@ -378,17 +378,17 @@ static CPU_RESET( v60 ) { v60_state *cpustate = get_safe_token(device); - cpustate->PSW = 0x10000000; - cpustate->PC = cpustate->start_pc; - cpustate->SBR = 0x00000000; - cpustate->SYCW = 0x00000070; - cpustate->TKCW = 0x0000e000; - cpustate->PSW2 = 0x0000f002; - - cpustate->_CY = 0; - cpustate->_OV = 0; - cpustate->_S = 0; - cpustate->_Z = 0; + cpustate->PSW = 0x10000000; + cpustate->PC = cpustate->start_pc; + cpustate->SBR = 0x00000000; + cpustate->SYCW = 0x00000070; + cpustate->TKCW = 0x0000e000; + cpustate->PSW2 = 0x0000f002; + + cpustate->_CY = 0; + cpustate->_OV = 0; + cpustate->_S = 0; + cpustate->_Z = 0; } static CPU_EXIT( v60 ) @@ -464,7 +464,7 @@ static CPU_EXECUTE( v60 ) UINT32 inc; cpustate->PPC = cpustate->PC; debugger_instruction_hook(device, cpustate->PC); - cpustate->icount -= 8; /* fix me -- this is just an average */ + cpustate->icount -= 8; /* fix me -- this is just an average */ inc = OpCodeTable[OpRead8(cpustate, cpustate->PC)](cpustate); cpustate->PC += inc; if (cpustate->irq_line != CLEAR_LINE) @@ -488,70 +488,70 @@ static CPU_SET_INFO( v60 ) switch (state) { /* --- the following bits of info are set as 64-bit signed integers --- */ - case CPUINFO_INT_INPUT_STATE + 0: set_irq_line(cpustate, 0, info->i); break; - case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: set_irq_line(cpustate, INPUT_LINE_NMI, info->i);break; - - case CPUINFO_INT_PC: cpustate->PC = info->i; break; - case CPUINFO_INT_SP: cpustate->SP = info->i; break; - - case CPUINFO_INT_REGISTER + V60_R0: cpustate->R0 = info->i; break; - case CPUINFO_INT_REGISTER + V60_R1: cpustate->R1 = info->i; break; - case CPUINFO_INT_REGISTER + V60_R2: cpustate->R2 = info->i; break; - case CPUINFO_INT_REGISTER + V60_R3: cpustate->R3 = info->i; break; - case CPUINFO_INT_REGISTER + V60_R4: cpustate->R4 = info->i; break; - case CPUINFO_INT_REGISTER + V60_R5: cpustate->R5 = info->i; break; - case CPUINFO_INT_REGISTER + V60_R6: cpustate->R6 = info->i; break; - case CPUINFO_INT_REGISTER + V60_R7: cpustate->R7 = info->i; break; - case CPUINFO_INT_REGISTER + V60_R8: cpustate->R8 = info->i; break; - case CPUINFO_INT_REGISTER + V60_R9: cpustate->R9 = info->i; break; - case CPUINFO_INT_REGISTER + V60_R10: cpustate->R10 = info->i; break; - case CPUINFO_INT_REGISTER + V60_R11: cpustate->R11 = info->i; break; - case CPUINFO_INT_REGISTER + V60_R12: cpustate->R12 = info->i; break; - case CPUINFO_INT_REGISTER + V60_R13: cpustate->R13 = info->i; break; - case CPUINFO_INT_REGISTER + V60_R14: cpustate->R14 = info->i; break; - case CPUINFO_INT_REGISTER + V60_R15: cpustate->R15 = info->i; break; - case CPUINFO_INT_REGISTER + V60_R16: cpustate->R16 = info->i; break; - case CPUINFO_INT_REGISTER + V60_R17: cpustate->R17 = info->i; break; - case CPUINFO_INT_REGISTER + V60_R18: cpustate->R18 = info->i; break; - case CPUINFO_INT_REGISTER + V60_R19: cpustate->R19 = info->i; break; - case CPUINFO_INT_REGISTER + V60_R20: cpustate->R20 = info->i; break; - case CPUINFO_INT_REGISTER + V60_R21: cpustate->R21 = info->i; break; - case CPUINFO_INT_REGISTER + V60_R22: cpustate->R22 = info->i; break; - case CPUINFO_INT_REGISTER + V60_R23: cpustate->R23 = info->i; break; - case CPUINFO_INT_REGISTER + V60_R24: cpustate->R24 = info->i; break; - case CPUINFO_INT_REGISTER + V60_R25: cpustate->R25 = info->i; break; - case CPUINFO_INT_REGISTER + V60_R26: cpustate->R26 = info->i; break; - case CPUINFO_INT_REGISTER + V60_R27: cpustate->R27 = info->i; break; - case CPUINFO_INT_REGISTER + V60_R28: cpustate->R28 = info->i; break; - case CPUINFO_INT_REGISTER + V60_AP: cpustate->AP = info->i; break; - case CPUINFO_INT_REGISTER + V60_FP: cpustate->FP = info->i; break; - case CPUINFO_INT_REGISTER + V60_SP: cpustate->SP = info->i; break; - case CPUINFO_INT_REGISTER + V60_PC: cpustate->PC = info->i; break; - case CPUINFO_INT_REGISTER + V60_PSW: v60WritePSW(cpustate, info->i); break; - case CPUINFO_INT_REGISTER + V60_ISP: cpustate->ISP = info->i; break; - case CPUINFO_INT_REGISTER + V60_L0SP: cpustate->L0SP = info->i; break; - case CPUINFO_INT_REGISTER + V60_L1SP: cpustate->L1SP = info->i; break; - case CPUINFO_INT_REGISTER + V60_L2SP: cpustate->L2SP = info->i; break; - case CPUINFO_INT_REGISTER + V60_L3SP: cpustate->L3SP = info->i; break; - case CPUINFO_INT_REGISTER + V60_SBR: cpustate->SBR = info->i; break; - case CPUINFO_INT_REGISTER + V60_TR: cpustate->TR = info->i; break; - case CPUINFO_INT_REGISTER + V60_SYCW: cpustate->SYCW = info->i; break; - case CPUINFO_INT_REGISTER + V60_TKCW: cpustate->TKCW = info->i; break; - case CPUINFO_INT_REGISTER + V60_PIR: cpustate->PIR = info->i; break; - case CPUINFO_INT_REGISTER + V60_PSW2: cpustate->PSW2 = info->i; break; - case CPUINFO_INT_REGISTER + V60_ATBR0: cpustate->ATBR0 = info->i; break; - case CPUINFO_INT_REGISTER + V60_ATLR0: cpustate->ATLR0 = info->i; break; - case CPUINFO_INT_REGISTER + V60_ATBR1: cpustate->ATBR1 = info->i; break; - case CPUINFO_INT_REGISTER + V60_ATLR1: cpustate->ATLR1 = info->i; break; - case CPUINFO_INT_REGISTER + V60_ATBR2: cpustate->ATBR2 = info->i; break; - case CPUINFO_INT_REGISTER + V60_ATLR2: cpustate->ATLR2 = info->i; break; - case CPUINFO_INT_REGISTER + V60_ATBR3: cpustate->ATBR3 = info->i; break; - case CPUINFO_INT_REGISTER + V60_ATLR3: cpustate->ATLR3 = info->i; break; - case CPUINFO_INT_REGISTER + V60_TRMODE: cpustate->TRMODE = info->i; break; - case CPUINFO_INT_REGISTER + V60_ADTR0: cpustate->ADTR0 = info->i; break; - case CPUINFO_INT_REGISTER + V60_ADTR1: cpustate->ADTR1 = info->i; break; - case CPUINFO_INT_REGISTER + V60_ADTMR0: cpustate->ADTMR0 = info->i; break; - case CPUINFO_INT_REGISTER + V60_ADTMR1: cpustate->ADTMR1 = info->i; break; + case CPUINFO_INT_INPUT_STATE + 0: set_irq_line(cpustate, 0, info->i); break; + case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: set_irq_line(cpustate, INPUT_LINE_NMI, info->i);break; + + case CPUINFO_INT_PC: cpustate->PC = info->i; break; + case CPUINFO_INT_SP: cpustate->SP = info->i; break; + + case CPUINFO_INT_REGISTER + V60_R0: cpustate->R0 = info->i; break; + case CPUINFO_INT_REGISTER + V60_R1: cpustate->R1 = info->i; break; + case CPUINFO_INT_REGISTER + V60_R2: cpustate->R2 = info->i; break; + case CPUINFO_INT_REGISTER + V60_R3: cpustate->R3 = info->i; break; + case CPUINFO_INT_REGISTER + V60_R4: cpustate->R4 = info->i; break; + case CPUINFO_INT_REGISTER + V60_R5: cpustate->R5 = info->i; break; + case CPUINFO_INT_REGISTER + V60_R6: cpustate->R6 = info->i; break; + case CPUINFO_INT_REGISTER + V60_R7: cpustate->R7 = info->i; break; + case CPUINFO_INT_REGISTER + V60_R8: cpustate->R8 = info->i; break; + case CPUINFO_INT_REGISTER + V60_R9: cpustate->R9 = info->i; break; + case CPUINFO_INT_REGISTER + V60_R10: cpustate->R10 = info->i; break; + case CPUINFO_INT_REGISTER + V60_R11: cpustate->R11 = info->i; break; + case CPUINFO_INT_REGISTER + V60_R12: cpustate->R12 = info->i; break; + case CPUINFO_INT_REGISTER + V60_R13: cpustate->R13 = info->i; break; + case CPUINFO_INT_REGISTER + V60_R14: cpustate->R14 = info->i; break; + case CPUINFO_INT_REGISTER + V60_R15: cpustate->R15 = info->i; break; + case CPUINFO_INT_REGISTER + V60_R16: cpustate->R16 = info->i; break; + case CPUINFO_INT_REGISTER + V60_R17: cpustate->R17 = info->i; break; + case CPUINFO_INT_REGISTER + V60_R18: cpustate->R18 = info->i; break; + case CPUINFO_INT_REGISTER + V60_R19: cpustate->R19 = info->i; break; + case CPUINFO_INT_REGISTER + V60_R20: cpustate->R20 = info->i; break; + case CPUINFO_INT_REGISTER + V60_R21: cpustate->R21 = info->i; break; + case CPUINFO_INT_REGISTER + V60_R22: cpustate->R22 = info->i; break; + case CPUINFO_INT_REGISTER + V60_R23: cpustate->R23 = info->i; break; + case CPUINFO_INT_REGISTER + V60_R24: cpustate->R24 = info->i; break; + case CPUINFO_INT_REGISTER + V60_R25: cpustate->R25 = info->i; break; + case CPUINFO_INT_REGISTER + V60_R26: cpustate->R26 = info->i; break; + case CPUINFO_INT_REGISTER + V60_R27: cpustate->R27 = info->i; break; + case CPUINFO_INT_REGISTER + V60_R28: cpustate->R28 = info->i; break; + case CPUINFO_INT_REGISTER + V60_AP: cpustate->AP = info->i; break; + case CPUINFO_INT_REGISTER + V60_FP: cpustate->FP = info->i; break; + case CPUINFO_INT_REGISTER + V60_SP: cpustate->SP = info->i; break; + case CPUINFO_INT_REGISTER + V60_PC: cpustate->PC = info->i; break; + case CPUINFO_INT_REGISTER + V60_PSW: v60WritePSW(cpustate, info->i); break; + case CPUINFO_INT_REGISTER + V60_ISP: cpustate->ISP = info->i; break; + case CPUINFO_INT_REGISTER + V60_L0SP: cpustate->L0SP = info->i; break; + case CPUINFO_INT_REGISTER + V60_L1SP: cpustate->L1SP = info->i; break; + case CPUINFO_INT_REGISTER + V60_L2SP: cpustate->L2SP = info->i; break; + case CPUINFO_INT_REGISTER + V60_L3SP: cpustate->L3SP = info->i; break; + case CPUINFO_INT_REGISTER + V60_SBR: cpustate->SBR = info->i; break; + case CPUINFO_INT_REGISTER + V60_TR: cpustate->TR = info->i; break; + case CPUINFO_INT_REGISTER + V60_SYCW: cpustate->SYCW = info->i; break; + case CPUINFO_INT_REGISTER + V60_TKCW: cpustate->TKCW = info->i; break; + case CPUINFO_INT_REGISTER + V60_PIR: cpustate->PIR = info->i; break; + case CPUINFO_INT_REGISTER + V60_PSW2: cpustate->PSW2 = info->i; break; + case CPUINFO_INT_REGISTER + V60_ATBR0: cpustate->ATBR0 = info->i; break; + case CPUINFO_INT_REGISTER + V60_ATLR0: cpustate->ATLR0 = info->i; break; + case CPUINFO_INT_REGISTER + V60_ATBR1: cpustate->ATBR1 = info->i; break; + case CPUINFO_INT_REGISTER + V60_ATLR1: cpustate->ATLR1 = info->i; break; + case CPUINFO_INT_REGISTER + V60_ATBR2: cpustate->ATBR2 = info->i; break; + case CPUINFO_INT_REGISTER + V60_ATLR2: cpustate->ATLR2 = info->i; break; + case CPUINFO_INT_REGISTER + V60_ATBR3: cpustate->ATBR3 = info->i; break; + case CPUINFO_INT_REGISTER + V60_ATLR3: cpustate->ATLR3 = info->i; break; + case CPUINFO_INT_REGISTER + V60_TRMODE: cpustate->TRMODE = info->i; break; + case CPUINFO_INT_REGISTER + V60_ADTR0: cpustate->ADTR0 = info->i; break; + case CPUINFO_INT_REGISTER + V60_ADTR1: cpustate->ADTR1 = info->i; break; + case CPUINFO_INT_REGISTER + V60_ADTMR0: cpustate->ADTMR0 = info->i; break; + case CPUINFO_INT_REGISTER + V60_ADTMR1: cpustate->ADTMR1 = info->i; break; } } @@ -568,170 +568,170 @@ CPU_GET_INFO( v60 ) switch (state) { /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(v60_state); break; - case CPUINFO_INT_INPUT_LINES: info->i = 1; break; - case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; - case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; - case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; - case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break; - case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 22; break; - case CPUINFO_INT_MIN_CYCLES: info->i = 1; break; - case CPUINFO_INT_MAX_CYCLES: info->i = 1; break; - - case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 16; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 24; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 16; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 24; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break; - - case CPUINFO_INT_INPUT_STATE + 0: info->i = cpustate->irq_line; break; - case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = cpustate->nmi_line; break; - - case CPUINFO_INT_PREVIOUSPC: info->i = cpustate->PPC; break; - - case CPUINFO_INT_REGISTER + V60_R0: info->i = cpustate->R0; break; - case CPUINFO_INT_REGISTER + V60_R1: info->i = cpustate->R1; break; - case CPUINFO_INT_REGISTER + V60_R2: info->i = cpustate->R2; break; - case CPUINFO_INT_REGISTER + V60_R3: info->i = cpustate->R3; break; - case CPUINFO_INT_REGISTER + V60_R4: info->i = cpustate->R4; break; - case CPUINFO_INT_REGISTER + V60_R5: info->i = cpustate->R5; break; - case CPUINFO_INT_REGISTER + V60_R6: info->i = cpustate->R6; break; - case CPUINFO_INT_REGISTER + V60_R7: info->i = cpustate->R7; break; - case CPUINFO_INT_REGISTER + V60_R8: info->i = cpustate->R8; break; - case CPUINFO_INT_REGISTER + V60_R9: info->i = cpustate->R9; break; - case CPUINFO_INT_REGISTER + V60_R10: info->i = cpustate->R10; break; - case CPUINFO_INT_REGISTER + V60_R11: info->i = cpustate->R11; break; - case CPUINFO_INT_REGISTER + V60_R12: info->i = cpustate->R12; break; - case CPUINFO_INT_REGISTER + V60_R13: info->i = cpustate->R13; break; - case CPUINFO_INT_REGISTER + V60_R14: info->i = cpustate->R14; break; - case CPUINFO_INT_REGISTER + V60_R15: info->i = cpustate->R15; break; - case CPUINFO_INT_REGISTER + V60_R16: info->i = cpustate->R16; break; - case CPUINFO_INT_REGISTER + V60_R17: info->i = cpustate->R17; break; - case CPUINFO_INT_REGISTER + V60_R18: info->i = cpustate->R18; break; - case CPUINFO_INT_REGISTER + V60_R19: info->i = cpustate->R19; break; - case CPUINFO_INT_REGISTER + V60_R20: info->i = cpustate->R20; break; - case CPUINFO_INT_REGISTER + V60_R21: info->i = cpustate->R21; break; - case CPUINFO_INT_REGISTER + V60_R22: info->i = cpustate->R22; break; - case CPUINFO_INT_REGISTER + V60_R23: info->i = cpustate->R23; break; - case CPUINFO_INT_REGISTER + V60_R24: info->i = cpustate->R24; break; - case CPUINFO_INT_REGISTER + V60_R25: info->i = cpustate->R25; break; - case CPUINFO_INT_REGISTER + V60_R26: info->i = cpustate->R26; break; - case CPUINFO_INT_REGISTER + V60_R27: info->i = cpustate->R27; break; - case CPUINFO_INT_REGISTER + V60_R28: info->i = cpustate->R28; break; - case CPUINFO_INT_REGISTER + V60_AP: info->i = cpustate->AP; break; - case CPUINFO_INT_REGISTER + V60_FP: info->i = cpustate->FP; break; + case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(v60_state); break; + case CPUINFO_INT_INPUT_LINES: info->i = 1; break; + case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; + case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; + case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; + case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; + case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 1; break; + case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 22; break; + case CPUINFO_INT_MIN_CYCLES: info->i = 1; break; + case CPUINFO_INT_MAX_CYCLES: info->i = 1; break; + + case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 16; break; + case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 24; break; + case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; + case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break; + case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 16; break; + case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 24; break; + case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break; + + case CPUINFO_INT_INPUT_STATE + 0: info->i = cpustate->irq_line; break; + case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = cpustate->nmi_line; break; + + case CPUINFO_INT_PREVIOUSPC: info->i = cpustate->PPC; break; + + case CPUINFO_INT_REGISTER + V60_R0: info->i = cpustate->R0; break; + case CPUINFO_INT_REGISTER + V60_R1: info->i = cpustate->R1; break; + case CPUINFO_INT_REGISTER + V60_R2: info->i = cpustate->R2; break; + case CPUINFO_INT_REGISTER + V60_R3: info->i = cpustate->R3; break; + case CPUINFO_INT_REGISTER + V60_R4: info->i = cpustate->R4; break; + case CPUINFO_INT_REGISTER + V60_R5: info->i = cpustate->R5; break; + case CPUINFO_INT_REGISTER + V60_R6: info->i = cpustate->R6; break; + case CPUINFO_INT_REGISTER + V60_R7: info->i = cpustate->R7; break; + case CPUINFO_INT_REGISTER + V60_R8: info->i = cpustate->R8; break; + case CPUINFO_INT_REGISTER + V60_R9: info->i = cpustate->R9; break; + case CPUINFO_INT_REGISTER + V60_R10: info->i = cpustate->R10; break; + case CPUINFO_INT_REGISTER + V60_R11: info->i = cpustate->R11; break; + case CPUINFO_INT_REGISTER + V60_R12: info->i = cpustate->R12; break; + case CPUINFO_INT_REGISTER + V60_R13: info->i = cpustate->R13; break; + case CPUINFO_INT_REGISTER + V60_R14: info->i = cpustate->R14; break; + case CPUINFO_INT_REGISTER + V60_R15: info->i = cpustate->R15; break; + case CPUINFO_INT_REGISTER + V60_R16: info->i = cpustate->R16; break; + case CPUINFO_INT_REGISTER + V60_R17: info->i = cpustate->R17; break; + case CPUINFO_INT_REGISTER + V60_R18: info->i = cpustate->R18; break; + case CPUINFO_INT_REGISTER + V60_R19: info->i = cpustate->R19; break; + case CPUINFO_INT_REGISTER + V60_R20: info->i = cpustate->R20; break; + case CPUINFO_INT_REGISTER + V60_R21: info->i = cpustate->R21; break; + case CPUINFO_INT_REGISTER + V60_R22: info->i = cpustate->R22; break; + case CPUINFO_INT_REGISTER + V60_R23: info->i = cpustate->R23; break; + case CPUINFO_INT_REGISTER + V60_R24: info->i = cpustate->R24; break; + case CPUINFO_INT_REGISTER + V60_R25: info->i = cpustate->R25; break; + case CPUINFO_INT_REGISTER + V60_R26: info->i = cpustate->R26; break; + case CPUINFO_INT_REGISTER + V60_R27: info->i = cpustate->R27; break; + case CPUINFO_INT_REGISTER + V60_R28: info->i = cpustate->R28; break; + case CPUINFO_INT_REGISTER + V60_AP: info->i = cpustate->AP; break; + case CPUINFO_INT_REGISTER + V60_FP: info->i = cpustate->FP; break; case CPUINFO_INT_SP: - case CPUINFO_INT_REGISTER + V60_SP: info->i = cpustate->SP; break; + case CPUINFO_INT_REGISTER + V60_SP: info->i = cpustate->SP; break; case CPUINFO_INT_PC: - case CPUINFO_INT_REGISTER + V60_PC: info->i = cpustate->PC; break; - case CPUINFO_INT_REGISTER + V60_PSW: info->i = v60ReadPSW(cpustate); break; - case CPUINFO_INT_REGISTER + V60_ISP: info->i = cpustate->ISP; break; - case CPUINFO_INT_REGISTER + V60_L0SP: info->i = cpustate->L0SP; break; - case CPUINFO_INT_REGISTER + V60_L1SP: info->i = cpustate->L1SP; break; - case CPUINFO_INT_REGISTER + V60_L2SP: info->i = cpustate->L2SP; break; - case CPUINFO_INT_REGISTER + V60_L3SP: info->i = cpustate->L3SP; break; - case CPUINFO_INT_REGISTER + V60_SBR: info->i = cpustate->SBR; break; - case CPUINFO_INT_REGISTER + V60_TR: info->i = cpustate->TR; break; - case CPUINFO_INT_REGISTER + V60_SYCW: info->i = cpustate->SYCW; break; - case CPUINFO_INT_REGISTER + V60_TKCW: info->i = cpustate->TKCW; break; - case CPUINFO_INT_REGISTER + V60_PIR: info->i = cpustate->PIR; break; - case CPUINFO_INT_REGISTER + V60_PSW2: info->i = cpustate->PSW2; break; - case CPUINFO_INT_REGISTER + V60_ATBR0: info->i = cpustate->ATBR0; break; - case CPUINFO_INT_REGISTER + V60_ATLR0: info->i = cpustate->ATLR0; break; - case CPUINFO_INT_REGISTER + V60_ATBR1: info->i = cpustate->ATBR1; break; - case CPUINFO_INT_REGISTER + V60_ATLR1: info->i = cpustate->ATLR1; break; - case CPUINFO_INT_REGISTER + V60_ATBR2: info->i = cpustate->ATBR2; break; - case CPUINFO_INT_REGISTER + V60_ATLR2: info->i = cpustate->ATLR2; break; - case CPUINFO_INT_REGISTER + V60_ATBR3: info->i = cpustate->ATBR3; break; - case CPUINFO_INT_REGISTER + V60_ATLR3: info->i = cpustate->ATLR3; break; - case CPUINFO_INT_REGISTER + V60_TRMODE: info->i = cpustate->TRMODE; break; - case CPUINFO_INT_REGISTER + V60_ADTR0: info->i = cpustate->ADTR0; break; - case CPUINFO_INT_REGISTER + V60_ADTR1: info->i = cpustate->ADTR1; break; - case CPUINFO_INT_REGISTER + V60_ADTMR0: info->i = cpustate->ADTMR0; break; - case CPUINFO_INT_REGISTER + V60_ADTMR1: info->i = cpustate->ADTMR1; break; + case CPUINFO_INT_REGISTER + V60_PC: info->i = cpustate->PC; break; + case CPUINFO_INT_REGISTER + V60_PSW: info->i = v60ReadPSW(cpustate); break; + case CPUINFO_INT_REGISTER + V60_ISP: info->i = cpustate->ISP; break; + case CPUINFO_INT_REGISTER + V60_L0SP: info->i = cpustate->L0SP; break; + case CPUINFO_INT_REGISTER + V60_L1SP: info->i = cpustate->L1SP; break; + case CPUINFO_INT_REGISTER + V60_L2SP: info->i = cpustate->L2SP; break; + case CPUINFO_INT_REGISTER + V60_L3SP: info->i = cpustate->L3SP; break; + case CPUINFO_INT_REGISTER + V60_SBR: info->i = cpustate->SBR; break; + case CPUINFO_INT_REGISTER + V60_TR: info->i = cpustate->TR; break; + case CPUINFO_INT_REGISTER + V60_SYCW: info->i = cpustate->SYCW; break; + case CPUINFO_INT_REGISTER + V60_TKCW: info->i = cpustate->TKCW; break; + case CPUINFO_INT_REGISTER + V60_PIR: info->i = cpustate->PIR; break; + case CPUINFO_INT_REGISTER + V60_PSW2: info->i = cpustate->PSW2; break; + case CPUINFO_INT_REGISTER + V60_ATBR0: info->i = cpustate->ATBR0; break; + case CPUINFO_INT_REGISTER + V60_ATLR0: info->i = cpustate->ATLR0; break; + case CPUINFO_INT_REGISTER + V60_ATBR1: info->i = cpustate->ATBR1; break; + case CPUINFO_INT_REGISTER + V60_ATLR1: info->i = cpustate->ATLR1; break; + case CPUINFO_INT_REGISTER + V60_ATBR2: info->i = cpustate->ATBR2; break; + case CPUINFO_INT_REGISTER + V60_ATLR2: info->i = cpustate->ATLR2; break; + case CPUINFO_INT_REGISTER + V60_ATBR3: info->i = cpustate->ATBR3; break; + case CPUINFO_INT_REGISTER + V60_ATLR3: info->i = cpustate->ATLR3; break; + case CPUINFO_INT_REGISTER + V60_TRMODE: info->i = cpustate->TRMODE; break; + case CPUINFO_INT_REGISTER + V60_ADTR0: info->i = cpustate->ADTR0; break; + case CPUINFO_INT_REGISTER + V60_ADTR1: info->i = cpustate->ADTR1; break; + case CPUINFO_INT_REGISTER + V60_ADTMR0: info->i = cpustate->ADTMR0; break; + case CPUINFO_INT_REGISTER + V60_ADTMR1: info->i = cpustate->ADTMR1; break; /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(v60); break; - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(v60); break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(v60); break; - case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(v60); break; - case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(v60); break; - case CPUINFO_FCT_BURN: info->burn = NULL; break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(v60); break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break; + case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(v60); break; + case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(v60); break; + case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(v60); break; + case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(v60); break; + case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(v60); break; + case CPUINFO_FCT_BURN: info->burn = NULL; break; + case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(v60); break; + case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break; /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "V60"); break; - case CPUINFO_STR_FAMILY: strcpy(info->s, "NEC V60"); break; - case CPUINFO_STR_VERSION: strcpy(info->s, "1.0"); break; - case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; - case CPUINFO_STR_CREDITS: strcpy(info->s, "Farfetch'd and R.Belmont"); break; - - case CPUINFO_STR_FLAGS: strcpy(info->s, " "); break; - - case CPUINFO_STR_REGISTER + V60_R0: sprintf(info->s, "R0:%08X", cpustate->R0); break; - case CPUINFO_STR_REGISTER + V60_R1: sprintf(info->s, "R1:%08X", cpustate->R1); break; - case CPUINFO_STR_REGISTER + V60_R2: sprintf(info->s, "R2:%08X", cpustate->R2); break; - case CPUINFO_STR_REGISTER + V60_R3: sprintf(info->s, "R3:%08X", cpustate->R3); break; - case CPUINFO_STR_REGISTER + V60_R4: sprintf(info->s, "R4:%08X", cpustate->R4); break; - case CPUINFO_STR_REGISTER + V60_R5: sprintf(info->s, "R5:%08X", cpustate->R5); break; - case CPUINFO_STR_REGISTER + V60_R6: sprintf(info->s, "R6:%08X", cpustate->R6); break; - case CPUINFO_STR_REGISTER + V60_R7: sprintf(info->s, "R7:%08X", cpustate->R7); break; - case CPUINFO_STR_REGISTER + V60_R8: sprintf(info->s, "R8:%08X", cpustate->R8); break; - case CPUINFO_STR_REGISTER + V60_R9: sprintf(info->s, "R9:%08X", cpustate->R9); break; - case CPUINFO_STR_REGISTER + V60_R10: sprintf(info->s, "R10:%08X", cpustate->R10); break; - case CPUINFO_STR_REGISTER + V60_R11: sprintf(info->s, "R11:%08X", cpustate->R11); break; - case CPUINFO_STR_REGISTER + V60_R12: sprintf(info->s, "R12:%08X", cpustate->R12); break; - case CPUINFO_STR_REGISTER + V60_R13: sprintf(info->s, "R13:%08X", cpustate->R13); break; - case CPUINFO_STR_REGISTER + V60_R14: sprintf(info->s, "R14:%08X", cpustate->R14); break; - case CPUINFO_STR_REGISTER + V60_R15: sprintf(info->s, "R15:%08X", cpustate->R15); break; - case CPUINFO_STR_REGISTER + V60_R16: sprintf(info->s, "R16:%08X", cpustate->R16); break; - case CPUINFO_STR_REGISTER + V60_R17: sprintf(info->s, "R17:%08X", cpustate->R17); break; - case CPUINFO_STR_REGISTER + V60_R18: sprintf(info->s, "R18:%08X", cpustate->R18); break; - case CPUINFO_STR_REGISTER + V60_R19: sprintf(info->s, "R19:%08X", cpustate->R19); break; - case CPUINFO_STR_REGISTER + V60_R20: sprintf(info->s, "R20:%08X", cpustate->R20); break; - case CPUINFO_STR_REGISTER + V60_R21: sprintf(info->s, "R21:%08X", cpustate->R21); break; - case CPUINFO_STR_REGISTER + V60_R22: sprintf(info->s, "R22:%08X", cpustate->R22); break; - case CPUINFO_STR_REGISTER + V60_R23: sprintf(info->s, "R23:%08X", cpustate->R23); break; - case CPUINFO_STR_REGISTER + V60_R24: sprintf(info->s, "R24:%08X", cpustate->R24); break; - case CPUINFO_STR_REGISTER + V60_R25: sprintf(info->s, "R25:%08X", cpustate->R25); break; - case CPUINFO_STR_REGISTER + V60_R26: sprintf(info->s, "R26:%08X", cpustate->R26); break; - case CPUINFO_STR_REGISTER + V60_R27: sprintf(info->s, "R27:%08X", cpustate->R27); break; - case CPUINFO_STR_REGISTER + V60_R28: sprintf(info->s, "R28:%08X", cpustate->R28); break; - case CPUINFO_STR_REGISTER + V60_AP: sprintf(info->s, "AP:%08X", cpustate->AP); break; - case CPUINFO_STR_REGISTER + V60_FP: sprintf(info->s, "FP:%08X", cpustate->FP); break; - case CPUINFO_STR_REGISTER + V60_SP: sprintf(info->s, "SP:%08X", cpustate->SP); break; - case CPUINFO_STR_REGISTER + V60_PC: sprintf(info->s, "PC:%08X", cpustate->PC); break; - case CPUINFO_STR_REGISTER + V60_PSW: sprintf(info->s, "PSW:%08X", v60ReadPSW(cpustate)); break; - case CPUINFO_STR_REGISTER + V60_ISP: sprintf(info->s, "ISP:%08X", cpustate->ISP); break; - case CPUINFO_STR_REGISTER + V60_L0SP: sprintf(info->s, "L0SP:%08X", cpustate->L0SP); break; - case CPUINFO_STR_REGISTER + V60_L1SP: sprintf(info->s, "L1SP:%08X", cpustate->L1SP); break; - case CPUINFO_STR_REGISTER + V60_L2SP: sprintf(info->s, "L2SP:%08X", cpustate->L2SP); break; - case CPUINFO_STR_REGISTER + V60_L3SP: sprintf(info->s, "L3SP:%08X", cpustate->L3SP); break; - case CPUINFO_STR_REGISTER + V60_SBR: sprintf(info->s, "SBR:%08X", cpustate->SBR); break; - case CPUINFO_STR_REGISTER + V60_TR: sprintf(info->s, "TR:%08X", cpustate->TR); break; - case CPUINFO_STR_REGISTER + V60_SYCW: sprintf(info->s, "SYCW:%08X", cpustate->SYCW); break; - case CPUINFO_STR_REGISTER + V60_TKCW: sprintf(info->s, "TKCW:%08X", cpustate->TKCW); break; - case CPUINFO_STR_REGISTER + V60_PIR: sprintf(info->s, "PIR:%08X", cpustate->PIR); break; - case CPUINFO_STR_REGISTER + V60_PSW2: sprintf(info->s, "PSW2:%08X", cpustate->PSW2); break; - case CPUINFO_STR_REGISTER + V60_ATBR0: sprintf(info->s, "ATBR0:%08X", cpustate->ATBR0); break; - case CPUINFO_STR_REGISTER + V60_ATLR0: sprintf(info->s, "ATLR0:%08X", cpustate->ATLR0); break; - case CPUINFO_STR_REGISTER + V60_ATBR1: sprintf(info->s, "ATBR1:%08X", cpustate->ATBR1); break; - case CPUINFO_STR_REGISTER + V60_ATLR1: sprintf(info->s, "ATLR1:%08X", cpustate->ATLR1); break; - case CPUINFO_STR_REGISTER + V60_ATBR2: sprintf(info->s, "ATBR2:%08X", cpustate->ATBR2); break; - case CPUINFO_STR_REGISTER + V60_ATLR2: sprintf(info->s, "ATLR2:%08X", cpustate->ATLR2); break; - case CPUINFO_STR_REGISTER + V60_ATBR3: sprintf(info->s, "ATBR3:%08X", cpustate->ATBR3); break; - case CPUINFO_STR_REGISTER + V60_ATLR3: sprintf(info->s, "ATLR3:%08X", cpustate->ATLR3); break; - case CPUINFO_STR_REGISTER + V60_TRMODE: sprintf(info->s, "TRMODE:%08X", cpustate->TRMODE); break; - case CPUINFO_STR_REGISTER + V60_ADTR0: sprintf(info->s, "ADTR0:%08X", cpustate->ADTR0); break; - case CPUINFO_STR_REGISTER + V60_ADTR1: sprintf(info->s, "ADTR1:%08X", cpustate->ADTR1); break; - case CPUINFO_STR_REGISTER + V60_ADTMR0: sprintf(info->s, "ADTMR0:%08X", cpustate->ADTMR0); break; - case CPUINFO_STR_REGISTER + V60_ADTMR1: sprintf(info->s, "ADTMR1:%08X", cpustate->ADTMR1); break; + case CPUINFO_STR_NAME: strcpy(info->s, "V60"); break; + case CPUINFO_STR_FAMILY: strcpy(info->s, "NEC V60"); break; + case CPUINFO_STR_VERSION: strcpy(info->s, "1.0"); break; + case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; + case CPUINFO_STR_CREDITS: strcpy(info->s, "Farfetch'd and R.Belmont"); break; + + case CPUINFO_STR_FLAGS: strcpy(info->s, " "); break; + + case CPUINFO_STR_REGISTER + V60_R0: sprintf(info->s, "R0:%08X", cpustate->R0); break; + case CPUINFO_STR_REGISTER + V60_R1: sprintf(info->s, "R1:%08X", cpustate->R1); break; + case CPUINFO_STR_REGISTER + V60_R2: sprintf(info->s, "R2:%08X", cpustate->R2); break; + case CPUINFO_STR_REGISTER + V60_R3: sprintf(info->s, "R3:%08X", cpustate->R3); break; + case CPUINFO_STR_REGISTER + V60_R4: sprintf(info->s, "R4:%08X", cpustate->R4); break; + case CPUINFO_STR_REGISTER + V60_R5: sprintf(info->s, "R5:%08X", cpustate->R5); break; + case CPUINFO_STR_REGISTER + V60_R6: sprintf(info->s, "R6:%08X", cpustate->R6); break; + case CPUINFO_STR_REGISTER + V60_R7: sprintf(info->s, "R7:%08X", cpustate->R7); break; + case CPUINFO_STR_REGISTER + V60_R8: sprintf(info->s, "R8:%08X", cpustate->R8); break; + case CPUINFO_STR_REGISTER + V60_R9: sprintf(info->s, "R9:%08X", cpustate->R9); break; + case CPUINFO_STR_REGISTER + V60_R10: sprintf(info->s, "R10:%08X", cpustate->R10); break; + case CPUINFO_STR_REGISTER + V60_R11: sprintf(info->s, "R11:%08X", cpustate->R11); break; + case CPUINFO_STR_REGISTER + V60_R12: sprintf(info->s, "R12:%08X", cpustate->R12); break; + case CPUINFO_STR_REGISTER + V60_R13: sprintf(info->s, "R13:%08X", cpustate->R13); break; + case CPUINFO_STR_REGISTER + V60_R14: sprintf(info->s, "R14:%08X", cpustate->R14); break; + case CPUINFO_STR_REGISTER + V60_R15: sprintf(info->s, "R15:%08X", cpustate->R15); break; + case CPUINFO_STR_REGISTER + V60_R16: sprintf(info->s, "R16:%08X", cpustate->R16); break; + case CPUINFO_STR_REGISTER + V60_R17: sprintf(info->s, "R17:%08X", cpustate->R17); break; + case CPUINFO_STR_REGISTER + V60_R18: sprintf(info->s, "R18:%08X", cpustate->R18); break; + case CPUINFO_STR_REGISTER + V60_R19: sprintf(info->s, "R19:%08X", cpustate->R19); break; + case CPUINFO_STR_REGISTER + V60_R20: sprintf(info->s, "R20:%08X", cpustate->R20); break; + case CPUINFO_STR_REGISTER + V60_R21: sprintf(info->s, "R21:%08X", cpustate->R21); break; + case CPUINFO_STR_REGISTER + V60_R22: sprintf(info->s, "R22:%08X", cpustate->R22); break; + case CPUINFO_STR_REGISTER + V60_R23: sprintf(info->s, "R23:%08X", cpustate->R23); break; + case CPUINFO_STR_REGISTER + V60_R24: sprintf(info->s, "R24:%08X", cpustate->R24); break; + case CPUINFO_STR_REGISTER + V60_R25: sprintf(info->s, "R25:%08X", cpustate->R25); break; + case CPUINFO_STR_REGISTER + V60_R26: sprintf(info->s, "R26:%08X", cpustate->R26); break; + case CPUINFO_STR_REGISTER + V60_R27: sprintf(info->s, "R27:%08X", cpustate->R27); break; + case CPUINFO_STR_REGISTER + V60_R28: sprintf(info->s, "R28:%08X", cpustate->R28); break; + case CPUINFO_STR_REGISTER + V60_AP: sprintf(info->s, "AP:%08X", cpustate->AP); break; + case CPUINFO_STR_REGISTER + V60_FP: sprintf(info->s, "FP:%08X", cpustate->FP); break; + case CPUINFO_STR_REGISTER + V60_SP: sprintf(info->s, "SP:%08X", cpustate->SP); break; + case CPUINFO_STR_REGISTER + V60_PC: sprintf(info->s, "PC:%08X", cpustate->PC); break; + case CPUINFO_STR_REGISTER + V60_PSW: sprintf(info->s, "PSW:%08X", v60ReadPSW(cpustate)); break; + case CPUINFO_STR_REGISTER + V60_ISP: sprintf(info->s, "ISP:%08X", cpustate->ISP); break; + case CPUINFO_STR_REGISTER + V60_L0SP: sprintf(info->s, "L0SP:%08X", cpustate->L0SP); break; + case CPUINFO_STR_REGISTER + V60_L1SP: sprintf(info->s, "L1SP:%08X", cpustate->L1SP); break; + case CPUINFO_STR_REGISTER + V60_L2SP: sprintf(info->s, "L2SP:%08X", cpustate->L2SP); break; + case CPUINFO_STR_REGISTER + V60_L3SP: sprintf(info->s, "L3SP:%08X", cpustate->L3SP); break; + case CPUINFO_STR_REGISTER + V60_SBR: sprintf(info->s, "SBR:%08X", cpustate->SBR); break; + case CPUINFO_STR_REGISTER + V60_TR: sprintf(info->s, "TR:%08X", cpustate->TR); break; + case CPUINFO_STR_REGISTER + V60_SYCW: sprintf(info->s, "SYCW:%08X", cpustate->SYCW); break; + case CPUINFO_STR_REGISTER + V60_TKCW: sprintf(info->s, "TKCW:%08X", cpustate->TKCW); break; + case CPUINFO_STR_REGISTER + V60_PIR: sprintf(info->s, "PIR:%08X", cpustate->PIR); break; + case CPUINFO_STR_REGISTER + V60_PSW2: sprintf(info->s, "PSW2:%08X", cpustate->PSW2); break; + case CPUINFO_STR_REGISTER + V60_ATBR0: sprintf(info->s, "ATBR0:%08X", cpustate->ATBR0); break; + case CPUINFO_STR_REGISTER + V60_ATLR0: sprintf(info->s, "ATLR0:%08X", cpustate->ATLR0); break; + case CPUINFO_STR_REGISTER + V60_ATBR1: sprintf(info->s, "ATBR1:%08X", cpustate->ATBR1); break; + case CPUINFO_STR_REGISTER + V60_ATLR1: sprintf(info->s, "ATLR1:%08X", cpustate->ATLR1); break; + case CPUINFO_STR_REGISTER + V60_ATBR2: sprintf(info->s, "ATBR2:%08X", cpustate->ATBR2); break; + case CPUINFO_STR_REGISTER + V60_ATLR2: sprintf(info->s, "ATLR2:%08X", cpustate->ATLR2); break; + case CPUINFO_STR_REGISTER + V60_ATBR3: sprintf(info->s, "ATBR3:%08X", cpustate->ATBR3); break; + case CPUINFO_STR_REGISTER + V60_ATLR3: sprintf(info->s, "ATLR3:%08X", cpustate->ATLR3); break; + case CPUINFO_STR_REGISTER + V60_TRMODE: sprintf(info->s, "TRMODE:%08X", cpustate->TRMODE); break; + case CPUINFO_STR_REGISTER + V60_ADTR0: sprintf(info->s, "ADTR0:%08X", cpustate->ADTR0); break; + case CPUINFO_STR_REGISTER + V60_ADTR1: sprintf(info->s, "ADTR1:%08X", cpustate->ADTR1); break; + case CPUINFO_STR_REGISTER + V60_ADTMR0: sprintf(info->s, "ADTMR0:%08X", cpustate->ADTMR0); break; + case CPUINFO_STR_REGISTER + V60_ADTMR1: sprintf(info->s, "ADTMR1:%08X", cpustate->ADTMR1); break; } } @@ -745,18 +745,18 @@ CPU_GET_INFO( v70 ) switch (state) { /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 32; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 32; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; + case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 32; break; + case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 32; break; + case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(v70); break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(v70); break; + case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(v70); break; + case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(v70); break; /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "V70"); break; + case CPUINFO_STR_NAME: strcpy(info->s, "V70"); break; - default: CPU_GET_INFO_CALL(v60); break; + default: CPU_GET_INFO_CALL(v60); break; } } diff --git a/src/emu/cpu/v60/v60d.c b/src/emu/cpu/v60/v60d.c index 1a181b448b2..98f953f3761 100644 --- a/src/emu/cpu/v60/v60d.c +++ b/src/emu/cpu/v60/v60d.c @@ -27,7 +27,7 @@ static const char *const v60_reg_names[69] = { static const UINT8 *rombase; static offs_t pcbase; -#define readop(a) rombase[(a) - pcbase] +#define readop(a) rombase[(a) - pcbase] static signed char read8(unsigned pc) { @@ -238,7 +238,7 @@ static int decode_AM(unsigned ipc, unsigned pc, int m, int opsize, char *out) out_AM_DisplacementIndexed(readop(pc+1)&0x1F, mod&0x1F, read32(pc+2), opsize, out); return 6; - case 3: // Register indirect indexed + case 3: // Register indirect indexed out_AM_RegisterIndirectIndexed(readop(pc+1)&0x1F, mod&0x1F, opsize, out); return 2; |