diff options
author | 2009-03-24 14:00:22 +0000 | |
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committer | 2009-03-24 14:00:22 +0000 | |
commit | 6b27889b992b1aea26b2688fd541d41dc53e99d6 (patch) | |
tree | 1842b52b552382e0df0e4bd25e63c180d899a973 /src/emu/cpu/sh4/sh4comn.c | |
parent | af6522fe8a5546a0f2f2fcce311a64673eaa75bb (diff) |
Added a preliminary implementation for the SLEEP opcode in SH-4 cpu. This fixes Quiz Keitai Q Mode booting [Angelo Salese]
Diffstat (limited to 'src/emu/cpu/sh4/sh4comn.c')
-rw-r--r-- | src/emu/cpu/sh4/sh4comn.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/emu/cpu/sh4/sh4comn.c b/src/emu/cpu/sh4/sh4comn.c index 75e0b0fae8f..bd888fcd1e8 100644 --- a/src/emu/cpu/sh4/sh4comn.c +++ b/src/emu/cpu/sh4/sh4comn.c @@ -212,6 +212,8 @@ void sh4_exception(SH4 *sh4, const char *message, int exception) // handle excep /* fetch PC */ sh4->pc = sh4->vbr + vector; + /* wake up if a sleep opcode is triggered */ + if(sh4->sleep_mode == 1) { sh4->sleep_mode = 2; } } static UINT32 compute_ticks_refresh_timer(emu_timer *timer, int hertz, int base, int divisor) @@ -644,9 +646,9 @@ WRITE32_HANDLER( sh4_internal_w ) case MMUCR: // MMU Control if (data & 1) fatalerror("SH4: MMUCR write enables MMU\n"); - + break; - + // Memory refresh case RTCSR: sh4->m[RTCSR] &= 255; |