diff options
author | 2009-12-28 09:04:00 +0000 | |
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committer | 2009-12-28 09:04:00 +0000 | |
commit | bd24fb23c10ca9fbf63e2191dc8e58a87b83b325 (patch) | |
tree | 5ba5c3cffeb38fb8f492e030130268c4bcbafb4d /src/emu/cpu/scmp | |
parent | 6763b10bf005f0bcd1ba23e440d652b31dcac447 (diff) |
Results of running the latest srcclean.
Diffstat (limited to 'src/emu/cpu/scmp')
-rw-r--r-- | src/emu/cpu/scmp/scmp.c | 62 | ||||
-rw-r--r-- | src/emu/cpu/scmp/scmpdasm.c | 50 |
2 files changed, 56 insertions, 56 deletions
diff --git a/src/emu/cpu/scmp/scmp.c b/src/emu/cpu/scmp/scmp.c index ce0ace1adf6..8781ebc6065 100644 --- a/src/emu/cpu/scmp/scmp.c +++ b/src/emu/cpu/scmp/scmp.c @@ -338,13 +338,13 @@ static void execute_one(scmp_state *cpustate, int opcode) } break; // Double-Byte Miscellaneous Instructions - case 0x8f: // DLY + case 0x8f: // DLY tmp = ARG(cpustate); cpustate->icount -= 13 + (cpustate->AC * 2) + (((UINT32)tmp) << 1) + (((UINT32)tmp) << 9); cpustate->AC = 0xff; break; // Others are illegal - default : cpustate->icount -= 1; + default : cpustate->icount -= 1; illegal (cpustate,opcode); break; } @@ -353,37 +353,37 @@ static void execute_one(scmp_state *cpustate, int opcode) switch (opcode) { // Extension Register Instructions - case 0x40: // LDE + case 0x40: // LDE cpustate->icount -= 6; cpustate->AC = cpustate->ER; break; - case 0x01: // XAE + case 0x01: // XAE cpustate->icount -= 7; tmp = cpustate->AC; cpustate->AC = cpustate->ER; cpustate->ER = tmp; break; - case 0x50: // ANE + case 0x50: // ANE cpustate->icount -= 6; cpustate->AC &= cpustate->ER; break; - case 0x58: // ORE + case 0x58: // ORE cpustate->icount -= 6; cpustate->AC |= cpustate->ER; break; - case 0x60: // XRE + case 0x60: // XRE cpustate->icount -= 6; cpustate->AC ^= cpustate->ER; break; - case 0x68: // DAE + case 0x68: // DAE cpustate->icount -= 11; DEC_ADD(cpustate,cpustate->ER); break; - case 0x70: // ADE + case 0x70: // ADE cpustate->icount -= 7; BIN_ADD(cpustate,cpustate->ER); break; - case 0x78: // CAE + case 0x78: // CAE cpustate->icount -= 8; BIN_ADD(cpustate,~cpustate->ER); break; @@ -394,14 +394,14 @@ static void execute_one(scmp_state *cpustate, int opcode) cpustate->AC = GET_PTR_REG(cpustate,ptr)->b.l; GET_PTR_REG(cpustate,ptr)->b.l = tmp; break; - case 0x34: case 0x35 :case 0x36: case 0x37: + case 0x34: case 0x35 :case 0x36: case 0x37: // XPAH cpustate->icount -= 8; tmp = cpustate->AC; cpustate->AC = GET_PTR_REG(cpustate,ptr)->b.h; GET_PTR_REG(cpustate,ptr)->b.h = tmp; break; - case 0x3c: case 0x3d :case 0x3e: case 0x3f: + case 0x3c: case 0x3d :case 0x3e: case 0x3f: // XPPC { UINT16 tmp = ADD12(cpustate->PC.w.l,-1); // Since PC is incremented we need to fix it @@ -413,70 +413,70 @@ static void execute_one(scmp_state *cpustate, int opcode) } break; // Shift, Rotate, Serial I/O Instructions - case 0x19: // SIO + case 0x19: // SIO cpustate->icount -= 5; devcb_call_write_line(&cpustate->sout_func, cpustate->ER & 0x01); cpustate->ER >>= 1; cpustate->ER |= devcb_call_read_line(&cpustate->sin_func) ? 0x80 : 0x00; break; - case 0x1c: // SR + case 0x1c: // SR cpustate->icount -= 5; cpustate->AC >>= 1; break; - case 0x1d: // SRL + case 0x1d: // SRL cpustate->icount -= 5; cpustate->AC >>= 1; cpustate->AC |= cpustate->SR & 0x80; // add C/L flag break; - case 0x1e: // RR + case 0x1e: // RR cpustate->icount -= 5; cpustate->AC = (cpustate->AC >> 1) | ((cpustate->AC & 0x01) << 7); break; - case 0x1f: // RRL + case 0x1f: // RRL cpustate->icount -= 5; tmp = (cpustate->AC & 0x01) << 7; cpustate->AC = (cpustate->AC >> 1) | (cpustate->SR & 0x80); cpustate->SR = (cpustate->SR & 0x7f) | tmp; break; // Single Byte Miscellaneous Instructions - case 0x00: // HALT + case 0x00: // HALT cpustate->icount -= 8; devcb_call_write_line(&cpustate->halt_func, 1); devcb_call_write_line(&cpustate->halt_func, 0); break; - case 0x02: // CCL + case 0x02: // CCL cpustate->icount -= 5; cpustate->SR &= 0x7f; break; - case 0x03: // SCL + case 0x03: // SCL cpustate->icount -= 5; cpustate->SR |= 0x80; break; - case 0x04: // DINT + case 0x04: // DINT cpustate->icount -= 6; cpustate->SR &= 0xf7; break; - case 0x05: // IEN + case 0x05: // IEN cpustate->icount -= 6; cpustate->SR |= 0x08; break; - case 0x06: // CSA + case 0x06: // CSA cpustate->icount -= 5; cpustate->SR &= 0xcf; // clear SA and SB flags cpustate->SR |= devcb_call_read_line(&cpustate->sensea_func) ? 0x10 : 0x00; cpustate->SR |= devcb_call_read_line(&cpustate->senseb_func) ? 0x20 : 0x00; cpustate->AC = cpustate->SR; break; - case 0x07: // CAS + case 0x07: // CAS cpustate->icount -= 6; cpustate->SR = cpustate->AC; devcb_call_write8(&cpustate->flag_out_func, 0, cpustate->SR & 0x07); break; - case 0x08: // NOP + case 0x08: // NOP cpustate->icount -= 5; break; // Others are illegal - default : cpustate->icount -= 1; + default : cpustate->icount -= 1; illegal (cpustate,opcode); break; } @@ -621,12 +621,12 @@ CPU_GET_INFO( scmp ) case CPUINFO_INT_ADDRBUS_SHIFT_PROGRAM: info->i = 0; break; case CPUINFO_INT_DATABUS_WIDTH_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT_DATA: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_WIDTH_DATA: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_SHIFT_DATA: info->i = 0; break; case CPUINFO_INT_DATABUS_WIDTH_IO: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH_IO: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT_IO: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_WIDTH_IO: info->i = 0; break; + case CPUINFO_INT_ADDRBUS_SHIFT_IO: info->i = 0; break; /* --- the following bits of info are returned as pointers to functions --- */ case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(scmp); break; @@ -649,7 +649,7 @@ CPU_GET_INFO( scmp ) case DEVINFO_STR_CREDITS: strcpy(info->s, "Copyright Miodrag Milanovic"); break; case CPUINFO_STR_FLAGS: - sprintf(info->s, "%c%c%c%c%c%c%c%c", + sprintf(info->s, "%c%c%c%c%c%c%c%c", (cpustate->SR & 0x80) ? 'C' : '.', (cpustate->SR & 0x40) ? 'V' : '.', (cpustate->SR & 0x20) ? 'B' : '.', diff --git a/src/emu/cpu/scmp/scmpdasm.c b/src/emu/cpu/scmp/scmpdasm.c index e0113efe543..2c685223fc9 100644 --- a/src/emu/cpu/scmp/scmpdasm.c +++ b/src/emu/cpu/scmp/scmpdasm.c @@ -105,7 +105,7 @@ CPU_DISASSEMBLE( scmp ) case 0x9d : case 0x9e : case 0x9f : sprintf (buffer,"jnz %s",aspr); break; // Double-Byte Miscellaneous Instructions - case 0x8f: sprintf (buffer,"dly $%02x",arg); break; + case 0x8f: sprintf (buffer,"dly $%02x",arg); break; // Others are illegal default : sprintf (buffer,"illegal"); pc--; break; // Illegal we consider without param } @@ -114,36 +114,36 @@ CPU_DISASSEMBLE( scmp ) switch (op) { // Extension Register Instructions - case 0x40: sprintf (buffer,"lde"); break; - case 0x01: sprintf (buffer,"xae"); break; - case 0x50: sprintf (buffer,"ane"); break; - case 0x58: sprintf (buffer,"ore"); break; - case 0x60: sprintf (buffer,"xre"); break; - case 0x68: sprintf (buffer,"dae"); break; - case 0x70: sprintf (buffer,"ade"); break; - case 0x78: sprintf (buffer,"cae"); break; + case 0x40: sprintf (buffer,"lde"); break; + case 0x01: sprintf (buffer,"xae"); break; + case 0x50: sprintf (buffer,"ane"); break; + case 0x58: sprintf (buffer,"ore"); break; + case 0x60: sprintf (buffer,"xre"); break; + case 0x68: sprintf (buffer,"dae"); break; + case 0x70: sprintf (buffer,"ade"); break; + case 0x78: sprintf (buffer,"cae"); break; // Pointer Register Move Instructions - case 0x30: case 0x31 :case 0x32: case 0x33: + case 0x30: case 0x31 :case 0x32: case 0x33: sprintf (buffer,"xpal %d",ptr); break; - case 0x34: case 0x35 :case 0x36: case 0x37: + case 0x34: case 0x35 :case 0x36: case 0x37: sprintf (buffer,"xpah %d",ptr); break; - case 0x3c: case 0x3d :case 0x3e: case 0x3f: + case 0x3c: case 0x3d :case 0x3e: case 0x3f: sprintf (buffer,"xppc %d",ptr); break; // Shift, Rotate, Serial I/O Instructions - case 0x19: sprintf (buffer,"sio"); break; - case 0x1c: sprintf (buffer,"sr"); break; - case 0x1d: sprintf (buffer,"srl"); break; - case 0x1e: sprintf (buffer,"rr"); break; - case 0x1f: sprintf (buffer,"rrl"); break; + case 0x19: sprintf (buffer,"sio"); break; + case 0x1c: sprintf (buffer,"sr"); break; + case 0x1d: sprintf (buffer,"srl"); break; + case 0x1e: sprintf (buffer,"rr"); break; + case 0x1f: sprintf (buffer,"rrl"); break; // Single Byte Miscellaneous Instructions - case 0x00: sprintf (buffer,"halt"); break; - case 0x02: sprintf (buffer,"ccl"); break; - case 0x03: sprintf (buffer,"scl"); break; - case 0x04: sprintf (buffer,"dint"); break; - case 0x05: sprintf (buffer,"ien"); break; - case 0x06: sprintf (buffer,"csa"); break; - case 0x07: sprintf (buffer,"cas"); break; - case 0x08: sprintf (buffer,"nop"); break; + case 0x00: sprintf (buffer,"halt"); break; + case 0x02: sprintf (buffer,"ccl"); break; + case 0x03: sprintf (buffer,"scl"); break; + case 0x04: sprintf (buffer,"dint"); break; + case 0x05: sprintf (buffer,"ien"); break; + case 0x06: sprintf (buffer,"csa"); break; + case 0x07: sprintf (buffer,"cas"); break; + case 0x08: sprintf (buffer,"nop"); break; // Others are illegal default : sprintf (buffer,"illegal"); break; } |