diff options
author | 2009-06-18 04:00:44 +0000 | |
---|---|---|
committer | 2009-06-18 04:00:44 +0000 | |
commit | cd8f2fb7ce3c6e8bd18bcce87c33b54ba6c65abf (patch) | |
tree | 08791a3ef155a6a26c7969682d034be42172baf5 /src/emu/cpu/minx | |
parent | f815d8a9ce1a367b6c01837dbf4ef079be54e417 (diff) |
From: Atari Ace [mailto:atari_ace@verizon.net]
Sent: Tuesday, June 16, 2009 7:09 AM
To: submit@mamedev.org
Cc: atariace@hotmail.com
Subject: [patch] Pointerify minx cpu
Hi mamedev,
I noticed that the minx CPU was never pointerified. It's only used by
MESS, which might be why it wasn't noticed.
~aa
Diffstat (limited to 'src/emu/cpu/minx')
-rw-r--r-- | src/emu/cpu/minx/minx.c | 221 | ||||
-rw-r--r-- | src/emu/cpu/minx/minxfunc.h | 200 | ||||
-rw-r--r-- | src/emu/cpu/minx/minxopce.h | 422 | ||||
-rw-r--r-- | src/emu/cpu/minx/minxopcf.h | 272 | ||||
-rw-r--r-- | src/emu/cpu/minx/minxops.h | 478 |
5 files changed, 803 insertions, 790 deletions
diff --git a/src/emu/cpu/minx/minx.c b/src/emu/cpu/minx/minx.c index d9ac6a0ab5d..7dd54e92621 100644 --- a/src/emu/cpu/minx/minx.c +++ b/src/emu/cpu/minx/minx.c @@ -85,23 +85,30 @@ typedef struct { cpu_irq_callback irq_callback; const device_config *device; const address_space *program; -} minx_regs; + int icount; +} minx_state; -static minx_regs regs; -static int minx_icount; +#define RD(offset) memory_read_byte_8be( minx->program, offset ) +#define WR(offset,data) memory_write_byte_8be( minx->program, offset, data ) +#define GET_MINX_PC ( ( minx->PC & 0x8000 ) ? ( minx->V << 15 ) | (minx->PC & 0x7FFF ) : minx->PC ) -#define RD(offset) memory_read_byte_8be( regs.program, offset ) -#define WR(offset,data) memory_write_byte_8be( regs.program, offset, data ) -#define GET_MINX_PC ( ( regs.PC & 0x8000 ) ? ( regs.V << 15 ) | (regs.PC & 0x7FFF ) : regs.PC ) +INLINE minx_state *get_safe_token(const device_config *device) +{ + assert(device != NULL); + assert(device->token != NULL); + assert(device->type == CPU); + assert(cpu_get_type(device) == CPU_MINX); + return (minx_state *)device->token; +} -INLINE UINT16 rd16( UINT32 offset ) +INLINE UINT16 rd16( minx_state *minx, UINT32 offset ) { return RD( offset ) | ( RD( offset + 1 ) << 8 ); } -INLINE void wr16( UINT32 offset, UINT16 data ) +INLINE void wr16( minx_state *minx, UINT32 offset, UINT16 data ) { WR( offset, ( data & 0x00FF ) ); WR( offset + 1, ( data >> 8 ) ); @@ -110,9 +117,10 @@ INLINE void wr16( UINT32 offset, UINT16 data ) static CPU_INIT( minx ) { - regs.irq_callback = irqcallback; - regs.device = device; - regs.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM); + minx_state *minx = get_safe_token(device); + minx->irq_callback = irqcallback; + minx->device = device; + minx->program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM); if ( device->static_config != NULL ) { } @@ -124,11 +132,12 @@ static CPU_INIT( minx ) static CPU_RESET( minx ) { - regs.SP = regs.BA = regs.HL = regs.X = regs.Y = 0; - regs.U = regs.V = regs.F = regs.E = regs.I = regs.XI = regs.YI = 0; - regs.halted = regs.interrupt_pending = 0; + minx_state *minx = get_safe_token(device); + minx->SP = minx->BA = minx->HL = minx->X = minx->Y = 0; + minx->U = minx->V = minx->F = minx->E = minx->I = minx->XI = minx->YI = 0; + minx->halted = minx->interrupt_pending = 0; - regs.PC = rd16( 0 ); + minx->PC = rd16( minx, 0 ); } @@ -137,18 +146,18 @@ static CPU_EXIT( minx ) } -INLINE UINT8 rdop( void ) +INLINE UINT8 rdop( minx_state *minx ) { UINT8 op = RD( GET_MINX_PC ); - regs.PC++; + minx->PC++; return op; } -INLINE UINT16 rdop16( void ) +INLINE UINT16 rdop16( minx_state *minx ) { - UINT16 op = rdop(); - op = op | ( rdop() << 8 ); + UINT16 op = rdop(minx); + op = op | ( rdop(minx) << 8 ); return op; } @@ -163,121 +172,124 @@ static CPU_EXECUTE( minx ) { UINT32 oldpc; UINT8 op; + minx_state *minx = get_safe_token(device); - minx_icount = cycles; + minx->icount = cycles; do { debugger_instruction_hook(device, GET_MINX_PC); oldpc = GET_MINX_PC; - if ( regs.interrupt_pending ) + if ( minx->interrupt_pending ) { - regs.halted = 0; - if ( ! ( regs.F & 0xc0 ) && regs.U == regs.V ) + minx->halted = 0; + if ( ! ( minx->F & 0xc0 ) && minx->U == minx->V ) { //logerror("minx_execute(): taking IRQ\n"); - PUSH8( regs.V ); - PUSH16( regs.PC ); - PUSH8( regs.F ); + PUSH8( minx, minx->V ); + PUSH16( minx, minx->PC ); + PUSH8( minx, minx->F ); /* Set Interrupt Branch flag */ - regs.F |= 0x80; - regs.V = 0; - regs.PC = rd16( regs.irq_callback( regs.device, 0 ) << 1 ); - minx_icount -= 28; /* This cycle count is a guess */ + minx->F |= 0x80; + minx->V = 0; + minx->PC = rd16( minx, minx->irq_callback( minx->device, 0 ) << 1 ); + minx->icount -= 28; /* This cycle count is a guess */ } } - if ( regs.halted ) + if ( minx->halted ) { - minx_icount -= insnminx_cycles_CE[0xAE]; + minx->icount -= insnminx_cycles_CE[0xAE]; } else { - op = rdop(); - insnminx[op](); - minx_icount -= insnminx_cycles[op]; + op = rdop(minx); + insnminx[op](minx); + minx->icount -= insnminx_cycles[op]; } - } while ( minx_icount > 0 ); - return cycles - minx_icount; + } while ( minx->icount > 0 ); + return cycles - minx->icount; } static CPU_BURN( minx ) { - minx_icount = 0; + minx_state *minx = get_safe_token(device); + minx->icount = 0; } -static unsigned minx_get_reg( int regnum ) +static unsigned minx_get_reg( minx_state *minx, int regnum ) { switch( regnum ) { case REG_GENPC: return GET_MINX_PC; - case MINX_PC: return regs.PC; + case MINX_PC: return minx->PC; case REG_GENSP: - case MINX_SP: return regs.SP; - case MINX_BA: return regs.BA; - case MINX_HL: return regs.HL; - case MINX_X: return regs.X; - case MINX_Y: return regs.Y; - case MINX_U: return regs.U; - case MINX_V: return regs.V; - case MINX_F: return regs.F; - case MINX_E: return regs.E; - case MINX_N: return regs.N; - case MINX_I: return regs.I; - case MINX_XI: return regs.XI; - case MINX_YI: return regs.YI; + case MINX_SP: return minx->SP; + case MINX_BA: return minx->BA; + case MINX_HL: return minx->HL; + case MINX_X: return minx->X; + case MINX_Y: return minx->Y; + case MINX_U: return minx->U; + case MINX_V: return minx->V; + case MINX_F: return minx->F; + case MINX_E: return minx->E; + case MINX_N: return minx->N; + case MINX_I: return minx->I; + case MINX_XI: return minx->XI; + case MINX_YI: return minx->YI; } return 0; } -static void minx_set_reg( int regnum, unsigned val ) +static void minx_set_reg( minx_state *minx, int regnum, unsigned val ) { switch( regnum ) { case REG_GENPC: break; - case MINX_PC: regs.PC = val; break; + case MINX_PC: minx->PC = val; break; case REG_GENSP: - case MINX_SP: regs.SP = val; break; - case MINX_BA: regs.BA = val; break; - case MINX_HL: regs.HL = val; break; - case MINX_X: regs.X = val; break; - case MINX_Y: regs.Y = val; break; - case MINX_U: regs.U = val; break; - case MINX_V: regs.V = val; break; - case MINX_F: regs.F = val; break; - case MINX_E: regs.E = val; break; - case MINX_N: regs.N = val; break; - case MINX_I: regs.I = val; break; - case MINX_XI: regs.XI = val; break; - case MINX_YI: regs.YI = val; break; + case MINX_SP: minx->SP = val; break; + case MINX_BA: minx->BA = val; break; + case MINX_HL: minx->HL = val; break; + case MINX_X: minx->X = val; break; + case MINX_Y: minx->Y = val; break; + case MINX_U: minx->U = val; break; + case MINX_V: minx->V = val; break; + case MINX_F: minx->F = val; break; + case MINX_E: minx->E = val; break; + case MINX_N: minx->N = val; break; + case MINX_I: minx->I = val; break; + case MINX_XI: minx->XI = val; break; + case MINX_YI: minx->YI = val; break; } } -static void minx_set_irq_line( int irqline, int state ) +static void minx_set_irq_line( minx_state *minx, int irqline, int state ) { if ( state == ASSERT_LINE ) { - regs.interrupt_pending = 1; + minx->interrupt_pending = 1; } else { - regs.interrupt_pending = 0; + minx->interrupt_pending = 0; } } static CPU_SET_INFO( minx ) { + minx_state *minx = get_safe_token(device); switch( state ) { case CPUINFO_INT_INPUT_STATE + 0: - minx_set_irq_line( state - CPUINFO_INT_INPUT_STATE, info->i ); break; + minx_set_irq_line( minx, state - CPUINFO_INT_INPUT_STATE, info->i ); break; case CPUINFO_INT_REGISTER + MINX_PC: case CPUINFO_INT_REGISTER + MINX_SP: @@ -293,16 +305,17 @@ static CPU_SET_INFO( minx ) case CPUINFO_INT_REGISTER + MINX_I: case CPUINFO_INT_REGISTER + MINX_XI: case CPUINFO_INT_REGISTER + MINX_YI: - minx_set_reg( state - CPUINFO_INT_REGISTER, info->i ); break; + minx_set_reg( minx, state - CPUINFO_INT_REGISTER, info->i ); break; } } CPU_GET_INFO( minx ) { + minx_state *minx = (device != NULL && device->token != NULL) ? get_safe_token(device) : NULL; switch( state ) { - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(minx_regs); break; + case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(minx_state); break; case CPUINFO_INT_INPUT_LINES: info->i = 1; break; case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0x00; break; case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; @@ -337,7 +350,7 @@ CPU_GET_INFO( minx ) case CPUINFO_INT_REGISTER + MINX_N: case CPUINFO_INT_REGISTER + MINX_I: case CPUINFO_INT_REGISTER + MINX_XI: - case CPUINFO_INT_REGISTER + MINX_YI: info->i = minx_get_reg( state - CPUINFO_INT_REGISTER ); break; + case CPUINFO_INT_REGISTER + MINX_YI: info->i = minx_get_reg( minx, state - CPUINFO_INT_REGISTER ); break; case CPUINFO_INT_PREVIOUSPC: info->i = 0x0000; break; case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(minx); break; case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(minx); break; @@ -346,7 +359,7 @@ CPU_GET_INFO( minx ) case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(minx); break; case CPUINFO_FCT_BURN: info->burn = CPU_BURN_NAME(minx); break; case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(minx); break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &minx_icount; break; + case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &minx->icount; break; case CPUINFO_STR_NAME: strcpy( info->s, "Minx" ); break; case CPUINFO_STR_CORE_FAMILY: strcpy( info->s, "Nintendo Minx" ); break; case CPUINFO_STR_CORE_VERSION: strcpy( info->s, "0.1" ); break; @@ -354,34 +367,34 @@ CPU_GET_INFO( minx ) case CPUINFO_STR_CORE_CREDITS: strcpy( info->s, "Copyright The MESS Team." ); break; case CPUINFO_STR_FLAGS: sprintf( info->s, "%c%c%c%c%c%c%c%c-%c%c%c%c%c", - regs.F & FLAG_I ? 'I' : '.', - regs.F & FLAG_D ? 'D' : '.', - regs.F & FLAG_L ? 'L' : '.', - regs.F & FLAG_B ? 'B' : '.', - regs.F & FLAG_S ? 'S' : '.', - regs.F & FLAG_O ? 'O' : '.', - regs.F & FLAG_C ? 'C' : '.', - regs.F & FLAG_Z ? 'Z' : '.', - regs.E & EXEC_X0 ? '0' : '.', - regs.E & EXEC_X1 ? '1' : '.', - regs.E & EXEC_X2 ? '2' : '.', - regs.E & EXEC_DZ ? 'z' : '.', - regs.E & EXEC_EN ? 'E' : '.' ); + minx->F & FLAG_I ? 'I' : '.', + minx->F & FLAG_D ? 'D' : '.', + minx->F & FLAG_L ? 'L' : '.', + minx->F & FLAG_B ? 'B' : '.', + minx->F & FLAG_S ? 'S' : '.', + minx->F & FLAG_O ? 'O' : '.', + minx->F & FLAG_C ? 'C' : '.', + minx->F & FLAG_Z ? 'Z' : '.', + minx->E & EXEC_X0 ? '0' : '.', + minx->E & EXEC_X1 ? '1' : '.', + minx->E & EXEC_X2 ? '2' : '.', + minx->E & EXEC_DZ ? 'z' : '.', + minx->E & EXEC_EN ? 'E' : '.' ); break; - case CPUINFO_STR_REGISTER + MINX_PC: sprintf( info->s, "PC:%04X", regs.PC ); break; - case CPUINFO_STR_REGISTER + MINX_SP: sprintf( info->s, "SP:%04X", regs.SP ); break; - case CPUINFO_STR_REGISTER + MINX_BA: sprintf( info->s, "BA:%04X", regs.BA ); break; - case CPUINFO_STR_REGISTER + MINX_HL: sprintf( info->s, "HL:%04X", regs.HL ); break; - case CPUINFO_STR_REGISTER + MINX_X: sprintf( info->s, "X:%04X", regs.X ); break; - case CPUINFO_STR_REGISTER + MINX_Y: sprintf( info->s, "Y:%04X", regs.Y ); break; - case CPUINFO_STR_REGISTER + MINX_U: sprintf( info->s, "U:%02X", regs.U ); break; - case CPUINFO_STR_REGISTER + MINX_V: sprintf( info->s, "V:%02X", regs.V ); break; - case CPUINFO_STR_REGISTER + MINX_F: sprintf( info->s, "F:%02X", regs.F ); break; - case CPUINFO_STR_REGISTER + MINX_E: sprintf( info->s, "E:%02X", regs.E ); break; - case CPUINFO_STR_REGISTER + MINX_N: sprintf( info->s, "N:%02X", regs.N ); break; - case CPUINFO_STR_REGISTER + MINX_I: sprintf( info->s, "I:%02X", regs.I ); break; - case CPUINFO_STR_REGISTER + MINX_XI: sprintf( info->s, "XI:%02X", regs.XI ); break; - case CPUINFO_STR_REGISTER + MINX_YI: sprintf( info->s, "YI:%02X", regs.YI ); break; + case CPUINFO_STR_REGISTER + MINX_PC: sprintf( info->s, "PC:%04X", minx->PC ); break; + case CPUINFO_STR_REGISTER + MINX_SP: sprintf( info->s, "SP:%04X", minx->SP ); break; + case CPUINFO_STR_REGISTER + MINX_BA: sprintf( info->s, "BA:%04X", minx->BA ); break; + case CPUINFO_STR_REGISTER + MINX_HL: sprintf( info->s, "HL:%04X", minx->HL ); break; + case CPUINFO_STR_REGISTER + MINX_X: sprintf( info->s, "X:%04X", minx->X ); break; + case CPUINFO_STR_REGISTER + MINX_Y: sprintf( info->s, "Y:%04X", minx->Y ); break; + case CPUINFO_STR_REGISTER + MINX_U: sprintf( info->s, "U:%02X", minx->U ); break; + case CPUINFO_STR_REGISTER + MINX_V: sprintf( info->s, "V:%02X", minx->V ); break; + case CPUINFO_STR_REGISTER + MINX_F: sprintf( info->s, "F:%02X", minx->F ); break; + case CPUINFO_STR_REGISTER + MINX_E: sprintf( info->s, "E:%02X", minx->E ); break; + case CPUINFO_STR_REGISTER + MINX_N: sprintf( info->s, "N:%02X", minx->N ); break; + case CPUINFO_STR_REGISTER + MINX_I: sprintf( info->s, "I:%02X", minx->I ); break; + case CPUINFO_STR_REGISTER + MINX_XI: sprintf( info->s, "XI:%02X", minx->XI ); break; + case CPUINFO_STR_REGISTER + MINX_YI: sprintf( info->s, "YI:%02X", minx->YI ); break; } } diff --git a/src/emu/cpu/minx/minxfunc.h b/src/emu/cpu/minx/minxfunc.h index 1bce11a73aa..1716418def1 100644 --- a/src/emu/cpu/minx/minxfunc.h +++ b/src/emu/cpu/minx/minxfunc.h @@ -1,7 +1,7 @@ -INLINE UINT8 ADD8( UINT8 arg1, UINT8 arg2 ) +INLINE UINT8 ADD8( minx_state *minx, UINT8 arg1, UINT8 arg2 ) { UINT32 res = arg1 + arg2; - regs.F = ( regs.F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) ) + minx->F = ( minx->F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) ) | ( ( res & 0x80 ) ? FLAG_S : 0 ) | ( ( ( arg2 ^ arg1 ^ 0x80 ) & ( arg2 ^ res ) & 0x80 ) ? FLAG_O : 0 ) | ( ( res & 0xFF00 ) ? FLAG_C : 0 ) @@ -11,10 +11,10 @@ INLINE UINT8 ADD8( UINT8 arg1, UINT8 arg2 ) } -INLINE UINT16 ADD16( UINT16 arg1, UINT16 arg2 ) +INLINE UINT16 ADD16( minx_state *minx, UINT16 arg1, UINT16 arg2 ) { UINT32 res = arg1 + arg2; - regs.F = ( regs.F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) ) + minx->F = ( minx->F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) ) | ( ( res & 0x8000 ) ? FLAG_S : 0 ) | ( ( ( arg2 ^ arg1 ^ 0x8000 ) & ( arg2 ^ res ) & 0x8000 ) ? FLAG_O : 0 ) | ( ( res & 0xFF0000 ) ? FLAG_C : 0 ) @@ -24,10 +24,10 @@ INLINE UINT16 ADD16( UINT16 arg1, UINT16 arg2 ) } -INLINE UINT8 ADDC8( UINT8 arg1, UINT8 arg2 ) +INLINE UINT8 ADDC8( minx_state *minx, UINT8 arg1, UINT8 arg2 ) { - UINT32 res = arg1 + arg2 + ( ( regs.F & FLAG_C ) ? 1 : 0 ); - regs.F = ( regs.F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) ) + UINT32 res = arg1 + arg2 + ( ( minx->F & FLAG_C ) ? 1 : 0 ); + minx->F = ( minx->F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) ) | ( ( res & 0x80 ) ? FLAG_S : 0 ) | ( ( ( arg2 ^ arg1 ^ 0x80 ) & ( arg2 ^ res ) & 0x80 ) ? FLAG_O : 0 ) | ( ( res & 0xFF00 ) ? FLAG_C : 0 ) @@ -37,10 +37,10 @@ INLINE UINT8 ADDC8( UINT8 arg1, UINT8 arg2 ) } -INLINE UINT16 ADDC16( UINT16 arg1, UINT16 arg2 ) +INLINE UINT16 ADDC16( minx_state *minx, UINT16 arg1, UINT16 arg2 ) { - UINT32 res = arg1 + arg2 + ( ( regs.F & FLAG_C ) ? 1 : 0 ); - regs.F = ( regs.F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) ) + UINT32 res = arg1 + arg2 + ( ( minx->F & FLAG_C ) ? 1 : 0 ); + minx->F = ( minx->F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) ) | ( ( res & 0x8000 ) ? FLAG_S : 0 ) | ( ( ( arg2 ^ arg1 ^ 0x8000 ) & ( arg2 ^ res ) & 0x8000 ) ? FLAG_O : 0 ) | ( ( res & 0xFF0000 ) ? FLAG_C : 0 ) @@ -50,32 +50,32 @@ INLINE UINT16 ADDC16( UINT16 arg1, UINT16 arg2 ) } -INLINE UINT8 INC8( UINT8 arg ) +INLINE UINT8 INC8( minx_state *minx, UINT8 arg ) { - UINT8 old_F = regs.F; - UINT8 res = ADD8( arg, 1 ); - regs.F = ( old_F & ~ ( FLAG_Z ) ) + UINT8 old_F = minx->F; + UINT8 res = ADD8( minx, arg, 1 ); + minx->F = ( old_F & ~ ( FLAG_Z ) ) | ( ( res ) ? 0 : FLAG_Z ) ; return res; } -INLINE UINT16 INC16( UINT16 arg ) +INLINE UINT16 INC16( minx_state *minx, UINT16 arg ) { - UINT8 old_F = regs.F; - UINT16 res = ADD16( arg, 1 ); - regs.F = ( old_F & ~ ( FLAG_Z ) ) + UINT8 old_F = minx->F; + UINT16 res = ADD16( minx, arg, 1 ); + minx->F = ( old_F & ~ ( FLAG_Z ) ) | ( ( res ) ? 0 : FLAG_Z ) ; return res; } -INLINE UINT8 SUB8( UINT8 arg1, UINT8 arg2 ) +INLINE UINT8 SUB8( minx_state *minx, UINT8 arg1, UINT8 arg2 ) { UINT32 res = arg1 - arg2; - regs.F = ( regs.F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) ) + minx->F = ( minx->F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) ) | ( ( res & 0x80 ) ? FLAG_S : 0 ) | ( ( ( arg2 ^ arg1 ) & ( arg1 ^ res ) & 0x80 ) ? FLAG_O : 0 ) | ( ( res & 0xFF00 ) ? FLAG_C : 0 ) @@ -85,10 +85,10 @@ INLINE UINT8 SUB8( UINT8 arg1, UINT8 arg2 ) } -INLINE UINT16 SUB16( UINT16 arg1, UINT16 arg2 ) +INLINE UINT16 SUB16( minx_state *minx, UINT16 arg1, UINT16 arg2 ) { UINT32 res = arg1 - arg2; - regs.F = ( regs.F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) ) + minx->F = ( minx->F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) ) | ( ( res & 0x8000 ) ? FLAG_S : 0 ) | ( ( ( arg2 ^ arg1 ) & ( arg1 ^ res ) & 0x8000 ) ? FLAG_O : 0 ) | ( ( res & 0xFF0000 ) ? FLAG_C : 0 ) @@ -98,10 +98,10 @@ INLINE UINT16 SUB16( UINT16 arg1, UINT16 arg2 ) } -INLINE UINT8 SUBC8( UINT8 arg1, UINT8 arg2 ) +INLINE UINT8 SUBC8( minx_state *minx, UINT8 arg1, UINT8 arg2 ) { - UINT32 res = arg1 - arg2 - ( ( regs.F & FLAG_C ) ? 1 : 0 ); - regs.F = ( regs.F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) ) + UINT32 res = arg1 - arg2 - ( ( minx->F & FLAG_C ) ? 1 : 0 ); + minx->F = ( minx->F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) ) | ( ( res & 0x80 ) ? FLAG_S : 0 ) | ( ( ( arg2 ^ arg1 ) & ( arg1 ^ res ) & 0x80 ) ? FLAG_O : 0 ) | ( ( res & 0xFF00 ) ? FLAG_C : 0 ) @@ -111,10 +111,10 @@ INLINE UINT8 SUBC8( UINT8 arg1, UINT8 arg2 ) } -INLINE UINT16 SUBC16( UINT16 arg1, UINT16 arg2 ) +INLINE UINT16 SUBC16( minx_state *minx, UINT16 arg1, UINT16 arg2 ) { - UINT32 res = arg1 - arg2 - ( ( regs.F & FLAG_C ) ? 1 : 0 ); - regs.F = ( regs.F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) ) + UINT32 res = arg1 - arg2 - ( ( minx->F & FLAG_C ) ? 1 : 0 ); + minx->F = ( minx->F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) ) | ( ( res & 0x8000 ) ? FLAG_S : 0 ) | ( ( ( arg2 ^ arg1 ) & ( arg1 ^ res ) & 0x8000 ) ? FLAG_O : 0 ) | ( ( res & 0xFF0000 ) ? FLAG_C : 0 ) @@ -124,32 +124,32 @@ INLINE UINT16 SUBC16( UINT16 arg1, UINT16 arg2 ) } -INLINE UINT8 DEC8( UINT8 arg ) +INLINE UINT8 DEC8( minx_state *minx, UINT8 arg ) { - UINT8 old_F = regs.F; - UINT8 res = SUB8( arg, 1 ); - regs.F = ( old_F & ~ ( FLAG_Z ) ) + UINT8 old_F = minx->F; + UINT8 res = SUB8( minx, arg, 1 ); + minx->F = ( old_F & ~ ( FLAG_Z ) ) | ( ( res ) ? 0 : FLAG_Z ) ; return res; } -INLINE UINT16 DEC16( UINT16 arg ) +INLINE UINT16 DEC16( minx_state *minx, UINT16 arg ) { - UINT8 old_F = regs.F; - UINT16 res = SUB16( arg, 1 ); - regs.F = ( old_F & ~ ( FLAG_Z ) ) + UINT8 old_F = minx->F; + UINT16 res = SUB16( minx, arg, 1 ); + minx->F = ( old_F & ~ ( FLAG_Z ) ) | ( ( res ) ? 0 : FLAG_Z ) ; return res; } -INLINE UINT8 AND8( UINT8 arg1, UINT8 arg2 ) +INLINE UINT8 AND8( minx_state *minx, UINT8 arg1, UINT8 arg2 ) { UINT8 res = arg1 & arg2; - regs.F = ( regs.F & ~ ( FLAG_S | FLAG_Z ) ) + minx->F = ( minx->F & ~ ( FLAG_S | FLAG_Z ) ) | ( ( res & 0x80 ) ? FLAG_S : 0 ) | ( ( res ) ? 0 : FLAG_Z ) ; @@ -157,10 +157,10 @@ INLINE UINT8 AND8( UINT8 arg1, UINT8 arg2 ) } -INLINE UINT8 OR8( UINT8 arg1, UINT8 arg2 ) +INLINE UINT8 OR8( minx_state *minx, UINT8 arg1, UINT8 arg2 ) { UINT8 res = arg1 | arg2; - regs.F = ( regs.F & ~ ( FLAG_S | FLAG_Z ) ) + minx->F = ( minx->F & ~ ( FLAG_S | FLAG_Z ) ) | ( ( res & 0x80 ) ? FLAG_S : 0 ) | ( ( res ) ? 0 : FLAG_Z ) ; @@ -168,10 +168,10 @@ INLINE UINT8 OR8( UINT8 arg1, UINT8 arg2 ) } -INLINE UINT8 XOR8( UINT8 arg1, UINT8 arg2 ) +INLINE UINT8 XOR8( minx_state *minx, UINT8 arg1, UINT8 arg2 ) { UINT8 res = arg1 ^ arg2; - regs.F = ( regs.F & ~ ( FLAG_S | FLAG_Z ) ) + minx->F = ( minx->F & ~ ( FLAG_S | FLAG_Z ) ) | ( ( res & 0x80 ) ? FLAG_S : 0 ) | ( ( res ) ? 0 : FLAG_Z ) ; @@ -179,10 +179,10 @@ INLINE UINT8 XOR8( UINT8 arg1, UINT8 arg2 ) } -INLINE UINT8 NOT8( UINT8 arg ) +INLINE UINT8 NOT8( minx_state *minx, UINT8 arg ) { UINT8 res = ~arg; - regs.F = ( regs.F & ~ ( FLAG_S | FLAG_Z ) ) + minx->F = ( minx->F & ~ ( FLAG_S | FLAG_Z ) ) | ( ( res & 0x80 ) ? FLAG_S : 0 ) | ( ( res ) ? 0 : FLAG_Z ) ; @@ -190,10 +190,10 @@ INLINE UINT8 NOT8( UINT8 arg ) } -INLINE UINT8 NEG8( UINT8 arg ) +INLINE UINT8 NEG8( minx_state *minx, UINT8 arg ) { UINT8 res = -arg; - regs.F = ( regs.F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) ) + minx->F = ( minx->F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) ) | ( ( res & 0x80 ) ? FLAG_S : 0 ) | ( ( res ) ? 0 : FLAG_Z ) ; @@ -201,10 +201,10 @@ INLINE UINT8 NEG8( UINT8 arg ) } -INLINE UINT8 SAL8( UINT8 arg ) +INLINE UINT8 SAL8( minx_state *minx, UINT8 arg ) { UINT16 res = arg << 1; - regs.F = ( regs.F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) ) + minx->F = ( minx->F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) ) | ( ( res & 0x80 ) ? FLAG_S : 0 ) | ( ( arg != 0 && res == 0 ) ? FLAG_O : 0 ) | ( ( arg & 0x80 ) ? FLAG_C : 0 ) @@ -214,10 +214,10 @@ INLINE UINT8 SAL8( UINT8 arg ) } -INLINE UINT8 SAR8( UINT8 arg ) +INLINE UINT8 SAR8( minx_state *minx, UINT8 arg ) { UINT16 res = ( arg >> 1 ) | ( arg & 0x80 ); - regs.F = ( regs.F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) ) + minx->F = ( minx->F & ~ ( FLAG_S | FLAG_O | FLAG_C | FLAG_Z ) ) | ( ( res & 0x80 ) ? FLAG_S : 0 ) | ( ( arg != 0x80 && res == 0x80 ) ? FLAG_O : 0 ) | ( ( arg & 0x01 ) ? FLAG_C : 0 ) @@ -227,10 +227,10 @@ INLINE UINT8 SAR8( UINT8 arg ) } -INLINE UINT8 SHL8( UINT8 arg ) +INLINE UINT8 SHL8( minx_state *minx, UINT8 arg ) { UINT16 res = arg << 1; - regs.F = ( regs.F & ~ ( FLAG_S | FLAG_C | FLAG_Z ) ) + minx->F = ( minx->F & ~ ( FLAG_S | FLAG_C | FLAG_Z ) ) | ( ( res & 0x80 ) ? FLAG_S : 0 ) | ( ( arg & 0x80 ) ? FLAG_C : 0 ) | ( ( res ) ? 0 : FLAG_Z ) @@ -239,10 +239,10 @@ INLINE UINT8 SHL8( UINT8 arg ) } -INLINE UINT8 SHR8( UINT8 arg ) +INLINE UINT8 SHR8( minx_state *minx, UINT8 arg ) { UINT16 res = arg >> 1; - regs.F = ( regs.F & ~ ( FLAG_S | FLAG_C | FLAG_Z ) ) + minx->F = ( minx->F & ~ ( FLAG_S | FLAG_C | FLAG_Z ) ) | ( ( res & 0x80 ) ? FLAG_S : 0 ) | ( ( arg & 0x01 ) ? FLAG_C : 0 ) | ( ( res ) ? 0 : FLAG_Z ) @@ -251,10 +251,10 @@ INLINE UINT8 SHR8( UINT8 arg ) } -INLINE UINT8 ROLC8( UINT8 arg ) +INLINE UINT8 ROLC8( minx_state *minx, UINT8 arg ) { - UINT16 res = ( arg << 1 ) | ( ( regs.F & FLAG_C ) ? 1 : 0 ); - regs.F = ( regs.F & ~ ( FLAG_S | FLAG_C | FLAG_Z ) ) + UINT16 res = ( arg << 1 ) | ( ( minx->F & FLAG_C ) ? 1 : 0 ); + minx->F = ( minx->F & ~ ( FLAG_S | FLAG_C | FLAG_Z ) ) | ( ( res & 0x80 ) ? FLAG_S : 0 ) | ( ( arg & 0x80 ) ? FLAG_C : 0 ) | ( ( res ) ? 0 : FLAG_Z ) @@ -263,10 +263,10 @@ INLINE UINT8 ROLC8( UINT8 arg ) } -INLINE UINT8 RORC8( UINT8 arg ) +INLINE UINT8 RORC8( minx_state *minx, UINT8 arg ) { - UINT16 res = ( arg >> 1 ) | ( ( regs.F & FLAG_C ) ? 0x80 : 0 ); - regs.F = ( regs.F & ~ ( FLAG_S | FLAG_C | FLAG_Z ) ) + UINT16 res = ( arg >> 1 ) | ( ( minx->F & FLAG_C ) ? 0x80 : 0 ); + minx->F = ( minx->F & ~ ( FLAG_S | FLAG_C | FLAG_Z ) ) | ( ( res & 0x80 ) ? FLAG_S : 0 ) | ( ( arg & 0x01 ) ? FLAG_C : 0 ) | ( ( res ) ? 0 : FLAG_Z ) @@ -275,10 +275,10 @@ INLINE UINT8 RORC8( UINT8 arg ) } -INLINE UINT8 ROL8( UINT8 arg ) +INLINE UINT8 ROL8( minx_state *minx, UINT8 arg ) { UINT16 res = ( arg << 1 ) | ( ( arg & 0x80 ) ? 1 : 0 ); - regs.F = ( regs.F & ~ ( FLAG_S | FLAG_C | FLAG_Z ) ) + minx->F = ( minx->F & ~ ( FLAG_S | FLAG_C | FLAG_Z ) ) | ( ( res & 0x80 ) ? FLAG_S : 0 ) | ( ( arg & 0x80 ) ? FLAG_C : 0 ) | ( ( res ) ? 0 : FLAG_Z ) @@ -287,10 +287,10 @@ INLINE UINT8 ROL8( UINT8 arg ) } -INLINE UINT8 ROR8( UINT8 arg ) +INLINE UINT8 ROR8( minx_state *minx, UINT8 arg ) { UINT16 res = ( arg >> 1 ) | ( ( arg & 0x01 ) ? 0x80 : 0 ); - regs.F = ( regs.F & ~ ( FLAG_S | FLAG_C | FLAG_Z ) ) + minx->F = ( minx->F & ~ ( FLAG_S | FLAG_C | FLAG_Z ) ) | ( ( res & 0x80 ) ? FLAG_S : 0 ) | ( ( arg & 0x01 ) ? FLAG_C : 0 ) | ( ( res ) ? 0 : FLAG_Z ) @@ -299,64 +299,64 @@ INLINE UINT8 ROR8( UINT8 arg ) } -INLINE void PUSH8( UINT8 arg ) +INLINE void PUSH8( minx_state *minx, UINT8 arg ) { - regs.SP = regs.SP - 1; - WR( regs.SP, arg ); + minx->SP = minx->SP - 1; + WR( minx->SP, arg ); } -INLINE void PUSH16( UINT16 arg ) +INLINE void PUSH16( minx_state *minx, UINT16 arg ) { - PUSH8( arg >> 8 ); - PUSH8( arg & 0x00FF ); + PUSH8( minx, arg >> 8 ); + PUSH8( minx, arg & 0x00FF ); } -INLINE UINT8 POP8( void ) +INLINE UINT8 POP8( minx_state *minx ) { - UINT8 res = RD( regs.SP ); - regs.SP = regs.SP + 1; + UINT8 res = RD( minx->SP ); + minx->SP = minx->SP + 1; return res; } -INLINE UINT16 POP16( void ) +INLINE UINT16 POP16( minx_state *minx ) { - return POP8() | ( POP8() << 8 ); + return POP8(minx) | ( POP8(minx) << 8 ); } -INLINE void JMP( UINT16 arg ) +INLINE void JMP( minx_state *minx, UINT16 arg ) { - regs.V = regs.U; - regs.PC = arg; + minx->V = minx->U; + minx->PC = arg; } -INLINE void CALL( UINT16 arg ) +INLINE void CALL( minx_state *minx, UINT16 arg ) { - PUSH8( regs.V ); - PUSH16( regs.PC ); - JMP( arg ); + PUSH8( minx, minx->V ); + PUSH16( minx, minx->PC ); + JMP( minx, arg ); } -#define AD1_IHL UINT32 addr1 = ( regs.I << 16 ) | regs.HL -#define AD1_IN8 UINT32 addr1 = ( regs.I << 16 ) | ( regs.N << 8 ) | rdop() -#define AD1_I16 UINT32 addr1 = ( regs.I << 16 ) | rdop16() -#define AD1_XIX UINT32 addr1 = ( regs.XI << 16 ) | regs.X -#define AD1_YIY UINT32 addr1 = ( regs.YI << 16 ) | regs.Y -#define AD1_X8 UINT32 addr1 = ( regs.XI << 16 ) | ( regs.X + rdop() ) -#define AD1_Y8 UINT32 addr1 = ( regs.YI << 16 ) | ( regs.Y + rdop() ) -#define AD1_XL UINT32 addr1 = ( regs.XI << 16 ) | ( regs.X + ( regs.HL & 0x00FF ) ) -#define AD1_YL UINT32 addr1 = ( regs.YI << 16 ) | ( regs.Y + ( regs.HL & 0x00FF ) ) -#define AD2_IHL UINT32 addr2 = ( regs.I << 16 ) | regs.HL -#define AD2_IN8 UINT32 addr2 = ( regs.I << 16 ) | ( regs.N << 8 ) | rdop() -#define AD2_I16 UINT32 addr2 = ( regs.I << 16 ) | rdop(); addr2 |= ( rdop() << 8 ) -#define AD2_XIX UINT32 addr2 = ( regs.XI << 16 ) | regs.X -#define AD2_YIY UINT32 addr2 = ( regs.YI << 16 ) | regs.Y -#define AD2_X8 UINT32 addr2 = ( regs.XI << 16 ) | ( regs.X + rdop() ) -#define AD2_Y8 UINT32 addr2 = ( regs.YI << 16 ) | ( regs.Y + rdop() ) -#define AD2_XL UINT32 addr2 = ( regs.XI << 16 ) | ( regs.X + ( regs.HL & 0x00FF ) ) -#define AD2_YL UINT32 addr2 = ( regs.YI << 16 ) | ( regs.Y + ( regs.HL & 0x00FF ) ) +#define AD1_IHL UINT32 addr1 = ( minx->I << 16 ) | minx->HL +#define AD1_IN8 UINT32 addr1 = ( minx->I << 16 ) | ( minx->N << 8 ) | rdop(minx) +#define AD1_I16 UINT32 addr1 = ( minx->I << 16 ) | rdop16(minx) +#define AD1_XIX UINT32 addr1 = ( minx->XI << 16 ) | minx->X +#define AD1_YIY UINT32 addr1 = ( minx->YI << 16 ) | minx->Y +#define AD1_X8 UINT32 addr1 = ( minx->XI << 16 ) | ( minx->X + rdop(minx) ) +#define AD1_Y8 UINT32 addr1 = ( minx->YI << 16 ) | ( minx->Y + rdop(minx) ) +#define AD1_XL UINT32 addr1 = ( minx->XI << 16 ) | ( minx->X + ( minx->HL & 0x00FF ) ) +#define AD1_YL UINT32 addr1 = ( minx->YI << 16 ) | ( minx->Y + ( minx->HL & 0x00FF ) ) +#define AD2_IHL UINT32 addr2 = ( minx->I << 16 ) | minx->HL +#define AD2_IN8 UINT32 addr2 = ( minx->I << 16 ) | ( minx->N << 8 ) | rdop(minx) +#define AD2_I16 UINT32 addr2 = ( minx->I << 16 ) | rdop(minx); addr2 |= ( rdop(minx) << 8 ) +#define AD2_XIX UINT32 addr2 = ( minx->XI << 16 ) | minx->X +#define AD2_YIY UINT32 addr2 = ( minx->YI << 16 ) | minx->Y +#define AD2_X8 UINT32 addr2 = ( minx->XI << 16 ) | ( minx->X + rdop(minx) ) +#define AD2_Y8 UINT32 addr2 = ( minx->YI << 16 ) | ( minx->Y + rdop(minx) ) +#define AD2_XL UINT32 addr2 = ( minx->XI << 16 ) | ( minx->X + ( minx->HL & 0x00FF ) ) +#define AD2_YL UINT32 addr2 = ( minx->YI << 16 ) | ( minx->Y + ( minx->HL & 0x00FF ) ) diff --git a/src/emu/cpu/minx/minxopce.h b/src/emu/cpu/minx/minxopce.h index 830b34e3ae9..282dccb3fab 100644 --- a/src/emu/cpu/minx/minxopce.h +++ b/src/emu/cpu/minx/minxopce.h @@ -1,107 +1,107 @@ #undef OP -#define OP(nn) INLINE void minx_CE_##nn(void) +#define OP(nn) INLINE void minx_CE_##nn(minx_state *minx) -OP(00) { AD2_X8; regs.BA = ( regs.BA & 0xFF00 ) | ADD8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(01) { AD2_Y8; regs.BA = ( regs.BA & 0xFF00 ) | ADD8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(02) { AD2_XL; regs.BA = ( regs.BA & 0xFF00 ) | ADD8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(03) { AD2_YL; regs.BA = ( regs.BA & 0xFF00 ) | ADD8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(04) { AD1_IHL; WR( addr1, ADD8( RD( addr1 ), ( regs.BA & 0x00FF ) ) ); } -OP(05) { AD1_IHL; WR( addr1, ADD8( RD( addr1 ), rdop() ) ); } -OP(06) { AD1_IHL; AD2_XIX; WR( addr1, ADD8( RD( addr1 ), RD( addr2 ) ) ); } -OP(07) { AD1_IHL; AD2_YIY; WR( addr1, ADD8( RD( addr1 ), RD( addr2 ) ) ); } -OP(08) { AD2_X8; regs.BA = ( regs.BA & 0xFF00 ) | ADDC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(09) { AD2_Y8; regs.BA = ( regs.BA & 0xFF00 ) | ADDC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(0A) { AD2_XL; regs.BA = ( regs.BA & 0xFF00 ) | ADDC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(0B) { AD2_YL; regs.BA = ( regs.BA & 0xFF00 ) | ADDC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(0C) { AD1_IHL; WR( addr1, ADDC8( RD( addr1 ), ( regs.BA & 0x00FF ) ) ); } -OP(0D) { AD1_IHL; WR( addr1, ADDC8( RD( addr1 ), rdop() ) ); } -OP(0E) { AD1_IHL; AD2_XIX; WR( addr1, ADDC8( RD( addr1 ), RD( addr2 ) ) ); } -OP(0F) { AD1_IHL; AD2_YIY; WR( addr1, ADDC8( RD( addr1 ), RD( addr2 ) ) ); } +OP(00) { AD2_X8; minx->BA = ( minx->BA & 0xFF00 ) | ADD8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(01) { AD2_Y8; minx->BA = ( minx->BA & 0xFF00 ) | ADD8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(02) { AD2_XL; minx->BA = ( minx->BA & 0xFF00 ) | ADD8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(03) { AD2_YL; minx->BA = ( minx->BA & 0xFF00 ) | ADD8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(04) { AD1_IHL; WR( addr1, ADD8( minx, RD( addr1 ), ( minx->BA & 0x00FF ) ) ); } +OP(05) { AD1_IHL; WR( addr1, ADD8( minx, RD( addr1 ), rdop(minx) ) ); } +OP(06) { AD1_IHL; AD2_XIX; WR( addr1, ADD8( minx, RD( addr1 ), RD( addr2 ) ) ); } +OP(07) { AD1_IHL; AD2_YIY; WR( addr1, ADD8( minx, RD( addr1 ), RD( addr2 ) ) ); } +OP(08) { AD2_X8; minx->BA = ( minx->BA & 0xFF00 ) | ADDC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(09) { AD2_Y8; minx->BA = ( minx->BA & 0xFF00 ) | ADDC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(0A) { AD2_XL; minx->BA = ( minx->BA & 0xFF00 ) | ADDC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(0B) { AD2_YL; minx->BA = ( minx->BA & 0xFF00 ) | ADDC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(0C) { AD1_IHL; WR( addr1, ADDC8( minx, RD( addr1 ), ( minx->BA & 0x00FF ) ) ); } +OP(0D) { AD1_IHL; WR( addr1, ADDC8( minx, RD( addr1 ), rdop(minx) ) ); } +OP(0E) { AD1_IHL; AD2_XIX; WR( addr1, ADDC8( minx, RD( addr1 ), RD( addr2 ) ) ); } +OP(0F) { AD1_IHL; AD2_YIY; WR( addr1, ADDC8( minx, RD( addr1 ), RD( addr2 ) ) ); } -OP(10) { AD2_X8; regs.BA = ( regs.BA & 0xFF00 ) | SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(11) { AD2_Y8; regs.BA = ( regs.BA & 0xFF00 ) | SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(12) { AD2_XL; regs.BA = ( regs.BA & 0xFF00 ) | SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(13) { AD2_YL; regs.BA = ( regs.BA & 0xFF00 ) | SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(14) { AD1_IHL; WR( addr1, SUB8( RD( addr1 ), ( regs.BA & 0x00FF ) ) ); } -OP(15) { AD1_IHL; WR( addr1, SUB8( RD( addr1 ), rdop() ) ); } -OP(16) { AD1_IHL; AD2_XIX; WR( addr1, SUB8( RD( addr1 ), RD( addr2 ) ) ); } -OP(17) { AD1_IHL; AD2_YIY; WR( addr1, SUB8( RD( addr1 ), RD( addr2 ) ) ); } -OP(18) { AD2_X8; regs.BA = ( regs.BA & 0xFF00 ) | SUBC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(19) { AD2_Y8; regs.BA = ( regs.BA & 0xFF00 ) | SUBC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(1A) { AD2_XL; regs.BA = ( regs.BA & 0xFF00 ) | SUBC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(1B) { AD2_YL; regs.BA = ( regs.BA & 0xFF00 ) | SUBC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(1C) { AD1_IHL; WR( addr1, SUBC8( RD( addr1 ), ( regs.BA & 0x00FF ) ) ); } -OP(1D) { AD1_IHL; WR( addr1, SUBC8( RD( addr1 ), rdop() ) ); } -OP(1E) { AD1_IHL; AD2_XIX; WR( addr1, SUBC8( RD( addr1 ), RD( addr2 ) ) ); } -OP(1F) { AD1_IHL; AD2_YIY; WR( addr1, SUBC8( RD( addr1 ), RD( addr2 ) ) ); } +OP(10) { AD2_X8; minx->BA = ( minx->BA & 0xFF00 ) | SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(11) { AD2_Y8; minx->BA = ( minx->BA & 0xFF00 ) | SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(12) { AD2_XL; minx->BA = ( minx->BA & 0xFF00 ) | SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(13) { AD2_YL; minx->BA = ( minx->BA & 0xFF00 ) | SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(14) { AD1_IHL; WR( addr1, SUB8( minx, RD( addr1 ), ( minx->BA & 0x00FF ) ) ); } +OP(15) { AD1_IHL; WR( addr1, SUB8( minx, RD( addr1 ), rdop(minx) ) ); } +OP(16) { AD1_IHL; AD2_XIX; WR( addr1, SUB8( minx, RD( addr1 ), RD( addr2 ) ) ); } +OP(17) { AD1_IHL; AD2_YIY; WR( addr1, SUB8( minx, RD( addr1 ), RD( addr2 ) ) ); } +OP(18) { AD2_X8; minx->BA = ( minx->BA & 0xFF00 ) | SUBC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(19) { AD2_Y8; minx->BA = ( minx->BA & 0xFF00 ) | SUBC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(1A) { AD2_XL; minx->BA = ( minx->BA & 0xFF00 ) | SUBC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(1B) { AD2_YL; minx->BA = ( minx->BA & 0xFF00 ) | SUBC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(1C) { AD1_IHL; WR( addr1, SUBC8( minx, RD( addr1 ), ( minx->BA & 0x00FF ) ) ); } +OP(1D) { AD1_IHL; WR( addr1, SUBC8( minx, RD( addr1 ), rdop(minx) ) ); } +OP(1E) { AD1_IHL; AD2_XIX; WR( addr1, SUBC8( minx, RD( addr1 ), RD( addr2 ) ) ); } +OP(1F) { AD1_IHL; AD2_YIY; WR( addr1, SUBC8( minx, RD( addr1 ), RD( addr2 ) ) ); } -OP(20) { AD2_X8; regs.BA = ( regs.BA & 0xFF00 ) | AND8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(21) { AD2_Y8; regs.BA = ( regs.BA & 0xFF00 ) | AND8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(22) { AD2_XL; regs.BA = ( regs.BA & 0xFF00 ) | AND8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(23) { AD2_YL; regs.BA = ( regs.BA & 0xFF00 ) | AND8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(24) { AD1_IHL; WR( addr1, AND8( RD( addr1 ), ( regs.BA & 0x00FF ) ) ); } -OP(25) { AD1_IHL; WR( addr1, AND8( RD( addr1 ), rdop() ) ); } -OP(26) { AD1_IHL; AD2_XIX; WR( addr1, AND8( RD( addr1 ), RD( addr2 ) ) ); } -OP(27) { AD1_IHL; AD2_YIY; WR( addr1, AND8( RD( addr1 ), RD( addr2 ) ) ); } -OP(28) { AD2_X8; regs.BA = ( regs.BA & 0xFF00 ) | OR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(29) { AD2_Y8; regs.BA = ( regs.BA & 0xFF00 ) | OR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(2A) { AD2_XL; regs.BA = ( regs.BA & 0xFF00 ) | OR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(2B) { AD2_YL; regs.BA = ( regs.BA & 0xFF00 ) | OR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(2C) { AD1_IHL; WR( addr1, OR8( RD( addr1 ), ( regs.BA & 0x00FF ) ) ); } -OP(2D) { AD1_IHL; WR( addr1, OR8( RD( addr1 ), rdop() ) ); } -OP(2E) { AD1_IHL; AD2_XIX; WR( addr1, OR8( RD( addr1 ), RD( addr2 ) ) ); } -OP(2F) { AD1_IHL; AD2_YIY; WR( addr1, OR8( RD( addr1 ), RD( addr2 ) ) ); } +OP(20) { AD2_X8; minx->BA = ( minx->BA & 0xFF00 ) | AND8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(21) { AD2_Y8; minx->BA = ( minx->BA & 0xFF00 ) | AND8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(22) { AD2_XL; minx->BA = ( minx->BA & 0xFF00 ) | AND8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(23) { AD2_YL; minx->BA = ( minx->BA & 0xFF00 ) | AND8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(24) { AD1_IHL; WR( addr1, AND8( minx, RD( addr1 ), ( minx->BA & 0x00FF ) ) ); } +OP(25) { AD1_IHL; WR( addr1, AND8( minx, RD( addr1 ), rdop(minx) ) ); } +OP(26) { AD1_IHL; AD2_XIX; WR( addr1, AND8( minx, RD( addr1 ), RD( addr2 ) ) ); } +OP(27) { AD1_IHL; AD2_YIY; WR( addr1, AND8( minx, RD( addr1 ), RD( addr2 ) ) ); } +OP(28) { AD2_X8; minx->BA = ( minx->BA & 0xFF00 ) | OR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(29) { AD2_Y8; minx->BA = ( minx->BA & 0xFF00 ) | OR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(2A) { AD2_XL; minx->BA = ( minx->BA & 0xFF00 ) | OR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(2B) { AD2_YL; minx->BA = ( minx->BA & 0xFF00 ) | OR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(2C) { AD1_IHL; WR( addr1, OR8( minx, RD( addr1 ), ( minx->BA & 0x00FF ) ) ); } +OP(2D) { AD1_IHL; WR( addr1, OR8( minx, RD( addr1 ), rdop(minx) ) ); } +OP(2E) { AD1_IHL; AD2_XIX; WR( addr1, OR8( minx, RD( addr1 ), RD( addr2 ) ) ); } +OP(2F) { AD1_IHL; AD2_YIY; WR( addr1, OR8( minx, RD( addr1 ), RD( addr2 ) ) ); } -OP(30) { AD2_X8; SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(31) { AD2_Y8; SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(32) { AD2_XL; SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(33) { AD2_YL; SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(34) { AD1_IHL; SUB8( RD( addr1 ), ( regs.BA & 0x00FF ) ); } -OP(35) { AD1_IHL; SUB8( RD( addr1 ), rdop() ); } -OP(36) { AD1_IHL; AD2_XIX; SUB8( RD( addr1 ), RD( addr2 ) ); } -OP(37) { AD1_IHL; AD2_YIY; SUB8( RD( addr1 ), RD( addr2 ) ); } -OP(38) { AD2_X8; regs.BA = ( regs.BA & 0xFF00 ) | XOR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(39) { AD2_Y8; regs.BA = ( regs.BA & 0xFF00 ) | XOR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(3A) { AD2_XL; regs.BA = ( regs.BA & 0xFF00 ) | XOR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(3B) { AD2_YL; regs.BA = ( regs.BA & 0xFF00 ) | XOR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(3C) { AD1_IHL; WR( addr1, XOR8( RD( addr1 ), ( regs.BA & 0x00FF ) ) ); } -OP(3D) { AD1_IHL; WR( addr1, XOR8( RD( addr1 ), rdop() ) ); } -OP(3E) { AD1_IHL; AD2_XIX; WR( addr1, XOR8( RD( addr1 ), RD( addr2 ) ) ); } -OP(3F) { AD1_IHL; AD2_YIY; WR( addr1, XOR8( RD( addr1 ), RD( addr2 ) ) ); } +OP(30) { AD2_X8; SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(31) { AD2_Y8; SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(32) { AD2_XL; SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(33) { AD2_YL; SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(34) { AD1_IHL; SUB8( minx, RD( addr1 ), ( minx->BA & 0x00FF ) ); } +OP(35) { AD1_IHL; SUB8( minx, RD( addr1 ), rdop(minx) ); } +OP(36) { AD1_IHL; AD2_XIX; SUB8( minx, RD( addr1 ), RD( addr2 ) ); } +OP(37) { AD1_IHL; AD2_YIY; SUB8( minx, RD( addr1 ), RD( addr2 ) ); } +OP(38) { AD2_X8; minx->BA = ( minx->BA & 0xFF00 ) | XOR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(39) { AD2_Y8; minx->BA = ( minx->BA & 0xFF00 ) | XOR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(3A) { AD2_XL; minx->BA = ( minx->BA & 0xFF00 ) | XOR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(3B) { AD2_YL; minx->BA = ( minx->BA & 0xFF00 ) | XOR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(3C) { AD1_IHL; WR( addr1, XOR8( minx, RD( addr1 ), ( minx->BA & 0x00FF ) ) ); } +OP(3D) { AD1_IHL; WR( addr1, XOR8( minx, RD( addr1 ), rdop(minx) ) ); } +OP(3E) { AD1_IHL; AD2_XIX; WR( addr1, XOR8( minx, RD( addr1 ), RD( addr2 ) ) ); } +OP(3F) { AD1_IHL; AD2_YIY; WR( addr1, XOR8( minx, RD( addr1 ), RD( addr2 ) ) ); } -OP(40) { AD2_X8; regs.BA = ( regs.BA & 0xFF00 ) | RD( addr2 ); } -OP(41) { AD2_Y8; regs.BA = ( regs.BA & 0xFF00 ) | RD( addr2 ); } -OP(42) { AD2_XL; regs.BA = ( regs.BA & 0xFF00 ) | RD( addr2 ); } -OP(43) { AD2_YL; regs.BA = ( regs.BA & 0xFF00 ) | RD( addr2 ); } -OP(44) { AD1_X8; WR( addr1, ( regs.BA & 0x00FF ) ); } -OP(45) { AD1_Y8; WR( addr1, ( regs.BA & 0x00FF ) ); } -OP(46) { AD1_XL; WR( addr1, ( regs.BA & 0x00FF ) ); } -OP(47) { AD1_YL; WR( addr1, ( regs.BA & 0x00FF ) ); } -OP(48) { AD2_X8; regs.BA = ( regs.BA & 0x00FF ) | ( RD( addr2 ) << 8 ); } -OP(49) { AD2_Y8; regs.BA = ( regs.BA & 0x00FF ) | ( RD( addr2 ) << 8 ); } -OP(4A) { AD2_XL; regs.BA = ( regs.BA & 0x00FF ) | ( RD( addr2 ) << 8 ); } -OP(4B) { AD2_YL; regs.BA = ( regs.BA & 0x00FF ) | ( RD( addr2 ) << 8 ); } -OP(4C) { AD1_X8; WR( addr1, ( regs.BA >> 8 ) ); } -OP(4D) { AD1_Y8; WR( addr1, ( regs.BA >> 8 ) ); } -OP(4E) { AD1_XL; WR( addr1, ( regs.BA >> 8 ) ); } -OP(4F) { AD1_YL; WR( addr1, ( regs.BA >> 8 ) ); } +OP(40) { AD2_X8; minx->BA = ( minx->BA & 0xFF00 ) | RD( addr2 ); } +OP(41) { AD2_Y8; minx->BA = ( minx->BA & 0xFF00 ) | RD( addr2 ); } +OP(42) { AD2_XL; minx->BA = ( minx->BA & 0xFF00 ) | RD( addr2 ); } +OP(43) { AD2_YL; minx->BA = ( minx->BA & 0xFF00 ) | RD( addr2 ); } +OP(44) { AD1_X8; WR( addr1, ( minx->BA & 0x00FF ) ); } +OP(45) { AD1_Y8; WR( addr1, ( minx->BA & 0x00FF ) ); } +OP(46) { AD1_XL; WR( addr1, ( minx->BA & 0x00FF ) ); } +OP(47) { AD1_YL; WR( addr1, ( minx->BA & 0x00FF ) ); } +OP(48) { AD2_X8; minx->BA = ( minx->BA & 0x00FF ) | ( RD( addr2 ) << 8 ); } +OP(49) { AD2_Y8; minx->BA = ( minx->BA & 0x00FF ) | ( RD( addr2 ) << 8 ); } +OP(4A) { AD2_XL; minx->BA = ( minx->BA & 0x00FF ) | ( RD( addr2 ) << 8 ); } +OP(4B) { AD2_YL; minx->BA = ( minx->BA & 0x00FF ) | ( RD( addr2 ) << 8 ); } +OP(4C) { AD1_X8; WR( addr1, ( minx->BA >> 8 ) ); } +OP(4D) { AD1_Y8; WR( addr1, ( minx->BA >> 8 ) ); } +OP(4E) { AD1_XL; WR( addr1, ( minx->BA >> 8 ) ); } +OP(4F) { AD1_YL; WR( addr1, ( minx->BA >> 8 ) ); } -OP(50) { AD2_X8; regs.HL = ( regs.HL & 0xFF00 ) | RD( addr2 ); } -OP(51) { AD2_Y8; regs.HL = ( regs.HL & 0xFF00 ) | RD( addr2 ); } -OP(52) { AD2_XL; regs.HL = ( regs.HL & 0xFF00 ) | RD( addr2 ); } -OP(53) { AD2_YL; regs.HL = ( regs.HL & 0xFF00 ) | RD( addr2 ); } -OP(54) { AD1_X8; WR( addr1, ( regs.HL & 0x00FF ) ); } -OP(55) { AD1_Y8; WR( addr1, ( regs.HL & 0x00FF ) ); } -OP(56) { AD1_XL; WR( addr1, ( regs.HL & 0x00FF ) ); } -OP(57) { AD1_YL; WR( addr1, ( regs.HL & 0x00FF ) ); } -OP(58) { AD2_X8; regs.HL = ( regs.HL & 0x00FF ) | ( RD( addr2 ) << 8 ); } -OP(59) { AD2_Y8; regs.HL = ( regs.HL & 0x00FF ) | ( RD( addr2 ) << 8 ); } -OP(5A) { AD2_XL; regs.HL = ( regs.HL & 0x00FF ) | ( RD( addr2 ) << 8 ); } -OP(5B) { AD2_YL; regs.HL = ( regs.HL & 0x00FF ) | ( RD( addr2 ) << 8 ); } -OP(5C) { AD1_X8; WR( addr1, ( regs.HL >> 8 ) ); } -OP(5D) { AD1_Y8; WR( addr1, ( regs.HL >> 8 ) ); } -OP(5E) { AD1_XL; WR( addr1, ( regs.HL >> 8 ) ); } -OP(5F) { AD1_YL; WR( addr1, ( regs.HL >> 8 ) ); } +OP(50) { AD2_X8; minx->HL = ( minx->HL & 0xFF00 ) | RD( addr2 ); } +OP(51) { AD2_Y8; minx->HL = ( minx->HL & 0xFF00 ) | RD( addr2 ); } +OP(52) { AD2_XL; minx->HL = ( minx->HL & 0xFF00 ) | RD( addr2 ); } +OP(53) { AD2_YL; minx->HL = ( minx->HL & 0xFF00 ) | RD( addr2 ); } +OP(54) { AD1_X8; WR( addr1, ( minx->HL & 0x00FF ) ); } +OP(55) { AD1_Y8; WR( addr1, ( minx->HL & 0x00FF ) ); } +OP(56) { AD1_XL; WR( addr1, ( minx->HL & 0x00FF ) ); } +OP(57) { AD1_YL; WR( addr1, ( minx->HL & 0x00FF ) ); } +OP(58) { AD2_X8; minx->HL = ( minx->HL & 0x00FF ) | ( RD( addr2 ) << 8 ); } +OP(59) { AD2_Y8; minx->HL = ( minx->HL & 0x00FF ) | ( RD( addr2 ) << 8 ); } +OP(5A) { AD2_XL; minx->HL = ( minx->HL & 0x00FF ) | ( RD( addr2 ) << 8 ); } +OP(5B) { AD2_YL; minx->HL = ( minx->HL & 0x00FF ) | ( RD( addr2 ) << 8 ); } +OP(5C) { AD1_X8; WR( addr1, ( minx->HL >> 8 ) ); } +OP(5D) { AD1_Y8; WR( addr1, ( minx->HL >> 8 ) ); } +OP(5E) { AD1_XL; WR( addr1, ( minx->HL >> 8 ) ); } +OP(5F) { AD1_YL; WR( addr1, ( minx->HL >> 8 ) ); } OP(60) { AD1_IHL; AD2_X8; WR( addr1, RD( addr2 ) ); } OP(61) { AD1_IHL; AD2_Y8; WR( addr1, RD( addr2 ) ); } @@ -137,101 +137,101 @@ OP(7D) { /* illegal operation? */ } OP(7E) { /* illegal operation? */ } OP(7F) { /* illegal operation? */ } -OP(80) { regs.BA = ( regs.BA & 0xFF00 ) | SAL8( regs.BA & 0x00FF ); } -OP(81) { regs.BA = ( regs.BA & 0x00FF ) | ( SAL8( regs.BA >> 8 )<< 8 ); } -OP(82) { AD1_IN8; WR( addr1, SAL8( RD( addr1 ) ) ); } -OP(83) { AD1_IHL; WR( addr1, SAL8( RD( addr1 ) ) ); } -OP(84) { regs.BA = ( regs.BA & 0xFF00 ) | SHL8( regs.BA & 0x00FF ); } -OP(85) { regs.BA = ( regs.BA & 0x00FF ) | ( SHL8( regs.BA >> 8 ) << 8 ); } -OP(86) { AD1_IN8; WR( addr1, SHL8( RD( addr1 ) ) ); } -OP(87) { AD1_IHL; WR( addr1, SHL8( RD( addr1 ) ) ); } -OP(88) { regs.BA = ( regs.BA & 0xFF00 ) | SAR8( regs.BA & 0x00FF ); } -OP(89) { regs.BA = ( regs.BA & 0x00FF ) | ( SAR8( regs.BA >> 8 ) << 8 ); } -OP(8A) { AD1_IN8; WR( addr1, SAR8( RD( addr1 ) ) ); } -OP(8B) { AD1_IHL; WR( addr1, SAR8( RD( addr1 ) ) ); } -OP(8C) { regs.BA = ( regs.BA & 0xFF00 ) | SHR8( regs.BA & 0x00FF ); } -OP(8D) { regs.BA = ( regs.BA & 0x00FF ) | ( SHR8( regs.BA >> 8 ) << 8 ); } -OP(8E) { AD1_IN8; WR( addr1, SHR8( RD( addr1 ) ) ); } -OP(8F) { AD1_IHL; WR( addr1, SHR8( RD( addr1 ) ) ); } +OP(80) { minx->BA = ( minx->BA & 0xFF00 ) | SAL8( minx, minx->BA & 0x00FF ); } +OP(81) { minx->BA = ( minx->BA & 0x00FF ) | ( SAL8( minx, minx->BA >> 8 )<< 8 ); } +OP(82) { AD1_IN8; WR( addr1, SAL8( minx, RD( addr1 ) ) ); } +OP(83) { AD1_IHL; WR( addr1, SAL8( minx, RD( addr1 ) ) ); } +OP(84) { minx->BA = ( minx->BA & 0xFF00 ) | SHL8( minx, minx->BA & 0x00FF ); } +OP(85) { minx->BA = ( minx->BA & 0x00FF ) | ( SHL8( minx, minx->BA >> 8 ) << 8 ); } +OP(86) { AD1_IN8; WR( addr1, SHL8( minx, RD( addr1 ) ) ); } +OP(87) { AD1_IHL; WR( addr1, SHL8( minx, RD( addr1 ) ) ); } +OP(88) { minx->BA = ( minx->BA & 0xFF00 ) | SAR8( minx, minx->BA & 0x00FF ); } +OP(89) { minx->BA = ( minx->BA & 0x00FF ) | ( SAR8( minx, minx->BA >> 8 ) << 8 ); } +OP(8A) { AD1_IN8; WR( addr1, SAR8( minx, RD( addr1 ) ) ); } +OP(8B) { AD1_IHL; WR( addr1, SAR8( minx, RD( addr1 ) ) ); } +OP(8C) { minx->BA = ( minx->BA & 0xFF00 ) | SHR8( minx, minx->BA & 0x00FF ); } +OP(8D) { minx->BA = ( minx->BA & 0x00FF ) | ( SHR8( minx, minx->BA >> 8 ) << 8 ); } +OP(8E) { AD1_IN8; WR( addr1, SHR8( minx, RD( addr1 ) ) ); } +OP(8F) { AD1_IHL; WR( addr1, SHR8( minx, RD( addr1 ) ) ); } -OP(90) { regs.BA = ( regs.BA & 0xFF00 ) | ROLC8( regs.BA & 0x00FF ); } -OP(91) { regs.BA = ( regs.BA & 0x00FF ) | ( ROLC8( regs.BA >> 8 ) << 8 ); } -OP(92) { AD1_IN8; WR( addr1, ROLC8( RD( addr1 ) ) ); } -OP(93) { AD1_IHL; WR( addr1, ROLC8( RD( addr1 ) ) ); } -OP(94) { regs.BA = ( regs.BA & 0xFF00 ) | ROL8( regs.BA & 0x00FF ); } -OP(95) { regs.BA = ( regs.BA & 0x00FF ) | ( ROL8( regs.BA >> 8 ) << 8 ); } -OP(96) { AD1_IN8; WR( addr1, ROL8( RD( addr1 ) ) ); } -OP(97) { AD1_IHL; WR( addr1, ROL8( RD( addr1 ) ) ); } -OP(98) { regs.BA = ( regs.BA & 0xFF00 ) | RORC8( regs.BA & 0x00FF ); } -OP(99) { regs.BA = ( regs.BA & 0x00FF ) | ( RORC8( regs.BA >> 8 ) << 8 ); } -OP(9A) { AD1_IN8; WR( addr1, RORC8( RD( addr1 ) ) ); } -OP(9B) { AD1_IHL; WR( addr1, RORC8( RD( addr1 ) ) ); } -OP(9C) { regs.BA = ( regs.BA & 0xFF00 ) | ROR8( regs.BA & 0x00FF ); } -OP(9D) { regs.BA = ( regs.BA & 0x00FF ) | ( ROR8( regs.BA >> 8 ) << 8 ); } -OP(9E) { AD1_IN8; WR( addr1, ROR8( RD( addr1 ) ) ); } -OP(9F) { AD1_IHL; WR( addr1, ROR8( RD( addr1 ) ) ); } +OP(90) { minx->BA = ( minx->BA & 0xFF00 ) | ROLC8( minx, minx->BA & 0x00FF ); } +OP(91) { minx->BA = ( minx->BA & 0x00FF ) | ( ROLC8( minx, minx->BA >> 8 ) << 8 ); } +OP(92) { AD1_IN8; WR( addr1, ROLC8( minx, RD( addr1 ) ) ); } +OP(93) { AD1_IHL; WR( addr1, ROLC8( minx, RD( addr1 ) ) ); } +OP(94) { minx->BA = ( minx->BA & 0xFF00 ) | ROL8( minx, minx->BA & 0x00FF ); } +OP(95) { minx->BA = ( minx->BA & 0x00FF ) | ( ROL8( minx, minx->BA >> 8 ) << 8 ); } +OP(96) { AD1_IN8; WR( addr1, ROL8( minx, RD( addr1 ) ) ); } +OP(97) { AD1_IHL; WR( addr1, ROL8( minx, RD( addr1 ) ) ); } +OP(98) { minx->BA = ( minx->BA & 0xFF00 ) | RORC8( minx, minx->BA & 0x00FF ); } +OP(99) { minx->BA = ( minx->BA & 0x00FF ) | ( RORC8( minx, minx->BA >> 8 ) << 8 ); } +OP(9A) { AD1_IN8; WR( addr1, RORC8( minx, RD( addr1 ) ) ); } +OP(9B) { AD1_IHL; WR( addr1, RORC8( minx, RD( addr1 ) ) ); } +OP(9C) { minx->BA = ( minx->BA & 0xFF00 ) | ROR8( minx, minx->BA & 0x00FF ); } +OP(9D) { minx->BA = ( minx->BA & 0x00FF ) | ( ROR8( minx, minx->BA >> 8 ) << 8 ); } +OP(9E) { AD1_IN8; WR( addr1, ROR8( minx, RD( addr1 ) ) ); } +OP(9F) { AD1_IHL; WR( addr1, ROR8( minx, RD( addr1 ) ) ); } -OP(A0) { regs.BA = ( regs.BA & 0xFF00 ) | NOT8( regs.BA & 0x00FF ); } -OP(A1) { regs.BA = ( regs.BA & 0x00FF ) | ( NOT8( regs.BA >> 8 ) << 8 ); } -OP(A2) { AD1_IN8; WR( addr1, NOT8( RD( addr1 ) ) ); } -OP(A3) { AD1_IHL; WR( addr1, NOT8( RD( addr1 ) ) ); } -OP(A4) { regs.BA = ( regs.BA & 0xFF00 ) | NEG8( regs.BA & 0x00FF ); } -OP(A5) { regs.BA = ( regs.BA & 0x00FF ) | ( NEG8( regs.BA >> 8 ) << 8 ); } -OP(A6) { AD1_IN8; WR( addr1, NEG8( RD( addr1 ) ) ); } -OP(A7) { AD1_IHL; WR( addr1, NEG8( RD( addr1 ) ) ); } -OP(A8) { regs.BA = ( ( regs.BA & 0x0080 ) ? ( 0xFF00 | regs.BA ) : ( regs.BA & 0x00FF ) ); } +OP(A0) { minx->BA = ( minx->BA & 0xFF00 ) | NOT8( minx, minx->BA & 0x00FF ); } +OP(A1) { minx->BA = ( minx->BA & 0x00FF ) | ( NOT8( minx, minx->BA >> 8 ) << 8 ); } +OP(A2) { AD1_IN8; WR( addr1, NOT8( minx, RD( addr1 ) ) ); } +OP(A3) { AD1_IHL; WR( addr1, NOT8( minx, RD( addr1 ) ) ); } +OP(A4) { minx->BA = ( minx->BA & 0xFF00 ) | NEG8( minx, minx->BA & 0x00FF ); } +OP(A5) { minx->BA = ( minx->BA & 0x00FF ) | ( NEG8( minx, minx->BA >> 8 ) << 8 ); } +OP(A6) { AD1_IN8; WR( addr1, NEG8( minx, RD( addr1 ) ) ); } +OP(A7) { AD1_IHL; WR( addr1, NEG8( minx, RD( addr1 ) ) ); } +OP(A8) { minx->BA = ( ( minx->BA & 0x0080 ) ? ( 0xFF00 | minx->BA ) : ( minx->BA & 0x00FF ) ); } OP(A9) { /* illegal operation? */ } OP(AA) { /* illegal operation? */ } OP(AB) { /* illegal operation? */ } OP(AC) { /* illegal operation? */ } OP(AD) { /* illegal operation? */ } -OP(AE) { /* HALT */ regs.halted = 1; } +OP(AE) { /* HALT */ minx->halted = 1; } OP(AF) { } -OP(B0) { regs.BA = ( regs.BA & 0x00FF ) | ( AND8( ( regs.BA >> 8 ), rdop() ) << 8 ); } -OP(B1) { regs.HL = ( regs.HL & 0xFF00 ) | AND8( ( regs.HL & 0x00FF ), rdop() ); } -OP(B2) { regs.HL = ( regs.HL & 0x00FF ) | ( AND8( ( regs.HL >> 8 ), rdop() ) << 8 ); } +OP(B0) { minx->BA = ( minx->BA & 0x00FF ) | ( AND8( minx, ( minx->BA >> 8 ), rdop(minx) ) << 8 ); } +OP(B1) { minx->HL = ( minx->HL & 0xFF00 ) | AND8( minx, ( minx->HL & 0x00FF ), rdop(minx) ); } +OP(B2) { minx->HL = ( minx->HL & 0x00FF ) | ( AND8( minx, ( minx->HL >> 8 ), rdop(minx) ) << 8 ); } OP(B3) { /* illegal operation? */ } -OP(B4) { regs.BA = ( regs.BA & 0x00FF ) | ( OR8( ( regs.BA >> 8 ), rdop() ) << 8 ); } -OP(B5) { regs.HL = ( regs.HL & 0xFF00 ) | OR8( ( regs.HL & 0x00FF ), rdop() ); } -OP(B6) { regs.HL = ( regs.HL & 0x00FF ) | ( OR8( ( regs.HL >> 8 ), rdop() ) << 8 ); } +OP(B4) { minx->BA = ( minx->BA & 0x00FF ) | ( OR8( minx, ( minx->BA >> 8 ), rdop(minx) ) << 8 ); } +OP(B5) { minx->HL = ( minx->HL & 0xFF00 ) | OR8( minx, ( minx->HL & 0x00FF ), rdop(minx) ); } +OP(B6) { minx->HL = ( minx->HL & 0x00FF ) | ( OR8( minx, ( minx->HL >> 8 ), rdop(minx) ) << 8 ); } OP(B7) { /* illegal operation? */ } -OP(B8) { regs.BA = ( regs.BA & 0x00FF ) | ( XOR8( ( regs.BA >> 8 ), rdop() ) << 8 ); } -OP(B9) { regs.HL = ( regs.HL & 0xFF00 ) | XOR8( ( regs.HL & 0x00FF ), rdop() ); } -OP(BA) { regs.HL = ( regs.HL & 0x00FF ) | ( XOR8( ( regs.HL >> 8 ), rdop() ) << 8 ); } +OP(B8) { minx->BA = ( minx->BA & 0x00FF ) | ( XOR8( minx, ( minx->BA >> 8 ), rdop(minx) ) << 8 ); } +OP(B9) { minx->HL = ( minx->HL & 0xFF00 ) | XOR8( minx, ( minx->HL & 0x00FF ), rdop(minx) ); } +OP(BA) { minx->HL = ( minx->HL & 0x00FF ) | ( XOR8( minx, ( minx->HL >> 8 ), rdop(minx) ) << 8 ); } OP(BB) { /* illegal operation? */ } -OP(BC) { SUB8( ( regs.BA >> 8 ), rdop() ); } -OP(BD) { SUB8( ( regs.HL & 0x00FF), rdop() ); } -OP(BE) { SUB8( ( regs.HL >> 8 ), rdop() ); } -OP(BF) { SUB8( regs.N, rdop() ); } +OP(BC) { SUB8( minx, ( minx->BA >> 8 ), rdop(minx) ); } +OP(BD) { SUB8( minx, ( minx->HL & 0x00FF), rdop(minx) ); } +OP(BE) { SUB8( minx, ( minx->HL >> 8 ), rdop(minx) ); } +OP(BF) { SUB8( minx, minx->N, rdop(minx) ); } -OP(C0) { regs.BA = ( regs.BA & 0xFF00 ) | regs.N; } -OP(C1) { regs.BA = ( regs.BA & 0xFF00 ) | regs.F; } -OP(C2) { regs.N = ( regs.BA & 0x00FF ); } -OP(C3) { regs.F = ( regs.BA & 0x00FF ); } -OP(C4) { regs.U = rdop(); } -OP(C5) { regs.I = rdop(); } -OP(C6) { regs.XI = rdop(); } -OP(C7) { regs.YI = rdop(); } -OP(C8) { regs.BA = ( regs.BA & 0xFF00 ) | regs.V; } -OP(C9) { regs.BA = ( regs.BA & 0xFF00 ) | regs.I; } -OP(CA) { regs.BA = ( regs.BA & 0xFF00 ) | regs.XI; } -OP(CB) { regs.BA = ( regs.BA & 0xFF00 ) | regs.YI; } -OP(CC) { regs.U = ( regs.BA & 0x00FF ); } -OP(CD) { regs.I = ( regs.BA & 0x00FF ); } -OP(CE) { regs.XI = ( regs.BA & 0x00FF ); } -OP(CF) { regs.YI = ( regs.BA & 0x00FF ); } +OP(C0) { minx->BA = ( minx->BA & 0xFF00 ) | minx->N; } +OP(C1) { minx->BA = ( minx->BA & 0xFF00 ) | minx->F; } +OP(C2) { minx->N = ( minx->BA & 0x00FF ); } +OP(C3) { minx->F = ( minx->BA & 0x00FF ); } +OP(C4) { minx->U = rdop(minx); } +OP(C5) { minx->I = rdop(minx); } +OP(C6) { minx->XI = rdop(minx); } +OP(C7) { minx->YI = rdop(minx); } +OP(C8) { minx->BA = ( minx->BA & 0xFF00 ) | minx->V; } +OP(C9) { minx->BA = ( minx->BA & 0xFF00 ) | minx->I; } +OP(CA) { minx->BA = ( minx->BA & 0xFF00 ) | minx->XI; } +OP(CB) { minx->BA = ( minx->BA & 0xFF00 ) | minx->YI; } +OP(CC) { minx->U = ( minx->BA & 0x00FF ); } +OP(CD) { minx->I = ( minx->BA & 0x00FF ); } +OP(CE) { minx->XI = ( minx->BA & 0x00FF ); } +OP(CF) { minx->YI = ( minx->BA & 0x00FF ); } -OP(D0) { AD2_I16; regs.BA = ( regs.BA & 0xFF00 ) | RD( addr2 ); } -OP(D1) { AD2_I16; regs.BA = ( regs.BA & 0x00FF ) | ( RD( addr2 ) << 8 ); } -OP(D2) { AD2_I16; regs.HL = ( regs.HL & 0xFF00 ) | RD( addr2 ); } -OP(D3) { AD2_I16; regs.HL = ( regs.HL & 0x00FF ) | ( RD( addr2 ) << 8 ); } -OP(D4) { AD1_I16; WR( addr1, ( regs.BA & 0x00FF ) ); } -OP(D5) { AD1_I16; WR( addr1, ( regs.BA >> 8 ) ); } -OP(D6) { AD1_I16; WR( addr1, ( regs.HL & 0x00FF ) ); } -OP(D7) { AD1_I16; WR( addr1, ( regs.HL >> 8 ) ); } -OP(D8) { regs.HL = ( regs.HL & 0x00FF ) * ( regs.BA & 0x00FF ); } -OP(D9) { int d = regs.HL / ( regs.BA & 0x00FF ); regs.HL = ( ( regs.HL - ( ( regs.BA & 0x00FF ) * d ) ) << 8 ) | d; } +OP(D0) { AD2_I16; minx->BA = ( minx->BA & 0xFF00 ) | RD( addr2 ); } +OP(D1) { AD2_I16; minx->BA = ( minx->BA & 0x00FF ) | ( RD( addr2 ) << 8 ); } +OP(D2) { AD2_I16; minx->HL = ( minx->HL & 0xFF00 ) | RD( addr2 ); } +OP(D3) { AD2_I16; minx->HL = ( minx->HL & 0x00FF ) | ( RD( addr2 ) << 8 ); } +OP(D4) { AD1_I16; WR( addr1, ( minx->BA & 0x00FF ) ); } +OP(D5) { AD1_I16; WR( addr1, ( minx->BA >> 8 ) ); } +OP(D6) { AD1_I16; WR( addr1, ( minx->HL & 0x00FF ) ); } +OP(D7) { AD1_I16; WR( addr1, ( minx->HL >> 8 ) ); } +OP(D8) { minx->HL = ( minx->HL & 0x00FF ) * ( minx->BA & 0x00FF ); } +OP(D9) { int d = minx->HL / ( minx->BA & 0x00FF ); minx->HL = ( ( minx->HL - ( ( minx->BA & 0x00FF ) * d ) ) << 8 ) | d; } OP(DA) { /* illegal operation? */ } OP(DB) { /* illegal operation? */ } OP(DC) { /* illegal operation? */ } @@ -239,41 +239,41 @@ OP(DD) { /* illegal operation? */ } OP(DE) { /* illegal operation? */ } OP(DF) { /* illegal operation? */ } -OP(E0) { INT8 d8 = rdop(); if ( ( ( regs.F & ( FLAG_S | FLAG_O ) ) == FLAG_S ) || ( ( regs.F & ( FLAG_S | FLAG_O ) ) == FLAG_O ) ) { JMP( regs.PC + d8 - 1 ); } } -OP(E1) { INT8 d8 = rdop(); if ( ( regs.F & FLAG_Z ) || ( ( regs.F & ( FLAG_S | FLAG_O ) ) == FLAG_S ) || ( ( regs.F & ( FLAG_S | FLAG_O ) ) == FLAG_O ) ) { JMP( regs.PC + d8 - 1 ); } } -OP(E2) { INT8 d8 = rdop(); if ( !( regs.F & FLAG_Z ) && ( ( ( regs.F & ( FLAG_S | FLAG_O ) ) == 0 ) || ( ( regs.F & ( FLAG_S | FLAG_O ) ) == ( FLAG_S | FLAG_O ) ) ) ) { JMP( regs.PC + d8 - 1 ); } } -OP(E3) { INT8 d8 = rdop(); if ( ( ( regs.F & ( FLAG_S | FLAG_O ) ) == 0 ) || ( ( regs.F & ( FLAG_S | FLAG_O ) ) == ( FLAG_S | FLAG_O ) ) ) { JMP( regs.PC + d8 - 1 ); } } -OP(E4) { INT8 d8 = rdop(); if ( ( regs.F & FLAG_O ) ) { JMP( regs.PC + d8 - 1 ); } } -OP(E5) { INT8 d8 = rdop(); if ( ! ( regs.F & FLAG_O ) ) { JMP( regs.PC + d8 - 1 ); } } -OP(E6) { INT8 d8 = rdop(); if ( ! ( regs.F & FLAG_S ) ) { JMP( regs.PC + d8 - 1 ); } } -OP(E7) { INT8 d8 = rdop(); if ( ( regs.F & FLAG_S ) ) { JMP( regs.PC + d8 - 1 ); } } -OP(E8) { INT8 d8 = rdop(); if ( ! ( regs.E & EXEC_X0 ) ) { JMP( regs.PC + d8 - 1 ); } } -OP(E9) { INT8 d8 = rdop(); if ( ! ( regs.E & EXEC_X1 ) ) { JMP( regs.PC + d8 - 1 ); } } -OP(EA) { INT8 d8 = rdop(); if ( ! ( regs.E & EXEC_X2 ) ) { JMP( regs.PC + d8 - 1 ); } } -OP(EB) { INT8 d8 = rdop(); if ( ! ( regs.E & EXEC_DZ ) ) { JMP( regs.PC + d8 - 1 ); } } -OP(EC) { INT8 d8 = rdop(); if ( ( regs.E & EXEC_X0 ) ) { JMP( regs.PC + d8 - 1 ); } } -OP(ED) { INT8 d8 = rdop(); if ( ( regs.E & EXEC_X1 ) ) { JMP( regs.PC + d8 - 1 ); } } -OP(EE) { INT8 d8 = rdop(); if ( ( regs.E & EXEC_X2 ) ) { JMP( regs.PC + d8 - 1 ); } } -OP(EF) { INT8 d8 = rdop(); if ( ( regs.E & EXEC_DZ ) ) { JMP( regs.PC + d8 - 1 ); } } +OP(E0) { INT8 d8 = rdop(minx); if ( ( ( minx->F & ( FLAG_S | FLAG_O ) ) == FLAG_S ) || ( ( minx->F & ( FLAG_S | FLAG_O ) ) == FLAG_O ) ) { JMP( minx, minx->PC + d8 - 1 ); } } +OP(E1) { INT8 d8 = rdop(minx); if ( ( minx->F & FLAG_Z ) || ( ( minx->F & ( FLAG_S | FLAG_O ) ) == FLAG_S ) || ( ( minx->F & ( FLAG_S | FLAG_O ) ) == FLAG_O ) ) { JMP( minx, minx->PC + d8 - 1 ); } } +OP(E2) { INT8 d8 = rdop(minx); if ( !( minx->F & FLAG_Z ) && ( ( ( minx->F & ( FLAG_S | FLAG_O ) ) == 0 ) || ( ( minx->F & ( FLAG_S | FLAG_O ) ) == ( FLAG_S | FLAG_O ) ) ) ) { JMP( minx, minx->PC + d8 - 1 ); } } +OP(E3) { INT8 d8 = rdop(minx); if ( ( ( minx->F & ( FLAG_S | FLAG_O ) ) == 0 ) || ( ( minx->F & ( FLAG_S | FLAG_O ) ) == ( FLAG_S | FLAG_O ) ) ) { JMP( minx, minx->PC + d8 - 1 ); } } +OP(E4) { INT8 d8 = rdop(minx); if ( ( minx->F & FLAG_O ) ) { JMP( minx, minx->PC + d8 - 1 ); } } +OP(E5) { INT8 d8 = rdop(minx); if ( ! ( minx->F & FLAG_O ) ) { JMP( minx, minx->PC + d8 - 1 ); } } +OP(E6) { INT8 d8 = rdop(minx); if ( ! ( minx->F & FLAG_S ) ) { JMP( minx, minx->PC + d8 - 1 ); } } +OP(E7) { INT8 d8 = rdop(minx); if ( ( minx->F & FLAG_S ) ) { JMP( minx, minx->PC + d8 - 1 ); } } +OP(E8) { INT8 d8 = rdop(minx); if ( ! ( minx->E & EXEC_X0 ) ) { JMP( minx, minx->PC + d8 - 1 ); } } +OP(E9) { INT8 d8 = rdop(minx); if ( ! ( minx->E & EXEC_X1 ) ) { JMP( minx, minx->PC + d8 - 1 ); } } +OP(EA) { INT8 d8 = rdop(minx); if ( ! ( minx->E & EXEC_X2 ) ) { JMP( minx, minx->PC + d8 - 1 ); } } +OP(EB) { INT8 d8 = rdop(minx); if ( ! ( minx->E & EXEC_DZ ) ) { JMP( minx, minx->PC + d8 - 1 ); } } +OP(EC) { INT8 d8 = rdop(minx); if ( ( minx->E & EXEC_X0 ) ) { JMP( minx, minx->PC + d8 - 1 ); } } +OP(ED) { INT8 d8 = rdop(minx); if ( ( minx->E & EXEC_X1 ) ) { JMP( minx, minx->PC + d8 - 1 ); } } +OP(EE) { INT8 d8 = rdop(minx); if ( ( minx->E & EXEC_X2 ) ) { JMP( minx, minx->PC + d8 - 1 ); } } +OP(EF) { INT8 d8 = rdop(minx); if ( ( minx->E & EXEC_DZ ) ) { JMP( minx, minx->PC + d8 - 1 ); } } -OP(F0) { INT8 d8 = rdop(); if ( ( ( regs.F & ( FLAG_S | FLAG_O ) ) == FLAG_S ) || ( ( regs.F & ( FLAG_S | FLAG_O ) ) == FLAG_O ) ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } -OP(F1) { INT8 d8 = rdop(); if ( ( regs.F & FLAG_Z ) || ( ( regs.F & ( FLAG_S | FLAG_O ) ) == FLAG_S ) || ( ( regs.F & ( FLAG_S | FLAG_O ) ) == FLAG_O ) ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } -OP(F2) { INT8 d8 = rdop(); if ( !( regs.F & FLAG_Z ) && ( ( ( regs.F & ( FLAG_S | FLAG_O ) ) == 0 ) || ( ( regs.F & ( FLAG_S | FLAG_O ) ) == ( FLAG_S | FLAG_O ) ) ) ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } -OP(F3) { INT8 d8 = rdop(); if ( ( ( regs.F & ( FLAG_S | FLAG_O ) ) == 0 ) || ( ( regs.F & ( FLAG_S | FLAG_O ) ) == ( FLAG_S | FLAG_O ) ) ) { CALL( regs.PC + d8 - 1 ); } } -OP(F4) { INT8 d8 = rdop(); if ( ( regs.F & FLAG_O ) ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } -OP(F5) { INT8 d8 = rdop(); if ( ! ( regs.F & FLAG_O ) ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } -OP(F6) { INT8 d8 = rdop(); if ( ! ( regs.F & FLAG_S ) ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } -OP(F7) { INT8 d8 = rdop(); if ( ( regs.F & FLAG_S ) ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } -OP(F8) { INT8 d8 = rdop(); if ( ! ( regs.E & EXEC_X0 ) ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } -OP(F9) { INT8 d8 = rdop(); if ( ! ( regs.E & EXEC_X1 ) ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } -OP(FA) { INT8 d8 = rdop(); if ( ! ( regs.E & EXEC_X2 ) ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } -OP(FB) { INT8 d8 = rdop(); if ( ! ( regs.E & EXEC_DZ ) ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } -OP(FC) { INT8 d8 = rdop(); if ( ( regs.E & EXEC_X0 ) ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } -OP(FD) { INT8 d8 = rdop(); if ( ( regs.E & EXEC_X1 ) ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } -OP(FE) { INT8 d8 = rdop(); if ( ( regs.E & EXEC_X2 ) ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } -OP(FF) { INT8 d8 = rdop(); if ( ( regs.E & EXEC_DZ ) ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } +OP(F0) { INT8 d8 = rdop(minx); if ( ( ( minx->F & ( FLAG_S | FLAG_O ) ) == FLAG_S ) || ( ( minx->F & ( FLAG_S | FLAG_O ) ) == FLAG_O ) ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } } +OP(F1) { INT8 d8 = rdop(minx); if ( ( minx->F & FLAG_Z ) || ( ( minx->F & ( FLAG_S | FLAG_O ) ) == FLAG_S ) || ( ( minx->F & ( FLAG_S | FLAG_O ) ) == FLAG_O ) ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } } +OP(F2) { INT8 d8 = rdop(minx); if ( !( minx->F & FLAG_Z ) && ( ( ( minx->F & ( FLAG_S | FLAG_O ) ) == 0 ) || ( ( minx->F & ( FLAG_S | FLAG_O ) ) == ( FLAG_S | FLAG_O ) ) ) ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } } +OP(F3) { INT8 d8 = rdop(minx); if ( ( ( minx->F & ( FLAG_S | FLAG_O ) ) == 0 ) || ( ( minx->F & ( FLAG_S | FLAG_O ) ) == ( FLAG_S | FLAG_O ) ) ) { CALL( minx, minx->PC + d8 - 1 ); } } +OP(F4) { INT8 d8 = rdop(minx); if ( ( minx->F & FLAG_O ) ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } } +OP(F5) { INT8 d8 = rdop(minx); if ( ! ( minx->F & FLAG_O ) ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } } +OP(F6) { INT8 d8 = rdop(minx); if ( ! ( minx->F & FLAG_S ) ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } } +OP(F7) { INT8 d8 = rdop(minx); if ( ( minx->F & FLAG_S ) ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } } +OP(F8) { INT8 d8 = rdop(minx); if ( ! ( minx->E & EXEC_X0 ) ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } } +OP(F9) { INT8 d8 = rdop(minx); if ( ! ( minx->E & EXEC_X1 ) ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } } +OP(FA) { INT8 d8 = rdop(minx); if ( ! ( minx->E & EXEC_X2 ) ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } } +OP(FB) { INT8 d8 = rdop(minx); if ( ! ( minx->E & EXEC_DZ ) ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } } +OP(FC) { INT8 d8 = rdop(minx); if ( ( minx->E & EXEC_X0 ) ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } } +OP(FD) { INT8 d8 = rdop(minx); if ( ( minx->E & EXEC_X1 ) ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } } +OP(FE) { INT8 d8 = rdop(minx); if ( ( minx->E & EXEC_X2 ) ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } } +OP(FF) { INT8 d8 = rdop(minx); if ( ( minx->E & EXEC_DZ ) ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } } -static void (*const insnminx_CE[256])(void) = { +static void (*const insnminx_CE[256])(minx_state *minx) = { minx_CE_00, minx_CE_01, minx_CE_02, minx_CE_03, minx_CE_04, minx_CE_05, minx_CE_06, minx_CE_07, minx_CE_08, minx_CE_09, minx_CE_0A, minx_CE_0B, minx_CE_0C, minx_CE_0D, minx_CE_0E, minx_CE_0F, minx_CE_10, minx_CE_11, minx_CE_12, minx_CE_13, minx_CE_14, minx_CE_15, minx_CE_16, minx_CE_17, diff --git a/src/emu/cpu/minx/minxopcf.h b/src/emu/cpu/minx/minxopcf.h index 09b59f9ce2e..ed606a2b68f 100644 --- a/src/emu/cpu/minx/minxopcf.h +++ b/src/emu/cpu/minx/minxopcf.h @@ -1,22 +1,22 @@ #undef OP -#define OP(nn) INLINE void minx_CF_##nn(void) +#define OP(nn) INLINE void minx_CF_##nn(minx_state *minx) -OP(00) { regs.BA = ADD16( regs.BA, regs.BA ); } -OP(01) { regs.BA = ADD16( regs.BA, regs.HL ); } -OP(02) { regs.BA = ADD16( regs.BA, regs.X ); } -OP(03) { regs.BA = ADD16( regs.BA, regs.Y ); } -OP(04) { regs.BA = ADDC16( regs.BA, regs.BA ); } -OP(05) { regs.BA = ADDC16( regs.BA, regs.HL ); } -OP(06) { regs.BA = ADDC16( regs.BA, regs.X ); } -OP(07) { regs.BA = ADDC16( regs.BA, regs.Y ); } -OP(08) { regs.BA = SUB16( regs.BA, regs.BA ); } -OP(09) { regs.BA = SUB16( regs.BA, regs.HL ); } -OP(0A) { regs.BA = SUB16( regs.BA, regs.X ); } -OP(0B) { regs.BA = SUB16( regs.BA, regs.Y ); } -OP(0C) { regs.BA = SUBC16( regs.BA, regs.BA ); } -OP(0D) { regs.BA = SUBC16( regs.BA, regs.HL ); } -OP(0E) { regs.BA = SUBC16( regs.BA, regs.X ); } -OP(0F) { regs.BA = SUBC16( regs.BA, regs.Y ); } +OP(00) { minx->BA = ADD16( minx, minx->BA, minx->BA ); } +OP(01) { minx->BA = ADD16( minx, minx->BA, minx->HL ); } +OP(02) { minx->BA = ADD16( minx, minx->BA, minx->X ); } +OP(03) { minx->BA = ADD16( minx, minx->BA, minx->Y ); } +OP(04) { minx->BA = ADDC16( minx, minx->BA, minx->BA ); } +OP(05) { minx->BA = ADDC16( minx, minx->BA, minx->HL ); } +OP(06) { minx->BA = ADDC16( minx, minx->BA, minx->X ); } +OP(07) { minx->BA = ADDC16( minx, minx->BA, minx->Y ); } +OP(08) { minx->BA = SUB16( minx, minx->BA, minx->BA ); } +OP(09) { minx->BA = SUB16( minx, minx->BA, minx->HL ); } +OP(0A) { minx->BA = SUB16( minx, minx->BA, minx->X ); } +OP(0B) { minx->BA = SUB16( minx, minx->BA, minx->Y ); } +OP(0C) { minx->BA = SUBC16( minx, minx->BA, minx->BA ); } +OP(0D) { minx->BA = SUBC16( minx, minx->BA, minx->HL ); } +OP(0E) { minx->BA = SUBC16( minx, minx->BA, minx->X ); } +OP(0F) { minx->BA = SUBC16( minx, minx->BA, minx->Y ); } OP(10) { /* illegal instruction? */ } OP(11) { /* illegal instruction? */ } @@ -26,31 +26,31 @@ OP(14) { /* illegal instruction? */ } OP(15) { /* illegal instruction? */ } OP(16) { /* illegal instruction? */ } OP(17) { /* illegal instruction? */ } -OP(18) { SUB16( regs.BA, regs.BA ); } -OP(19) { SUB16( regs.BA, regs.HL ); } -OP(1A) { SUB16( regs.BA, regs.X ); } -OP(1B) { SUB16( regs.BA, regs.Y ); } +OP(18) { SUB16( minx, minx->BA, minx->BA ); } +OP(19) { SUB16( minx, minx->BA, minx->HL ); } +OP(1A) { SUB16( minx, minx->BA, minx->X ); } +OP(1B) { SUB16( minx, minx->BA, minx->Y ); } OP(1C) { /* illegal instruction? */ } OP(1D) { /* illegal instruction? */ } OP(1E) { /* illegal instruction? */ } OP(1F) { /* illegal instruction? */ } -OP(20) { regs.HL = ADD16( regs.HL, regs.BA ); } -OP(21) { regs.HL = ADD16( regs.HL, regs.HL ); } -OP(22) { regs.HL = ADD16( regs.HL, regs.X ); } -OP(23) { regs.HL = ADD16( regs.HL, regs.Y ); } -OP(24) { regs.HL = ADDC16( regs.HL, regs.BA ); } -OP(25) { regs.HL = ADDC16( regs.HL, regs.HL ); } -OP(26) { regs.HL = ADDC16( regs.HL, regs.X ); } -OP(27) { regs.HL = ADDC16( regs.HL, regs.Y ); } -OP(28) { regs.HL = SUB16( regs.HL, regs.BA ); } -OP(29) { regs.HL = SUB16( regs.HL, regs.HL ); } -OP(2A) { regs.HL = SUB16( regs.HL, regs.X ); } -OP(2B) { regs.HL = SUB16( regs.HL, regs.Y ); } -OP(2C) { regs.HL = SUBC16( regs.HL, regs.BA ); } -OP(2D) { regs.HL = SUBC16( regs.HL, regs.HL ); } -OP(2E) { regs.HL = SUBC16( regs.HL, regs.X ); } -OP(2F) { regs.HL = SUBC16( regs.HL, regs.Y ); } +OP(20) { minx->HL = ADD16( minx, minx->HL, minx->BA ); } +OP(21) { minx->HL = ADD16( minx, minx->HL, minx->HL ); } +OP(22) { minx->HL = ADD16( minx, minx->HL, minx->X ); } +OP(23) { minx->HL = ADD16( minx, minx->HL, minx->Y ); } +OP(24) { minx->HL = ADDC16( minx, minx->HL, minx->BA ); } +OP(25) { minx->HL = ADDC16( minx, minx->HL, minx->HL ); } +OP(26) { minx->HL = ADDC16( minx, minx->HL, minx->X ); } +OP(27) { minx->HL = ADDC16( minx, minx->HL, minx->Y ); } +OP(28) { minx->HL = SUB16( minx, minx->HL, minx->BA ); } +OP(29) { minx->HL = SUB16( minx, minx->HL, minx->HL ); } +OP(2A) { minx->HL = SUB16( minx, minx->HL, minx->X ); } +OP(2B) { minx->HL = SUB16( minx, minx->HL, minx->Y ); } +OP(2C) { minx->HL = SUBC16( minx, minx->HL, minx->BA ); } +OP(2D) { minx->HL = SUBC16( minx, minx->HL, minx->HL ); } +OP(2E) { minx->HL = SUBC16( minx, minx->HL, minx->X ); } +OP(2F) { minx->HL = SUBC16( minx, minx->HL, minx->Y ); } OP(30) { /* illegal instruction? */ } OP(31) { /* illegal instruction? */ } @@ -60,29 +60,29 @@ OP(34) { /* illegal instruction? */ } OP(35) { /* illegal instruction? */ } OP(36) { /* illegal instruction? */ } OP(37) { /* illegal instruction? */ } -OP(38) { SUB16( regs.HL, regs.BA ); } -OP(39) { SUB16( regs.HL, regs.HL ); } -OP(3A) { SUB16( regs.HL, regs.X ); } -OP(3B) { SUB16( regs.HL, regs.Y ); } +OP(38) { SUB16( minx, minx->HL, minx->BA ); } +OP(39) { SUB16( minx, minx->HL, minx->HL ); } +OP(3A) { SUB16( minx, minx->HL, minx->X ); } +OP(3B) { SUB16( minx, minx->HL, minx->Y ); } OP(3C) { /* illegal instruction? */ } OP(3D) { /* illegal instruction? */ } OP(3E) { /* illegal instruction? */ } OP(3F) { /* illegal instruction? */ } -OP(40) { regs.X = ADD16( regs.X, regs.BA ); } -OP(41) { regs.X = ADD16( regs.X, regs.HL ); } -OP(42) { regs.Y = ADD16( regs.Y, regs.BA ); } -OP(43) { regs.Y = ADD16( regs.Y, regs.HL ); } -OP(44) { regs.SP = ADD16( regs.SP, regs.BA ); } -OP(45) { regs.SP = ADD16( regs.SP, regs.HL ); } +OP(40) { minx->X = ADD16( minx, minx->X, minx->BA ); } +OP(41) { minx->X = ADD16( minx, minx->X, minx->HL ); } +OP(42) { minx->Y = ADD16( minx, minx->Y, minx->BA ); } +OP(43) { minx->Y = ADD16( minx, minx->Y, minx->HL ); } +OP(44) { minx->SP = ADD16( minx, minx->SP, minx->BA ); } +OP(45) { minx->SP = ADD16( minx, minx->SP, minx->HL ); } OP(46) { /* illegal instruction? */ } OP(47) { /* illegal instruction? */ } -OP(48) { regs.X = SUB16( regs.X, regs.BA ); } -OP(49) { regs.X = SUB16( regs.X, regs.HL ); } -OP(4A) { regs.Y = SUB16( regs.Y, regs.BA ); } -OP(4B) { regs.Y = SUB16( regs.Y, regs.HL ); } -OP(4C) { regs.SP = SUB16( regs.SP, regs.BA ); } -OP(4D) { regs.SP = SUB16( regs.SP, regs.HL ); } +OP(48) { minx->X = SUB16( minx, minx->X, minx->BA ); } +OP(49) { minx->X = SUB16( minx, minx->X, minx->HL ); } +OP(4A) { minx->Y = SUB16( minx, minx->Y, minx->BA ); } +OP(4B) { minx->Y = SUB16( minx, minx->Y, minx->HL ); } +OP(4C) { minx->SP = SUB16( minx, minx->SP, minx->BA ); } +OP(4D) { minx->SP = SUB16( minx, minx->SP, minx->HL ); } OP(4E) { /* illegal instruction? */ } OP(4F) { /* illegal instruction? */ } @@ -98,41 +98,41 @@ OP(58) { /* illegal instruction? */ } OP(59) { /* illegal instruction? */ } OP(5A) { /* illegal instruction? */ } OP(5B) { /* illegal instruction? */ } -OP(5C) { SUB16( regs.SP, regs.BA ); } -OP(5D) { SUB16( regs.SP, regs.HL ); } +OP(5C) { SUB16( minx, minx->SP, minx->BA ); } +OP(5D) { SUB16( minx, minx->SP, minx->HL ); } OP(5E) { /* illegal instruction? */ } OP(5F) { /* illegal instruction? */ } -OP(60) { ADDC16( regs.BA, rdop16() ); /* ??? */ } -OP(61) { ADDC16( regs.HL, rdop16() ); /* ??? */ } -OP(62) { ADDC16( regs.X, rdop16() ); /* ??? */ } -OP(63) { ADDC16( regs.Y, rdop16() ); /* ??? */ } +OP(60) { ADDC16( minx, minx->BA, rdop16(minx) ); /* ??? */ } +OP(61) { ADDC16( minx, minx->HL, rdop16(minx) ); /* ??? */ } +OP(62) { ADDC16( minx, minx->X, rdop16(minx) ); /* ??? */ } +OP(63) { ADDC16( minx, minx->Y, rdop16(minx) ); /* ??? */ } OP(64) { /* illegal instruction? */ } OP(65) { /* illegal instruction? */ } OP(66) { /* illegal instruction? */ } OP(67) { /* illegal instruction? */ } -OP(68) { regs.SP = ADD16( regs.SP, rdop16() ); } +OP(68) { minx->SP = ADD16( minx, minx->SP, rdop16(minx) ); } OP(69) { /* illegal instruction? */ } -OP(6A) { regs.SP = SUB16( regs.SP, rdop16() ); } +OP(6A) { minx->SP = SUB16( minx, minx->SP, rdop16(minx) ); } OP(6B) { /* illegal instruction? */ } -OP(6C) { SUB16( regs.SP, rdop16() ); } +OP(6C) { SUB16( minx, minx->SP, rdop16(minx) ); } OP(6D) { /* illegal instruction? */ } -OP(6E) { regs.SP = rdop16(); } +OP(6E) { minx->SP = rdop16(minx); } OP(6F) { /* illegal instruction? */ } -OP(70) { UINT8 ofs8 = rdop(); regs.BA = rd16( regs.SP + ofs8 ); } -OP(71) { UINT8 ofs8 = rdop(); regs.HL = rd16( regs.SP + ofs8 ); } -OP(72) { UINT8 ofs8 = rdop(); regs.X = rd16( regs.SP + ofs8 ); } -OP(73) { UINT8 ofs8 = rdop(); regs.Y = rd16( regs.SP + ofs8 ); } -OP(74) { UINT8 ofs8 = rdop(); wr16( regs.SP + ofs8, regs.BA ); } -OP(75) { UINT8 ofs8 = rdop(); wr16( regs.SP + ofs8, regs.HL ); } -OP(76) { UINT8 ofs8 = rdop(); wr16( regs.SP + ofs8, regs.X ); } -OP(77) { UINT8 ofs8 = rdop(); wr16( regs.SP + ofs8, regs.Y ); } -OP(78) { AD2_I16; regs.SP = rd16( addr2 ); } +OP(70) { UINT8 ofs8 = rdop(minx); minx->BA = rd16( minx, minx->SP + ofs8 ); } +OP(71) { UINT8 ofs8 = rdop(minx); minx->HL = rd16( minx, minx->SP + ofs8 ); } +OP(72) { UINT8 ofs8 = rdop(minx); minx->X = rd16( minx, minx->SP + ofs8 ); } +OP(73) { UINT8 ofs8 = rdop(minx); minx->Y = rd16( minx, minx->SP + ofs8 ); } +OP(74) { UINT8 ofs8 = rdop(minx); wr16( minx, minx->SP + ofs8, minx->BA ); } +OP(75) { UINT8 ofs8 = rdop(minx); wr16( minx, minx->SP + ofs8, minx->HL ); } +OP(76) { UINT8 ofs8 = rdop(minx); wr16( minx, minx->SP + ofs8, minx->X ); } +OP(77) { UINT8 ofs8 = rdop(minx); wr16( minx, minx->SP + ofs8, minx->Y ); } +OP(78) { AD2_I16; minx->SP = rd16( minx, addr2 ); } OP(79) { /* illegal instruction? */ } OP(7A) { /* illegal instruction? */ } OP(7B) { /* illegal instruction? */ } -OP(7C) { AD1_I16; wr16( addr1, regs.SP ); } +OP(7C) { AD1_I16; wr16( minx, addr1, minx->SP ); } OP(7D) { /* illegal instruction? */ } OP(7E) { /* illegal instruction? */ } OP(7F) { /* illegal instruction? */ } @@ -188,31 +188,31 @@ OP(AD) { /* illegal instruction? */ } OP(AE) { /* illegal instruction? */ } OP(AF) { /* illegal instruction? */ } -OP(B0) { PUSH8( regs.BA & 0x00FF ); } -OP(B1) { PUSH8( regs.BA >> 8 ); } -OP(B2) { PUSH8( regs.HL & 0x00FF ); } -OP(B3) { PUSH8( regs.HL >> 8 ); } -OP(B4) { regs.BA = ( regs.BA & 0xFF00 ) | POP8(); } -OP(B5) { regs.BA = ( regs.BA & 0x00FF ) | ( POP8() << 8 ); } -OP(B6) { regs.HL = ( regs.HL & 0xFF00 ) | POP8(); } -OP(B7) { regs.HL = ( regs.HL & 0x00FF ) | ( POP8() << 8 ); } -OP(B8) { PUSH16( regs.BA ); PUSH16( regs.HL ); PUSH16( regs.X ); PUSH16( regs.Y ); PUSH8( regs.N ); } -OP(B9) { PUSH16( regs.BA ); PUSH16( regs.HL ); PUSH16( regs.X ); PUSH16( regs.Y ); PUSH8( regs.N ); PUSH8( regs.I ); PUSH8( regs.XI ); PUSH8( regs.YI ); } +OP(B0) { PUSH8( minx, minx->BA & 0x00FF ); } +OP(B1) { PUSH8( minx, minx->BA >> 8 ); } +OP(B2) { PUSH8( minx, minx->HL & 0x00FF ); } +OP(B3) { PUSH8( minx, minx->HL >> 8 ); } +OP(B4) { minx->BA = ( minx->BA & 0xFF00 ) | POP8(minx); } +OP(B5) { minx->BA = ( minx->BA & 0x00FF ) | ( POP8(minx) << 8 ); } +OP(B6) { minx->HL = ( minx->HL & 0xFF00 ) | POP8(minx); } +OP(B7) { minx->HL = ( minx->HL & 0x00FF ) | ( POP8(minx) << 8 ); } +OP(B8) { PUSH16( minx, minx->BA ); PUSH16( minx, minx->HL ); PUSH16( minx, minx->X ); PUSH16( minx, minx->Y ); PUSH8( minx, minx->N ); } +OP(B9) { PUSH16( minx, minx->BA ); PUSH16( minx, minx->HL ); PUSH16( minx, minx->X ); PUSH16( minx, minx->Y ); PUSH8( minx, minx->N ); PUSH8( minx, minx->I ); PUSH8( minx, minx->XI ); PUSH8( minx, minx->YI ); } OP(BA) { /* illegal instruction? */ } OP(BB) { /* illegal instruction? */ } -OP(BC) { regs.N = POP8(); regs.Y = POP16(); regs.X = POP16(); regs.HL = POP16(); regs.BA = POP16(); } -OP(BD) { regs.YI = POP8(); regs.XI = POP8(); regs.I = POP8(); regs.N = POP8(); regs.Y = POP16(); regs.X = POP16(); regs.HL = POP16(); regs.BA = POP16(); } +OP(BC) { minx->N = POP8(minx); minx->Y = POP16(minx); minx->X = POP16(minx); minx->HL = POP16(minx); minx->BA = POP16(minx); } +OP(BD) { minx->YI = POP8(minx); minx->XI = POP8(minx); minx->I = POP8(minx); minx->N = POP8(minx); minx->Y = POP16(minx); minx->X = POP16(minx); minx->HL = POP16(minx); minx->BA = POP16(minx); } OP(BE) { /* illegal instruction? */ } OP(BF) { /* illegal instruction? */ } -OP(C0) { AD2_IHL; regs.BA = rd16( addr2 ); } -OP(C1) { AD2_IHL; regs.HL = rd16( addr2 ); } -OP(C2) { AD2_IHL; regs.X = rd16( addr2 ); } -OP(C3) { AD2_IHL; regs.Y = rd16( addr2 ); } -OP(C4) { AD1_IHL; wr16( addr1, regs.BA ); } -OP(C5) { AD1_IHL; wr16( addr1, regs.HL ); } -OP(C6) { AD1_IHL; wr16( addr1, regs.X ); } -OP(C7) { AD1_IHL; wr16( addr1, regs.Y ); } +OP(C0) { AD2_IHL; minx->BA = rd16( minx, addr2 ); } +OP(C1) { AD2_IHL; minx->HL = rd16( minx, addr2 ); } +OP(C2) { AD2_IHL; minx->X = rd16( minx, addr2 ); } +OP(C3) { AD2_IHL; minx->Y = rd16( minx, addr2 ); } +OP(C4) { AD1_IHL; wr16( minx, addr1, minx->BA ); } +OP(C5) { AD1_IHL; wr16( minx, addr1, minx->HL ); } +OP(C6) { AD1_IHL; wr16( minx, addr1, minx->X ); } +OP(C7) { AD1_IHL; wr16( minx, addr1, minx->Y ); } OP(C8) { /* illegal instruction? */ } OP(C9) { /* illegal instruction? */ } OP(CA) { /* illegal instruction? */ } @@ -222,58 +222,58 @@ OP(CD) { /* illegal instruction? */ } OP(CE) { /* illegal instruction? */ } OP(CF) { /* illegal instruction? */ } -OP(D0) { AD2_XIX; regs.BA = rd16( addr2 ); } -OP(D1) { AD2_XIX; regs.HL = rd16( addr2 ); } -OP(D2) { AD2_XIX; regs.X = rd16( addr2 ); } -OP(D3) { AD2_XIX; regs.Y = rd16( addr2 ); } -OP(D4) { AD1_XIX; wr16( addr1, regs.BA ); } -OP(D5) { AD1_XIX; wr16( addr1, regs.HL ); } -OP(D6) { AD1_XIX; wr16( addr1, regs.X ); } -OP(D7) { AD1_XIX; wr16( addr1, regs.Y ); } -OP(D8) { AD2_YIY; regs.BA = rd16( addr2 ); } -OP(D9) { AD2_YIY; regs.HL = rd16( addr2 ); } -OP(DA) { AD2_YIY; regs.X = rd16( addr2 ); } -OP(DB) { AD2_YIY; regs.Y = rd16( addr2 ); } -OP(DC) { AD1_YIY; wr16( addr1, regs.BA ); } -OP(DD) { AD1_YIY; wr16( addr1, regs.HL ); } -OP(DE) { AD1_YIY; wr16( addr1, regs.X ); } -OP(DF) { AD1_YIY; wr16( addr1, regs.Y ); } +OP(D0) { AD2_XIX; minx->BA = rd16( minx, addr2 ); } +OP(D1) { AD2_XIX; minx->HL = rd16( minx, addr2 ); } +OP(D2) { AD2_XIX; minx->X = rd16( minx, addr2 ); } +OP(D3) { AD2_XIX; minx->Y = rd16( minx, addr2 ); } +OP(D4) { AD1_XIX; wr16( minx, addr1, minx->BA ); } +OP(D5) { AD1_XIX; wr16( minx, addr1, minx->HL ); } +OP(D6) { AD1_XIX; wr16( minx, addr1, minx->X ); } +OP(D7) { AD1_XIX; wr16( minx, addr1, minx->Y ); } +OP(D8) { AD2_YIY; minx->BA = rd16( minx, addr2 ); } +OP(D9) { AD2_YIY; minx->HL = rd16( minx, addr2 ); } +OP(DA) { AD2_YIY; minx->X = rd16( minx, addr2 ); } +OP(DB) { AD2_YIY; minx->Y = rd16( minx, addr2 ); } +OP(DC) { AD1_YIY; wr16( minx, addr1, minx->BA ); } +OP(DD) { AD1_YIY; wr16( minx, addr1, minx->HL ); } +OP(DE) { AD1_YIY; wr16( minx, addr1, minx->X ); } +OP(DF) { AD1_YIY; wr16( minx, addr1, minx->Y ); } -OP(E0) { regs.BA = regs.BA; } -OP(E1) { regs.BA = regs.HL; } -OP(E2) { regs.BA = regs.X; } -OP(E3) { regs.BA = regs.Y; } -OP(E4) { regs.HL = regs.BA; } -OP(E5) { regs.HL = regs.HL; } -OP(E6) { regs.HL = regs.X; } -OP(E7) { regs.HL = regs.Y; } -OP(E8) { regs.X = regs.BA; } -OP(E9) { regs.X = regs.HL; } -OP(EA) { regs.X = regs.X; } -OP(EB) { regs.X = regs.Y; } -OP(EC) { regs.Y = regs.BA; } -OP(ED) { regs.Y = regs.HL; } -OP(EE) { regs.Y = regs.X; } -OP(EF) { regs.Y = regs.Y; } +OP(E0) { minx->BA = minx->BA; } +OP(E1) { minx->BA = minx->HL; } +OP(E2) { minx->BA = minx->X; } +OP(E3) { minx->BA = minx->Y; } +OP(E4) { minx->HL = minx->BA; } +OP(E5) { minx->HL = minx->HL; } +OP(E6) { minx->HL = minx->X; } +OP(E7) { minx->HL = minx->Y; } +OP(E8) { minx->X = minx->BA; } +OP(E9) { minx->X = minx->HL; } +OP(EA) { minx->X = minx->X; } +OP(EB) { minx->X = minx->Y; } +OP(EC) { minx->Y = minx->BA; } +OP(ED) { minx->Y = minx->HL; } +OP(EE) { minx->Y = minx->X; } +OP(EF) { minx->Y = minx->Y; } -OP(F0) { regs.SP = regs.BA; } -OP(F1) { regs.SP = regs.HL; } -OP(F2) { regs.SP = regs.X; } -OP(F3) { regs.SP = regs.Y; } -OP(F4) { regs.HL = regs.SP; } -OP(F5) { regs.HL = regs.PC; } +OP(F0) { minx->SP = minx->BA; } +OP(F1) { minx->SP = minx->HL; } +OP(F2) { minx->SP = minx->X; } +OP(F3) { minx->SP = minx->Y; } +OP(F4) { minx->HL = minx->SP; } +OP(F5) { minx->HL = minx->PC; } OP(F6) { /* illegal instruction? */ } OP(F7) { /* illegal instruction? */ } -OP(F8) { regs.BA = regs.SP; } -OP(F9) { regs.BA = regs.PC; } -OP(FA) { regs.X = regs.SP; } +OP(F8) { minx->BA = minx->SP; } +OP(F9) { minx->BA = minx->PC; } +OP(FA) { minx->X = minx->SP; } OP(FB) { /* illegal instruction? */ } OP(FC) { /* illegal instruction? */ } OP(FD) { /* illegal instruction? */ } -OP(FE) { regs.Y = regs.SP; } +OP(FE) { minx->Y = minx->SP; } OP(FF) { /* illegal instruction? */ } -static void (*const insnminx_CF[256])(void) = { +static void (*const insnminx_CF[256])(minx_state *minx) = { minx_CF_00, minx_CF_01, minx_CF_02, minx_CF_03, minx_CF_04, minx_CF_05, minx_CF_06, minx_CF_07, minx_CF_08, minx_CF_09, minx_CF_0A, minx_CF_0B, minx_CF_0C, minx_CF_0D, minx_CF_0E, minx_CF_0F, minx_CF_10, minx_CF_11, minx_CF_12, minx_CF_13, minx_CF_14, minx_CF_15, minx_CF_16, minx_CF_17, diff --git a/src/emu/cpu/minx/minxops.h b/src/emu/cpu/minx/minxops.h index 484b2e7c2d7..fce4bb70652 100644 --- a/src/emu/cpu/minx/minxops.h +++ b/src/emu/cpu/minx/minxops.h @@ -1,279 +1,279 @@ #undef OP -#define OP(nn) INLINE void minx_##nn(void) +#define OP(nn) INLINE void minx_##nn(minx_state *minx) -OP(00) { regs.BA = ( regs.BA & 0xFF00 ) | ADD8( ( regs.BA & 0x00FF ), ( regs.BA & 0xFF ) ); } -OP(01) { regs.BA = ( regs.BA & 0xFF00 ) | ADD8( ( regs.BA & 0x00FF ), ( regs.BA >> 8 ) ); } -OP(02) { regs.BA = ( regs.BA & 0xFF00 ) | ADD8( ( regs.BA & 0x00FF ), rdop() ); } -OP(03) { AD2_IHL; regs.BA = ( regs.BA & 0xFF00 ) | ADD8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(04) { AD2_IN8; regs.BA = ( regs.BA & 0xFF00 ) | ADD8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(05) { AD2_I16; regs.BA = ( regs.BA & 0xFF00 ) | ADD8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(06) { AD2_XIX; regs.BA = ( regs.BA & 0xFF00 ) | ADD8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(07) { AD2_YIY; regs.BA = ( regs.BA & 0xFF00 ) | ADD8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(08) { regs.BA = ( regs.BA & 0xFF00 ) | ADDC8( ( regs.BA & 0x00FF ), ( regs.BA & 0xFF ) ); } -OP(09) { regs.BA = ( regs.BA & 0xFF00 ) | ADDC8( ( regs.BA & 0x00FF ), ( regs.BA >> 8 ) ); } -OP(0A) { regs.BA = ( regs.BA & 0xFF00 ) | ADDC8( ( regs.BA & 0x00FF ), rdop() ); } -OP(0B) { AD2_IHL; regs.BA = ( regs.BA & 0xFF00 ) | ADDC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(0C) { AD2_IN8; regs.BA = ( regs.BA & 0xFF00 ) | ADDC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(0D) { AD2_I16; regs.BA = ( regs.BA & 0xFF00 ) | ADDC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(0E) { AD2_XIX; regs.BA = ( regs.BA & 0xFF00 ) | ADDC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(0F) { AD2_YIY; regs.BA = ( regs.BA & 0xFF00 ) | ADDC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(00) { minx->BA = ( minx->BA & 0xFF00 ) | ADD8( minx, ( minx->BA & 0x00FF ), ( minx->BA & 0xFF ) ); } +OP(01) { minx->BA = ( minx->BA & 0xFF00 ) | ADD8( minx, ( minx->BA & 0x00FF ), ( minx->BA >> 8 ) ); } +OP(02) { minx->BA = ( minx->BA & 0xFF00 ) | ADD8( minx, ( minx->BA & 0x00FF ), rdop(minx) ); } +OP(03) { AD2_IHL; minx->BA = ( minx->BA & 0xFF00 ) | ADD8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(04) { AD2_IN8; minx->BA = ( minx->BA & 0xFF00 ) | ADD8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(05) { AD2_I16; minx->BA = ( minx->BA & 0xFF00 ) | ADD8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(06) { AD2_XIX; minx->BA = ( minx->BA & 0xFF00 ) | ADD8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(07) { AD2_YIY; minx->BA = ( minx->BA & 0xFF00 ) | ADD8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(08) { minx->BA = ( minx->BA & 0xFF00 ) | ADDC8( minx, ( minx->BA & 0x00FF ), ( minx->BA & 0xFF ) ); } +OP(09) { minx->BA = ( minx->BA & 0xFF00 ) | ADDC8( minx, ( minx->BA & 0x00FF ), ( minx->BA >> 8 ) ); } +OP(0A) { minx->BA = ( minx->BA & 0xFF00 ) | ADDC8( minx, ( minx->BA & 0x00FF ), rdop(minx) ); } +OP(0B) { AD2_IHL; minx->BA = ( minx->BA & 0xFF00 ) | ADDC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(0C) { AD2_IN8; minx->BA = ( minx->BA & 0xFF00 ) | ADDC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(0D) { AD2_I16; minx->BA = ( minx->BA & 0xFF00 ) | ADDC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(0E) { AD2_XIX; minx->BA = ( minx->BA & 0xFF00 ) | ADDC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(0F) { AD2_YIY; minx->BA = ( minx->BA & 0xFF00 ) | ADDC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } -OP(10) { regs.BA = ( regs.BA & 0xFF00 ) | SUB8( ( regs.BA & 0x00FF ), ( regs.BA & 0xFF ) ); } -OP(11) { regs.BA = ( regs.BA & 0xFF00 ) | SUB8( ( regs.BA & 0x00FF ), ( regs.BA >> 8 ) ); } -OP(12) { regs.BA = ( regs.BA & 0xFF00 ) | SUB8( ( regs.BA & 0x00FF ), rdop() ); } -OP(13) { AD2_IHL; regs.BA = ( regs.BA & 0xFF00 ) | SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(14) { AD2_IN8; regs.BA = ( regs.BA & 0xFF00 ) | SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(15) { AD2_I16; regs.BA = ( regs.BA & 0xFF00 ) | SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(16) { AD2_XIX; regs.BA = ( regs.BA & 0xFF00 ) | SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(17) { AD2_YIY; regs.BA = ( regs.BA & 0xFF00 ) | SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(18) { regs.BA = ( regs.BA & 0xFF00 ) | SUBC8( ( regs.BA & 0x00FF ), ( regs.BA & 0xFF ) ); } -OP(19) { regs.BA = ( regs.BA & 0xFF00 ) | SUBC8( ( regs.BA & 0x00FF ), ( regs.BA >> 8 ) ); } -OP(1A) { regs.BA = ( regs.BA & 0xFF00 ) | SUBC8( ( regs.BA & 0x00FF ), rdop() ); } -OP(1B) { AD2_IHL; regs.BA = ( regs.BA & 0xFF00 ) | SUBC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(1C) { AD2_IN8; regs.BA = ( regs.BA & 0xFF00 ) | SUBC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(1D) { AD2_I16; regs.BA = ( regs.BA & 0xFF00 ) | SUBC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(1E) { AD2_XIX; regs.BA = ( regs.BA & 0xFF00 ) | SUBC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(1F) { AD2_YIY; regs.BA = ( regs.BA & 0xFF00 ) | SUBC8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(10) { minx->BA = ( minx->BA & 0xFF00 ) | SUB8( minx, ( minx->BA & 0x00FF ), ( minx->BA & 0xFF ) ); } +OP(11) { minx->BA = ( minx->BA & 0xFF00 ) | SUB8( minx, ( minx->BA & 0x00FF ), ( minx->BA >> 8 ) ); } +OP(12) { minx->BA = ( minx->BA & 0xFF00 ) | SUB8( minx, ( minx->BA & 0x00FF ), rdop(minx) ); } +OP(13) { AD2_IHL; minx->BA = ( minx->BA & 0xFF00 ) | SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(14) { AD2_IN8; minx->BA = ( minx->BA & 0xFF00 ) | SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(15) { AD2_I16; minx->BA = ( minx->BA & 0xFF00 ) | SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(16) { AD2_XIX; minx->BA = ( minx->BA & 0xFF00 ) | SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(17) { AD2_YIY; minx->BA = ( minx->BA & 0xFF00 ) | SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(18) { minx->BA = ( minx->BA & 0xFF00 ) | SUBC8( minx, ( minx->BA & 0x00FF ), ( minx->BA & 0xFF ) ); } +OP(19) { minx->BA = ( minx->BA & 0xFF00 ) | SUBC8( minx, ( minx->BA & 0x00FF ), ( minx->BA >> 8 ) ); } +OP(1A) { minx->BA = ( minx->BA & 0xFF00 ) | SUBC8( minx, ( minx->BA & 0x00FF ), rdop(minx) ); } +OP(1B) { AD2_IHL; minx->BA = ( minx->BA & 0xFF00 ) | SUBC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(1C) { AD2_IN8; minx->BA = ( minx->BA & 0xFF00 ) | SUBC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(1D) { AD2_I16; minx->BA = ( minx->BA & 0xFF00 ) | SUBC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(1E) { AD2_XIX; minx->BA = ( minx->BA & 0xFF00 ) | SUBC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(1F) { AD2_YIY; minx->BA = ( minx->BA & 0xFF00 ) | SUBC8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } -OP(20) { regs.BA = ( regs.BA & 0xFF00 ) | AND8( ( regs.BA & 0x00FF ), ( regs.BA & 0xFF ) ); } -OP(21) { regs.BA = ( regs.BA & 0xFF00 ) | AND8( ( regs.BA & 0x00FF ), ( regs.BA >> 8 ) ); } -OP(22) { regs.BA = ( regs.BA & 0xFF00 ) | AND8( ( regs.BA & 0x00FF ), rdop() ); } -OP(23) { AD2_IHL; regs.BA = ( regs.BA & 0xFF00 ) | AND8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(24) { AD2_IN8; regs.BA = ( regs.BA & 0xFF00 ) | AND8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(25) { AD2_I16; regs.BA = ( regs.BA & 0xFF00 ) | AND8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(26) { AD2_XIX; regs.BA = ( regs.BA & 0xFF00 ) | AND8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(27) { AD2_YIY; regs.BA = ( regs.BA & 0xFF00 ) | AND8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(28) { regs.BA = ( regs.BA & 0xFF00 ) | OR8( ( regs.BA & 0x00FF ), ( regs.BA & 0xFF ) ); } -OP(29) { regs.BA = ( regs.BA & 0xFF00 ) | OR8( ( regs.BA & 0x00FF ), ( regs.BA >> 8 ) ); } -OP(2A) { regs.BA = ( regs.BA & 0xFF00 ) | OR8( ( regs.BA & 0x00FF ), rdop() ); } -OP(2B) { AD2_IHL; regs.BA = ( regs.BA & 0xFF00 ) | OR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(2C) { AD2_IN8; regs.BA = ( regs.BA & 0xFF00 ) | OR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(2D) { AD2_I16; regs.BA = ( regs.BA & 0xFF00 ) | OR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(2E) { AD2_XIX; regs.BA = ( regs.BA & 0xFF00 ) | OR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(2F) { AD2_YIY; regs.BA = ( regs.BA & 0xFF00 ) | OR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(20) { minx->BA = ( minx->BA & 0xFF00 ) | AND8( minx, ( minx->BA & 0x00FF ), ( minx->BA & 0xFF ) ); } +OP(21) { minx->BA = ( minx->BA & 0xFF00 ) | AND8( minx, ( minx->BA & 0x00FF ), ( minx->BA >> 8 ) ); } +OP(22) { minx->BA = ( minx->BA & 0xFF00 ) | AND8( minx, ( minx->BA & 0x00FF ), rdop(minx) ); } +OP(23) { AD2_IHL; minx->BA = ( minx->BA & 0xFF00 ) | AND8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(24) { AD2_IN8; minx->BA = ( minx->BA & 0xFF00 ) | AND8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(25) { AD2_I16; minx->BA = ( minx->BA & 0xFF00 ) | AND8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(26) { AD2_XIX; minx->BA = ( minx->BA & 0xFF00 ) | AND8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(27) { AD2_YIY; minx->BA = ( minx->BA & 0xFF00 ) | AND8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(28) { minx->BA = ( minx->BA & 0xFF00 ) | OR8( minx, ( minx->BA & 0x00FF ), ( minx->BA & 0xFF ) ); } +OP(29) { minx->BA = ( minx->BA & 0xFF00 ) | OR8( minx, ( minx->BA & 0x00FF ), ( minx->BA >> 8 ) ); } +OP(2A) { minx->BA = ( minx->BA & 0xFF00 ) | OR8( minx, ( minx->BA & 0x00FF ), rdop(minx) ); } +OP(2B) { AD2_IHL; minx->BA = ( minx->BA & 0xFF00 ) | OR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(2C) { AD2_IN8; minx->BA = ( minx->BA & 0xFF00 ) | OR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(2D) { AD2_I16; minx->BA = ( minx->BA & 0xFF00 ) | OR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(2E) { AD2_XIX; minx->BA = ( minx->BA & 0xFF00 ) | OR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(2F) { AD2_YIY; minx->BA = ( minx->BA & 0xFF00 ) | OR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } -OP(30) { SUB8( ( regs.BA & 0x00FF ), ( regs.BA & 0xFF ) ); } -OP(31) { SUB8( ( regs.BA & 0x00FF ), ( regs.BA >> 8 ) ); } -OP(32) { SUB8( ( regs.BA & 0x00FF ), rdop() ); } -OP(33) { AD2_IHL; SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(34) { AD2_IN8; SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(35) { AD2_I16; SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(36) { AD2_XIX; SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(37) { AD2_YIY; SUB8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(38) { regs.BA = ( regs.BA & 0xFF00 ) | XOR8( ( regs.BA & 0x00FF ), ( regs.BA & 0xFF ) ); } -OP(39) { regs.BA = ( regs.BA & 0xFF00 ) | XOR8( ( regs.BA & 0x00FF ), ( regs.BA >> 8 ) ); } -OP(3A) { regs.BA = ( regs.BA & 0xFF00 ) | XOR8( ( regs.BA & 0x00FF ), rdop() ); } -OP(3B) { AD2_IHL; regs.BA = ( regs.BA & 0xFF00 ) | XOR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(3C) { AD2_IN8; regs.BA = ( regs.BA & 0xFF00 ) | XOR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(3D) { AD2_I16; regs.BA = ( regs.BA & 0xFF00 ) | XOR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(3E) { AD2_XIX; regs.BA = ( regs.BA & 0xFF00 ) | XOR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } -OP(3F) { AD2_YIY; regs.BA = ( regs.BA & 0xFF00 ) | XOR8( ( regs.BA & 0x00FF ), RD( addr2 ) ); } +OP(30) { SUB8( minx, ( minx->BA & 0x00FF ), ( minx->BA & 0xFF ) ); } +OP(31) { SUB8( minx, ( minx->BA & 0x00FF ), ( minx->BA >> 8 ) ); } +OP(32) { SUB8( minx, ( minx->BA & 0x00FF ), rdop(minx) ); } +OP(33) { AD2_IHL; SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(34) { AD2_IN8; SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(35) { AD2_I16; SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(36) { AD2_XIX; SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(37) { AD2_YIY; SUB8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(38) { minx->BA = ( minx->BA & 0xFF00 ) | XOR8( minx, ( minx->BA & 0x00FF ), ( minx->BA & 0xFF ) ); } +OP(39) { minx->BA = ( minx->BA & 0xFF00 ) | XOR8( minx, ( minx->BA & 0x00FF ), ( minx->BA >> 8 ) ); } +OP(3A) { minx->BA = ( minx->BA & 0xFF00 ) | XOR8( minx, ( minx->BA & 0x00FF ), rdop(minx) ); } +OP(3B) { AD2_IHL; minx->BA = ( minx->BA & 0xFF00 ) | XOR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(3C) { AD2_IN8; minx->BA = ( minx->BA & 0xFF00 ) | XOR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(3D) { AD2_I16; minx->BA = ( minx->BA & 0xFF00 ) | XOR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(3E) { AD2_XIX; minx->BA = ( minx->BA & 0xFF00 ) | XOR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } +OP(3F) { AD2_YIY; minx->BA = ( minx->BA & 0xFF00 ) | XOR8( minx, ( minx->BA & 0x00FF ), RD( addr2 ) ); } -OP(40) { regs.BA = ( regs.BA & 0xFF00 ) | ( regs.BA & 0x00FF); } -OP(41) { regs.BA = ( regs.BA & 0xFF00 ) | ( regs.BA >> 8 ); } -OP(42) { regs.BA = ( regs.BA & 0xFF00 ) | ( regs.HL & 0x00FF); } -OP(43) { regs.BA = ( regs.BA & 0xFF00 ) | ( regs.HL >> 8 ); } -OP(44) { AD2_IN8; regs.BA = ( regs.BA & 0xFF00 ) | RD( addr2 ); } -OP(45) { AD2_IHL; regs.BA = ( regs.BA & 0xFF00 ) | RD( addr2 ); } -OP(46) { AD2_XIX; regs.BA = ( regs.BA & 0xFF00 ) | RD( addr2 ); } -OP(47) { AD2_YIY; regs.BA = ( regs.BA & 0xFF00 ) | RD( addr2 ); } -OP(48) { regs.BA = ( regs.BA & 0x00FF ) | ( ( regs.BA & 0x00FF) << 8 ); } -OP(49) { regs.BA = ( regs.BA & 0x00FF ) | ( ( regs.BA >> 8 ) << 8 ); } -OP(4A) { regs.BA = ( regs.BA & 0x00FF ) | ( ( regs.HL & 0x00FF) << 8 ); } -OP(4B) { regs.BA = ( regs.BA & 0x00FF ) | ( ( regs.HL >> 8 ) << 8 ); } -OP(4C) { AD2_IN8; regs.BA = ( regs.BA & 0x00FF ) | ( RD( addr2 ) << 8 ); } -OP(4D) { AD2_IHL; regs.BA = ( regs.BA & 0x00FF ) | ( RD( addr2 ) << 8 ); } -OP(4E) { AD2_XIX; regs.BA = ( regs.BA & 0x00FF ) | ( RD( addr2 ) << 8 ); } -OP(4F) { AD2_YIY; regs.BA = ( regs.BA & 0x00FF ) | ( RD( addr2 ) << 8 ); } +OP(40) { minx->BA = ( minx->BA & 0xFF00 ) | ( minx->BA & 0x00FF); } +OP(41) { minx->BA = ( minx->BA & 0xFF00 ) | ( minx->BA >> 8 ); } +OP(42) { minx->BA = ( minx->BA & 0xFF00 ) | ( minx->HL & 0x00FF); } +OP(43) { minx->BA = ( minx->BA & 0xFF00 ) | ( minx->HL >> 8 ); } +OP(44) { AD2_IN8; minx->BA = ( minx->BA & 0xFF00 ) | RD( addr2 ); } +OP(45) { AD2_IHL; minx->BA = ( minx->BA & 0xFF00 ) | RD( addr2 ); } +OP(46) { AD2_XIX; minx->BA = ( minx->BA & 0xFF00 ) | RD( addr2 ); } +OP(47) { AD2_YIY; minx->BA = ( minx->BA & 0xFF00 ) | RD( addr2 ); } +OP(48) { minx->BA = ( minx->BA & 0x00FF ) | ( ( minx->BA & 0x00FF) << 8 ); } +OP(49) { minx->BA = ( minx->BA & 0x00FF ) | ( ( minx->BA >> 8 ) << 8 ); } +OP(4A) { minx->BA = ( minx->BA & 0x00FF ) | ( ( minx->HL & 0x00FF) << 8 ); } +OP(4B) { minx->BA = ( minx->BA & 0x00FF ) | ( ( minx->HL >> 8 ) << 8 ); } +OP(4C) { AD2_IN8; minx->BA = ( minx->BA & 0x00FF ) | ( RD( addr2 ) << 8 ); } +OP(4D) { AD2_IHL; minx->BA = ( minx->BA & 0x00FF ) | ( RD( addr2 ) << 8 ); } +OP(4E) { AD2_XIX; minx->BA = ( minx->BA & 0x00FF ) | ( RD( addr2 ) << 8 ); } +OP(4F) { AD2_YIY; minx->BA = ( minx->BA & 0x00FF ) | ( RD( addr2 ) << 8 ); } -OP(50) { regs.HL = ( regs.HL & 0xFF00 ) | ( regs.BA & 0x00FF); } -OP(51) { regs.HL = ( regs.HL & 0xFF00 ) | ( regs.BA >> 8 ); } -OP(52) { regs.HL = ( regs.HL & 0xFF00 ) | ( regs.HL & 0x00FF); } -OP(53) { regs.HL = ( regs.HL & 0xFF00 ) | ( regs.HL >> 8 ); } -OP(54) { AD2_IN8; regs.HL = ( regs.HL & 0xFF00 ) | RD( addr2 ); } -OP(55) { AD2_IHL; regs.HL = ( regs.HL & 0xFF00 ) | RD( addr2 ); } -OP(56) { AD2_XIX; regs.HL = ( regs.HL & 0xFF00 ) | RD( addr2 ); } -OP(57) { AD2_YIY; regs.HL = ( regs.HL & 0xFF00 ) | RD( addr2 ); } -OP(58) { regs.HL = ( regs.HL & 0x00FF ) | ( ( regs.BA & 0x00FF) << 8 ); } -OP(59) { regs.HL = ( regs.HL & 0x00FF ) | ( ( regs.BA >> 8 ) << 8 ); } -OP(5A) { regs.HL = ( regs.HL & 0x00FF ) | ( ( regs.HL & 0x00FF) << 8 ); } -OP(5B) { regs.HL = ( regs.HL & 0x00FF ) | ( ( regs.HL >> 8 ) << 8 ); } -OP(5C) { AD2_IN8; regs.HL = ( regs.HL & 0x00FF ) | ( RD( addr2 ) << 8 ); } -OP(5D) { AD2_IHL; regs.HL = ( regs.HL & 0x00FF ) | ( RD( addr2 ) << 8 ); } -OP(5E) { AD2_XIX; regs.HL = ( regs.HL & 0x00FF ) | ( RD( addr2 ) << 8 ); } -OP(5F) { AD2_YIY; regs.HL = ( regs.HL & 0x00FF ) | ( RD( addr2 ) << 8 ); } +OP(50) { minx->HL = ( minx->HL & 0xFF00 ) | ( minx->BA & 0x00FF); } +OP(51) { minx->HL = ( minx->HL & 0xFF00 ) | ( minx->BA >> 8 ); } +OP(52) { minx->HL = ( minx->HL & 0xFF00 ) | ( minx->HL & 0x00FF); } +OP(53) { minx->HL = ( minx->HL & 0xFF00 ) | ( minx->HL >> 8 ); } +OP(54) { AD2_IN8; minx->HL = ( minx->HL & 0xFF00 ) | RD( addr2 ); } +OP(55) { AD2_IHL; minx->HL = ( minx->HL & 0xFF00 ) | RD( addr2 ); } +OP(56) { AD2_XIX; minx->HL = ( minx->HL & 0xFF00 ) | RD( addr2 ); } +OP(57) { AD2_YIY; minx->HL = ( minx->HL & 0xFF00 ) | RD( addr2 ); } +OP(58) { minx->HL = ( minx->HL & 0x00FF ) | ( ( minx->BA & 0x00FF) << 8 ); } +OP(59) { minx->HL = ( minx->HL & 0x00FF ) | ( ( minx->BA >> 8 ) << 8 ); } +OP(5A) { minx->HL = ( minx->HL & 0x00FF ) | ( ( minx->HL & 0x00FF) << 8 ); } +OP(5B) { minx->HL = ( minx->HL & 0x00FF ) | ( ( minx->HL >> 8 ) << 8 ); } +OP(5C) { AD2_IN8; minx->HL = ( minx->HL & 0x00FF ) | ( RD( addr2 ) << 8 ); } +OP(5D) { AD2_IHL; minx->HL = ( minx->HL & 0x00FF ) | ( RD( addr2 ) << 8 ); } +OP(5E) { AD2_XIX; minx->HL = ( minx->HL & 0x00FF ) | ( RD( addr2 ) << 8 ); } +OP(5F) { AD2_YIY; minx->HL = ( minx->HL & 0x00FF ) | ( RD( addr2 ) << 8 ); } -OP(60) { AD1_XIX; WR( addr1, ( regs.BA & 0x00FF ) ); } -OP(61) { AD1_XIX; WR( addr1, ( regs.BA >> 8 ) ); } -OP(62) { AD1_XIX; WR( addr1, ( regs.HL & 0x00FF ) ); } -OP(63) { AD1_XIX; WR( addr1, ( regs.HL >> 8 ) ); } +OP(60) { AD1_XIX; WR( addr1, ( minx->BA & 0x00FF ) ); } +OP(61) { AD1_XIX; WR( addr1, ( minx->BA >> 8 ) ); } +OP(62) { AD1_XIX; WR( addr1, ( minx->HL & 0x00FF ) ); } +OP(63) { AD1_XIX; WR( addr1, ( minx->HL >> 8 ) ); } OP(64) { AD1_XIX; AD2_IN8; WR( addr1, RD( addr2 ) ); } OP(65) { AD1_XIX; AD2_IHL; WR( addr1, RD( addr2 ) ); } OP(66) { AD1_XIX; AD2_XIX; WR( addr1, RD( addr2 ) ); } OP(67) { AD1_XIX; AD2_YIY; WR( addr1, RD( addr2 ) ); } -OP(68) { AD1_IHL; WR( addr1, ( regs.BA & 0x00FF ) ); } -OP(69) { AD1_IHL; WR( addr1, ( regs.BA >> 8 ) ); } -OP(6A) { AD1_IHL; WR( addr1, ( regs.HL & 0x00FF ) ); } -OP(6B) { AD1_IHL; WR( addr1, ( regs.HL >> 8 ) ); } +OP(68) { AD1_IHL; WR( addr1, ( minx->BA & 0x00FF ) ); } +OP(69) { AD1_IHL; WR( addr1, ( minx->BA >> 8 ) ); } +OP(6A) { AD1_IHL; WR( addr1, ( minx->HL & 0x00FF ) ); } +OP(6B) { AD1_IHL; WR( addr1, ( minx->HL >> 8 ) ); } OP(6C) { AD1_IHL; AD2_IN8; WR( addr1, RD( addr2 ) ); } OP(6D) { AD1_IHL; AD2_IHL; WR( addr1, RD( addr2 ) ); } OP(6E) { AD1_IHL; AD2_XIX; WR( addr1, RD( addr2 ) ); } OP(6F) { AD1_IHL; AD2_YIY; WR( addr1, RD( addr2 ) ); } -OP(70) { AD1_YIY; WR( addr1, ( regs.BA & 0x00FF ) ); } -OP(71) { AD1_YIY; WR( addr1, ( regs.BA >> 8 ) ); } -OP(72) { AD1_YIY; WR( addr1, ( regs.HL & 0x00FF ) ); } -OP(73) { AD1_YIY; WR( addr1, ( regs.HL >> 8 ) ); } +OP(70) { AD1_YIY; WR( addr1, ( minx->BA & 0x00FF ) ); } +OP(71) { AD1_YIY; WR( addr1, ( minx->BA >> 8 ) ); } +OP(72) { AD1_YIY; WR( addr1, ( minx->HL & 0x00FF ) ); } +OP(73) { AD1_YIY; WR( addr1, ( minx->HL >> 8 ) ); } OP(74) { AD1_YIY; AD2_IN8; WR( addr1, RD( addr2 ) ); } OP(75) { AD1_YIY; AD2_IHL; WR( addr1, RD( addr2 ) ); } OP(76) { AD1_YIY; AD2_XIX; WR( addr1, RD( addr2 ) ); } OP(77) { AD1_YIY; AD2_YIY; WR( addr1, RD( addr2 ) ); } -OP(78) { AD1_IN8; WR( addr1, ( regs.BA & 0x00FF ) ); } -OP(79) { AD1_IN8; WR( addr1, ( regs.BA >> 8 ) ); } -OP(7A) { AD1_IN8; WR( addr1, ( regs.HL & 0x00FF ) ); } -OP(7B) { AD1_IN8; WR( addr1, ( regs.HL >> 8 ) ); } +OP(78) { AD1_IN8; WR( addr1, ( minx->BA & 0x00FF ) ); } +OP(79) { AD1_IN8; WR( addr1, ( minx->BA >> 8 ) ); } +OP(7A) { AD1_IN8; WR( addr1, ( minx->HL & 0x00FF ) ); } +OP(7B) { AD1_IN8; WR( addr1, ( minx->HL >> 8 ) ); } OP(7C) { /* illegal operation? */ } OP(7D) { AD1_IN8; AD2_IHL; WR( addr1, RD( addr2 ) ); } OP(7E) { AD1_IN8; AD2_XIX; WR( addr1, RD( addr2 ) ); } OP(7F) { AD1_IN8; AD2_YIY; WR( addr1, RD( addr2 ) ); } -OP(80) { regs.BA = ( regs.BA & 0xFF00 ) | INC8( regs.BA & 0x00FF ); } -OP(81) { regs.BA = ( regs.BA & 0x00FF ) | ( INC8( regs.BA >> 8 ) << 8 ); } -OP(82) { regs.HL = ( regs.HL & 0xFF00 ) | INC8( regs.HL & 0x00FF ); } -OP(83) { regs.HL = ( regs.HL & 0x00FF ) | ( INC8( regs.HL >> 8 ) << 8 ); } -OP(84) { regs.N = INC8( regs.N ); } -OP(85) { AD1_IN8; WR( addr1, INC8( RD( addr1 ) ) ); } -OP(86) { AD1_IHL; WR( addr1, INC8( RD( addr1 ) ) ); } -OP(87) { regs.SP = INC16( regs.SP ); } -OP(88) { regs.BA = ( regs.BA & 0xFF00 ) | DEC8( regs.BA & 0x00FF ); } -OP(89) { regs.BA = ( regs.BA & 0x00FF ) | ( DEC8( regs.BA >> 8 ) << 8 ); } -OP(8A) { regs.HL = ( regs.HL & 0xFF00 ) | DEC8( regs.HL & 0x00FF ); } -OP(8B) { regs.HL = ( regs.HL & 0x00FF ) | ( DEC8( regs.HL >> 8 ) << 8 ); } -OP(8C) { regs.N = DEC8( regs.N ); } -OP(8D) { AD1_IN8; WR( addr1, DEC8( RD( addr1 ) ) ); } -OP(8E) { AD1_IHL; WR( addr1, DEC8( RD( addr1 ) ) ); } -OP(8F) { regs.SP = DEC8( regs.SP ); } +OP(80) { minx->BA = ( minx->BA & 0xFF00 ) | INC8( minx, minx->BA & 0x00FF ); } +OP(81) { minx->BA = ( minx->BA & 0x00FF ) | ( INC8( minx, minx->BA >> 8 ) << 8 ); } +OP(82) { minx->HL = ( minx->HL & 0xFF00 ) | INC8( minx, minx->HL & 0x00FF ); } +OP(83) { minx->HL = ( minx->HL & 0x00FF ) | ( INC8( minx, minx->HL >> 8 ) << 8 ); } +OP(84) { minx->N = INC8( minx, minx->N ); } +OP(85) { AD1_IN8; WR( addr1, INC8( minx, RD( addr1 ) ) ); } +OP(86) { AD1_IHL; WR( addr1, INC8( minx, RD( addr1 ) ) ); } +OP(87) { minx->SP = INC16( minx, minx->SP ); } +OP(88) { minx->BA = ( minx->BA & 0xFF00 ) | DEC8( minx, minx->BA & 0x00FF ); } +OP(89) { minx->BA = ( minx->BA & 0x00FF ) | ( DEC8( minx, minx->BA >> 8 ) << 8 ); } +OP(8A) { minx->HL = ( minx->HL & 0xFF00 ) | DEC8( minx, minx->HL & 0x00FF ); } +OP(8B) { minx->HL = ( minx->HL & 0x00FF ) | ( DEC8( minx, minx->HL >> 8 ) << 8 ); } +OP(8C) { minx->N = DEC8( minx, minx->N ); } +OP(8D) { AD1_IN8; WR( addr1, DEC8( minx, RD( addr1 ) ) ); } +OP(8E) { AD1_IHL; WR( addr1, DEC8( minx, RD( addr1 ) ) ); } +OP(8F) { minx->SP = DEC8( minx, minx->SP ); } -OP(90) { regs.BA = INC16( regs.BA ); } -OP(91) { regs.HL = INC16( regs.HL ); } -OP(92) { regs.X = INC16( regs.X ); } -OP(93) { regs.Y = INC16( regs.Y ); } -OP(94) { regs.F = ( AND8( ( regs.BA & 0x00FF ), ( regs.BA >> 8 ) ) ) ? regs.F & ~FLAG_Z : regs.F | FLAG_Z;} -OP(95) { AD1_IHL; regs.F = ( AND8( RD( addr1 ), rdop() ) ) ? regs.F & ~FLAG_Z : regs.F | FLAG_Z; } -OP(96) { regs.F = ( AND8( ( regs.BA & 0x00FF ), rdop() ) ) ? regs.F & ~FLAG_Z : regs.F | FLAG_Z; } -OP(97) { regs.F = ( AND8( ( regs.BA >> 8 ), rdop() ) ) ? regs.F & ~FLAG_Z : regs.F | FLAG_Z; } -OP(98) { regs.BA = DEC16( regs.BA ); } -OP(99) { regs.HL = DEC16( regs.HL ); } -OP(9A) { regs.X = DEC16( regs.X ); } -OP(9B) { regs.Y = DEC16( regs.Y ); } -OP(9C) { regs.F = regs.F & rdop(); } -OP(9D) { regs.F = regs.F | rdop(); } -OP(9E) { regs.F = regs.F ^ rdop(); } -OP(9F) { regs.F = rdop(); } +OP(90) { minx->BA = INC16( minx, minx->BA ); } +OP(91) { minx->HL = INC16( minx, minx->HL ); } +OP(92) { minx->X = INC16( minx, minx->X ); } +OP(93) { minx->Y = INC16( minx, minx->Y ); } +OP(94) { minx->F = ( AND8( minx, ( minx->BA & 0x00FF ), ( minx->BA >> 8 ) ) ) ? minx->F & ~FLAG_Z : minx->F | FLAG_Z;} +OP(95) { AD1_IHL; minx->F = ( AND8( minx, RD( addr1 ), rdop(minx) ) ) ? minx->F & ~FLAG_Z : minx->F | FLAG_Z; } +OP(96) { minx->F = ( AND8( minx, ( minx->BA & 0x00FF ), rdop(minx) ) ) ? minx->F & ~FLAG_Z : minx->F | FLAG_Z; } +OP(97) { minx->F = ( AND8( minx, ( minx->BA >> 8 ), rdop(minx) ) ) ? minx->F & ~FLAG_Z : minx->F | FLAG_Z; } +OP(98) { minx->BA = DEC16( minx, minx->BA ); } +OP(99) { minx->HL = DEC16( minx, minx->HL ); } +OP(9A) { minx->X = DEC16( minx, minx->X ); } +OP(9B) { minx->Y = DEC16( minx, minx->Y ); } +OP(9C) { minx->F = minx->F & rdop(minx); } +OP(9D) { minx->F = minx->F | rdop(minx); } +OP(9E) { minx->F = minx->F ^ rdop(minx); } +OP(9F) { minx->F = rdop(minx); } -OP(A0) { PUSH16( regs.BA ); } -OP(A1) { PUSH16( regs.HL ); } -OP(A2) { PUSH16( regs.X ); } -OP(A3) { PUSH16( regs.Y ); } -OP(A4) { PUSH8( regs.N ); } -OP(A5) { PUSH8( regs.I ); } -OP(A6) { PUSH8( regs.XI ); PUSH8( regs.YI ); } -OP(A7) { PUSH8( regs.F ); } -OP(A8) { regs.BA = POP16(); } -OP(A9) { regs.HL = POP16();} -OP(AA) { regs.X = POP16(); } -OP(AB) { regs.Y = POP16(); } -OP(AC) { regs.N = POP8(); } -OP(AD) { regs.I = POP8(); } -OP(AE) { regs.YI = POP8(); regs.XI = POP8(); } -OP(AF) { regs.F = POP8(); } +OP(A0) { PUSH16( minx, minx->BA ); } +OP(A1) { PUSH16( minx, minx->HL ); } +OP(A2) { PUSH16( minx, minx->X ); } +OP(A3) { PUSH16( minx, minx->Y ); } +OP(A4) { PUSH8( minx, minx->N ); } +OP(A5) { PUSH8( minx, minx->I ); } +OP(A6) { PUSH8( minx, minx->XI ); PUSH8( minx, minx->YI ); } +OP(A7) { PUSH8( minx, minx->F ); } +OP(A8) { minx->BA = POP16(minx); } +OP(A9) { minx->HL = POP16(minx);} +OP(AA) { minx->X = POP16(minx); } +OP(AB) { minx->Y = POP16(minx); } +OP(AC) { minx->N = POP8(minx); } +OP(AD) { minx->I = POP8(minx); } +OP(AE) { minx->YI = POP8(minx); minx->XI = POP8(minx); } +OP(AF) { minx->F = POP8(minx); } -OP(B0) { UINT8 op = rdop(); regs.BA = ( regs.BA & 0xFF00 ) | op; } -OP(B1) { UINT8 op = rdop(); regs.BA = ( regs.BA & 0x00FF ) | ( op << 8 ); } -OP(B2) { UINT8 op = rdop(); regs.HL = ( regs.HL & 0xFF00 ) | op; } -OP(B3) { UINT8 op = rdop(); regs.HL = ( regs.HL & 0x00FF ) | ( op << 8 ); } -OP(B4) { UINT8 op = rdop(); regs.N = op; } -OP(B5) { AD1_IHL; UINT8 op = rdop(); WR( addr1, op); } -OP(B6) { AD1_XIX; UINT8 op = rdop(); WR( addr1, op ); } -OP(B7) { AD1_YIY; UINT8 op = rdop(); WR( addr1, op ); } -OP(B8) { AD2_I16; regs.BA = rd16( addr2 ); } -OP(B9) { AD2_I16; regs.HL = rd16( addr2 ); } -OP(BA) { AD2_I16; regs.X = rd16( addr2 ); } -OP(BB) { AD2_I16; regs.Y = rd16( addr2 ); } -OP(BC) { AD1_I16; wr16( addr1, regs.BA ); } -OP(BD) { AD1_I16; wr16( addr1, regs.HL ); } -OP(BE) { AD1_I16; wr16( addr1, regs.X ); } -OP(BF) { AD1_I16; wr16( addr1, regs.Y ); } +OP(B0) { UINT8 op = rdop(minx); minx->BA = ( minx->BA & 0xFF00 ) | op; } +OP(B1) { UINT8 op = rdop(minx); minx->BA = ( minx->BA & 0x00FF ) | ( op << 8 ); } +OP(B2) { UINT8 op = rdop(minx); minx->HL = ( minx->HL & 0xFF00 ) | op; } +OP(B3) { UINT8 op = rdop(minx); minx->HL = ( minx->HL & 0x00FF ) | ( op << 8 ); } +OP(B4) { UINT8 op = rdop(minx); minx->N = op; } +OP(B5) { AD1_IHL; UINT8 op = rdop(minx); WR( addr1, op); } +OP(B6) { AD1_XIX; UINT8 op = rdop(minx); WR( addr1, op ); } +OP(B7) { AD1_YIY; UINT8 op = rdop(minx); WR( addr1, op ); } +OP(B8) { AD2_I16; minx->BA = rd16( minx, addr2 ); } +OP(B9) { AD2_I16; minx->HL = rd16( minx, addr2 ); } +OP(BA) { AD2_I16; minx->X = rd16( minx, addr2 ); } +OP(BB) { AD2_I16; minx->Y = rd16( minx, addr2 ); } +OP(BC) { AD1_I16; wr16( minx, addr1, minx->BA ); } +OP(BD) { AD1_I16; wr16( minx, addr1, minx->HL ); } +OP(BE) { AD1_I16; wr16( minx, addr1, minx->X ); } +OP(BF) { AD1_I16; wr16( minx, addr1, minx->Y ); } -OP(C0) { regs.BA = ADD16( regs.BA, rdop16() ); } -OP(C1) { regs.HL = ADD16( regs.HL, rdop16() ); } -OP(C2) { regs.X = ADD16( regs.X, rdop16() ); } -OP(C3) { regs.Y = ADD16( regs.Y, rdop16() ); } -OP(C4) { regs.BA = rdop16(); } -OP(C5) { regs.HL = rdop16(); } -OP(C6) { regs.X = rdop16(); } -OP(C7) { regs.Y = rdop16(); } -OP(C8) { UINT16 t = regs.BA; regs.BA = regs.HL; regs.HL = t; } -OP(C9) { UINT16 t = regs.BA; regs.BA = regs.X; regs.X = t; } -OP(CA) { UINT16 t = regs.BA; regs.BA = regs.Y; regs.Y = t; } -OP(CB) { UINT16 t = regs.BA; regs.BA = regs.SP; regs.SP = t; } -OP(CC) { regs.BA = ( regs.BA >> 8 ) | ( ( regs.BA & 0x00FF ) << 8 ); } -OP(CD) { UINT8 t; AD2_IHL; t = RD( addr2 ); WR( addr2, ( regs.BA & 0x00FF ) ); regs.BA = ( regs.BA & 0xFF00 ) | t; } -OP(CE) { UINT8 op = rdop(); insnminx_CE[op](); minx_icount -= insnminx_cycles_CE[op]; } -OP(CF) { UINT8 op = rdop(); insnminx_CF[op](); minx_icount -= insnminx_cycles_CF[op]; } +OP(C0) { minx->BA = ADD16( minx, minx->BA, rdop16(minx) ); } +OP(C1) { minx->HL = ADD16( minx, minx->HL, rdop16(minx) ); } +OP(C2) { minx->X = ADD16( minx, minx->X, rdop16(minx) ); } +OP(C3) { minx->Y = ADD16( minx, minx->Y, rdop16(minx) ); } +OP(C4) { minx->BA = rdop16(minx); } +OP(C5) { minx->HL = rdop16(minx); } +OP(C6) { minx->X = rdop16(minx); } +OP(C7) { minx->Y = rdop16(minx); } +OP(C8) { UINT16 t = minx->BA; minx->BA = minx->HL; minx->HL = t; } +OP(C9) { UINT16 t = minx->BA; minx->BA = minx->X; minx->X = t; } +OP(CA) { UINT16 t = minx->BA; minx->BA = minx->Y; minx->Y = t; } +OP(CB) { UINT16 t = minx->BA; minx->BA = minx->SP; minx->SP = t; } +OP(CC) { minx->BA = ( minx->BA >> 8 ) | ( ( minx->BA & 0x00FF ) << 8 ); } +OP(CD) { UINT8 t; AD2_IHL; t = RD( addr2 ); WR( addr2, ( minx->BA & 0x00FF ) ); minx->BA = ( minx->BA & 0xFF00 ) | t; } +OP(CE) { UINT8 op = rdop(minx); insnminx_CE[op](minx); minx->icount -= insnminx_cycles_CE[op]; } +OP(CF) { UINT8 op = rdop(minx); insnminx_CF[op](minx); minx->icount -= insnminx_cycles_CF[op]; } -OP(D0) { regs.BA = SUB16( regs.BA, rdop16() ); } -OP(D1) { regs.HL = SUB16( regs.HL, rdop16() ); } -OP(D2) { regs.X = SUB16( regs.X, rdop16() ); } -OP(D3) { regs.Y = SUB16( regs.Y, rdop16() ); } -OP(D4) { SUB16( regs.BA, rdop16() ); } -OP(D5) { SUB16( regs.HL, rdop16() ); } -OP(D6) { SUB16( regs.X, rdop16() ); } -OP(D7) { SUB16( regs.Y, rdop16() ); } -OP(D8) { AD1_IN8; WR( addr1, AND8( RD( addr1 ), rdop() ) ); } -OP(D9) { AD1_IN8; WR( addr1, OR8( RD( addr1 ), rdop() ) ); } -OP(DA) { AD1_IN8; WR( addr1, XOR8( RD( addr1 ), rdop() ) ); } -OP(DB) { AD1_IN8; SUB8( RD( addr1 ), rdop() ); } -OP(DC) { AD1_IN8; regs.F = ( AND8( RD( addr1 ), rdop() ) ) ? regs.F & ~FLAG_Z : regs.F | FLAG_Z; } -OP(DD) { AD1_IN8; WR( addr1, rdop() ); } -OP(DE) { regs.BA = ( regs.BA & 0xFF00 ) | ( ( regs.BA & 0x000F ) | ( ( regs.BA & 0x0F00 ) >> 4 ) ); } -OP(DF) { regs.BA = ( ( regs.BA & 0x0080 ) ? 0xFF00 : 0x0000 ) | ( regs.BA & 0x000F ); } +OP(D0) { minx->BA = SUB16( minx, minx->BA, rdop16(minx) ); } +OP(D1) { minx->HL = SUB16( minx, minx->HL, rdop16(minx) ); } +OP(D2) { minx->X = SUB16( minx, minx->X, rdop16(minx) ); } +OP(D3) { minx->Y = SUB16( minx, minx->Y, rdop16(minx) ); } +OP(D4) { SUB16( minx, minx->BA, rdop16(minx) ); } +OP(D5) { SUB16( minx, minx->HL, rdop16(minx) ); } +OP(D6) { SUB16( minx, minx->X, rdop16(minx) ); } +OP(D7) { SUB16( minx, minx->Y, rdop16(minx) ); } +OP(D8) { AD1_IN8; WR( addr1, AND8( minx, RD( addr1 ), rdop(minx) ) ); } +OP(D9) { AD1_IN8; WR( addr1, OR8( minx, RD( addr1 ), rdop(minx) ) ); } +OP(DA) { AD1_IN8; WR( addr1, XOR8( minx, RD( addr1 ), rdop(minx) ) ); } +OP(DB) { AD1_IN8; SUB8( minx, RD( addr1 ), rdop(minx) ); } +OP(DC) { AD1_IN8; minx->F = ( AND8( minx, RD( addr1 ), rdop(minx) ) ) ? minx->F & ~FLAG_Z : minx->F | FLAG_Z; } +OP(DD) { AD1_IN8; WR( addr1, rdop(minx) ); } +OP(DE) { minx->BA = ( minx->BA & 0xFF00 ) | ( ( minx->BA & 0x000F ) | ( ( minx->BA & 0x0F00 ) >> 4 ) ); } +OP(DF) { minx->BA = ( ( minx->BA & 0x0080 ) ? 0xFF00 : 0x0000 ) | ( minx->BA & 0x000F ); } -OP(E0) { INT8 d8 = rdop(); if ( regs.F & FLAG_C ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } -OP(E1) { INT8 d8 = rdop(); if ( ! ( regs.F & FLAG_C ) ) { CALL( regs.PC + d8- 1 ); minx_icount -= 12; } } -OP(E2) { INT8 d8 = rdop(); if ( regs.F & FLAG_Z ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } -OP(E3) { INT8 d8 = rdop(); if ( ! ( regs.F & FLAG_Z ) ) { CALL( regs.PC + d8 - 1 ); minx_icount -= 12; } } -OP(E4) { INT8 d8 = rdop(); if ( regs.F & FLAG_C ) { JMP( regs.PC + d8 - 1 ); } } -OP(E5) { INT8 d8 = rdop(); if ( ! ( regs.F & FLAG_C ) ) { JMP( regs.PC + d8 - 1 ); } } -OP(E6) { INT8 d8 = rdop(); if ( regs.F & FLAG_Z ) { JMP( regs.PC + d8 - 1 ); } } -OP(E7) { INT8 d8 = rdop(); if ( ! ( regs.F & FLAG_Z ) ) { JMP( regs.PC + d8 - 1 ); } } -OP(E8) { UINT16 d16 = rdop16(); if ( regs.F & FLAG_C ) { CALL( regs.PC + d16 - 1 ); minx_icount -= 12; } } -OP(E9) { UINT16 d16 = rdop16(); if ( ! ( regs.F & FLAG_C ) ) { CALL( regs.PC + d16 - 1 ); minx_icount -= 12; } } -OP(EA) { UINT16 d16 = rdop16(); if ( regs.F & FLAG_Z ) { CALL( regs.PC + d16 - 1 ); minx_icount -= 12; } } -OP(EB) { UINT16 d16 = rdop16(); if ( ! ( regs.F & FLAG_Z ) ) { CALL( regs.PC + d16 - 1 ); minx_icount -= 12; } } -OP(EC) { UINT16 d16 = rdop16(); if ( regs.F & FLAG_C ) { JMP( regs.PC + d16 - 1 ); } } -OP(ED) { UINT16 d16 = rdop16(); if ( ! ( regs.F & FLAG_C ) ) { JMP( regs.PC + d16 - 1 ); } } -OP(EE) { UINT16 d16 = rdop16(); if ( regs.F & FLAG_Z ) { JMP( regs.PC + d16 - 1 ); } } -OP(EF) { UINT16 d16 = rdop16(); if ( ! ( regs.F & FLAG_Z ) ) { JMP( regs.PC + d16 - 1 ); } } +OP(E0) { INT8 d8 = rdop(minx); if ( minx->F & FLAG_C ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } } +OP(E1) { INT8 d8 = rdop(minx); if ( ! ( minx->F & FLAG_C ) ) { CALL( minx, minx->PC + d8- 1 ); minx->icount -= 12; } } +OP(E2) { INT8 d8 = rdop(minx); if ( minx->F & FLAG_Z ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } } +OP(E3) { INT8 d8 = rdop(minx); if ( ! ( minx->F & FLAG_Z ) ) { CALL( minx, minx->PC + d8 - 1 ); minx->icount -= 12; } } +OP(E4) { INT8 d8 = rdop(minx); if ( minx->F & FLAG_C ) { JMP( minx, minx->PC + d8 - 1 ); } } +OP(E5) { INT8 d8 = rdop(minx); if ( ! ( minx->F & FLAG_C ) ) { JMP( minx, minx->PC + d8 - 1 ); } } +OP(E6) { INT8 d8 = rdop(minx); if ( minx->F & FLAG_Z ) { JMP( minx, minx->PC + d8 - 1 ); } } +OP(E7) { INT8 d8 = rdop(minx); if ( ! ( minx->F & FLAG_Z ) ) { JMP( minx, minx->PC + d8 - 1 ); } } +OP(E8) { UINT16 d16 = rdop16(minx); if ( minx->F & FLAG_C ) { CALL( minx, minx->PC + d16 - 1 ); minx->icount -= 12; } } +OP(E9) { UINT16 d16 = rdop16(minx); if ( ! ( minx->F & FLAG_C ) ) { CALL( minx, minx->PC + d16 - 1 ); minx->icount -= 12; } } +OP(EA) { UINT16 d16 = rdop16(minx); if ( minx->F & FLAG_Z ) { CALL( minx, minx->PC + d16 - 1 ); minx->icount -= 12; } } +OP(EB) { UINT16 d16 = rdop16(minx); if ( ! ( minx->F & FLAG_Z ) ) { CALL( minx, minx->PC + d16 - 1 ); minx->icount -= 12; } } +OP(EC) { UINT16 d16 = rdop16(minx); if ( minx->F & FLAG_C ) { JMP( minx, minx->PC + d16 - 1 ); } } +OP(ED) { UINT16 d16 = rdop16(minx); if ( ! ( minx->F & FLAG_C ) ) { JMP( minx, minx->PC + d16 - 1 ); } } +OP(EE) { UINT16 d16 = rdop16(minx); if ( minx->F & FLAG_Z ) { JMP( minx, minx->PC + d16 - 1 ); } } +OP(EF) { UINT16 d16 = rdop16(minx); if ( ! ( minx->F & FLAG_Z ) ) { JMP( minx, minx->PC + d16 - 1 ); } } -OP(F0) { INT8 d8 = rdop(); CALL( regs.PC + d8 - 1 ); } -OP(F1) { INT8 d8 = rdop(); JMP( regs.PC + d8 - 1 ); } -OP(F2) { UINT16 d16 = rdop16(); CALL( regs.PC + d16 - 1 ); } -OP(F3) { UINT16 d16 = rdop16(); JMP( regs.PC + d16 - 1 ); } -OP(F4) { JMP( regs.HL ); } -OP(F5) { INT8 d8 = rdop(); regs.BA = regs.BA - 0x0100; if ( regs.BA & 0xFF00 ) { JMP( regs.PC + d8 - 1 ); } } -OP(F6) { regs.BA = ( regs.BA & 0xFF00 ) | ( ( regs.BA & 0x00F0 ) >> 4 ) | ( ( regs.BA & 0x000F ) << 4 ); } +OP(F0) { INT8 d8 = rdop(minx); CALL( minx, minx->PC + d8 - 1 ); } +OP(F1) { INT8 d8 = rdop(minx); JMP( minx, minx->PC + d8 - 1 ); } +OP(F2) { UINT16 d16 = rdop16(minx); CALL( minx, minx->PC + d16 - 1 ); } +OP(F3) { UINT16 d16 = rdop16(minx); JMP( minx, minx->PC + d16 - 1 ); } +OP(F4) { JMP( minx, minx->HL ); } +OP(F5) { INT8 d8 = rdop(minx); minx->BA = minx->BA - 0x0100; if ( minx->BA & 0xFF00 ) { JMP( minx, minx->PC + d8 - 1 ); } } +OP(F6) { minx->BA = ( minx->BA & 0xFF00 ) | ( ( minx->BA & 0x00F0 ) >> 4 ) | ( ( minx->BA & 0x000F ) << 4 ); } OP(F7) { UINT8 d; AD1_IHL; d = RD( addr1 ); WR( addr1, ( ( d & 0xF0 ) >> 4 ) | ( ( d & 0x0F ) << 4 ) ); } -OP(F8) { regs.PC = POP16(); regs.V = POP8(); regs.U = regs.V; } -OP(F9) { regs.F = POP8(); regs.PC = POP16(); regs.V = POP8(); regs.U = regs.V; } -OP(FA) { regs.PC = POP16() + 2; regs.V = POP8(); regs.U = regs.V; } -OP(FB) { AD1_I16; CALL( rd16( addr1 ) ); } -OP(FC) { UINT8 i = rdop() & 0xFE; CALL( rd16(i) ); PUSH8( regs.F ); } -OP(FD) { UINT8 i = rdop() & 0xFE; JMP( rd16(i) ); /* PUSH8( regs.F );?? */ } +OP(F8) { minx->PC = POP16(minx); minx->V = POP8(minx); minx->U = minx->V; } +OP(F9) { minx->F = POP8(minx); minx->PC = POP16(minx); minx->V = POP8(minx); minx->U = minx->V; } +OP(FA) { minx->PC = POP16(minx) + 2; minx->V = POP8(minx); minx->U = minx->V; } +OP(FB) { AD1_I16; CALL( minx, rd16( minx, addr1 ) ); } +OP(FC) { UINT8 i = rdop(minx) & 0xFE; CALL( minx, rd16( minx, i ) ); PUSH8( minx, minx->F ); } +OP(FD) { UINT8 i = rdop(minx) & 0xFE; JMP( minx, rd16( minx, i ) ); /* PUSH8( minx, minx->F );?? */ } OP(FE) { /* illegal operation? */ } OP(FF) { } -static void (*const insnminx[256])(void) = { +static void (*const insnminx[256])(minx_state *minx) = { minx_00, minx_01, minx_02, minx_03, minx_04, minx_05, minx_06, minx_07, minx_08, minx_09, minx_0A, minx_0B, minx_0C, minx_0D, minx_0E, minx_0F, minx_10, minx_11, minx_12, minx_13, minx_14, minx_15, minx_16, minx_17, |