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author Wilbert Pol <wilbert@jdg.info>2008-06-01 16:43:24 +0000
committer Wilbert Pol <wilbert@jdg.info>2008-06-01 16:43:24 +0000
commit6b1719e1c659a400edcd15198c89e353cd2a6017 (patch)
tree579b7bf44e6f054ba77dc1d2ff2e8b9bee832526 /src/emu/cpu/minx/minxopcf.h
parentdc19a5250ce2ffc05b0b85a1b7733ecdcc75a3fa (diff)
Some Nintendo Minx cpu core updates:
- Styling changes - Added instruction cycle counts. - Added interrupt support. - Added HALT support. - Fixed INT instruction. - Added incomplete support for DIV and MUL instructions. - Fixed MOV [#nnnn],BA and MOV [#nnnn],HL instructions.
Diffstat (limited to 'src/emu/cpu/minx/minxopcf.h')
-rw-r--r--src/emu/cpu/minx/minxopcf.h51
1 files changed, 27 insertions, 24 deletions
diff --git a/src/emu/cpu/minx/minxopcf.h b/src/emu/cpu/minx/minxopcf.h
index fefea13354f..01a942c47cc 100644
--- a/src/emu/cpu/minx/minxopcf.h
+++ b/src/emu/cpu/minx/minxopcf.h
@@ -121,14 +121,14 @@ OP(6D) { /* illegal instruction? */ }
OP(6E) { regs.SP = rdop16(); }
OP(6F) { /* illegal instruction? */ }
-OP(70) { UINT8 ofs8 = rdop(); regs.BA = rd( regs.SP + ofs8 ); }
-OP(71) { UINT8 ofs8 = rdop(); regs.HL = rd( regs.SP + ofs8 ); }
-OP(72) { UINT8 ofs8 = rdop(); regs.X = rd( regs.SP + ofs8 ); }
-OP(73) { UINT8 ofs8 = rdop(); regs.Y = rd( regs.SP + ofs8 ); }
-OP(74) { UINT8 ofs8 = rdop(); wr( regs.SP + ofs8, regs.BA ); }
-OP(75) { UINT8 ofs8 = rdop(); wr( regs.SP + ofs8, regs.HL ); }
-OP(76) { UINT8 ofs8 = rdop(); wr( regs.SP + ofs8, regs.X ); }
-OP(77) { UINT8 ofs8 = rdop(); wr( regs.SP + ofs8, regs.Y ); }
+OP(70) { UINT8 ofs8 = rdop(); regs.BA = RD( regs.SP + ofs8 ); }
+OP(71) { UINT8 ofs8 = rdop(); regs.HL = RD( regs.SP + ofs8 ); }
+OP(72) { UINT8 ofs8 = rdop(); regs.X = RD( regs.SP + ofs8 ); }
+OP(73) { UINT8 ofs8 = rdop(); regs.Y = RD( regs.SP + ofs8 ); }
+OP(74) { UINT8 ofs8 = rdop(); WR( regs.SP + ofs8, regs.BA ); }
+OP(75) { UINT8 ofs8 = rdop(); WR( regs.SP + ofs8, regs.HL ); }
+OP(76) { UINT8 ofs8 = rdop(); WR( regs.SP + ofs8, regs.X ); }
+OP(77) { UINT8 ofs8 = rdop(); WR( regs.SP + ofs8, regs.Y ); }
OP(78) { AD2_I16; regs.SP = rd16( addr2 ); }
OP(79) { /* illegal instruction? */ }
OP(7A) { /* illegal instruction? */ }
@@ -310,21 +310,24 @@ static void (*const insnminx_CF[256])(void) = {
};
static const int insnminx_cycles_CF[256] = {
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1
+ 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
+ 1, 1, 1, 1, 1, 1, 1, 1, 16, 16, 16, 16, 1, 1, 1, 1,
+ 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
+ 1, 1, 1, 1, 1, 1, 1, 1, 16, 16, 16, 16, 1, 1, 1, 1,
+
+ 16, 16, 16, 16, 16, 16, 1, 1, 16, 16, 16, 16, 16, 16, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 16, 16, 1, 1,
+ 16, 16, 16, 16, 1, 1, 1, 1, 16, 1, 16, 1, 16, 1, 16, 1,
+ 24, 24, 24, 24, 24, 24, 24, 24, 24, 1, 1, 1, 24, 1, 1, 1,
+
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 12, 12, 12, 12, 12, 12, 12, 12, 48, 60, 1, 1, 32, 40, 1, 1,
+
+ 20, 20, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1, 1,
+ 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20,
+ 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
+ 8, 8, 8, 8, 8, 8, 1, 1, 8, 8, 8, 1, 1, 1, 8, 1
};