diff options
author | 2009-10-20 06:11:07 +0000 | |
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committer | 2009-10-20 06:11:07 +0000 | |
commit | b1183137b90dcdc9b4463a94b6ae56cad6efa183 (patch) | |
tree | 3c486579f29eb82b243ba909b13b341ee7453b45 /src/emu/cpu/dsp56k/dsp56mem.c | |
parent | 77d010978bb8c1b73922d62964115ee21eec8a22 (diff) |
Fixed dsp56156 DO & BSCC opcode bugs. [Andrew Gardner]
(Also makes the code prettier in parts)
(The dsp now goes into its calculation loop, but some
opcode doesn't set flags properly, so it never drops
out of the loop).
Diffstat (limited to 'src/emu/cpu/dsp56k/dsp56mem.c')
-rw-r--r-- | src/emu/cpu/dsp56k/dsp56mem.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/emu/cpu/dsp56k/dsp56mem.c b/src/emu/cpu/dsp56k/dsp56mem.c index 440f7543642..2bd17e87168 100644 --- a/src/emu/cpu/dsp56k/dsp56mem.c +++ b/src/emu/cpu/dsp56k/dsp56mem.c @@ -336,8 +336,8 @@ static void HCR_set(dsp56k_core* cpustate, UINT16 value) HTIE_bit_set(cpustate, (value & 0x0002) >> 1); HRIE_bit_set(cpustate, (value & 0x0001) >> 0); } -//static UINT16 HF3_bit(dsp56k_core* cpustate); #define hf3BIT ((HCR & 0x0010) != 0) -//static UINT16 HF2_bit(dsp56k_core* cpustate); #define hf2BIT ((HCR & 0x0008) != 0) +//static UINT16 HF3_bit(dsp56k_core* cpustate) { return ((HCR & 0x0010) != 0); } +//static UINT16 HF2_bit(dsp56k_core* cpustate) { return ((HCR & 0x0008) != 0); } static UINT16 HCIE_bit(dsp56k_core* cpustate) { return ((HCR & 0x0004) != 0); } static UINT16 HTIE_bit(dsp56k_core* cpustate) { return ((HCR & 0x0002) != 0); } static UINT16 HRIE_bit(dsp56k_core* cpustate) { return ((HCR & 0x0001) != 0); } @@ -380,10 +380,10 @@ static void HRIE_bit_set(dsp56k_core* cpustate, UINT16 value) /***********************************/ /* Host Status Register (HSR) Bits */ /***********************************/ -//static UINT16 DMA_bit(dsp56k_core* cpustate); #define dmaBIT ((HSR & 0x0080) != 0) -//static UINT16 HF1_bit(dsp56k_core* cpustate); #define hf1BIT ((HSR & 0x0010) != 0) -//static UINT16 HF0_bit(dsp56k_core* cpustate); #define hf0BIT ((HSR & 0x0008) != 0) -//static UINT16 HCP_bit(dsp56k_core* cpustate); #define hcpBIT ((HSR & 0x0004) != 0) +//static UINT16 DMA_bit(dsp56k_core* cpustate) { return ((HSR & 0x0080) != 0); } +//static UINT16 HF1_bit(dsp56k_core* cpustate) { return ((HSR & 0x0010) != 0); } +//static UINT16 HF0_bit(dsp56k_core* cpustate) { return ((HSR & 0x0008) != 0); } +//static UINT16 HCP_bit(dsp56k_core* cpustate) { return ((HSR & 0x0004) != 0); } static UINT16 HTDE_bit(dsp56k_core* cpustate) { return ((HSR & 0x0002) != 0); } static UINT16 HRDF_bit(dsp56k_core* cpustate) { return ((HSR & 0x0001) != 0); } |