diff options
| author | 2014-10-15 07:19:47 +0000 | |
|---|---|---|
| committer | 2014-10-15 07:19:47 +0000 | |
| commit | c93ed344fbd26a9c2c49bdbc99014d8dc0cbe9ef (patch) | |
| tree | a5017b8341bdadc5bcd1185ae49fe4c0a85424b8 /src/emu/bus/vcs | |
| parent | a4dd32afb6cbfaae0e452c90486060682ab1c31c (diff) | |
Cleanups and version bumpmame0155
Diffstat (limited to 'src/emu/bus/vcs')
| -rw-r--r-- | src/emu/bus/vcs/compumat.c | 4 | ||||
| -rw-r--r-- | src/emu/bus/vcs/compumat.h | 4 | ||||
| -rw-r--r-- | src/emu/bus/vcs/dpc.c | 11 | ||||
| -rw-r--r-- | src/emu/bus/vcs/dpc.h | 8 | ||||
| -rwxr-xr-x | src/emu/bus/vcs/rom.c | 131 | ||||
| -rwxr-xr-x | src/emu/bus/vcs/rom.h | 76 | ||||
| -rw-r--r-- | src/emu/bus/vcs/scharger.c | 38 | ||||
| -rw-r--r-- | src/emu/bus/vcs/scharger.h | 6 | ||||
| -rwxr-xr-x | src/emu/bus/vcs/vcs_slot.c | 86 | ||||
| -rwxr-xr-x | src/emu/bus/vcs/vcs_slot.h | 6 |
10 files changed, 184 insertions, 186 deletions
diff --git a/src/emu/bus/vcs/compumat.c b/src/emu/bus/vcs/compumat.c index fe67e120c41..57de9257711 100644 --- a/src/emu/bus/vcs/compumat.c +++ b/src/emu/bus/vcs/compumat.c @@ -1,10 +1,10 @@ /*************************************************************************** - Atari 2600 cart Spectravideo Compumate (Cart + keyboard!) + Atari 2600 cart Spectravideo Compumate (Cart + keyboard!) This is tricky to implement and it is only a skeleton ATM. The device needs to interface with both the TIA and the RIOT. - + ***************************************************************************/ diff --git a/src/emu/bus/vcs/compumat.h b/src/emu/bus/vcs/compumat.h index d2d81fc83f0..b18988181ac 100644 --- a/src/emu/bus/vcs/compumat.h +++ b/src/emu/bus/vcs/compumat.h @@ -19,10 +19,10 @@ public: virtual void device_start(); virtual ioport_constructor device_input_ports() const; virtual void device_reset(); - + // reading and writing virtual DECLARE_READ8_MEMBER(read_rom); - + private: }; diff --git a/src/emu/bus/vcs/dpc.c b/src/emu/bus/vcs/dpc.c index 85d8689067d..7387c6dbb34 100644 --- a/src/emu/bus/vcs/dpc.c +++ b/src/emu/bus/vcs/dpc.c @@ -37,7 +37,7 @@ void dpc_device::device_reset() m_df[data_fetcher].music_mode = 0; } m_oscillator->adjust(attotime::from_hz(18400), 0, attotime::from_hz(18400)); - + } void dpc_device::check_flag(UINT8 data_fetcher) @@ -60,7 +60,7 @@ void dpc_device::decrement_counter(UINT8 data_fetcher) if (data_fetcher > 4 && m_df[data_fetcher].music_mode) m_df[data_fetcher].low = m_df[data_fetcher].top; } - + check_flag(data_fetcher); } @@ -149,7 +149,7 @@ READ8_MEMBER(dpc_device::read) data = m_df[data_fetcher].flag ? 0xff : 0x00; break; } - + if (data_fetcher < 5 || !m_df[data_fetcher].osc_clk) { decrement_counter(data_fetcher); @@ -161,7 +161,7 @@ READ8_MEMBER(dpc_device::read) WRITE8_MEMBER(dpc_device::write) { UINT8 data_fetcher = offset & 0x07; - + switch (offset & 0x38) { case 0x00: // Top count @@ -235,7 +235,7 @@ void a26_rom_dpc_device::device_reset() m_base_bank = 0; } -void a26_rom_dpc_device::setup_addon_ptr(UINT8 *ptr) +void a26_rom_dpc_device::setup_addon_ptr(UINT8 *ptr) { m_dpc->set_display_data(ptr); } @@ -279,4 +279,3 @@ DIRECT_UPDATE_MEMBER(a26_rom_dpc_device::cart_opbase) } return address; } - diff --git a/src/emu/bus/vcs/dpc.h b/src/emu/bus/vcs/dpc.h index 8cf12d893eb..a54e67e5778 100644 --- a/src/emu/bus/vcs/dpc.h +++ b/src/emu/bus/vcs/dpc.h @@ -19,7 +19,7 @@ struct df_t { UINT8 osc_clk; /* Only used by data fetchers 5,6, and 7 */ }; -// m_dpc.oscillator = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(a2600_state::modeDPC_timer_callback),this)); +// m_dpc.oscillator = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(a2600_state::modeDPC_timer_callback),this)); class dpc_device : public device_t { @@ -74,16 +74,16 @@ public: virtual void device_reset(); required_device<dpc_device> m_dpc; - + // reading and writing virtual DECLARE_READ8_MEMBER(read_rom); virtual DECLARE_WRITE8_MEMBER(write_bank); virtual DECLARE_DIRECT_UPDATE_MEMBER(cart_opbase); virtual void setup_addon_ptr(UINT8 *ptr); - + protected: -// int m_reset_bank; +// int m_reset_bank; }; diff --git a/src/emu/bus/vcs/rom.c b/src/emu/bus/vcs/rom.c index a585734c6f4..f9cc271b316 100755 --- a/src/emu/bus/vcs/rom.c +++ b/src/emu/bus/vcs/rom.c @@ -62,13 +62,13 @@ a26_rom_4k_device::a26_rom_4k_device(const machine_config &mconfig, const char * a26_rom_f6_device::a26_rom_f6_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source) : a26_rom_2k_device(mconfig, type, name, tag, owner, clock, shortname, source), - m_base_bank(-1) // set to -1 to help the Xin1 multicart... + m_base_bank(-1) // set to -1 to help the Xin1 multicart... { } a26_rom_f6_device::a26_rom_f6_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : a26_rom_2k_device(mconfig, A26_ROM_F6, "Atari VCS 2600 ROM Carts w/F6 bankswitch", tag, owner, clock, "vcs_f6", __FILE__), - m_base_bank(-1) // set to -1 to help the Xin1 multicart... + m_base_bank(-1) // set to -1 to help the Xin1 multicart... { } @@ -337,7 +337,7 @@ READ8_MEMBER(a26_rom_2k_device::read_rom) /*------------------------------------------------- "F4 Bankswitch" Carts: - read/write access to 0x1ff4-0x1ffb determines the + read/write access to 0x1ff4-0x1ffb determines the 4K ROM bank to be read GAMES: Fatal Run @@ -350,7 +350,7 @@ READ8_MEMBER(a26_rom_f4_device::read_rom) { return m_ram[offset & (m_ram.count() - 1)]; } - + // update banks if (!space.debugger_access()) { @@ -368,7 +368,7 @@ READ8_MEMBER(a26_rom_f4_device::read_rom) break; } } - + return m_rom[offset + (m_base_bank * 0x1000)]; } @@ -380,7 +380,7 @@ WRITE8_MEMBER(a26_rom_f4_device::write_bank) m_ram[offset & (m_ram.count() - 1)] = data; return; } - + switch (offset) { case 0x0ff4: @@ -401,10 +401,10 @@ WRITE8_MEMBER(a26_rom_f4_device::write_bank) /*------------------------------------------------- "F6 Bankswitch" Carts: - read/write access to 0x1ff6-0x1ff9 determines the + read/write access to 0x1ff6-0x1ff9 determines the 4K ROM bank to be read - GAMES: Atari 16K games, like Crossbow, Crystal + GAMES: Atari 16K games, like Crossbow, Crystal Castles and the 2-in-1 carts -------------------------------------------------*/ @@ -469,7 +469,7 @@ DIRECT_UPDATE_MEMBER(a26_rom_f6_device::cart_opbase) /*------------------------------------------------- "F8 Bankswitch" Carts: - read/write access to 0x1ff8-0x1ff9 determines the + read/write access to 0x1ff8-0x1ff9 determines the 4K ROM bank to be read GAMES: Atari 8K games, like Asteroids, Battlezone @@ -484,7 +484,7 @@ READ8_MEMBER(a26_rom_f8_device::read_rom) { return m_ram[offset & (m_ram.count() - 1)]; } - + // update banks if (!space.debugger_access()) { @@ -496,7 +496,7 @@ READ8_MEMBER(a26_rom_f8_device::read_rom) break; } } - + return m_rom[offset + (m_base_bank * 0x1000)]; } @@ -508,7 +508,7 @@ WRITE8_MEMBER(a26_rom_f8_device::write_bank) m_ram[offset & (m_ram.count() - 1)] = data; return; } - + switch (offset) { case 0x0ff8: @@ -523,12 +523,12 @@ WRITE8_MEMBER(a26_rom_f8_device::write_bank) /*------------------------------------------------- "FA Bankswitch" Carts: - read/write access to 0x1ff8-0x1ffa determines the + read/write access to 0x1ff8-0x1ffa determines the 4K ROM bank to be read - These games contained the CBS RAM+ chip (256bytes + These games contained the CBS RAM+ chip (256bytes of RAM) - - GAMES: CBS RAM Plus games like Omega Race and Tunnel + + GAMES: CBS RAM Plus games like Omega Race and Tunnel Runner -------------------------------------------------*/ @@ -540,7 +540,7 @@ READ8_MEMBER(a26_rom_fa_device::read_rom) { return m_ram[offset & (m_ram.count() - 1)]; } - + // update banks if (!space.debugger_access()) { @@ -553,7 +553,7 @@ READ8_MEMBER(a26_rom_fa_device::read_rom) break; } } - + return m_rom[offset + (m_base_bank * 0x1000)]; } @@ -563,8 +563,8 @@ WRITE8_MEMBER(a26_rom_fa_device::write_bank) if (m_ram && offset < 0x100) { m_ram[offset & (m_ram.count() - 1)] = data; - } - + } + switch (offset) { case 0x0ff8: @@ -580,22 +580,22 @@ WRITE8_MEMBER(a26_rom_fa_device::write_bank) /*------------------------------------------------- "FE Bankswitch" Carts: - read/write access to 0x01fe-0x1ff determines the + read/write access to 0x01fe-0x1ff determines the 4K ROM bank to be read - + GAMES: Activision 8K games like Decathlon -------------------------------------------------*/ /* - + There seems to be a kind of lag between the writing to address 0x1FE and the Activision switcher springing into action. It waits for the next byte to arrive on the data bus, which is the new PCH in the case of a JSR, and the PCH of the stored PC on the stack in the case of an RTS. - + depending on last byte & 0x20 -> 0x00 -> switch to bank #1 -> 0x20 -> switch to bank #0 - + */ READ8_MEMBER(a26_rom_fe_device::read_rom) @@ -607,9 +607,9 @@ READ8_MEMBER(a26_rom_fe_device::read_rom) { return m_ram[offset & (m_ram.count() - 1)]; } - + data = m_rom[offset + (m_base_bank * 0x1000)]; - + if (!space.debugger_access()) { if (m_trigger_on_next_access) @@ -618,7 +618,7 @@ READ8_MEMBER(a26_rom_fe_device::read_rom) m_trigger_on_next_access = 0; } } - + return data; } @@ -634,7 +634,7 @@ WRITE8_MEMBER(a26_rom_fe_device::write_ram) READ8_MEMBER(a26_rom_fe_device::read_bank) { UINT8 data = space.read_byte(0xfe + offset); - + if (!space.debugger_access()) { switch (offset & 1) @@ -643,7 +643,7 @@ READ8_MEMBER(a26_rom_fe_device::read_bank) // The next byte on the data bus determines which bank to switch to m_trigger_on_next_access = 1; break; - + case 1: if (m_trigger_on_next_access) { @@ -667,11 +667,11 @@ WRITE8_MEMBER(a26_rom_fe_device::write_bank) } /*------------------------------------------------- - "3E Bankswitch" Carts: - write access to 0x3e determines the 2K ROM bank to - be read, write access to 0x3f determines the RAM bank + "3E Bankswitch" Carts: + write access to 0x3e determines the 2K ROM bank to + be read, write access to 0x3f determines the RAM bank to be read - + GAMES: Boulder Dash (Homebrew) -------------------------------------------------*/ @@ -680,7 +680,7 @@ READ8_MEMBER(a26_rom_3e_device::read_rom) { if (m_ram && m_ram_enable && offset < 0x400) return m_ram[offset + (m_ram_bank * 0x400)]; - + if (offset >= 0x800) return m_rom[(offset & 0x7ff) + (m_num_bank - 1) * 0x800]; else @@ -709,11 +709,11 @@ WRITE8_MEMBER(a26_rom_3e_device::write_ram) /*------------------------------------------------- - "3F Bankswitch" Carts: - write access to 0x00-0x3f determines the 2K ROM bank + "3F Bankswitch" Carts: + write access to 0x00-0x3f determines the 2K ROM bank to be read - GAMES: Tigervision 8K games like Espial and Miner + GAMES: Tigervision 8K games like Espial and Miner 2049er. Extended version with bankswitch up to 512K shall be supported as well (but we lack a test case) @@ -733,8 +733,8 @@ WRITE8_MEMBER(a26_rom_3f_device::write_bank) } /*------------------------------------------------- - "E0 Bankswitch" Carts: - read/write access to 0x1fe0-0x1ff8 determines the + "E0 Bankswitch" Carts: + read/write access to 0x1fe0-0x1ff8 determines the 1K ROM bank to be read in each 1K chunk (0x1c00-0x1fff always points to the last 1K of the ROM) @@ -769,16 +769,16 @@ WRITE8_MEMBER(a26_rom_e0_device::write_bank) 1800-19ff is RAM 1a00-1fff is fixed to the last 0x600 of ROM - The selectable bank can be ROM (if selected by - 0x1fe0-0x1fe6 access) or a first 1K of RAM (if + The selectable bank can be ROM (if selected by + 0x1fe0-0x1fe6 access) or a first 1K of RAM (if selected by 0x1fe7 access). - The other 256byte RAM bank can be one of the + The other 256byte RAM bank can be one of the four different chunks forming the other 1K of RAM (the bank is selected by accessing 0x1fe8-0x1feb) - GAMES: M Network 16K games like Burgertime and + GAMES: M Network 16K games like Burgertime and Bump'n Jump - + -------------------------------------------------*/ READ8_MEMBER(a26_rom_e7_device::read_rom) @@ -833,12 +833,12 @@ WRITE8_MEMBER(a26_rom_e7_device::write_bank) } /*------------------------------------------------- - "UA Bankswitch" Carts: - read/write access to 0x200-0x27f determines the + "UA Bankswitch" Carts: + read/write access to 0x200-0x27f determines the 4K ROM bank to be read (0x220-0x23f for low 4K, 0x240-0x27f for high 4K) - GAMES: UA Ltd. 8K games like Funky Flash and + GAMES: UA Ltd. 8K games like Funky Flash and Pleaides -------------------------------------------------*/ @@ -863,9 +863,9 @@ WRITE8_MEMBER(a26_rom_ua_device::write_bank) /*------------------------------------------------- - Commavid Carts: + Commavid Carts: It allows for both ROM and RAM on the cartridge, - without using bankswitching. There's 2K of ROM + without using bankswitching. There's 2K of ROM and 1K of RAM. GAMES: Magicard and Video Life by Commavid @@ -894,8 +894,8 @@ WRITE8_MEMBER(a26_rom_cv_device::write_bank) /*------------------------------------------------- - Dynacom Megaboy Carts (aka "F0 Banswitch"): - read/write access to 0x1ff0 determines the 4K ROM + Dynacom Megaboy Carts (aka "F0 Banswitch"): + read/write access to 0x1ff0 determines the 4K ROM bank to be read (each access increases the bank index up to 16, since the cart was 64K wide) @@ -925,8 +925,8 @@ WRITE8_MEMBER(a26_rom_dc_device::write_bank) /*------------------------------------------------- - "FV Bankswitch" Carts: - The first access to 0x1fd0 switch the bank, but + "FV Bankswitch" Carts: + The first access to 0x1fd0 switch the bank, but only if pc() & 0x1f00 == 0x1f00! GAMES: Challenge by HES @@ -964,14 +964,14 @@ WRITE8_MEMBER(a26_rom_fv_device::write_bank) /*------------------------------------------------- - "JVP Bankswitch" Carts: - read/write access to 0x0fa0-0x0fc0 determines the + "JVP Bankswitch" Carts: + read/write access to 0x0fa0-0x0fc0 determines the 4K ROM bank to be read (notice that this overlaps the RIOT, currently handled in the main driver until I can better investigate the behavior) - + GAMES: No test case!?! - + -------------------------------------------------*/ READ8_MEMBER(a26_rom_jvp_device::read_rom) @@ -997,9 +997,9 @@ WRITE8_MEMBER(a26_rom_jvp_device::write_bank) /*------------------------------------------------- 4 in 1 Carts (Reset based): the 4K bank changes at each reset - + GAMES: 4 in 1 carts - + -------------------------------------------------*/ READ8_MEMBER(a26_rom_4in1_device::read_rom) @@ -1012,9 +1012,9 @@ READ8_MEMBER(a26_rom_4in1_device::read_rom) 8 in 1 Carts (Reset based): the 8K banks change at each reset, and internally each game runs as a F8-bankswitched cart - + GAMES: 8 in 1 cart - + -------------------------------------------------*/ READ8_MEMBER(a26_rom_8in1_device::read_rom) @@ -1029,7 +1029,7 @@ READ8_MEMBER(a26_rom_8in1_device::read_rom) break; } } - + return m_rom[offset + (m_base_bank * 0x1000) + (m_reset_bank * 0x2000)]; } @@ -1037,13 +1037,12 @@ READ8_MEMBER(a26_rom_8in1_device::read_rom) /*------------------------------------------------- 32 in 1 Carts (Reset based): the 2K banks change at each reset - + GAMES: 32 in 1 cart - + -------------------------------------------------*/ READ8_MEMBER(a26_rom_32in1_device::read_rom) { return m_rom[(offset & 0x7ff) + (m_base_bank * 0x800)]; } - diff --git a/src/emu/bus/vcs/rom.h b/src/emu/bus/vcs/rom.h index 33b00d0b5ea..a0434bd35c4 100755 --- a/src/emu/bus/vcs/rom.h +++ b/src/emu/bus/vcs/rom.h @@ -30,7 +30,7 @@ class a26_rom_4k_device : public a26_rom_2k_device public: // construction/destruction a26_rom_4k_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // reading and writing // accesses just use the 2K ones, since it is just direct access to ROM/RAM @@ -46,16 +46,16 @@ public: // construction/destruction a26_rom_f6_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source); a26_rom_f6_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // device-level overrides virtual void device_start(); virtual void device_reset(); - + // reading and writing virtual DECLARE_READ8_MEMBER(read_rom); virtual DECLARE_WRITE8_MEMBER(write_bank); virtual DECLARE_DIRECT_UPDATE_MEMBER(cart_opbase); - + protected: int m_base_bank; }; @@ -68,10 +68,10 @@ class a26_rom_f4_device : public a26_rom_f6_device public: // construction/destruction a26_rom_f4_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // device-level overrides virtual void device_reset(); - + // reading and writing virtual DECLARE_READ8_MEMBER(read_rom); virtual DECLARE_WRITE8_MEMBER(write_bank); @@ -86,7 +86,7 @@ public: // construction/destruction a26_rom_f8_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source); a26_rom_f8_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // reading and writing virtual DECLARE_READ8_MEMBER(read_rom); virtual DECLARE_WRITE8_MEMBER(write_bank); @@ -100,7 +100,7 @@ class a26_rom_f8_sw_device : public a26_rom_f8_device public: // construction/destruction a26_rom_f8_sw_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // device-level overrides virtual void device_reset(); }; @@ -113,7 +113,7 @@ class a26_rom_fa_device : public a26_rom_f6_device public: // construction/destruction a26_rom_fa_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // reading and writing virtual DECLARE_READ8_MEMBER(read_rom); virtual DECLARE_WRITE8_MEMBER(write_bank); @@ -127,17 +127,17 @@ class a26_rom_fe_device : public a26_rom_2k_device public: // construction/destruction a26_rom_fe_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // device-level overrides virtual void device_start(); virtual void device_reset(); - + // reading and writing virtual DECLARE_READ8_MEMBER(read_rom); virtual DECLARE_READ8_MEMBER(read_bank); virtual DECLARE_WRITE8_MEMBER(write_ram); virtual DECLARE_WRITE8_MEMBER(write_bank); - + protected: int m_base_bank; int m_trigger_on_next_access; @@ -151,16 +151,16 @@ class a26_rom_3e_device : public a26_rom_f6_device public: // construction/destruction a26_rom_3e_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // device-level overrides virtual void device_start(); virtual void device_reset(); - + // reading and writing virtual DECLARE_READ8_MEMBER(read_rom); virtual DECLARE_WRITE8_MEMBER(write_bank); virtual DECLARE_WRITE8_MEMBER(write_ram); - + protected: int m_num_bank; int m_ram_bank; @@ -175,14 +175,14 @@ class a26_rom_3f_device : public a26_rom_f6_device public: // construction/destruction a26_rom_3f_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // device-level overrides virtual void device_reset(); - + // reading and writing virtual DECLARE_READ8_MEMBER(read_rom); virtual DECLARE_WRITE8_MEMBER(write_bank); - + protected: int m_num_bank; }; @@ -195,15 +195,15 @@ class a26_rom_e0_device : public a26_rom_f6_device public: // construction/destruction a26_rom_e0_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // device-level overrides virtual void device_start(); virtual void device_reset(); - + // reading and writing virtual DECLARE_READ8_MEMBER(read_rom); virtual DECLARE_WRITE8_MEMBER(write_bank); - + protected: int m_base_banks[4]; }; @@ -216,15 +216,15 @@ class a26_rom_e7_device : public a26_rom_f6_device public: // construction/destruction a26_rom_e7_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // device-level overrides virtual void device_start(); virtual void device_reset(); - + // reading and writing virtual DECLARE_READ8_MEMBER(read_rom); virtual DECLARE_WRITE8_MEMBER(write_bank); - + protected: int m_ram_bank; }; @@ -237,10 +237,10 @@ class a26_rom_ua_device : public a26_rom_f6_device public: // construction/destruction a26_rom_ua_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // device-level overrides virtual void device_reset(); - + // reading and writing virtual DECLARE_READ8_MEMBER(read_rom); virtual DECLARE_READ8_MEMBER(read_bank); @@ -255,7 +255,7 @@ class a26_rom_cv_device : public a26_rom_2k_device public: // construction/destruction a26_rom_cv_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // reading and writing virtual DECLARE_READ8_MEMBER(read_rom); virtual DECLARE_WRITE8_MEMBER(write_bank); @@ -269,7 +269,7 @@ class a26_rom_dc_device : public a26_rom_f6_device public: // construction/destruction a26_rom_dc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // reading and writing virtual DECLARE_READ8_MEMBER(read_rom); virtual DECLARE_WRITE8_MEMBER(write_bank); @@ -283,15 +283,15 @@ class a26_rom_fv_device : public a26_rom_f6_device public: // construction/destruction a26_rom_fv_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // device-level overrides virtual void device_start(); virtual void device_reset(); - + // reading and writing virtual DECLARE_READ8_MEMBER(read_rom); virtual DECLARE_WRITE8_MEMBER(write_bank); - + protected: int m_locked; }; @@ -304,7 +304,7 @@ class a26_rom_jvp_device : public a26_rom_f6_device public: // construction/destruction a26_rom_jvp_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // reading and writing virtual DECLARE_READ8_MEMBER(read_rom); virtual DECLARE_WRITE8_MEMBER(write_bank); @@ -318,10 +318,10 @@ class a26_rom_4in1_device : public a26_rom_f6_device public: // construction/destruction a26_rom_4in1_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // device-level overrides virtual void device_reset(); - + // reading and writing virtual DECLARE_READ8_MEMBER(read_rom); }; @@ -334,11 +334,11 @@ class a26_rom_8in1_device : public a26_rom_f8_device public: // construction/destruction a26_rom_8in1_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // device-level overrides virtual void device_start(); virtual void device_reset(); - + // reading and writing virtual DECLARE_READ8_MEMBER(read_rom); @@ -354,10 +354,10 @@ class a26_rom_32in1_device : public a26_rom_f6_device public: // construction/destruction a26_rom_32in1_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - + // device-level overrides virtual void device_reset(); - + // reading and writing virtual DECLARE_READ8_MEMBER(read_rom); }; diff --git a/src/emu/bus/vcs/scharger.c b/src/emu/bus/vcs/scharger.c index efd685a5969..e536a474c18 100644 --- a/src/emu/bus/vcs/scharger.c +++ b/src/emu/bus/vcs/scharger.c @@ -2,31 +2,31 @@ Atari 2600 cart Starpath Supercharger (Cart + Tape drive!) - - + + From kevtris notes ( http://blog.kevtris.org/blogfiles/Atari%202600%20Mappers.txt ): - + - Control register [0x1ff8] - + 7 0 --------- 1FF8: DDDB BBWE - + D: write delay (see below) B: bankswitching mode (see below) W: RAM write enable (1 = enabled, 0 = disabled) E: ROM power enable (0 = enabled, 1 = turn off ROM) - + - Audio input register [0x1ff9] - + 7 0 - --------- + --------- 1FF9: 0000 000A - + A: Supercharger audio data. 0 = low input, 1 = high input. - - + + ***************************************************************************/ @@ -83,8 +83,8 @@ static MACHINE_CONFIG_FRAGMENT( a26_ss ) MCFG_CASSETTE_DEFAULT_STATE(CASSETTE_STOPPED | CASSETTE_MOTOR_ENABLED | CASSETTE_SPEAKER_ENABLED) MCFG_CASSETTE_INTERFACE("a2600_cass") -// MCFG_SOUND_WAVE_ADD(WAVE_TAG, "cassette") -// MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.25) +// MCFG_SOUND_WAVE_ADD(WAVE_TAG, "cassette") +// MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.25) MACHINE_CONFIG_END machine_config_constructor a26_rom_ss_device::device_mconfig_additions() const @@ -109,17 +109,17 @@ READ8_MEMBER(a26_rom_ss_device::read_rom) if (space.debugger_access()) return read_byte(offset); - // Bankswitch + // Bankswitch if (offset == 0xff8) { //logerror("%04X: Access to control register data = %02X\n", m_maincpu->pc(), m_modeSS_byte); m_write_delay = m_reg >> 5; m_ram_write_enabled = BIT(m_reg, 1); m_rom_enabled = !BIT(m_reg, 0); - + // compensate time spent in this access to avoid spurious RAM write m_byte_started -= 5; - + // handle bankswitch switch (m_reg & 0x1c) { @@ -164,10 +164,10 @@ READ8_MEMBER(a26_rom_ss_device::read_rom) { //logerror("%04X: Cassette port read, tap_val = %f\n", m_maincpu->pc(), tap_val); double tap_val = m_cassette->input(); - + // compensate time spent in this access to avoid spurious RAM write m_byte_started -= 5; - + if (tap_val < 0) return 0x00; else @@ -181,7 +181,7 @@ READ8_MEMBER(a26_rom_ss_device::read_rom) /* Check for dummy read from same address */ if (m_last_address == offset) m_diff_adjust++; - + int diff = m_maincpu->total_cycles() - m_byte_started; //logerror("%04X: offset = %04X, %d\n", m_maincpu->pc(), offset, diff); diff --git a/src/emu/bus/vcs/scharger.h b/src/emu/bus/vcs/scharger.h index d13d8e5b6d7..94ffda7230c 100644 --- a/src/emu/bus/vcs/scharger.h +++ b/src/emu/bus/vcs/scharger.h @@ -22,14 +22,14 @@ public: virtual void device_reset(); required_device<cassette_image_device> m_cassette; - + // reading and writing virtual DECLARE_READ8_MEMBER(read_rom); - + private: cpu_device *m_maincpu; inline UINT8 read_byte(UINT32 offset); - + int m_base_banks[2]; UINT8 m_reg; UINT8 m_write_delay, m_ram_write_enabled, m_rom_enabled; diff --git a/src/emu/bus/vcs/vcs_slot.c b/src/emu/bus/vcs/vcs_slot.c index a60cf55da52..a1a8797c18b 100755 --- a/src/emu/bus/vcs/vcs_slot.c +++ b/src/emu/bus/vcs/vcs_slot.c @@ -186,14 +186,14 @@ bool vcs_cart_slot_device::call_load() { UINT8 *ROM; UINT32 len; - + if (software_entry() != NULL) len = get_software_region_length("rom"); else len = length(); - + //printf("Size: 0x%X\n", len); - + // check that filesize is among the supported ones switch (len) { @@ -208,21 +208,21 @@ bool vcs_cart_slot_device::call_load() case 0x10000: case 0x80000: break; - + default: seterror(IMAGE_ERROR_UNSUPPORTED, "Invalid rom file size" ); return IMAGE_INIT_FAIL; } - + m_cart->rom_alloc(len, tag()); ROM = m_cart->get_rom_base(); - + if (software_entry() != NULL) { const char *pcb_name; bool has_ram = get_software_region("ram") ? TRUE : FALSE; memcpy(ROM, get_software_region("rom"), len); - + if ((pcb_name = get_feature("slot")) != NULL) m_type = vcs_get_pcb_id(pcb_name); else @@ -272,7 +272,7 @@ bool vcs_cart_slot_device::call_load() { fread(ROM, len); m_type = identify_cart_type(ROM, len); - + // check for Special Chip (128bytes of RAM) if (len == 0x2000 || len == 0x4000 || len == 0x8000) if (detect_super_chip(ROM, len)) @@ -284,7 +284,7 @@ bool vcs_cart_slot_device::call_load() // dig dig, crystal castles, millipede, stargate, defender ii, jr. Pac Man, // desert falcon, dark chambers, super football, sprintmaster, fatal run, // off the wall, shooting arcade, secret quest, radar lock, save mary, klax - + // add CBS RAM+ (256bytes of RAM) if (m_type == A26_FA) m_cart->ram_alloc(0x100); @@ -301,16 +301,16 @@ bool vcs_cart_slot_device::call_load() else if (m_type == A26_3E) m_cart->ram_alloc(0x8000); } - + //printf("Type: %s\n", vcs_get_slot(m_type)); - + // pass a pointer to the now allocated ROM for the DPC chip if (m_type == A26_DPC) m_cart->setup_addon_ptr((UINT8 *)m_cart->get_rom_base() + 0x2000); - + return IMAGE_INIT_PASS; } - + return IMAGE_INIT_PASS; } @@ -356,7 +356,7 @@ int vcs_cart_slot_device::detect_modeDC(UINT8 *cart, UINT32 len) } } } - if (numfound) + if (numfound) return 1; return 0; } @@ -376,7 +376,7 @@ int vcs_cart_slot_device::detect_modeF6(UINT8 *cart, UINT32 len) } } } - if (numfound) + if (numfound) return 1; return 0; } @@ -408,7 +408,7 @@ int vcs_cart_slot_device::detect_mode3E(UINT8 *cart, UINT32 len) } } } - if (numfound) + if (numfound) return 1; return 0; } @@ -428,7 +428,7 @@ int vcs_cart_slot_device::detect_modeSS(UINT8 *cart, UINT32 len) } } } - if (numfound) + if (numfound) return 1; return 0; } @@ -456,7 +456,7 @@ int vcs_cart_slot_device::detect_modeFE(UINT8 *cart, UINT32 len) } } } - if (numfound) + if (numfound) return 1; return 0; } @@ -486,7 +486,7 @@ int vcs_cart_slot_device::detect_modeE0(UINT8 *cart, UINT32 len) } } } - if (numfound) + if (numfound) return 1; return 0; } @@ -512,7 +512,7 @@ int vcs_cart_slot_device::detect_modeCV(UINT8 *cart, UINT32 len) } } } - if (numfound) + if (numfound) return 1; return 0; } @@ -535,7 +535,7 @@ int vcs_cart_slot_device::detect_modeFV(UINT8 *cart, UINT32 len) } } } - if (numfound) + if (numfound) return 1; return 0; } @@ -561,7 +561,7 @@ int vcs_cart_slot_device::detect_modeJVP(UINT8 *cart, UINT32 len) } } } - if (numfound) + if (numfound) return 1; return 0; } @@ -587,7 +587,7 @@ int vcs_cart_slot_device::detect_modeE7(UINT8 *cart, UINT32 len) } } } - if (numfound) + if (numfound) return 1; return 0; } @@ -607,7 +607,7 @@ int vcs_cart_slot_device::detect_modeUA(UINT8 *cart, UINT32 len) } } } - if (numfound) + if (numfound) return 1; return 0; } @@ -633,7 +633,7 @@ int vcs_cart_slot_device::detect_8K_mode3F(UINT8 *cart, UINT32 len) } } } - if (numfound == 0x03) + if (numfound == 0x03) return 1; return 0; } @@ -653,7 +653,7 @@ int vcs_cart_slot_device::detect_32K_mode3F(UINT8 *cart, UINT32 len) } } } - if (numfound > 1) + if (numfound > 1) return 1; return 0; } @@ -705,33 +705,33 @@ int vcs_cart_slot_device::identify_cart_type(UINT8 *ROM, UINT32 len) int type = 0xff; // auto-detect bank mode - if (detect_modeDC(ROM, len)) + if (detect_modeDC(ROM, len)) type = A26_DC; - else if (detect_mode3E(ROM, len)) + else if (detect_mode3E(ROM, len)) type = A26_3E; - else if (detect_modeFE(ROM, len)) + else if (detect_modeFE(ROM, len)) type = A26_FE; - else if (detect_modeSS(ROM, len)) + else if (detect_modeSS(ROM, len)) type = A26_SS; - else if (detect_modeE0(ROM, len)) + else if (detect_modeE0(ROM, len)) type = A26_E0; else if (detect_modeCV(ROM, len)) type = A26_CV; - else if (detect_modeFV(ROM, len)) + else if (detect_modeFV(ROM, len)) type = A26_FV; - else if (detect_modeJVP(ROM, len)) + else if (detect_modeJVP(ROM, len)) type = A26_JVP; - else if (detect_modeUA(ROM, len)) + else if (detect_modeUA(ROM, len)) type = A26_UA; - else if (detect_8K_mode3F(ROM, len)) + else if (detect_8K_mode3F(ROM, len)) type = A26_3F; - else if (detect_32K_mode3F(ROM, len)) + else if (detect_32K_mode3F(ROM, len)) type = A26_3F; - else if (detect_modeE7(ROM, len)) + else if (detect_modeE7(ROM, len)) type = A26_E7; else if (detect_snowhite(ROM, len)) type = A26_F8SW; - + // otherwise, choose based on size if (type == 0xff) { @@ -771,7 +771,7 @@ int vcs_cart_slot_device::identify_cart_type(UINT8 *ROM, UINT32 len) break; } } - + return type; } @@ -787,14 +787,14 @@ void vcs_cart_slot_device::get_default_card_software(astring &result) UINT32 len = core_fsize(m_file); dynamic_buffer rom(len); int type; - + core_fread(m_file, rom, len); - + type = identify_cart_type(rom, len); slot_string = vcs_get_slot(type); - + clear(); - + result.cpy(slot_string); } else diff --git a/src/emu/bus/vcs/vcs_slot.h b/src/emu/bus/vcs/vcs_slot.h index 18d604b1a69..3d393395f5a 100755 --- a/src/emu/bus/vcs/vcs_slot.h +++ b/src/emu/bus/vcs/vcs_slot.h @@ -18,7 +18,7 @@ enum A26_F8SW, A26_FA, A26_FE, - A26_3E, // to test + A26_3E, // to test A26_3F, A26_E0, A26_E7, @@ -26,7 +26,7 @@ enum A26_DC, A26_CV, A26_FV, - A26_JVP, // to test + A26_JVP, // to test A26_32IN1, A26_8IN1, A26_4IN1, @@ -49,7 +49,7 @@ public: virtual DECLARE_READ8_MEMBER(read_rom) { return 0xff; } // writing to RAM chips (sometimes it is in a different range than write_bank!) virtual DECLARE_WRITE8_MEMBER(write_ram) {} - + // read/write to bankswitch address virtual DECLARE_READ8_MEMBER(read_bank) { return 0xff; } virtual DECLARE_WRITE8_MEMBER(write_bank) {} |
