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author Vas Crabb <vas@vastheman.com>2022-12-25 01:33:31 +1100
committer Vas Crabb <vas@vastheman.com>2022-12-25 01:33:31 +1100
commitbb457cea6cc7fef408c0a964c1be0559b5cbfeff (patch)
tree0792a3d3bb6ba8a8127d910a9425c6188661abd2 /src/devices/video
parent8fe688782983df45485084f6babdc16a3b7b62b5 (diff)
srcclean in preparation for 0.251 branch
Diffstat (limited to 'src/devices/video')
-rw-r--r--src/devices/video/mc68328lcd.h4
-rw-r--r--src/devices/video/sed1375.h92
2 files changed, 48 insertions, 48 deletions
diff --git a/src/devices/video/mc68328lcd.h b/src/devices/video/mc68328lcd.h
index 0954eaa6505..c9a644f65a1 100644
--- a/src/devices/video/mc68328lcd.h
+++ b/src/devices/video/mc68328lcd.h
@@ -12,8 +12,8 @@
#pragma once
class mc68328_lcd_device : public device_t,
- public device_palette_interface,
- public device_video_interface
+ public device_palette_interface,
+ public device_video_interface
{
public:
mc68328_lcd_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
diff --git a/src/devices/video/sed1375.h b/src/devices/video/sed1375.h
index 3301bea5193..eeba865e8a3 100644
--- a/src/devices/video/sed1375.h
+++ b/src/devices/video/sed1375.h
@@ -92,74 +92,74 @@ protected:
enum : u8
{
- MODE0_MASK = 0xff,
- MODE0_WIDTH_MASK = 0x03,
- MODE0_FPSHIFT_BIT = 2,
- MODE0_FPFRAME_POL_BIT = 3,
- MODE0_FPLINE_POL_BIT = 4,
- MODE0_COLOR_BIT = 5,
- MODE0_DUAL_BIT = 6,
- MODE0_TFT_BIT = 7,
+ MODE0_MASK = 0xff,
+ MODE0_WIDTH_MASK = 0x03,
+ MODE0_FPSHIFT_BIT = 2,
+ MODE0_FPFRAME_POL_BIT = 3,
+ MODE0_FPLINE_POL_BIT = 4,
+ MODE0_COLOR_BIT = 5,
+ MODE0_DUAL_BIT = 6,
+ MODE0_TFT_BIT = 7,
- MODE1_MASK = 0xff,
- MODE1_SWINVERT_BIT = 0,
- MODE1_HWINVERT_BIT = 1,
- MODE1_FRREPEAT_BIT = 2,
- MODE1_BLANK_BIT = 3,
- MODE1_CLKDIV_BIT = 4,
- MODE1_HIPERF_BIT = 5,
- MODE1_BPP_MASK = 0xc0,
- MODE1_BPP_SHIFT = 6,
+ MODE1_MASK = 0xff,
+ MODE1_SWINVERT_BIT = 0,
+ MODE1_HWINVERT_BIT = 1,
+ MODE1_FRREPEAT_BIT = 2,
+ MODE1_BLANK_BIT = 3,
+ MODE1_CLKDIV_BIT = 4,
+ MODE1_HIPERF_BIT = 5,
+ MODE1_BPP_MASK = 0xc0,
+ MODE1_BPP_SHIFT = 6,
- MODE2_MASK = 0x0f,
- MODE2_SWPWRSAVE_MASK = 0x03,
- MODE2_SWPWRSAVE_SHIFT = 0,
- MODE2_HWPWRSAVE_BIT = 2,
- MODE2_LCDPWR_OVR_BIT = 3,
+ MODE2_MASK = 0x0f,
+ MODE2_SWPWRSAVE_MASK = 0x03,
+ MODE2_SWPWRSAVE_SHIFT = 0,
+ MODE2_HWPWRSAVE_BIT = 2,
+ MODE2_LCDPWR_OVR_BIT = 3,
- PANEL_HSIZE_MASK = 0x7f,
+ PANEL_HSIZE_MASK = 0x7f,
- FPLINE_START_MASK = 0x1f,
+ FPLINE_START_MASK = 0x1f,
- HBLANK_MASK = 0x1f,
+ HBLANK_MASK = 0x1f,
- FPFRAME_START_MASK = 0x3f,
+ FPFRAME_START_MASK = 0x3f,
- VBLANK_MASK = 0x3f,
- VBLANK_VBL_BIT = 7,
+ VBLANK_MASK = 0x3f,
+ VBLANK_VBL_BIT = 7,
- MODRATE_MASK = 0x3f,
+ MODRATE_MASK = 0x3f,
- START_OVF_MASK = 0x01,
+ START_OVF_MASK = 0x01,
- MEM_ADDR_OFFSET_MASK = 0xff,
+ MEM_ADDR_OFFSET_MASK = 0xff,
- LUT_ADDR_MASK = 0xff,
+ LUT_ADDR_MASK = 0xff,
- LUT_DATA_MASK = 0xf0,
- LUT_DATA_SHIFT = 4,
+ LUT_DATA_MASK = 0xf0,
+ LUT_DATA_SHIFT = 4,
- GPIO_CONFIG_MASK = 0x1f,
- GPIO_STATUS_MASK = 0x1f,
+ GPIO_CONFIG_MASK = 0x1f,
+ GPIO_STATUS_MASK = 0x1f,
- SCRATCH_MASK = 0xff,
+ SCRATCH_MASK = 0xff,
- SWIVEL_MODE_MASK = 0xc3,
- SWIVEL_CLKSEL_MASK = 0x03,
- SWIVEL_MODE_BIT = 6,
- SWIVEL_ENABLE_BIT = 7,
+ SWIVEL_MODE_MASK = 0xc3,
+ SWIVEL_CLKSEL_MASK = 0x03,
+ SWIVEL_MODE_BIT = 6,
+ SWIVEL_ENABLE_BIT = 7,
- SWIVEL_BYTECNT_MASK = 0xff
+ SWIVEL_BYTECNT_MASK = 0xff
};
enum : u16
{
- PANEL_VSIZE_MASK = 0x03ff,
+ PANEL_VSIZE_MASK = 0x03ff,
- SCREEN1_START_MASK = 0xffff,
- SCREEN2_START_MASK = 0xffff,
+ SCREEN1_START_MASK = 0xffff,
+ SCREEN2_START_MASK = 0xffff,
- SCREEN1_VSIZE_MASK = 0x03ff
+ SCREEN1_VSIZE_MASK = 0x03ff
};
memory_share_creator<u8> m_vram;