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author Brandon Munger <bmunger@gmail.com>2015-12-13 22:30:37 -0500
committer Brandon Munger <bmunger@gmail.com>2015-12-20 17:46:13 -0500
commitd256291daf8b6d015372e83b704c7edb2a6d69f2 (patch)
tree32e6450b448d460fcfa9d149f23837bf978dd35f /src/devices/machine/pdc.cpp
parentce577865e7ef5790100191584fa24177cf12e3b2 (diff)
r9751: Fix floppy disk access and add log defines
Diffstat (limited to 'src/devices/machine/pdc.cpp')
-rw-r--r--src/devices/machine/pdc.cpp145
1 files changed, 89 insertions, 56 deletions
diff --git a/src/devices/machine/pdc.cpp b/src/devices/machine/pdc.cpp
index b45146e369d..afcc9912bd0 100644
--- a/src/devices/machine/pdc.cpp
+++ b/src/devices/machine/pdc.cpp
@@ -22,6 +22,11 @@
#define HDC_TAG "hdc"
#define FDCDMA_TAG "i8237dma"
+#define TRACE_PDC_FDC 0
+#define TRACE_PDC_HDC 0
+#define TRACE_PDC_DMA 0
+#define TRACE_PDC_CMD 0
+
//**************************************************************************
// DEVICE DEFINITIONS
//**************************************************************************
@@ -65,9 +70,10 @@ static ADDRESS_MAP_START( pdc_io, AS_IO, 8, pdc_device )
AM_RANGE(0x21, 0x2F) AM_READWRITE(fdd_68k_r,fdd_68k_w) AM_MIRROR(0xFF00)
AM_RANGE(0x38, 0x38) AM_READ(p38_r) AM_MIRROR(0xFF00) // Possibly UPD765 interrupt
AM_RANGE(0x39, 0x39) AM_READ(p39_r) AM_MIRROR(0xFF00) // HDD related
+ AM_RANGE(0x3c, 0x3d) AM_READ(ds_r) AM_MIRROR(0xFF00) // Dipswitches??
AM_RANGE(0x40, 0x41) AM_DEVREADWRITE(HDC_TAG, hdc9224_device,read,write) AM_MIRROR(0xFF00)
AM_RANGE(0x42, 0x43) AM_DEVICE(FDC_TAG, upd765a_device, map) AM_MIRROR(0xFF00)
- AM_RANGE(0x50, 0x53) AM_WRITE(p50_53_w) AM_MIRROR(0xFF00)
+ AM_RANGE(0x50, 0x5f) AM_WRITE(p50_5f_w) AM_MIRROR(0xFF00)
AM_RANGE(0x60, 0x6f) AM_DEVREADWRITE(FDCDMA_TAG,am9517a_device,read,write) AM_MIRROR(0xFF00)
ADDRESS_MAP_END
@@ -116,7 +122,6 @@ static MACHINE_CONFIG_FRAGMENT( pdc )
// Floppy disk drive
MCFG_FLOPPY_DRIVE_ADD(FDC_TAG":0", pdc_floppies, "35hd", pdc_device::floppy_formats)
- //MCFG_FLOPPY_DRIVE_ADD(FDC_TAG":0", pdc_floppies, "35hd", floppy_image_device::default_floppy_formats)
/* DMA Controller - Intel P8237A-5 */
/* Channel 0: uPD765a Floppy Disk Controller */
@@ -130,7 +135,6 @@ static MACHINE_CONFIG_FRAGMENT( pdc )
MCFG_I8237_OUT_IOW_0_CB(WRITE8(pdc_device, i8237_fdc_dma_w))
MCFG_I8237_IN_IOR_1_CB(READ8(pdc_device, m68k_dma_r))
MCFG_I8237_OUT_IOW_1_CB(WRITE8(pdc_device, m68k_dma_w))
- // MCFG_AM9517A_OUT_DACK_0_CB(WRITELINE(pdc_device, fdc_dack_w))
/* Hard Disk Controller - HDC9224 */
MCFG_DEVICE_ADD(HDC_TAG, HDC9224, 0)
@@ -160,8 +164,6 @@ pdc_device::pdc_device(const machine_config &mconfig, const char *tag, device_t
m_pdccpu(*this, Z80_TAG),
m_dma8237(*this, FDCDMA_TAG),
m_fdc(*this, FDC_TAG),
- //m_floppy(*this, FDC_TAG ":0"),
- //m_floppy(*this, FDC_TAG ":0:35hd"),
m_hdc9224(*this, HDC_TAG),
m_pdc_ram(*this, "pdc_ram"),
m_m68k_r_cb(*this),
@@ -175,10 +177,6 @@ pdc_device::pdc_device(const machine_config &mconfig, const char *tag, device_t
void pdc_device::device_start()
{
-// m_fdc->set_floppy(m_floppy);
-// floppy_image_device *m_floppy;
-// m_floppy = machine().device<floppy_connector>("fdc:0")->get_device();
-
}
//-------------------------------------------------
@@ -191,11 +189,6 @@ void pdc_device::device_reset()
reg_p38 = 0;
reg_p38 |= 4; /* ready for 68k ram DMA */
//reg_p38 |= 0x20; // no idea at all - bit 5 (32)
- //m_fdc->ready_w(true);
- //m_floppy->mon_w(0);
- //m_fdc->set_floppy(m_floppy);
- //m_fdc->tc_w(1);
- //m_floppy->ready_w(true);
/* Reset CPU */
m_pdccpu->reset();
@@ -204,8 +197,6 @@ void pdc_device::device_reset()
m_m68k_r_cb.resolve_safe(0);
m_m68k_w_cb.resolve_safe();
- //machine().device<floppy_connector>(FDC_TAG":0")->get_device()->mon_w(false);
- //subdevice<floppy_connector>("fdc:0")->get_device()->mon_w(true);
m_fdc->set_rate(500000) ;
}
@@ -239,13 +230,13 @@ WRITE8_MEMBER(pdc_device::i8237_dma_mem_w)
READ8_MEMBER(pdc_device::i8237_fdc_dma_r)
{
UINT8 ret = m_fdc->dma_r();
- logerror("PDC: 8237 DMA CHANNEL 0 READ ADDRESS: %08X, DATA: %02X\n", offset, ret );
+ if(TRACE_PDC_DMA) logerror("PDC: 8237 DMA CHANNEL 0 READ ADDRESS: %08X, DATA: %02X\n", offset, ret );
return ret;
}
WRITE8_MEMBER(pdc_device::i8237_fdc_dma_w)
{
- logerror("PDC: 8237 DMA CHANNEL 0 WRITE ADDRESS: %08X, DATA: %02X\n", offset, data );
+ if(TRACE_PDC_DMA) logerror("PDC: 8237 DMA CHANNEL 0 WRITE ADDRESS: %08X, DATA: %02X\n", offset, data );
m_fdc->dma_w(data);
}
@@ -254,17 +245,17 @@ READ8_MEMBER(pdc_device::m68k_dma_r)
UINT32 address;
UINT8 data;
- address = fdd_68k_dma_r_address++;
+ address = fdd_68k_dma_address++;
data = m_m68k_r_cb(address);
- logerror("PDC: 8237 DMA CHANNEL 1 READ ADDRESS: %08X, DATA: %02X\n", address, data );
+ if(TRACE_PDC_DMA) logerror("PDC: 8237 DMA CHANNEL 1 READ ADDRESS: %08X, DATA: %02X\n", address, data );
return data;
}
WRITE8_MEMBER(pdc_device::m68k_dma_w)
{
- logerror("PDC: 8237 DMA CHANNEL 1 WRITE ADDRESS: %08X, DATA: %02X\n", fdd_68k_dma_w_address, data );
+ if(TRACE_PDC_DMA) logerror("PDC: 8237 DMA CHANNEL 1 WRITE ADDRESS: %08X, DATA: %02X\n", fdd_68k_dma_address, data );
m_m68k_w_cb(data);
- fdd_68k_dma_w_address++;
+ fdd_68k_dma_address++;
}
WRITE_LINE_MEMBER(pdc_device::hdd_irq)
@@ -281,27 +272,25 @@ READ8_MEMBER(pdc_device::p0_7_r)
switch(offset)
{
case 0: /* Port 0: Old style command low byte [0x5FF041B0] */
- logerror("PDC: Port 0x00 READ: %02X\n", reg_p0);
+ if(TRACE_PDC_CMD) logerror("PDC: Port 0x00 READ: %02X\n", reg_p0);
return reg_p0;
case 1: /* Port 1: Old style command high byte [0x5FF041B0] */
- logerror("PDC: Port 0x01 READ: %02X\n", reg_p1);
+ if(TRACE_PDC_CMD) logerror("PDC: Port 0x01 READ: %02X\n", reg_p1);
return reg_p1;
case 2: /* Port 2: FDD command address low byte [0x5FF0C0B0][0x5FF0C1B0] */
- logerror("PDC: Port 0x02 READ: %02X\n", reg_p2);
- fdd_68k_dma_r_address = (fdd_68k_dma_r_address & (0xFF<<9)) | (reg_p2 << 1);
+ if(TRACE_PDC_FDC) logerror("PDC: Port 0x02 READ: %02X\n", reg_p2);
return reg_p2;
case 3: /* Port 3: FDD command address high byte [0x5FF0C0B0][0x5FF0C1B0] */
- logerror("PDC: Port 0x03 READ: %02X\n", reg_p3);
- fdd_68k_dma_r_address = (fdd_68k_dma_r_address & (0xFF<<1)) | (reg_p3 << 9);
+ if(TRACE_PDC_FDC) logerror("PDC: Port 0x03 READ: %02X\n", reg_p3);
return reg_p3;
case 6: /* Port 6: FDD data destination address low byte [0x5FF080B0] */
- logerror("PDC: Port 0x06 READ: %02X\n", reg_p6);
+ if(TRACE_PDC_FDC) logerror("PDC: Port 0x06 READ: %02X\n", reg_p6);
return reg_p6;
case 7: /* Port 7: FDD data destination address high byte [0x5FF080B0] */
- logerror("PDC: Port 0x07 READ: %02X\n", reg_p7);
+ if(TRACE_PDC_FDC) logerror("PDC: Port 0x07 READ: %02X\n", reg_p7);
return reg_p7;
default:
- logerror("(!)PDC: Port %02X READ: \n", offset);
+ if(TRACE_PDC_CMD) logerror("(!)PDC: Port %02X READ: \n", offset);
return 0;
}
}
@@ -311,15 +300,15 @@ WRITE8_MEMBER(pdc_device::p0_7_w)
switch(offset)
{
case 4: /* Port 4: FDD command completion status low byte [0x5FF030B0] */
- logerror("PDC: Port 0x04 WRITE: %02X\n", data);
+ if(TRACE_PDC_FDC) logerror("PDC: Port 0x04 WRITE: %02X\n", data);
reg_p4 = data;
break;
case 5: /* Port 5: FDD command completion status high byte [0x5FF030B0] */
- logerror("PDC: Port 0x05 WRITE: %02X\n", data);
+ if(TRACE_PDC_FDC) logerror("PDC: Port 0x05 WRITE: %02X\n", data);
reg_p5 = data;
break;
default:
- logerror("(!)PDC: Port %02X WRITE: %02X\n", offset, data);
+ if(TRACE_PDC_FDC) logerror("(!)PDC: Port %02X WRITE: %02X\n", offset, data);
break;
}
}
@@ -330,7 +319,7 @@ READ8_MEMBER(pdc_device::fdd_68k_r)
switch(address)
{
default:
- logerror("(!)PDC: Port %02X READ: \n", address);
+ if(TRACE_PDC_FDC) logerror("(!)PDC: Port %02X READ: \n", address);
return 0;
}
}
@@ -340,20 +329,20 @@ WRITE8_MEMBER(pdc_device::fdd_68k_w)
switch(address)
{
case 0x21: /* Port 21: ?? */
- logerror("PDC: Port 0x21 WRITE: %02X\n", data);
- logerror("PDC: Resetting 0x38 bit 1\n");
+ if(TRACE_PDC_FDC) logerror("PDC: Port 0x21 WRITE: %02X\n", data);
+ if(TRACE_PDC_FDC) logerror("PDC: Resetting 0x38 bit 1\n");
reg_p38 &= ~2; // Clear bit 1
reg_p21 = data;
break;
case 0x23: /* Port 23: FDD 68k DMA high byte */
/* The address is << 1 on the 68k side */
- fdd_68k_dma_w_address = (fdd_68k_dma_w_address & (0xFF<<1)) | (data << 9);
- logerror("PDC: Port %02X WRITE: %02X\n", address, data);
+ fdd_68k_dma_address = (fdd_68k_dma_address & (0xFF<<1)) | (data << 9);
+ if(TRACE_PDC_FDC) logerror("PDC: Port %02X WRITE: %02X\n", address, data);
break;
case 0x24: /* Port 24: FDD 68k DMA low byte */
/* The address is << 1 on the 68k side */
- fdd_68k_dma_w_address = (fdd_68k_dma_w_address & (0xFF<<9)) | (data << 1);
- logerror("PDC: Port %02X WRITE: %02X\n", address, data);
+ fdd_68k_dma_address = (fdd_68k_dma_address & (0xFF<<9)) | (data << 1);
+ if(TRACE_PDC_FDC) logerror("PDC: Port %02X WRITE: %02X\n", address, data);
break;
case 0x26:
switch(data)
@@ -361,7 +350,7 @@ WRITE8_MEMBER(pdc_device::fdd_68k_w)
case 0x80:
m_dma8237->dreq1_w(1);
reg_p38 &= ~4; // Clear bit 4
- logerror("PDC: Port 0x26 WRITE: 0x80, DMA REQ CH 1\n");
+ if(TRACE_PDC_DMA) logerror("PDC: Port 0x26 WRITE: 0x80, DMA REQ CH 1\n");
break;
}
break;
@@ -370,19 +359,19 @@ WRITE8_MEMBER(pdc_device::fdd_68k_w)
{
case 0xFF:
m_dma8237->dreq1_w(0);
- logerror("PDC: Port 0x2C WRITE: 0xFF, DMA REQ CH 1 OFF\n");
+ if(TRACE_PDC_DMA) logerror("PDC: Port 0x2C WRITE: 0xFF, DMA REQ CH 1 OFF\n");
break;
}
break;
default:
- logerror("(!)PDC: Port %02X WRITE: %02X, PC: %X\n", address, data, space.device().safe_pc());
+ if(TRACE_PDC_FDC) logerror("(!)PDC: Port %02X WRITE: %02X, PC: %X\n", address, data, space.device().safe_pc());
break;
}
}
WRITE8_MEMBER(pdc_device::p38_w)
{
- logerror("PDC: Port 0x38 WRITE: %i\n", data);
+ if(TRACE_PDC_CMD) logerror("PDC: Port 0x38 WRITE: %i\n", data);
//reg_p38 |= data;
reg_p38 = data;
}
@@ -390,11 +379,7 @@ WRITE8_MEMBER(pdc_device::p38_w)
READ8_MEMBER(pdc_device::p38_r)
{
reg_p38 ^= 0x20; /* Invert bit 5 (32) */
- //UINT8 retn;
- logerror("PDC: Port 0x38 READ: %02X, PC: %X\n", reg_p38, space.device().safe_pc());
- //retn = reg_p38;
- //reg_p38 &= ~2; // Clear bit 1
- //return retn;
+ if(TRACE_PDC_CMD) logerror("PDC: Port 0x38 READ: %02X, PC: %X\n", reg_p38, space.device().safe_pc());
return reg_p38;
}
@@ -402,27 +387,75 @@ READ8_MEMBER(pdc_device::p39_r)
{
UINT8 data = 1;
if(b_fdc_irq) data |= 8; // Set bit 3
- logerror("PDC: Port 0x39 READ: %02X, PC: %X\n", data, space.device().safe_pc());
+ if(TRACE_PDC_CMD) logerror("PDC: Port 0x39 READ: %02X, PC: %X\n", data, space.device().safe_pc());
return data;
}
-WRITE8_MEMBER(pdc_device::p50_53_w)
+WRITE8_MEMBER(pdc_device::p50_5f_w)
{
UINT8 address = 0x50 + offset;
switch(address)
{
- case 0x53: /* Port 53: Almost certainly not FDD motor control, but seems to work */
+ case 0x52:
switch(data)
{
+ case 0x00:
+ if(TRACE_PDC_FDC) logerror("PDC: FDD (all) Motor off.\n");
+ m_fdc->subdevice<floppy_connector>("0")->get_device()->mon_w(1);
+ break;
+ case 0x80:
+ if(TRACE_PDC_FDC) logerror("PDC: FDD (all) Motor on.\n");
+ m_fdc->subdevice<floppy_connector>("0")->get_device()->mon_w(0);
+ break;
+ default:
+ if(TRACE_PDC_FDC) logerror("PDC: Port 0x52 WRITE: %x\n", data);
+ }
+ break;
+ case 0x53: /* Probably set_rate here */
+ if(TRACE_PDC_FDC) logerror("PDC: Port 0x53 WRITE: %x\n", data);
+ break;
+ case 0x54: /* Port 54: FDD Unit 1 Motor control */
+ switch(data)
+ {
+ case 0x00:
+ if(TRACE_PDC_FDC) logerror("PDC: FDD 1 Motor off.\n");
+ m_fdc->subdevice<floppy_connector>("0")->get_device()->mon_w(1);
+ break;
case 0x80:
- logerror("PDC: FDD Motor on.\n");
+ if(TRACE_PDC_FDC) logerror("PDC: FDD 1 Motor on.\n");
m_fdc->subdevice<floppy_connector>("0")->get_device()->mon_w(0);
break;
default:
- logerror("PDC: Port 0x53 WRITE: %x\n", data);
+ if(TRACE_PDC_FDC) logerror("PDC: Port 0x54 WRITE: %x\n", data);
}
break;
+ case 0x55: /* Port 54: FDD Unit 2 Motor control */
+ if(TRACE_PDC_FDC) logerror("PDC: FDD 2 motor control: %02X\n", data);
+ break;
+ case 0x56: /* Port 54: FDD Unit 3 Motor control */
+ if(TRACE_PDC_FDC) logerror("PDC: FDD 3 motor control: %02X\n", data);
+ break;
+ case 0x57: /* Port 54: FDD Unit 4 Motor control */
+ if(TRACE_PDC_FDC) logerror("PDC: FDD 4 motor control: %02X\n", data);
+ break;
default:
- logerror("PDC: Port %02x WRITE: %x\n", address, data);
+ if(TRACE_PDC_FDC) logerror("PDC: Port %02x WRITE: %x\n", address, data);
+ }
+}
+
+READ8_MEMBER(pdc_device::ds_r)
+{
+ switch(offset)
+ {
+ case 0x00:
+ logerror("PDC: Dipswitch %02X READ\n", offset);
+ return 0xFE;
+ break;
+ case 0x01:
+ logerror("PDC: Dipswitch %02X READ\n", offset);
+ return 0x0;
+ break;
+ default:
+ return 0;
}
}