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author Brandon Munger <bmunger@gmail.com>2015-12-01 19:37:47 -0500
committer Brandon Munger <bmunger@gmail.com>2015-12-20 17:46:11 -0500
commit862abdaf2154100bff4ca17767faef324686e57d (patch)
treedf74e41e8c920f271973f1343e253ea063bb5e9d /src/devices/machine/pdc.cpp
parentb3b834c45ae603c62b5bbd451ce2db5036762c80 (diff)
r9751: Initial DMA hookups and driver cleanup
Diffstat (limited to 'src/devices/machine/pdc.cpp')
-rw-r--r--src/devices/machine/pdc.cpp209
1 files changed, 105 insertions, 104 deletions
diff --git a/src/devices/machine/pdc.cpp b/src/devices/machine/pdc.cpp
index 241892d69d9..2921344d425 100644
--- a/src/devices/machine/pdc.cpp
+++ b/src/devices/machine/pdc.cpp
@@ -51,14 +51,9 @@ const rom_entry *pdc_device::device_rom_region() const
//-------------------------------------------------
static ADDRESS_MAP_START( pdc_mem, AS_PROGRAM, 8, pdc_device )
-// AM_RANGE(0x0000, 0x07ff) AM_MIRROR(0x6000) AM_RAM
-// AM_RANGE(0x1800, 0x180f) AM_MIRROR(0x63f0) AM_DEVREADWRITE(M6522_0_TAG, via6522_device, read, write)
-// AM_RANGE(0x1c00, 0x1c0f) AM_MIRROR(0x63f0) AM_DEVREADWRITE(M6522_1_TAG, via6522_device, read, write)
-// AM_RANGE(0x8000, 0xbfff) AM_MIRROR(0x4000) AM_ROM AM_REGION(M6502_TAG, 0)
AM_RANGE(0x0000, 0x3fff) AM_ROM AM_REGION("rom", 0)
AM_RANGE(0x8000, 0x9FFF) AM_RAM AM_SHARE("pdc_ram") // HM6264ALP-12 SRAM 8KB
AM_RANGE(0xC000, 0xC7FF) AM_RAM // HM6116P-2 SRAM 2KB
-// AM_RANGE(0x0000, 0x3fff) AM_RAM AM_SHARE("pdc_ram")
ADDRESS_MAP_END
//-------------------------------------------------
@@ -67,12 +62,12 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( pdc_io, AS_IO, 8, pdc_device )
AM_RANGE(0x00, 0x05) AM_READWRITE(p0_5_r,p0_5_w) AM_MIRROR(0xFF00)
- AM_RANGE(0x21, 0x21) AM_WRITE(p21_w) AM_MIRROR(0xFF00)
+ AM_RANGE(0x21, 0x2F) AM_READWRITE(fdd_68k_r,fdd_68k_w) AM_MIRROR(0xFF00)
AM_RANGE(0x38, 0x38) AM_READ(p38_r) AM_MIRROR(0xFF00) // Possibly UPD765 interrupt
AM_RANGE(0x39, 0x39) AM_READ(p39_r) AM_MIRROR(0xFF00) // HDD related
AM_RANGE(0x40, 0x41) AM_DEVREADWRITE(HDC_TAG, hdc9224_device,read,write) AM_MIRROR(0xFF00)
AM_RANGE(0x42, 0x43) AM_DEVICE(FDC_TAG, upd765a_device, map) AM_MIRROR(0xFF00)
- AM_RANGE(0xd0, 0xdf) AM_DEVREADWRITE(FDCDMA_TAG,am9517a_device,read,write) AM_MIRROR(0xFF00)
+ AM_RANGE(0x60, 0x6f) AM_DEVREADWRITE(FDCDMA_TAG,am9517a_device,read,write) AM_MIRROR(0xFF00)
ADDRESS_MAP_END
//-------------------------------------------------
@@ -107,57 +102,35 @@ FLOPPY_FORMATS_END
//-------------------------------------------------
static MACHINE_CONFIG_FRAGMENT( pdc )
- // CPU - Zilog Z0840006PSC
+ /* CPU - Zilog Z0840006PSC */
MCFG_CPU_ADD(Z80_TAG, Z80, XTAL_10MHz / 2)
MCFG_CPU_PROGRAM_MAP(pdc_mem)
MCFG_CPU_IO_MAP(pdc_io)
-// MCFG_QUANTUM_PERFECT_CPU(M6502_TAG)
-
-// MCFG_DEVICE_ADD(M6522_0_TAG, VIA6522, XTAL_16MHz/16)
-// MCFG_VIA6522_READPA_HANDLER(READ8(c1541_base_t, via0_pa_r))
-// MCFG_VIA6522_READPB_HANDLER(READ8(c1541_base_t, via0_pb_r))
-// MCFG_VIA6522_WRITEPA_HANDLER(WRITE8(c1541_base_t, via0_pa_w))
-// MCFG_VIA6522_WRITEPB_HANDLER(WRITE8(c1541_base_t, via0_pb_w))
-// MCFG_VIA6522_CB2_HANDLER(WRITELINE(c1541_base_t, via0_ca2_w))
-// MCFG_VIA6522_IRQ_HANDLER(WRITELINE(c1541_base_t, via0_irq_w))
-
-// MCFG_DEVICE_ADD(M6522_1_TAG, VIA6522, XTAL_16MHz/16)
-// MCFG_VIA6522_READPA_HANDLER(DEVREAD8(C64H156_TAG, c64h156_device, yb_r))
-// MCFG_VIA6522_READPB_HANDLER(READ8(c1541_base_t, via1_pb_r))
-// MCFG_VIA6522_WRITEPA_HANDLER(DEVWRITE8(C64H156_TAG, c64h156_device, yb_w))
-// MCFG_VIA6522_WRITEPB_HANDLER(WRITE8(c1541_base_t, via1_pb_w))
-// MCFG_VIA6522_CA2_HANDLER(DEVWRITELINE(C64H156_TAG, c64h156_device, soe_w))
-// MCFG_VIA6522_CB2_HANDLER(DEVWRITELINE(C64H156_TAG, c64h156_device, oe_w))
-// MCFG_VIA6522_IRQ_HANDLER(WRITELINE(c1541_base_t, via1_irq_w))
-
-// MCFG_DEVICE_ADD(C64H156_TAG, C64H156, XTAL_16MHz)
-// MCFG_64H156_ATN_CALLBACK(WRITELINE(c1541_base_t, atn_w))
-// MCFG_64H156_BYTE_CALLBACK(WRITELINE(c1541_base_t, byte_w))
-// MCFG_FLOPPY_DRIVE_ADD(C64H156_TAG":0", c1540_floppies, "525ssqd", c1541_base_t::floppy_formats)
-
- // uPD765a FDC - NEC D765AC-2
-// MCFG_UPD765A_ADD("upd765a", true, false)
+ //MCFG_QUANTUM_PERFECT_CPU(M6502_TAG)
+
+ /* Floppy Disk Controller - uPD765a - NEC D765AC-2 */
MCFG_UPD765A_ADD(FDC_TAG, true, true)
-// MCFG_UPD765_INTRQ_CALLBACK(DEVWRITELINE("ctc", z80ctc_device, trg3))
- //MCFG_UPD765_INTRQ_CALLBACK(INPUTLINE(Z80_TAG, INPUT_LINE_IRQ0))
+ MCFG_UPD765_INTRQ_CALLBACK(WRITELINE(pdc_device, fdc_irq))
MCFG_UPD765_DRQ_CALLBACK(DEVWRITELINE(FDCDMA_TAG, am9517a_device, dreq0_w)) MCFG_DEVCB_INVERT
// Floppy disk drive
MCFG_FLOPPY_DRIVE_ADD(FDC_TAG":0", pdc_floppies, "35hd", pdc_device::floppy_formats)
- // FDC DMA Controller - Intel P8237A-5
+ /* DMA Controller - Intel P8237A-5 */
+ /* Channel 0: uPD765a Floppy Disk Controller */
+ /* Channel 1: M68K main system memory */
MCFG_DEVICE_ADD(FDCDMA_TAG, AM9517A, XTAL_10MHz / 2)
-// MCFG_I8237_IN_MEMR_CB(READ8(pdc_device, memory_read_byte))
-// MCFG_I8237_OUT_MEMW_CB(WRITE8(pdc_device, memory_write_byte))
MCFG_I8237_OUT_HREQ_CB(WRITELINE(pdc_device, i8237_hreq_w))
MCFG_I8237_OUT_EOP_CB(WRITELINE(pdc_device, i8237_eop_w))
MCFG_I8237_IN_MEMR_CB(READ8(pdc_device, i8237_dma_mem_r))
MCFG_I8237_OUT_MEMW_CB(WRITE8(pdc_device, i8237_dma_mem_w))
MCFG_I8237_IN_IOR_0_CB(READ8(pdc_device, i8237_fdc_dma_r))
MCFG_I8237_OUT_IOW_0_CB(WRITE8(pdc_device, i8237_fdc_dma_w))
+ MCFG_I8237_IN_IOR_1_CB(READ8(pdc_device, m68k_dma_r))
+ MCFG_I8237_OUT_IOW_0_CB(WRITE8(pdc_device, m68k_dma_w))
// MCFG_AM9517A_OUT_DACK_0_CB(WRITELINE(pdc_device, fdc_dack_w))
- // HDC9224 HDC
+ /* Hard Disk Controller - HDC9224 */
MCFG_DEVICE_ADD(HDC_TAG, HDC9224, 0)
MCFG_MFM_HARDDISK_CONN_ADD("h1", pdc_harddisks, NULL, MFM_BYTE, 3000, 20, MFMHD_GEN_FORMAT)
MACHINE_CONFIG_END
@@ -177,54 +150,28 @@ machine_config_constructor pdc_device::device_mconfig_additions() const
//**************************************************************************
//-------------------------------------------------
-// c1541_base_t - constructor
+// pdc_device - constructor
//-------------------------------------------------
-//pdc_device::pdc_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source) :
pdc_device::pdc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
- //device_t(mconfig, type, name, tag, owner, clock, shortname, source),
device_t(mconfig, PDC, "ROLM PDC", tag, owner, clock, "pdc", __FILE__),
- //device_cbm_iec_interface(mconfig, *this),
- //device_c64_floppy_parallel_interface(mconfig, *this),
m_pdccpu(*this, Z80_TAG),
- //m_via0(*this, M6522_0_TAG),
- //m_via1(*this, M6522_1_TAG),
- //m_ga(*this, C64H156_TAG),
- //m_floppy(*this, C64H156_TAG":0:525ssqd"),
-// m_fdc(*this, FDC_TAG ":35hd")
m_dma8237(*this, FDCDMA_TAG),
m_fdc(*this, FDC_TAG),
m_floppy(*this, FDC_TAG ":0"),
m_hdc9224(*this, HDC_TAG),
-// m_harddisk(*this, "h1"),
- //m_address(*this, "ADDRESS"),
- //m_data_out(1),
- //m_via0_irq(CLEAR_LINE),
- //m_via1_irq(CLEAR_LINE)
- m_pdc_ram(*this, "pdc_ram")
+ m_pdc_ram(*this, "pdc_ram"),
+ m_m68k_r_cb(*this),
+ m_m68k_w_cb(*this)
{
}
//-------------------------------------------------
-// c1540_t - constructor
-//-------------------------------------------------
-
-//pdc_device::pdc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
-// : pdc_device_t(mconfig, PDC, "ROLM PDC", tag, owner, clock, "pdc", __FILE__) { }
-
-//-------------------------------------------------
// device_start - device-specific startup
//-------------------------------------------------
void pdc_device::device_start()
{
- // install image callbacks
-// m_ga->set_floppy(m_floppy);
-
- // register for state saving
-// save_item(NAME(m_data_out));
-// save_item(NAME(m_via0_irq));
-// save_item(NAME(m_via1_irq));
}
//-------------------------------------------------
@@ -233,36 +180,21 @@ void pdc_device::device_start()
void pdc_device::device_reset()
{
-// UINT8 *rom = memregion("rom")->base();
-// UINT8 *ram = m_pdc_ram;
-// memcpy(ram, rom, 0x4000);
+ /* Reset registers */
reg_p38 = 0;
- m_pdccpu->reset();
-// m_via0->reset();
-// m_via1->reset();
+ /* Reset CPU */
+ m_pdccpu->reset();
- // initialize gate array
-// m_ga->accl_w(0);
-// m_ga->ted_w(1);
+ /* Resolve callbacks */
+ m_m68k_r_cb.resolve_safe(0);
+ m_m68k_w_cb.resolve_safe();
}
//-------------------------------------------------
// I8237 DMA
//-------------------------------------------------
-//READ8_MEMBER(pdc_device::memory_read_byte)
-//{
-// address_space& prog_space = m_pdccpu->space(AS_PROGRAM);
-// return prog_space.read_byte(offset);
-//}
-
-//WRITE8_MEMBER(pdc_device::memory_write_byte)
-//{
-// address_space& prog_space = m_pdccpu->space(AS_PROGRAM);
-// return prog_space.write_byte(offset, data);
-//}
-
WRITE_LINE_MEMBER(pdc_device::i8237_hreq_w)
{
m_pdccpu->set_input_line(INPUT_LINE_HALT, state ? ASSERT_LINE : CLEAR_LINE);
@@ -295,25 +227,47 @@ WRITE8_MEMBER(pdc_device::i8237_fdc_dma_w)
m_fdc->dma_w(data);
}
+READ8_MEMBER(pdc_device::m68k_dma_r)
+{
+ //return m_m68k_r_cb(offset);
+ UINT32 address;
+ UINT8 data;
+
+ address = fdd_68k_dma_address++;
+ data = m_m68k_r_cb(address);
+ logerror("PDC: 8237 DMA CHANNEL 1 READ ADDRESS: %08X, DATA: %02X\n", address, data );
+ return data;
+}
+
+WRITE8_MEMBER(pdc_device::m68k_dma_w)
+{
+ //m_m68k_w_cb(offset,data);
+ logerror("PDC: 8237 DMA CHANNEL 1 WRITE ADDRESS: %08X, DATA: %02X\n", offset, data );
+}
+
WRITE_LINE_MEMBER(pdc_device::hdd_irq)
{
m_pdccpu->set_input_line(INPUT_LINE_IRQ0, HOLD_LINE);
}
+WRITE_LINE_MEMBER(pdc_device::fdc_irq)
+{
+ b_fdc_irq = state != 0;
+}
READ8_MEMBER(pdc_device::p0_5_r)
{
switch(offset)
{
- case 0: /* Port 0 */
+ case 0: /* Port 0: Old style command low byte [0x5FF041B0] */
logerror("PDC: Port 0x00 READ: %02X\n", reg_p0);
return reg_p0;
- case 1: /* Port 1 */
+ case 1: /* Port 1: Old style command high byte [0x5FF041B0] */
logerror("PDC: Port 0x01 READ: %02X\n", reg_p1);
return reg_p1;
- case 2:
+ case 2: /* Port 2: FDD command address low byte [0x5FF0C0B0][0x5FF0C1B0] */
logerror("PDC: Port 0x02 READ: %02X\n", reg_p2);
return reg_p2;
- case 3:
+ case 3: /* Port 3: FDD command address high byte [0x5FF0C0B0][0x5FF0C1B0] */
logerror("PDC: Port 0x03 READ: %02X\n", reg_p3);
return reg_p3;
default:
@@ -326,11 +280,11 @@ WRITE8_MEMBER(pdc_device::p0_5_w)
{
switch(offset)
{
- case 4:
+ case 4: /* Port 4: FDD command completion status low byte [0x5FF030B0] */
logerror("PDC: Port 0x04 WRITE: %02X\n", data);
reg_p4 = data;
break;
- case 5:
+ case 5: /* Port 5: FDD command completion status high byte [0x5FF030B0] */
logerror("PDC: Port 0x05 WRITE: %02X\n", data);
reg_p5 = data;
break;
@@ -340,12 +294,57 @@ WRITE8_MEMBER(pdc_device::p0_5_w)
}
}
-WRITE8_MEMBER(pdc_device::p21_w)
+READ8_MEMBER(pdc_device::fdd_68k_r)
+{
+ UINT8 address = offset + 0x21;
+ switch(address)
+ {
+ default:
+ logerror("(!)PDC: Port %02X READ: \n", address);
+ return 0;
+ }
+}
+WRITE8_MEMBER(pdc_device::fdd_68k_w)
{
- logerror("PDC: Port 0x21 WRITE: %02X\n", data);
- logerror("PDC: Resetting 0x38 bit 1\n");
- reg_p38 &= ~2; // Clear bit 1
- reg_p21 = data;
+ UINT8 address = offset + 0x21;
+ switch(address)
+ {
+ case 0x21: /* Port 21: ?? */
+ logerror("PDC: Port 0x21 WRITE: %02X\n", data);
+ logerror("PDC: Resetting 0x38 bit 1\n");
+ reg_p38 &= ~2; // Clear bit 1
+ reg_p21 = data;
+ break;
+ case 0x23: /* Port 23: FDD 68k DMA low byte */
+ /* The address is << 1 on the 68k side */
+ fdd_68k_dma_address = (fdd_68k_dma_address & (0xFF<<1)) | (data << 9);
+ logerror("PDC: Port %02X WRITE: %02X\n", address, data);
+ break;
+ case 0x24: /* Port 24: FDD 68k DMA high byte */
+ /* The address is << 1 on the 68k side */
+ fdd_68k_dma_address = (fdd_68k_dma_address & (0xFF<<9)) | (data << 1);
+ logerror("PDC: Port %02X WRITE: %02X\n", address, data);
+ break;
+ case 0x26:
+ switch(data)
+ {
+ case 0x80:
+ m_dma8237->dreq1_w(1);
+ break;
+ }
+ break;
+ case 0x2C:
+ switch(data)
+ {
+ case 0xFF:
+ m_dma8237->dreq1_w(0);
+ break;
+ }
+ break;
+ default:
+ logerror("(!)PDC: Port %02X WRITE: %02X\n", address, data);
+ break;
+ }
}
WRITE8_MEMBER(pdc_device::p38_w)
@@ -358,7 +357,7 @@ WRITE8_MEMBER(pdc_device::p38_w)
READ8_MEMBER(pdc_device::p38_r)
{
//UINT8 retn;
- logerror("PDC: Port 0x38 READ: %02X\n", reg_p38);
+// logerror("PDC: Port 0x38 READ: %02X\n", reg_p38);
//retn = reg_p38;
//reg_p38 &= ~2; // Clear bit 1
//return retn;
@@ -367,5 +366,7 @@ READ8_MEMBER(pdc_device::p38_r)
READ8_MEMBER(pdc_device::p39_r)
{
- return 1;
+ UINT8 data = 1;
+ if(b_fdc_irq) data |= 8; // Set bit 3
+ return data;
}