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author Angelo Salese <angelosa@users.noreply.github.com>2022-05-23 17:27:33 +0200
committer GitHub <noreply@github.com>2022-05-23 17:27:33 +0200
commite6180e3510bef6ea8ffb6abddf64d7d3006829ed (patch)
treebc5df1fb8bc2eaf5cff54675f7f60fadc59087a8 /src/devices/machine/pci.cpp
parent09062b24a3be57139beaf823af3d7c5532ab256f (diff)
Initial work towards a sis630 based chipset driver (#9635)
- Add more or less complete implementations of sis630_host, sis950_lpc, sis630_gui, sis5513_ide, sis7001_usb, sis7018_audio, sis900_eth devices; - Removed gamecstl.cpp in favour to the new sis630.cpp driver; - i386.cpp: enable CMOV feature for Pentium III and 4; - i386.cpp: add PSN stub feature for Pentium III; New machines marked as NOT_WORKING ---------------------------------- Shuttle MS-11 [Angelo Salese, archive.org]
Diffstat (limited to 'src/devices/machine/pci.cpp')
-rw-r--r--src/devices/machine/pci.cpp22
1 files changed, 22 insertions, 0 deletions
diff --git a/src/devices/machine/pci.cpp b/src/devices/machine/pci.cpp
index 2620f1fc642..993d45efed4 100644
--- a/src/devices/machine/pci.cpp
+++ b/src/devices/machine/pci.cpp
@@ -1,5 +1,10 @@
// license:BSD-3-Clause
// copyright-holders:Olivier Galibert
+/*
+ * References:
+ * - PCI local bus (rev 2.x)
+ * - https://wiki.osdev.org/PCI
+ */
#include "emu.h"
#include "pci.h"
@@ -87,6 +92,12 @@ pci_device::pci_device(const machine_config &mconfig, device_type type, const ch
}
}
+// main_id << 16 = vendor ID ($00-$01)
+// main_id & 0xffff = device ID ($02-$03)
+// revision = board versioning ($08)
+// pclass = programming interface/sub class code/base class code ($09-$0b)
+// subsystem_id << 16 = sub vendor ID ($2c-$2d) - NB: not all cards have these
+// subsystem_id & 0xffff = sub device ID ($2e-$2f) /
void pci_device::set_ids(uint32_t _main_id, uint8_t _revision, uint32_t _pclass, uint32_t _subsystem_id)
{
main_id = _main_id;
@@ -257,6 +268,17 @@ void pci_device::expansion_base_w(offs_t offset, uint32_t data, uint32_t mem_mas
remap_cb();
}
+// if non-zero a CAPability PoinTeR marks an offset in PCI config space where a standard extension is located
+// For example if capptr_r is 0xc0 then [offset+0xc0] has a capability identifier that is set with:
+// bits 31-16 <capability dependant, usually revision and supported sub-features>
+// bits 15-8 next capptr offset, 0x00 to determine the given item as last
+// bits 7-0 capability ID:
+// - 0x01 PMI Power Management Interface
+// - 0x02 AGP Accelerated Graphics Port
+// - 0x03 VPD Vital Product Data
+// - 0x04 Slot Identification
+// - 0x05 MSI Message Signaled Interrupts
+// - 0x06 CompactPCI Hot Swap
uint8_t pci_device::capptr_r()
{
return 0x00;