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author Ted Green <tedgreen99@inbox.com>2016-06-08 12:01:13 -0600
committer Ted Green <tedgreen99@inbox.com>2016-06-08 12:01:59 -0600
commit680a81e95051670589cc7855b4c156f3649816e7 (patch)
tree02af06c5aa44ab120f6e03919eb7401b23d74e5d /src/devices/machine/pci-ide.cpp
parent4f223dea16aa7ca8e5f3833f2793c3dc8e7dd5f7 (diff)
vegas: Corrected sub-device lookup string (nw)
vegas: Added Nile 4 timer scaling (nw) pci-ide: Added IRQ callback (nw) atlantis: Added more address map locations (nw) dcs: Add sport timer for dcs2 dsio device (nw)
Diffstat (limited to 'src/devices/machine/pci-ide.cpp')
-rw-r--r--src/devices/machine/pci-ide.cpp28
1 files changed, 22 insertions, 6 deletions
diff --git a/src/devices/machine/pci-ide.cpp b/src/devices/machine/pci-ide.cpp
index c90a8afb311..e6c18219e0d 100644
--- a/src/devices/machine/pci-ide.cpp
+++ b/src/devices/machine/pci-ide.cpp
@@ -8,7 +8,8 @@ ide_pci_device::ide_pci_device(const machine_config &mconfig, const char *tag, d
: pci_device(mconfig, IDE_PCI, "IDE PCI interface", tag, owner, clock, "ide_pci", __FILE__),
m_ide(*this, "ide"),
m_ide2(*this, "ide2"),
- m_irq_num(-1)
+ m_irq_num(-1),
+ m_irq_handler(*this)
{
}
@@ -63,7 +64,8 @@ void ide_pci_device::set_irq_info(const char *tag, const int irq_num)
void ide_pci_device::device_start()
{
- m_cpu = machine().device<cpu_device>(m_cpu_tag);
+ if (m_irq_num != -1)
+ m_cpu = machine().device<cpu_device>(m_cpu_tag);
pci_device::device_start();
@@ -77,6 +79,8 @@ void ide_pci_device::device_start()
bank_infos[3].adr = 0x374;
add_map(16, M_IO, FUNC(ide_pci_device::bus_master_map));
bank_infos[4].adr = 0xf00;
+
+ m_irq_handler.resolve_safe();
}
void ide_pci_device::device_reset()
@@ -119,12 +123,21 @@ WRITE32_MEMBER(ide_pci_device::ide2_write_cs1)
WRITE_LINE_MEMBER(ide_pci_device::ide_interrupt)
{
+ // Assert/Clear the interrupt if the irq num is set.
if (m_irq_num != -1) {
m_cpu->set_input_line(m_irq_num, state);
}
+ // Call the callback
+ m_irq_handler(state);
+
// PCI646U2 Offset 0x50 is interrupt status
- if (main_id == 0x10950646 && state)
- m_config_data[0x10/4] |= 0x4;
+ if (main_id == 0x10950646) {
+
+ if (state)
+ m_config_data[0x10 / 4] |= 0x4;
+ else
+ m_config_data[0x10 / 4] &= ~0x4;
+ }
if (0)
logerror("%s:ide_interrupt %i set to %i\n", machine().describe_context(), m_irq_num, state);
}
@@ -138,8 +151,11 @@ WRITE32_MEMBER(ide_pci_device::pcictrl_w)
{
COMBINE_DATA(&m_config_data[offset]);
// PCI646U2 Offset 0x50 is interrupt status
- if (main_id == 0x10950646 && offset == 0x10/4 && (data & 0x4))
- m_config_data[0x10/4] &= ~0x4;
+ if (main_id == 0x10950646 && offset == 0x10 / 4 && (data & 0x4)) {
+ m_config_data[0x10 / 4] &= ~0x4;
+ if (0)
+ logerror("%s:ide_pci_device::pcictrl_w Clearing interrupt status\n", machine().describe_context());
+ }
}
WRITE32_MEMBER(ide_pci_device::address_base_w)