summaryrefslogtreecommitdiffstatshomepage
path: root/src/devices/machine/atmel_arm_aic.h
diff options
context:
space:
mode:
author MetalliC <0vetal0@gmail.com>2017-12-16 17:19:52 +0200
committer MetalliC <0vetal0@gmail.com>2017-12-16 17:19:52 +0200
commit8255459e5d674edd8822124a4fc9bf9b30f895d4 (patch)
treec310f0433aa5a8dabcef19a2084e0eef9e20bd72 /src/devices/machine/atmel_arm_aic.h
parent0932b9c2ae7c59681144e8b65862ed541a01c47f (diff)
Atmel AIC: implement most of features
Diffstat (limited to 'src/devices/machine/atmel_arm_aic.h')
-rw-r--r--src/devices/machine/atmel_arm_aic.h32
1 files changed, 27 insertions, 5 deletions
diff --git a/src/devices/machine/atmel_arm_aic.h b/src/devices/machine/atmel_arm_aic.h
index 9083c44fd95..c17d95e86d0 100644
--- a/src/devices/machine/atmel_arm_aic.h
+++ b/src/devices/machine/atmel_arm_aic.h
@@ -31,17 +31,27 @@ public:
DECLARE_READ32_MEMBER(irq_vector_r);
DECLARE_READ32_MEMBER(firq_vector_r);
+ DECLARE_READ32_MEMBER(aic_isr_r) { return m_status; };
+ DECLARE_READ32_MEMBER(aic_cisr_r) { return m_core_status; };
+ DECLARE_READ32_MEMBER(aic_ipr_r) { return m_irqs_pending; };
+ DECLARE_READ32_MEMBER(aic_imr_r) { return m_irqs_enabled; };
+ DECLARE_READ32_MEMBER(aic_ffsr_r) { return m_fast_irqs; };
// can't use AM_RAM and AM_SHARE in device submaps
DECLARE_READ32_MEMBER(aic_smr_r) { return m_aic_smr[offset]; };
DECLARE_READ32_MEMBER(aic_svr_r) { return m_aic_svr[offset]; };
DECLARE_WRITE32_MEMBER(aic_smr_w) { COMBINE_DATA(&m_aic_smr[offset]); };
DECLARE_WRITE32_MEMBER(aic_svr_w) { COMBINE_DATA(&m_aic_svr[offset]); };
+ DECLARE_WRITE32_MEMBER(aic_spu_w) { COMBINE_DATA(&m_spurious_vector); };
+ DECLARE_WRITE32_MEMBER(aic_dcr_w) { COMBINE_DATA(&m_debug); check_irqs(); };
+ DECLARE_WRITE32_MEMBER(aic_ffer_w) { m_fast_irqs |= data & mem_mask; check_irqs(); };
+ DECLARE_WRITE32_MEMBER(aic_ffdr_w) { m_fast_irqs &= ~(data & mem_mask) | 1; check_irqs(); };
- DECLARE_WRITE32_MEMBER(aic_iecr_w) { m_irqs_enabled |= data & mem_mask; recalc_irqs(); };
- DECLARE_WRITE32_MEMBER(aic_idcr_w) { m_irqs_enabled &= ~(data & mem_mask); recalc_irqs(); };
- DECLARE_WRITE32_MEMBER(aic_iccr_w) { m_irqs_pending &= ~(data & mem_mask); recalc_irqs(); };
- DECLARE_WRITE32_MEMBER(aic_eoicr_w){ /*logerror("%s: aic_eoicr_w (End of Interrupt Command Register)\n", machine().describe_context().c_str());*/ }; // value doesn't matter
+ DECLARE_WRITE32_MEMBER(aic_iecr_w) { m_irqs_enabled |= data & mem_mask; check_irqs(); };
+ DECLARE_WRITE32_MEMBER(aic_idcr_w) { m_irqs_enabled &= ~(data & mem_mask); check_irqs(); };
+ DECLARE_WRITE32_MEMBER(aic_iccr_w) { m_irqs_pending &= ~(data & mem_mask); check_irqs(); };
+ DECLARE_WRITE32_MEMBER(aic_iscr_w) { m_irqs_pending |= data & mem_mask; check_irqs(); };
+ DECLARE_WRITE32_MEMBER(aic_eoicr_w) { m_status = 0; pop_level(); check_irqs(); };
void set_irq(int line, int state);
@@ -54,12 +64,24 @@ private:
uint32_t m_irqs_pending;
uint32_t m_current_irq_vector;
uint32_t m_current_firq_vector;
+ uint32_t m_status;
+ uint32_t m_core_status;
+ uint32_t m_spurious_vector;
+ uint32_t m_debug;
+ uint32_t m_fast_irqs;
+ int m_lvlidx;
+ int m_level_stack[9];
uint32_t m_aic_smr[32];
uint32_t m_aic_svr[32];
devcb_write_line m_irq_out;
- void recalc_irqs();
+ void check_irqs();
+ void set_lines() { m_irq_out((m_core_status & ~m_debug & 2) ? ASSERT_LINE : CLEAR_LINE); }; // TODO FIQ
+
+ void push_level(int lvl) { m_level_stack[++m_lvlidx] = lvl; };
+ void pop_level() { if (m_lvlidx) --m_lvlidx; };
+ int get_level() { return m_level_stack[m_lvlidx]; };
};
#endif