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author Vas Crabb <vas@vastheman.com>2017-05-07 23:18:47 +1000
committer Vas Crabb <vas@vastheman.com>2017-05-14 21:44:11 +1000
commit0f0d39ef81562c75e79176dd3bebb1e491ca39d5 (patch)
tree201cee7fdf55ee800f83859a92efd2cfe66cf2b3 /src/devices/machine/68307sim.cpp
parente6c4be2b4d71c7a6c95be0bae111eb416ff0f9e7 (diff)
Move static data out of devices into the device types. This is a significant change, so please pay attention.
The core changes are: * Short name, full name and source file are no longer members of device_t, they are part of the device type * MACHINE_COFIG_START no longer needs a driver class * MACHINE_CONFIG_DERIVED_CLASS is no longer necessary * Specify the state class you want in the GAME/COMP/CONS line * The compiler will work out the base class where the driver init member is declared * There is one static device type object per driver rather than one per machine configuration Use DECLARE_DEVICE_TYPE or DECLARE_DEVICE_TYPE_NS to declare device type. * DECLARE_DEVICE_TYPE forward-declares teh device type and class, and declares extern object finders. * DECLARE_DEVICE_TYPE_NS is for devices classes in namespaces - it doesn't forward-declare the device type. Use DEFINE_DEVICE_TYPE or DEFINE_DEVICE_TYPE_NS to define device types. * These macros declare storage for the static data, and instantiate the device type and device finder templates. The rest of the changes are mostly just moving stuff out of headers that shouldn't be there, renaming stuff for consistency, and scoping stuff down where appropriate. Things I've actually messed with substantially: * More descriptive names for a lot of devices * Untangled the fantasy sound from the driver state, which necessitates breaking up sound/flip writes * Changed DECO BSMT2000 ready callback into a device delegate * Untangled Microprose 3D noise from driver state * Used object finders for CoCo multipak, KC85 D002, and Irem sound subdevices * Started to get TI-99 stuff out of the TI-990 directory and arrange bus devices properly * Started to break out common parts of Samsung ARM SoC devices * Turned some of FM, SID, SCSP DSP, EPIC12 and Voodoo cores into something resmbling C++ * Tried to make Z180 table allocation/setup a bit safer * Converted generic keyboard/terminal to not use WRITE8 - space/offset aren't relevant * Dynamically allocate generic terminal buffer so derived devices (e.g. teleprinter) can specify size * Imporved encapsulation of Z80DART channels * Refactored the SPC7110 bit table generator loop to make it more readable * Added wrappers for SNES PPU operations so members can be made protected * Factored out some boilerplate for YM chips with PSG * toaplan2 gfx * stic/intv resolution * Video System video * Out Run/Y-board sprite alignment * GIC video hookup * Amstrad CPC ROM box members * IQ151 ROM cart region * MSX cart IRQ callback resolution time * SMS passthrough control devices starting subslots I've smoke-tested several drivers, but I've probably missed something. Things I've missed will likely blow up spectacularly with failure to bind errors and the like. Let me know if there's more subtle breakage (could have happened in FM or Voodoo). And can everyone please, please try to keep stuff clean. In particular, please stop polluting the global namespace. Keep things out of headers that don't need to be there, and use things that can be scoped down rather than macros. It feels like an uphill battle trying to get this stuff under control while more of it's added.
Diffstat (limited to 'src/devices/machine/68307sim.cpp')
-rw-r--r--src/devices/machine/68307sim.cpp294
1 files changed, 154 insertions, 140 deletions
diff --git a/src/devices/machine/68307sim.cpp b/src/devices/machine/68307sim.cpp
index 47479cae1da..2913d64e0a5 100644
--- a/src/devices/machine/68307sim.cpp
+++ b/src/devices/machine/68307sim.cpp
@@ -3,167 +3,181 @@
/* 68307 SIM module */
#include "emu.h"
-#include "68307.h"
-
-
-READ16_MEMBER( m68307cpu_device::m68307_internal_sim_r )
+#include "68307sim.h"
+
+/* ports */
+#define m68307SIM_PACNT (0x10)
+#define m68307SIM_PADDR (0x12)
+#define m68307SIM_PADAT (0x14)
+#define m68307SIM_PBCNT (0x16)
+#define m68307SIM_PBDDR (0x18)
+#define m68307SIM_PBDAT (0x1a)
+
+
+/* interrupt logic */
+#define m68307SIM_LICR1 (0x20)
+#define m68307SIM_LICR2 (0x22)
+#define m68307SIM_PICR (0x24)
+#define m68307SIM_PIVR (0x26)
+
+/* used for the CS logic */
+#define m68307SIM_BR0 (0x40)
+#define m68307SIM_OR0 (0x42)
+#define m68307SIM_BR1 (0x44)
+#define m68307SIM_OR1 (0x46)
+#define m68307SIM_BR2 (0x48)
+#define m68307SIM_OR2 (0x4a)
+#define m68307SIM_BR3 (0x4c)
+#define m68307SIM_OR3 (0x4e)
+
+READ16_MEMBER( m68307_cpu_device::m68307_internal_sim_r )
{
- m68307cpu_device *m68k = this;
- m68307_sim* sim = m68k->m68307SIM;
- assert(sim != nullptr);
+ assert(m68307SIM);
+ m68307_sim &sim = *m68307SIM;
int pc = space.device().safe_pc();
- if (sim)
+ switch (offset<<1)
{
- switch (offset<<1)
- {
- case m68307SIM_PADAT: return sim->read_padat(this, space, mem_mask);
- case m68307SIM_PBDAT: return sim->read_pbdat(this, space, mem_mask);
-
- case m68307SIM_LICR2: return (sim->m_licr2);
-
- case m68307SIM_BR0: return (sim->m_br[0]);
- case m68307SIM_OR0: return (sim->m_or[0]);
- case m68307SIM_BR1: return (sim->m_br[1]);
- case m68307SIM_OR1: return (sim->m_or[1]);
- case m68307SIM_BR2: return (sim->m_br[2]);
- case m68307SIM_OR2: return (sim->m_or[2]);
- case m68307SIM_BR3: return (sim->m_br[3]);
- case m68307SIM_OR3: return (sim->m_or[3]);
-
- default:
- logerror("%08x m68307_internal_sim_r %08x, (%04x)\n", pc, offset*2,mem_mask);
- return 0xff;
-
- }
+ case m68307SIM_PADAT: return sim.read_padat(this, space, mem_mask);
+ case m68307SIM_PBDAT: return sim.read_pbdat(this, space, mem_mask);
+
+ case m68307SIM_LICR2: return sim.m_licr2;
+
+ case m68307SIM_BR0: return sim.m_br[0];
+ case m68307SIM_OR0: return sim.m_or[0];
+ case m68307SIM_BR1: return sim.m_br[1];
+ case m68307SIM_OR1: return sim.m_or[1];
+ case m68307SIM_BR2: return sim.m_br[2];
+ case m68307SIM_OR2: return sim.m_or[2];
+ case m68307SIM_BR3: return sim.m_br[3];
+ case m68307SIM_OR3: return sim.m_or[3];
+
+ default:
+ logerror("%08x m68307_internal_sim_r %08x, (%04x)\n", pc, offset*2, mem_mask);
+ return 0xff;
}
return 0x0000;
}
-WRITE16_MEMBER( m68307cpu_device::m68307_internal_sim_w )
+WRITE16_MEMBER( m68307_cpu_device::m68307_internal_sim_w )
{
- m68307cpu_device *m68k = this;
- m68307_sim* sim = m68k->m68307SIM;
- assert(sim != nullptr);
+ assert(m68307SIM);
+ m68307_sim &sim = *m68307SIM;
int pc = space.device().safe_pc();
- if (sim)
+ switch (offset<<1)
{
- switch (offset<<1)
- {
- case m68307SIM_PACNT:
- logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port A (8-bit) Control Register - PACNT)\n", pc, offset*2,data,mem_mask);
- sim->write_pacnt(data,mem_mask);
- break;
-
- case m68307SIM_PADDR:
- logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port A (8-bit) Direction Register - PADDR)\n", pc, offset*2,data,mem_mask);
- sim->write_paddr(data,mem_mask);
- break;
-
- case m68307SIM_PADAT:
- sim->write_padat(this, space, data,mem_mask);
- break;
-
- case m68307SIM_PBCNT:
- logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port B (16-bit) Control Register - PBCNT)\n", pc, offset*2,data,mem_mask);
- sim->write_pbcnt(data,mem_mask);
- break;
-
- case m68307SIM_PBDDR:
- logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port B (16-bit) Direction Register - PBDDR)\n", pc, offset*2,data,mem_mask);
- sim->write_pbddr(data,mem_mask);
- break;
-
- case m68307SIM_PBDAT:
- sim->write_pbdat(this, space, data, mem_mask);
- break;
-
-
- case m68307SIM_LICR1:
- logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Latched Interrupt Control Register 1 - LICR1)\n", pc, offset*2,data,mem_mask);
- sim->write_licr1(this,data,mem_mask);
- break;
-
- case m68307SIM_LICR2:
- logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Latched Interrupt Control Register 2 - LICR2)\n", pc, offset*2,data,mem_mask);
- sim->write_licr2(this,data,mem_mask);
- break;
-
- case m68307SIM_PICR:
- logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Peripheral Interrupt Control Register - PICR)\n", pc, offset*2,data,mem_mask);
- sim->write_picr(this,data,mem_mask);
- break;
-
- case m68307SIM_PIVR:
- logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Peripheral Interrupt Vector Register - PIVR)\n", pc, offset*2,data,mem_mask);
- sim->write_pivr(this,data,mem_mask);
- break;
-
- case m68307SIM_BR0:
- COMBINE_DATA(&sim->m_br[0]);
- break;
- case m68307SIM_OR0:
- COMBINE_DATA(&sim->m_or[0]);
- break;
- case m68307SIM_BR1:
- COMBINE_DATA(&sim->m_br[1]);
- break;
- case m68307SIM_OR1:
- COMBINE_DATA(&sim->m_or[1]);
- break;
- case m68307SIM_BR2:
- COMBINE_DATA(&sim->m_br[2]);
- break;
- case m68307SIM_OR2:
- COMBINE_DATA(&sim->m_or[2]);
- break;
- case m68307SIM_BR3:
- COMBINE_DATA(&sim->m_br[3]);
- break;
- case m68307SIM_OR3:
- COMBINE_DATA(&sim->m_or[3]);
- break;
-
-
-
- default :
- logerror("%08x m68307_internal_sim_w %08x, %04x (%04x)\n", pc, offset*2,data,mem_mask);
- break;
-
- }
+ case m68307SIM_PACNT:
+ logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port A (8-bit) Control Register - PACNT)\n", pc, offset*2,data,mem_mask);
+ sim.write_pacnt(data,mem_mask);
+ break;
+
+ case m68307SIM_PADDR:
+ logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port A (8-bit) Direction Register - PADDR)\n", pc, offset*2,data,mem_mask);
+ sim.write_paddr(data,mem_mask);
+ break;
+
+ case m68307SIM_PADAT:
+ sim.write_padat(this, space, data,mem_mask);
+ break;
+
+ case m68307SIM_PBCNT:
+ logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port B (16-bit) Control Register - PBCNT)\n", pc, offset*2,data,mem_mask);
+ sim.write_pbcnt(data,mem_mask);
+ break;
+
+ case m68307SIM_PBDDR:
+ logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port B (16-bit) Direction Register - PBDDR)\n", pc, offset*2,data,mem_mask);
+ sim.write_pbddr(data,mem_mask);
+ break;
+
+ case m68307SIM_PBDAT:
+ sim.write_pbdat(this, space, data, mem_mask);
+ break;
+
+
+ case m68307SIM_LICR1:
+ logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Latched Interrupt Control Register 1 - LICR1)\n", pc, offset*2,data,mem_mask);
+ sim.write_licr1(this,data,mem_mask);
+ break;
+
+ case m68307SIM_LICR2:
+ logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Latched Interrupt Control Register 2 - LICR2)\n", pc, offset*2,data,mem_mask);
+ sim.write_licr2(this,data,mem_mask);
+ break;
+
+ case m68307SIM_PICR:
+ logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Peripheral Interrupt Control Register - PICR)\n", pc, offset*2,data,mem_mask);
+ sim.write_picr(this,data,mem_mask);
+ break;
+
+ case m68307SIM_PIVR:
+ logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Peripheral Interrupt Vector Register - PIVR)\n", pc, offset*2,data,mem_mask);
+ sim.write_pivr(this,data,mem_mask);
+ break;
+
+ case m68307SIM_BR0:
+ COMBINE_DATA(&sim.m_br[0]);
+ break;
+ case m68307SIM_OR0:
+ COMBINE_DATA(&sim.m_or[0]);
+ break;
+ case m68307SIM_BR1:
+ COMBINE_DATA(&sim.m_br[1]);
+ break;
+ case m68307SIM_OR1:
+ COMBINE_DATA(&sim.m_or[1]);
+ break;
+ case m68307SIM_BR2:
+ COMBINE_DATA(&sim.m_br[2]);
+ break;
+ case m68307SIM_OR2:
+ COMBINE_DATA(&sim.m_or[2]);
+ break;
+ case m68307SIM_BR3:
+ COMBINE_DATA(&sim.m_br[3]);
+ break;
+ case m68307SIM_OR3:
+ COMBINE_DATA(&sim.m_or[3]);
+ break;
+
+
+
+ default :
+ logerror("%08x m68307_internal_sim_w %08x, %04x (%04x)\n", pc, offset*2,data,mem_mask);
+ break;
}
}
-void m68307_sim::write_pacnt(uint16_t data, uint16_t mem_mask)
+void m68307_cpu_device::m68307_sim::write_pacnt(uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_pacnt);
}
-void m68307_sim::write_paddr(uint16_t data, uint16_t mem_mask)
+void m68307_cpu_device::m68307_sim::write_paddr(uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_paddr);
}
-uint16_t m68307_sim::read_padat(m68307cpu_device* m68k, address_space &space, uint16_t mem_mask)
+uint16_t m68307_cpu_device::m68307_sim::read_padat(m68307_cpu_device* m68k, address_space &space, uint16_t mem_mask)
{
int pc = space.device().safe_pc();
- if (!m68k->m_m68307_porta_r.isnull())
+ if (!m68k->m_porta_r.isnull())
{
// for general purpose bits, if configured as 'output' then anything output gets latched
// and anything configured as input is read from the port
uint8_t outputbits = m_paddr;
uint8_t inputbits = ~m_paddr;
uint8_t general_purpose_bits = ~m_pacnt;
- uint8_t indat = m68k->m_m68307_porta_r(space, false, (inputbits & general_purpose_bits)&mem_mask) & ((inputbits & general_purpose_bits) & mem_mask); // read general purpose input lines
- indat |= m68k->m_m68307_porta_r(space, true, (inputbits & ~general_purpose_bits)&mem_mask) & ((inputbits & ~general_purpose_bits)& mem_mask); // read dedicated input lines
+ uint8_t indat = m68k->m_porta_r(space, false, (inputbits & general_purpose_bits)&mem_mask) & ((inputbits & general_purpose_bits) & mem_mask); // read general purpose input lines
+ indat |= m68k->m_porta_r(space, true, (inputbits & ~general_purpose_bits)&mem_mask) & ((inputbits & ~general_purpose_bits)& mem_mask); // read dedicated input lines
uint8_t outdat = (m_padat & outputbits) & general_purpose_bits; // read general purpose output lines (reads latched data)
return (indat | outdat);
@@ -177,14 +191,14 @@ uint16_t m68307_sim::read_padat(m68307cpu_device* m68k, address_space &space, ui
}
-void m68307_sim::write_padat(m68307cpu_device* m68k, address_space &space, uint16_t data, uint16_t mem_mask)
+void m68307_cpu_device::m68307_sim::write_padat(m68307_cpu_device* m68k, address_space &space, uint16_t data, uint16_t mem_mask)
{
int pc = space.device().safe_pc();
COMBINE_DATA(&m_padat);
- if (!m68k->m_m68307_porta_w.isnull())
+ if (!m68k->m_porta_w.isnull())
{
- m68k->m_m68307_porta_w(space, false, data, 0xff);
+ m68k->m_porta_w(space, false, data, 0xff);
}
else
{
@@ -192,21 +206,21 @@ void m68307_sim::write_padat(m68307cpu_device* m68k, address_space &space, uint1
}
}
-void m68307_sim::write_pbcnt(uint16_t data, uint16_t mem_mask)
+void m68307_cpu_device::m68307_sim::write_pbcnt(uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_pbcnt);
}
-void m68307_sim::write_pbddr(uint16_t data, uint16_t mem_mask)
+void m68307_cpu_device::m68307_sim::write_pbddr(uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_pbddr);
}
-uint16_t m68307_sim::read_pbdat(m68307cpu_device* m68k, address_space &space, uint16_t mem_mask)
+uint16_t m68307_cpu_device::m68307_sim::read_pbdat(m68307_cpu_device* m68k, address_space &space, uint16_t mem_mask)
{
int pc = space.device().safe_pc();
- if (!m68k->m_m68307_portb_r.isnull())
+ if (!m68k->m_portb_r.isnull())
{
// for general purpose bits, if configured as 'output' then anything output gets latched
// and anything configured as input is read from the port
@@ -214,8 +228,8 @@ uint16_t m68307_sim::read_pbdat(m68307cpu_device* m68k, address_space &space, ui
uint16_t inputbits = ~m_pbddr;
uint16_t general_purpose_bits = ~m_pbcnt;
- uint16_t indat = m68k->m_m68307_portb_r(space, false, (inputbits & general_purpose_bits)&mem_mask) & ((inputbits & general_purpose_bits) & mem_mask); // read general purpose input lines
- indat |= m68k->m_m68307_portb_r(space, true, (inputbits & ~general_purpose_bits)&mem_mask) & ((inputbits & ~general_purpose_bits)& mem_mask); // read dedicated input lines
+ uint16_t indat = m68k->m_portb_r(space, false, (inputbits & general_purpose_bits)&mem_mask) & ((inputbits & general_purpose_bits) & mem_mask); // read general purpose input lines
+ indat |= m68k->m_portb_r(space, true, (inputbits & ~general_purpose_bits)&mem_mask) & ((inputbits & ~general_purpose_bits)& mem_mask); // read dedicated input lines
uint16_t outdat = (m_pbdat & outputbits) & general_purpose_bits; // read general purpose output lines (reads latched data)
return (indat | outdat);
@@ -228,14 +242,14 @@ uint16_t m68307_sim::read_pbdat(m68307cpu_device* m68k, address_space &space, ui
}
-void m68307_sim::write_pbdat(m68307cpu_device* m68k, address_space &space, uint16_t data, uint16_t mem_mask)
+void m68307_cpu_device::m68307_sim::write_pbdat(m68307_cpu_device* m68k, address_space &space, uint16_t data, uint16_t mem_mask)
{
int pc = space.device().safe_pc();
COMBINE_DATA(&m_pbdat);
- if (!m68k->m_m68307_portb_w.isnull())
+ if (!m68k->m_portb_w.isnull())
{
- m68k->m_m68307_portb_w(space, false, data, mem_mask);
+ m68k->m_portb_w(space, false, data, mem_mask);
}
else
{
@@ -243,7 +257,7 @@ void m68307_sim::write_pbdat(m68307cpu_device* m68k, address_space &space, uint1
}
}
-void m68307_sim::write_licr1(m68307cpu_device* m68k, uint16_t data, uint16_t mem_mask)
+void m68307_cpu_device::m68307_sim::write_licr1(m68307_cpu_device* m68k, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_licr1);
data = m_licr1;
@@ -259,7 +273,7 @@ void m68307_sim::write_licr1(m68307cpu_device* m68k, uint16_t data, uint16_t mem
m68k->logerror("\n");
}
-void m68307_sim::write_licr2(m68307cpu_device* m68k, uint16_t data, uint16_t mem_mask)
+void m68307_cpu_device::m68307_sim::write_licr2(m68307_cpu_device* m68k, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_licr2);
uint16_t newdata = m_licr2;
@@ -283,7 +297,7 @@ void m68307_sim::write_licr2(m68307cpu_device* m68k, uint16_t data, uint16_t mem
}
-void m68307_sim::write_picr(m68307cpu_device* m68k, uint16_t data, uint16_t mem_mask)
+void m68307_cpu_device::m68307_sim::write_picr(m68307_cpu_device* m68k, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_picr);
data = m_picr;
@@ -295,7 +309,7 @@ void m68307_sim::write_picr(m68307cpu_device* m68k, uint16_t data, uint16_t mem_
m68k->logerror("\n");
}
-void m68307_sim::write_pivr(m68307cpu_device* m68k, uint16_t data, uint16_t mem_mask)
+void m68307_cpu_device::m68307_sim::write_pivr(m68307_cpu_device* m68k, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_pivr);
data = m_pivr;
@@ -304,7 +318,7 @@ void m68307_sim::write_pivr(m68307cpu_device* m68k, uint16_t data, uint16_t mem_
m68k->logerror("high vector %01x\n", (data>>4)&0xf);
}
-void m68307_sim::reset(void)
+void m68307_cpu_device::m68307_sim::reset()
{
for (int i=0;i<4;i++)
{