diff options
author | 2022-03-27 14:23:03 -0400 | |
---|---|---|
committer | 2022-03-27 14:29:51 -0400 | |
commit | c7597225b4f0a3531d53dd806048b136956eb850 (patch) | |
tree | 3ed5b758cbd0a94a43d9c6fe9f83f402b169657d /src/devices/cpu/vt61 | |
parent | c3162e739d625d31ca207ab8b591ea87c5f1fe03 (diff) |
Debugger feature improvements
- Add 'gbt' and 'gbf' debugger commands to step until a true or false conditional branch has been detected.
- Update over 100 of the disassemblers in MAME to output a new STEP_COND flag for all conditional branches. Besides being used for execution of the new 'gbt' and 'gbf' commands, this flag also now helps the debugger 'out' command to properly handle conditional return instructions.
- Remove STEP_OVER from many instructions that aren't actually subroutine calls (e.g. DJNZ on Z80). A 'gni' debugger command (go next instruction) has been added to accommodate some of the misuse.
- Add instruction flag support to several more disassemblers that lacked them entirely (e.g. st62xx)
- Don't pass over delay slots for debugging in ASAP core
Diffstat (limited to 'src/devices/cpu/vt61')
-rw-r--r-- | src/devices/cpu/vt61/vt61dasm.cpp | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/src/devices/cpu/vt61/vt61dasm.cpp b/src/devices/cpu/vt61/vt61dasm.cpp index 7c89354b3e3..8657be1ab11 100644 --- a/src/devices/cpu/vt61/vt61dasm.cpp +++ b/src/devices/cpu/vt61/vt61dasm.cpp @@ -90,13 +90,13 @@ const char *const vt61_disassembler::s_conditions[32][2] = { { "T", "F" }, // TRUE H { "NVSR", "VSR" }, // VID SERV REQ L { "?H", "?L" }, - { "?H", "?L" }, - { "?H", "?L" }, - { "?H", "?L" }, - { "?H", "?L" }, - { "?H", "?L" }, - { "?H", "?L" }, - { "?H", "?L" } + { "?H", "?L" }, + { "?H", "?L" }, + { "?H", "?L" }, + { "?H", "?L" }, + { "?H", "?L" }, + { "?H", "?L" }, + { "?H", "?L" } }; u32 vt61_disassembler::opcode_alignment() const @@ -196,6 +196,8 @@ offs_t vt61_disassembler::disassemble(std::ostream &stream, offs_t pc, const vt6 else if (BIT(inst, 14)) { util::stream_format(stream, "JMP %s,%03o", s_conditions[(inst & 017400) >> 8][BIT(inst, 13)], inst & 000377); + if ((inst & 017400) != 013000) + flags |= STEP_COND; } else if (BIT(inst, 13)) { |