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author Olivier Galibert <galibert@pobox.com>2018-04-20 23:18:35 +0200
committer Olivier Galibert <galibert@pobox.com>2018-04-20 23:18:58 +0200
commit5fa87ba20e70b7420fee748b5f313a5f1570c421 (patch)
treef8d474259e8f1fa3a2061eb774e2f99ef18c265e /src/devices/cpu/tlcs90
parent6716ab2efb15904f41620f8176263c3af15ec609 (diff)
maps: Finish devices/cpu (nw)
Diffstat (limited to 'src/devices/cpu/tlcs90')
-rw-r--r--src/devices/cpu/tlcs90/tlcs90.cpp53
1 files changed, 29 insertions, 24 deletions
diff --git a/src/devices/cpu/tlcs90/tlcs90.cpp b/src/devices/cpu/tlcs90/tlcs90.cpp
index 1e109c0048e..817716e9806 100644
--- a/src/devices/cpu/tlcs90/tlcs90.cpp
+++ b/src/devices/cpu/tlcs90/tlcs90.cpp
@@ -41,35 +41,40 @@ enum e_ir
};
-ADDRESS_MAP_START(tlcs90_device::tmp90840_mem)
- AM_RANGE( 0x0000, 0x1fff ) AM_ROM // 8KB ROM (internal)
- AM_RANGE( 0xfec0, 0xffbf ) AM_RAM // 256b RAM (internal)
- AM_RANGE( T90_IOBASE, T90_IOBASE+47 ) AM_READWRITE( t90_internal_registers_r, t90_internal_registers_w )
-ADDRESS_MAP_END
+void tlcs90_device::tmp90840_mem(address_map &map)
+{
+ map(0x0000, 0x1fff).rom(); // 8KB ROM (internal)
+ map(0xfec0, 0xffbf).ram(); // 256b RAM (internal)
+ map(T90_IOBASE, T90_IOBASE+47).rw(this, FUNC(tlcs90_device::t90_internal_registers_r), FUNC(tlcs90_device::t90_internal_registers_w));
+}
-ADDRESS_MAP_START(tlcs90_device::tmp90841_mem)
+void tlcs90_device::tmp90841_mem(address_map &map)
+{
// AM_RANGE( 0x0000, 0x1fff ) AM_ROM // rom-less
- AM_RANGE( 0xfec0, 0xffbf ) AM_RAM // 256b RAM (internal)
- AM_RANGE( T90_IOBASE, T90_IOBASE+47 ) AM_READWRITE( t90_internal_registers_r, t90_internal_registers_w )
-ADDRESS_MAP_END
+ map(0xfec0, 0xffbf).ram(); // 256b RAM (internal)
+ map(T90_IOBASE, T90_IOBASE+47).rw(this, FUNC(tlcs90_device::t90_internal_registers_r), FUNC(tlcs90_device::t90_internal_registers_w));
+}
-ADDRESS_MAP_START(tlcs90_device::tmp91640_mem)
- AM_RANGE( 0x0000, 0x3fff ) AM_ROM // 16KB ROM (internal)
- AM_RANGE( 0xfdc0, 0xffbf ) AM_RAM // 512b RAM (internal)
- AM_RANGE( T90_IOBASE, T90_IOBASE+47 ) AM_READWRITE( t90_internal_registers_r, t90_internal_registers_w )
-ADDRESS_MAP_END
+void tlcs90_device::tmp91640_mem(address_map &map)
+{
+ map(0x0000, 0x3fff).rom(); // 16KB ROM (internal)
+ map(0xfdc0, 0xffbf).ram(); // 512b RAM (internal)
+ map(T90_IOBASE, T90_IOBASE+47).rw(this, FUNC(tlcs90_device::t90_internal_registers_r), FUNC(tlcs90_device::t90_internal_registers_w));
+}
-ADDRESS_MAP_START(tlcs90_device::tmp91641_mem)
+void tlcs90_device::tmp91641_mem(address_map &map)
+{
// AM_RANGE( 0x0000, 0x3fff ) AM_ROM // rom-less
- AM_RANGE( 0xfdc0, 0xffbf ) AM_RAM // 512b RAM (internal)
- AM_RANGE( T90_IOBASE, T90_IOBASE+47 ) AM_READWRITE( t90_internal_registers_r, t90_internal_registers_w )
-ADDRESS_MAP_END
-
-ADDRESS_MAP_START(tlcs90_device::tmp90ph44_mem)
- AM_RANGE( 0x0000, 0x3fff ) AM_ROM // 16KB PROM (internal)
- AM_RANGE( 0xfdc0, 0xffbf ) AM_RAM // 512b RAM (internal)
- AM_RANGE( T90_IOBASE, T90_IOBASE+55 ) AM_READWRITE( t90_internal_registers_r, t90_internal_registers_w ) // TODO: has 8 more registers
-ADDRESS_MAP_END
+ map(0xfdc0, 0xffbf).ram(); // 512b RAM (internal)
+ map(T90_IOBASE, T90_IOBASE+47).rw(this, FUNC(tlcs90_device::t90_internal_registers_r), FUNC(tlcs90_device::t90_internal_registers_w));
+}
+
+void tlcs90_device::tmp90ph44_mem(address_map &map)
+{
+ map(0x0000, 0x3fff).rom(); // 16KB PROM (internal)
+ map(0xfdc0, 0xffbf).ram(); // 512b RAM (internal)
+ map(T90_IOBASE, T90_IOBASE+55).rw(this, FUNC(tlcs90_device::t90_internal_registers_r), FUNC(tlcs90_device::t90_internal_registers_w)); // TODO: has 8 more registers
+}
tlcs90_device::tlcs90_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, address_map_constructor program_map)