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author Vas Crabb <vas@vastheman.com>2025-04-27 02:42:17 +1000
committer Vas Crabb <vas@vastheman.com>2025-04-27 02:42:17 +1000
commitcfc4dde4e9f4a0a36c233dfaec4145d3ddad1364 (patch)
tree362289a97ad6c08f76c6cd16ae2c61d94ddca1eb /src/devices/cpu/sh
parent1ae7456ff639bee447cefda421b84c19a37bd63d (diff)
srcclean in preparation for release.
Diffstat (limited to 'src/devices/cpu/sh')
-rw-r--r--src/devices/cpu/sh/sh3comn.cpp2
-rw-r--r--src/devices/cpu/sh/sh4comn.cpp34
2 files changed, 18 insertions, 18 deletions
diff --git a/src/devices/cpu/sh/sh3comn.cpp b/src/devices/cpu/sh/sh3comn.cpp
index 8b0f149cf6d..7829097750b 100644
--- a/src/devices/cpu/sh/sh3comn.cpp
+++ b/src/devices/cpu/sh/sh3comn.cpp
@@ -880,7 +880,7 @@ void sh3_base_device::irr0_w(offs_t offset, uint8_t data, uint8_t mem_mask)
{
COMBINE_DATA(&m_irr0);
logerror("'%s' (%08x): INTC unmapped internal write %02x & %02x (IRR0)\n", tag(), m_sh2_state->pc, data, mem_mask);
- // not sure if this is how we should clear lines in this core...
+ // not sure if this is how we should clear lines in this core...
if (!(data & 0x01)) execute_set_input(0, CLEAR_LINE);
if (!(data & 0x02)) execute_set_input(1, CLEAR_LINE);
if (!(data & 0x04)) execute_set_input(2, CLEAR_LINE);
diff --git a/src/devices/cpu/sh/sh4comn.cpp b/src/devices/cpu/sh/sh4comn.cpp
index 6f2831585a2..313230b70a6 100644
--- a/src/devices/cpu/sh/sh4comn.cpp
+++ b/src/devices/cpu/sh/sh4comn.cpp
@@ -636,12 +636,12 @@ void sh4_base_device::pteh_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
// for use with LDTLB opcode
/*
- NNNN NNNN NNNN NNNN NNNN NN-- AAAA AAAA
+ NNNN NNNN NNNN NNNN NNNN NN-- AAAA AAAA
- N = VPM = Virtual Page Number
- A = ASID = Address Space Identifier
+ N = VPM = Virtual Page Number
+ A = ASID = Address Space Identifier
- same as the address table part of the utlb but with 2 unused bits (these are sourced from PTEL instead when LDTLB is called)
+ same as the address table part of the utlb but with 2 unused bits (these are sourced from PTEL instead when LDTLB is called)
*/
COMBINE_DATA(&m_pteh);
}
@@ -654,9 +654,9 @@ uint32_t sh4_base_device::ptel_r(offs_t offset, uint32_t mem_mask)
void sh4_base_device::ptel_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
/*
- ---P PPPP PPPP PPPP PPPP PP-V zRRz CDHW
+ ---P PPPP PPPP PPPP PPPP PP-V zRRz CDHW
- same format as data array 1 of the utlb
+ same format as data array 1 of the utlb
*/
COMBINE_DATA(&m_ptel);
}
@@ -692,15 +692,15 @@ void sh4_base_device::mmucr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
// MMU Control
/*
- LLLL LL-- BBBB BB-- CCCC CCQV ---- -T-A
-
- L = LRUI = Least recently used ITLB
- B = URB = UTLB replace boundary
- C = URC = UTLB replace counter
- Q = SQMD = Store Queue Mode Bit
- V = SV = Single Virtual Mode Bit
- T = TI = TLB invalidate
- A = AT = Address translation bit (enable)
+ LLLL LL-- BBBB BB-- CCCC CCQV ---- -T-A
+
+ L = LRUI = Least recently used ITLB
+ B = URB = UTLB replace boundary
+ C = URC = UTLB replace counter
+ Q = SQMD = Store Queue Mode Bit
+ V = SV = Single Virtual Mode Bit
+ T = TI = TLB invalidate
+ A = AT = Address translation bit (enable)
*/
COMBINE_DATA(&m_mmucr);
// MMUCR_AT
@@ -823,9 +823,9 @@ uint32_t sh4_base_device::ptea_r(offs_t offset, uint32_t mem_mask)
void sh4_base_device::ptea_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
/*
- ---- ---- ---- ---- ---- ---- ---- TSSS
+ ---- ---- ---- ---- ---- ---- ---- TSSS
- same format as data array 2 of the utlb
+ same format as data array 2 of the utlb
*/
COMBINE_DATA(&m_ptea);
}