diff options
| author | 2025-04-11 15:21:07 +0200 | |
|---|---|---|
| committer | 2025-04-11 15:21:15 +0200 | |
| commit | 74877969c18275966e6f72ee5690f1768b03c958 (patch) | |
| tree | bcdfadb5fa1d2b373d4a269fd16e0d6ec20cdd8e /src/devices/cpu/sh | |
| parent | 14644cb8459e8e695334d17b2cfcfcda63342bac (diff) | |
misc cpu: no need to check debug enabled flag manually
Diffstat (limited to 'src/devices/cpu/sh')
| -rw-r--r-- | src/devices/cpu/sh/sh.cpp | 2 | ||||
| -rw-r--r-- | src/devices/cpu/sh/sh2.cpp | 2 | ||||
| -rw-r--r-- | src/devices/cpu/sh/sh4.cpp | 10 | ||||
| -rw-r--r-- | src/devices/cpu/sh/sh4comn.cpp | 2 |
4 files changed, 8 insertions, 8 deletions
diff --git a/src/devices/cpu/sh/sh.cpp b/src/devices/cpu/sh/sh.cpp index f6478f289e4..08054e047fe 100644 --- a/src/devices/cpu/sh/sh.cpp +++ b/src/devices/cpu/sh/sh.cpp @@ -2502,7 +2502,7 @@ void sh_common_execution::generate_sequence_instruction(drcuml_block &block, com } /* if we are debugging, call the debugger */ - if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0) + if (debugger_enabled()) { UML_MOV(block, mem(&m_sh2_state->pc), desc->pc); // mov [pc],desc->pc save_fast_iregs(block); diff --git a/src/devices/cpu/sh/sh2.cpp b/src/devices/cpu/sh/sh2.cpp index 72c6ebcbfad..ae8acd76ee4 100644 --- a/src/devices/cpu/sh/sh2.cpp +++ b/src/devices/cpu/sh/sh2.cpp @@ -691,7 +691,7 @@ void sh2_device::static_generate_memory_accessor(int size, int iswrite, const ch UML_LABEL(block, label++); // label: - if ((machine().debug_flags & DEBUG_FLAG_ENABLED) == 0) + if (!debugger_enabled()) { for (auto & elem : m_fastram) { diff --git a/src/devices/cpu/sh/sh4.cpp b/src/devices/cpu/sh/sh4.cpp index 926e4843787..0e83680dc64 100644 --- a/src/devices/cpu/sh/sh4.cpp +++ b/src/devices/cpu/sh/sh4.cpp @@ -452,7 +452,7 @@ inline void sh34_base_device::LDCSR(const uint16_t opcode) // important to store the value now so that it doesn't get affected by the bank change uint32_t reg = m_sh2_state->r[REG_N]; - if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0) + if (debugger_enabled()) sh4_syncronize_register_bank((m_sh2_state->sr & sRB) >> 29); if ((m_sh2_state->r[REG_N] & sRB) != (m_sh2_state->sr & sRB)) @@ -468,7 +468,7 @@ inline void sh34_base_device::LDCMSR(const uint16_t opcode) uint32_t old = m_sh2_state->sr; m_sh2_state->ea = m_sh2_state->r[REG_N]; m_sh2_state->sr = read_long(m_sh2_state->ea) & SH34_FLAGS; - if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0) + if (debugger_enabled()) sh4_syncronize_register_bank((old & sRB) >> 29); if ((old & sRB) != (m_sh2_state->sr & sRB)) sh4_change_register_bank(m_sh2_state->sr & sRB ? 1 : 0); @@ -482,7 +482,7 @@ inline void sh34_base_device::RTE() { m_sh2_state->m_delay = m_sh2_state->ea = m_sh2_state->m_spc; - if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0) + if (debugger_enabled()) sh4_syncronize_register_bank((m_sh2_state->sr & sRB) >> 29); if ((m_sh2_state->m_ssr & sRB) != (m_sh2_state->sr & sRB)) sh4_change_register_bank(m_sh2_state->m_ssr & sRB ? 1 : 0); @@ -512,7 +512,7 @@ inline void sh34_base_device::TRAPA(uint32_t i) m_sh2_state->m_sgr = m_sh2_state->r[15]; m_sh2_state->sr |= MD; - if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0) + if (debugger_enabled()) sh4_syncronize_register_bank((m_sh2_state->sr & sRB) >> 29); if (!(m_sh2_state->sr & sRB)) sh4_change_register_bank(1); @@ -2814,7 +2814,7 @@ void sh34_base_device::static_generate_memory_accessor(int size, int iswrite, co UML_LABEL(block, label++); // label: - if ((machine().debug_flags & DEBUG_FLAG_ENABLED) == 0) + if (!debugger_enabled()) { for (auto & elem : m_fastram) { diff --git a/src/devices/cpu/sh/sh4comn.cpp b/src/devices/cpu/sh/sh4comn.cpp index b8c59aa7ee5..aa424099012 100644 --- a/src/devices/cpu/sh/sh4comn.cpp +++ b/src/devices/cpu/sh/sh4comn.cpp @@ -363,7 +363,7 @@ void sh34_base_device::sh4_exception_process(int exception, uint32_t vector) //printf("stored m_spc %08x m_ssr %08x m_sgr %08x\n", m_spc, m_ssr, m_sgr); m_sh2_state->sr |= MD; - if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0) + if (debugger_enabled()) sh4_syncronize_register_bank((m_sh2_state->sr & sRB) >> 29); if (!(m_sh2_state->sr & sRB)) sh4_change_register_bank(1); |
