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author Vas Crabb <vas@vastheman.com>2026-03-05 03:43:49 +1100
committer Vas Crabb <vas@vastheman.com>2026-03-05 03:43:49 +1100
commit3c6ffd84b0ae8c7138ea7199ebc8d74e77be0f3e (patch)
tree01c4e52cbea7c7f4e160176ea4069e79d8988ce2 /src/devices/cpu/sh
parentd18fa74d69d49353f4e6dd3fd0afd9dd6591a30d (diff)
-cpu/e132xs: Log analysed instructions in UML log when using recompiler.
-cpu/powerpc: Modernised recompiler front-end code, improved instruction analysis logging. -cpu/sh: Cleaned up instruction analysis logging a little -util/client_ws.hpp, util/server_ws_impl.hpp, capcom/cps2comm.cpp: Updated some use of deprecation ASIO APIs. -nakajima/nakajies.cpp: Use range-based loops.
Diffstat (limited to 'src/devices/cpu/sh')
-rw-r--r--src/devices/cpu/sh/sh.cpp86
-rw-r--r--src/devices/cpu/sh/sh.h1
-rw-r--r--src/devices/cpu/sh/sh_fe.cpp50
-rw-r--r--src/devices/cpu/sh/sh_fe.h5
4 files changed, 75 insertions, 67 deletions
diff --git a/src/devices/cpu/sh/sh.cpp b/src/devices/cpu/sh/sh.cpp
index c507410d759..72945b2e364 100644
--- a/src/devices/cpu/sh/sh.cpp
+++ b/src/devices/cpu/sh/sh.cpp
@@ -11,6 +11,10 @@
#include "emuopts.h"
+#include "util/vecstream.h"
+
+#include <locale>
+
sh_common_execution::sh_common_execution(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, endianness_t endianness, address_map_constructor internal)
: cpu_device(mconfig, type, tag, owner, clock)
@@ -2029,59 +2033,6 @@ void sh_common_execution::save_fast_iregs(drcuml_block &block)
/*-------------------------------------------------
- log_desc_flags_to_string - generate a string
- representing the instruction description
- flags
--------------------------------------------------*/
-
-const char *sh_common_execution::log_desc_flags_to_string(const opcode_desc &desc)
-{
- static char tempbuf[30];
- char *dest = tempbuf;
-
- /* branches */
- if (desc.is_unconditional_branch())
- *dest++ = 'U';
- else if (desc.is_conditional_branch())
- *dest++ = 'C';
- else
- *dest++ = '.';
-
- /* intrablock branches */
- *dest++ = desc.intrablock_branch() ? 'i' : '.';
-
- /* branch targets */
- *dest++ = desc.is_branch_target() ? 'B' : '.';
-
- /* delay slots */
- *dest++ = desc.in_delay_slot() ? 'D' : '.';
-
- /* exceptions */
- if (desc.will_cause_exception())
- *dest++ = 'E';
- else if (desc.can_cause_exception())
- *dest++ = 'e';
- else
- *dest++ = '.';
-
- /* read/write */
- if (desc.reads_memory())
- *dest++ = 'R';
- else if (desc.writes_memory())
- *dest++ = 'W';
- else
- *dest++ = '.';
-
- /* TLB validation */
- *dest++ = desc.validate_tlb() ? 'V' : '.';
-
- /* redispatch */
- *dest++ = desc.redispatch() ? 'R' : '.';
- return tempbuf;
-}
-
-
-/*-------------------------------------------------
log_register_list - log a list of GPR registers
-------------------------------------------------*/
@@ -2156,6 +2107,10 @@ void sh_common_execution::log_register_list(const char *string, const std::bitse
void sh_common_execution::log_opcode_desc(const opcode_desc *desclist, int indent)
{
+ sh_disassembler sh2d(false);
+ util::ovectorstream buffer;
+ buffer.imbue(std::locale::classic());
+
/* open the file, creating it if necessary */
if (indent == 0)
m_drcuml->log_printf("\nDescriptor list @ %08X\n", desclist->pc);
@@ -2163,22 +2118,21 @@ void sh_common_execution::log_opcode_desc(const opcode_desc *desclist, int inden
/* output each descriptor */
for ( ; desclist != nullptr; desclist = desclist->next())
{
- std::ostringstream stream;
+ buffer.clear();
+ buffer.seekp(0);
+ desclist->log_flags(buffer);
+ buffer.put('\0');
+ m_drcuml->log_printf("%08X [%08X] t:%08X f:%s: ", desclist->pc, desclist->physpc, desclist->targetpc, &buffer.vec()[0]);
/* disassemle the current instruction and output it to the log */
- if (m_drcuml->logging() || m_drcuml->logging_native())
- {
- if (desclist->virtual_noop())
- stream << "<virtual nop>";
- else
- {
- sh_disassembler sh2d(false);
- sh2d.dasm_one(stream, desclist->pc, desclist->opptr);
- }
- }
+ buffer.clear();
+ buffer.seekp(0);
+ if (desclist->virtual_noop())
+ buffer << "<virtual nop>";
else
- stream << "???";
- m_drcuml->log_printf("%08X [%08X] t:%08X f:%s: %-30s", desclist->pc, desclist->physpc, desclist->targetpc, log_desc_flags_to_string(*desclist), stream.str());
+ sh2d.dasm_one(buffer, desclist->pc, desclist->opptr);
+ buffer.put('\0');
+ m_drcuml->log_printf("%-36s", &buffer.vec()[0]);
/* output register states */
log_register_list("use", desclist->regin, nullptr);
diff --git a/src/devices/cpu/sh/sh.h b/src/devices/cpu/sh/sh.h
index 3d726db11bd..c06fbeddf10 100644
--- a/src/devices/cpu/sh/sh.h
+++ b/src/devices/cpu/sh/sh.h
@@ -443,7 +443,6 @@ public:
void alloc_handle(uml::code_handle *&handleptr, const char *name);
void load_fast_iregs(drcuml_block &block);
void save_fast_iregs(drcuml_block &block);
- const char *log_desc_flags_to_string(const opcode_desc &flags);
void log_register_list(const char *string, const std::bitset<32> &reglist, const std::bitset<32> *regnostarlist);
void log_opcode_desc(const opcode_desc *desclist, int indent);
void log_add_disasm_comment(drcuml_block &block, uint32_t pc, uint32_t op);
diff --git a/src/devices/cpu/sh/sh_fe.cpp b/src/devices/cpu/sh/sh_fe.cpp
index f62ecf110fb..0716231aef7 100644
--- a/src/devices/cpu/sh/sh_fe.cpp
+++ b/src/devices/cpu/sh/sh_fe.cpp
@@ -14,6 +14,56 @@
#include "cpu/drcfe.ipp"
+
+/*-------------------------------------------------
+ log_flags - log the instruction description to
+ a stream
+-------------------------------------------------*/
+
+void sh_common_execution::opcode_desc::log_flags(std::ostream &stream) const
+{
+ // branches
+ if (is_unconditional_branch())
+ stream << 'U';
+ else if (is_conditional_branch())
+ stream << 'C';
+ else
+ stream << '.';
+
+ // intrablock branches
+ stream << (intrablock_branch() ? 'i' : '.');
+
+ // branch targets
+ stream << (is_branch_target() ? 'B' : '.');
+
+ // delay slots
+ stream << (in_delay_slot() ? 'D' : '.');
+
+ // exceptions
+ if (will_cause_exception())
+ stream << 'E';
+ else if (can_cause_exception())
+ stream << 'e';
+ else
+ stream << '.';
+
+ // read/write
+ if (reads_memory())
+ stream << (writes_memory() ? '+' : 'R');
+ else if (writes_memory())
+ stream << 'W';
+ else
+ stream << '.';
+
+ // TLB validation
+ stream << (validate_tlb() ? 'V' : '.');
+
+ // redispatch
+ stream << (redispatch() ? 'R' : '.');
+}
+
+
+
/***************************************************************************
INSTRUCTION PARSERS
***************************************************************************/
diff --git a/src/devices/cpu/sh/sh_fe.h b/src/devices/cpu/sh/sh_fe.h
index 26439f8af8d..ba63138e3eb 100644
--- a/src/devices/cpu/sh/sh_fe.h
+++ b/src/devices/cpu/sh/sh_fe.h
@@ -16,6 +16,9 @@
#include "cpu/drcfe.h"
+#include <cassert>
+#include <iosfwd>
+
class sh_common_execution::opcode_desc : public opcode_desc_base<opcode_desc, 32>
{
@@ -83,6 +86,8 @@ public:
m_can_expose_external_int = false;
}
+ void log_flags(std::ostream &stream) const;
+
private:
bool m_reads_memory;
bool m_writes_memory;