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author Vas Crabb <cuavas@users.noreply.github.com>2026-01-04 14:18:18 +1100
committer GitHub <noreply@github.com>2026-01-04 14:18:18 +1100
commit2209d46c9477c638eba937516b63dd71a01328db (patch)
tree8fbfa21bd53c4f1f334c3a5b0c3d2bfeace2e401 /src/devices/cpu/sh
parent5784c8ac521970b432c05385cc829e17358467be (diff)
cpu/drccache.cpp: Defer allocating to start, allow forcing W^X mode. (#14760)
cpu/drccache.cpp: Added helpers for allocating structures/objects in the cache. cpu/drccache.cpp: Supply desired alignment when allocating cache memory (not fully implemented). cpu/drccache.cpp: Log some statistics on destruction. emu/emuopts.cpp: Added -[no]drc_rwx option to allow forcing W^X mode when writable executable pages are permitted. cpu/mips, cpu/powerpc: Allow DRC cache size to be set externally at configuration time, so systems can override the default. cpu/dspp, cpu/e132xs, cpu/unsp: Don't allocate DRC resources if recompiler is disabled.
Diffstat (limited to 'src/devices/cpu/sh')
-rw-r--r--src/devices/cpu/sh/sh.cpp27
-rw-r--r--src/devices/cpu/sh/sh.h20
2 files changed, 28 insertions, 19 deletions
diff --git a/src/devices/cpu/sh/sh.cpp b/src/devices/cpu/sh/sh.cpp
index 08054e047fe..4c1d987f639 100644
--- a/src/devices/cpu/sh/sh.cpp
+++ b/src/devices/cpu/sh/sh.cpp
@@ -3,13 +3,38 @@
#include "emu.h"
#include "sh.h"
+
#include "sh_dasm.h"
+
#include "cpu/drcumlsh.h"
+#include "emuopts.h"
+
+
+sh_common_execution::sh_common_execution(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, endianness_t endianness, address_map_constructor internal)
+ : cpu_device(mconfig, type, tag, owner, clock)
+ , m_sh2_state(nullptr)
+ , m_cache(CACHE_SIZE + sizeof(internal_sh2_state))
+ , m_drcuml(nullptr)
+ , m_drcoptions(0)
+ , m_entry(nullptr)
+ , m_read8(nullptr)
+ , m_write8(nullptr)
+ , m_read16(nullptr)
+ , m_write16(nullptr)
+ , m_read32(nullptr)
+ , m_write32(nullptr)
+ , m_interrupt(nullptr)
+ , m_nocode(nullptr)
+ , m_out_of_cycles(nullptr)
+{
+}
+
void sh_common_execution::device_start()
{
/* allocate the implementation-specific state from the full cache */
- m_sh2_state = (internal_sh2_state *)m_cache.alloc_near(sizeof(internal_sh2_state));
+ m_cache.allocate_cache(mconfig().options().drc_rwx());
+ m_sh2_state = m_cache.alloc_near<internal_sh2_state>();
save_item(NAME(m_sh2_state->pc));
save_item(NAME(m_sh2_state->sr));
diff --git a/src/devices/cpu/sh/sh.h b/src/devices/cpu/sh/sh.h
index 9980fa87709..44023ac096e 100644
--- a/src/devices/cpu/sh/sh.h
+++ b/src/devices/cpu/sh/sh.h
@@ -101,24 +101,6 @@ class sh_common_execution : public cpu_device
{
public:
- sh_common_execution(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, endianness_t endianness, address_map_constructor internal)
- : cpu_device(mconfig, type, tag, owner, clock)
- , m_sh2_state(nullptr)
- , m_cache(CACHE_SIZE + sizeof(internal_sh2_state))
- , m_drcuml(nullptr)
- , m_drcoptions(0)
- , m_entry(nullptr)
- , m_read8(nullptr)
- , m_write8(nullptr)
- , m_read16(nullptr)
- , m_write16(nullptr)
- , m_read32(nullptr)
- , m_write32(nullptr)
- , m_interrupt(nullptr)
- , m_nocode(nullptr)
- , m_out_of_cycles(nullptr)
- { }
-
// Data that needs to be stored close to the generated DRC code
struct internal_sh2_state
{
@@ -204,6 +186,8 @@ protected:
EXECUTE_RESET_CACHE = 3
};
+ sh_common_execution(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, endianness_t endianness, address_map_constructor internal);
+
void ADD(uint32_t m, uint32_t n);
void ADDI(uint32_t i, uint32_t n);
void ADDC(uint32_t m, uint32_t n);