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author smf- <smf-@users.noreply.github.com>2025-04-17 18:29:05 +0100
committer smf- <smf-@users.noreply.github.com>2025-04-17 18:29:29 +0100
commitb26662f1bba6809df145d9e8b3f78f66e3a7c7db (patch)
tree9a4aed26e67a71e18b63a9465cc5cf2afb797bf8 /src/devices/cpu/sh/sh4dmac.h
parent7fc77f3f4c3d4ba696bf384b4ee2cd44010854c6 (diff)
Implemented specific SH3/SH4 chips & pass the required endian into the constructor, SH4 internal registers now work when using big endian. The debugger is now aware that the SH3/SH4 has an MMU. [smf]
Diffstat (limited to 'src/devices/cpu/sh/sh4dmac.h')
-rw-r--r--src/devices/cpu/sh/sh4dmac.h35
1 files changed, 0 insertions, 35 deletions
diff --git a/src/devices/cpu/sh/sh4dmac.h b/src/devices/cpu/sh/sh4dmac.h
index b7918fac997..a3ad1d0b5dc 100644
--- a/src/devices/cpu/sh/sh4dmac.h
+++ b/src/devices/cpu/sh/sh4dmac.h
@@ -26,38 +26,3 @@
#define DMAOR_AE 0x0004
#define DMAOR_NMIF 0x0002
#define DMAOR_DME 0x0001
-
-void sh4_handle_sar0_addr_w(uint32_t data, uint32_t mem_mask);
-void sh4_handle_sar1_addr_w(uint32_t data, uint32_t mem_mask);
-void sh4_handle_sar2_addr_w(uint32_t data, uint32_t mem_mask);
-void sh4_handle_sar3_addr_w(uint32_t data, uint32_t mem_mask);
-void sh4_handle_dar0_addr_w(uint32_t data, uint32_t mem_mask);
-void sh4_handle_dar1_addr_w(uint32_t data, uint32_t mem_mask);
-void sh4_handle_dar2_addr_w(uint32_t data, uint32_t mem_mask);
-void sh4_handle_dar3_addr_w(uint32_t data, uint32_t mem_mask);
-void sh4_handle_dmatcr0_addr_w(uint32_t data, uint32_t mem_mask);
-void sh4_handle_dmatcr1_addr_w(uint32_t data, uint32_t mem_mask);
-void sh4_handle_dmatcr2_addr_w(uint32_t data, uint32_t mem_mask);
-void sh4_handle_dmatcr3_addr_w(uint32_t data, uint32_t mem_mask);
-void sh4_handle_chcr0_addr_w(uint32_t data, uint32_t mem_mask);
-void sh4_handle_chcr1_addr_w(uint32_t data, uint32_t mem_mask);
-void sh4_handle_chcr2_addr_w(uint32_t data, uint32_t mem_mask);
-void sh4_handle_chcr3_addr_w(uint32_t data, uint32_t mem_mask);
-void sh4_handle_dmaor_addr_w(uint32_t data, uint32_t mem_mask);
-uint32_t sh4_handle_sar0_addr_r(uint32_t mem_mask);
-uint32_t sh4_handle_sar1_addr_r(uint32_t mem_mask);
-uint32_t sh4_handle_sar2_addr_r(uint32_t mem_mask);
-uint32_t sh4_handle_sar3_addr_r(uint32_t mem_mask);
-uint32_t sh4_handle_dar0_addr_r(uint32_t mem_mask);
-uint32_t sh4_handle_dar1_addr_r(uint32_t mem_mask);
-uint32_t sh4_handle_dar2_addr_r(uint32_t mem_mask);
-uint32_t sh4_handle_dar3_addr_r(uint32_t mem_mask);
-uint32_t sh4_handle_dmatcr0_addr_r(uint32_t mem_mask);
-uint32_t sh4_handle_dmatcr1_addr_r(uint32_t mem_mask);
-uint32_t sh4_handle_dmatcr2_addr_r(uint32_t mem_mask);
-uint32_t sh4_handle_dmatcr3_addr_r(uint32_t mem_mask);
-uint32_t sh4_handle_chcr0_addr_r(uint32_t mem_mask);
-uint32_t sh4_handle_chcr1_addr_r(uint32_t mem_mask);
-uint32_t sh4_handle_chcr2_addr_r(uint32_t mem_mask);
-uint32_t sh4_handle_chcr3_addr_r(uint32_t mem_mask);
-uint32_t sh4_handle_dmaor_addr_r(uint32_t mem_mask);