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author Miodrag Milanovic <mmicko@gmail.com>2015-09-13 08:41:44 +0200
committer Miodrag Milanovic <mmicko@gmail.com>2015-09-13 08:41:44 +0200
commitf88cefad27a1737c76e09d99c9fb43e173506081 (patch)
tree2d8167d03579c46e226471747eb4407bd00ed6fa /src/devices/cpu/g65816
parente92ac9e0fa8e99869894bea00589bbb526be30aa (diff)
Move all devices into separate part of src tree (nw)
Diffstat (limited to 'src/devices/cpu/g65816')
-rw-r--r--src/devices/cpu/g65816/g65816.c1136
-rw-r--r--src/devices/cpu/g65816/g65816.h1570
-rw-r--r--src/devices/cpu/g65816/g65816cm.h262
-rw-r--r--src/devices/cpu/g65816/g65816ds.c349
-rw-r--r--src/devices/cpu/g65816/g65816ds.h22
-rw-r--r--src/devices/cpu/g65816/g65816o0.c8
-rw-r--r--src/devices/cpu/g65816/g65816o1.c8
-rw-r--r--src/devices/cpu/g65816/g65816o2.c8
-rw-r--r--src/devices/cpu/g65816/g65816o3.c8
-rw-r--r--src/devices/cpu/g65816/g65816o4.c8
-rw-r--r--src/devices/cpu/g65816/g65816op.h1961
11 files changed, 5340 insertions, 0 deletions
diff --git a/src/devices/cpu/g65816/g65816.c b/src/devices/cpu/g65816/g65816.c
new file mode 100644
index 00000000000..03e7320eb89
--- /dev/null
+++ b/src/devices/cpu/g65816/g65816.c
@@ -0,0 +1,1136 @@
+// license:BSD-3-Clause
+// copyright-holders:Karl Stenerud
+/* ======================================================================== */
+/* =============================== COPYRIGHT ============================== */
+/* ======================================================================== */
+/*
+
+G65C816 CPU Emulator V1.00
+
+Copyright Karl Stenerud
+All rights reserved.
+
+*/
+/* ======================================================================== */
+/* ================================= NOTES ================================ */
+/* ======================================================================== */
+/*
+
+Changes:
+ 1.01 (2010-04-04):
+ Angelo Salese
+ - Added boundary checks for MVP and MVN in M mode.
+
+ 1.00 (2008-11-27):
+ R. Belmont
+ - Reworked for modern MAME
+
+ 0.94 (2007-06-14):
+ Zsolt Vasvari
+ - Removed unnecessary checks from MVP and MVN
+
+ 0.93 (2003-07-05):
+ Angelo Salese
+ - Fixed the BCD conversion when using the Decimal Flag in ADC and SBC.
+ - Removed the two conversion tables for ADC and SBC as they aren't
+ needed anymore.
+
+ 0.92 (2000-05-28):
+ Lee Hammerton <lee-hammerton@hammerhead.ltd.uk>
+ - Fixed debugger bug that caused D to be misrepresented.
+ - Fixed MVN and MVP (they were reversed)
+
+ 0.91 (2000-05-22):
+ Lee Hammerton <lee-hammerton@hammerhead.ltd.uk>
+ - Fixed reset vector fetch to be little endian
+ - Fixed disassembler call bug
+ - Fixed C flag in SBC (should be inverted before operation)
+ - Fixed JSR to stack PC-1 and RTS to pull PC and add 1
+
+ Karl Stenerud <karl@higashiyama-unet.ocn.ne.jp>
+ - Added correct timing for absolute indexed operations
+ - SBC: fixed corruption of interim values
+
+ 0.90 (2000-05-17):
+ Karl Stenerud <karl@higashiyama-unet.ocn.ne.jp>
+ - first public release
+
+
+Note on timings:
+ - For instructions that write to memory (ASL, ASR, LSL, ROL, ROR, DEC,
+ INC, STA, STZ), the absolute indexed addressing mode takes 1 extra
+ cycle to complete.
+ - The spec says fc (JMP axi) is 6 cyles, but elsewhere says 8 cycles
+ (which is what it should be)
+
+
+TODO general:
+ - WAI will not stop if RDY is held high.
+
+ - RDY internally held low when WAI executed and returned to hi when RES,
+ ABORT, NMI, or IRQ asserted.
+
+ - ABORT will terminate WAI instruction but wil not restart the processor
+
+ - If interrupt occurs after ABORT of WAI, processor returns to WAI
+ instruction.
+
+ - Add one cycle when indexing across page boundary and E=1 except for STA
+ and STZ instructions.
+
+ - Add 1 cycle if branch is taken. In Emulation (E= 1 ) mode only --add 1
+ cycle if the branch is taken and crosses a page boundary.
+
+ - Add 1 cycle in Emulation mode (E=1) for (dir),y; abs,x; and abs,y
+ addressing modes.
+
+*/
+/* ======================================================================== */
+/* ================================= DATA ================================= */
+/* ======================================================================== */
+
+#include "emu.h"
+#include "g65816.h"
+
+
+const device_type G65816 = &device_creator<g65816_device>;
+const device_type _5A22 = &device_creator<_5a22_device>;
+
+
+g65816_device::g65816_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
+ : cpu_device(mconfig, G65816, "G65C816", tag, owner, clock, "g65c816", __FILE__)
+ , m_program_config("program", ENDIANNESS_LITTLE, 8, 24, 0)
+ , m_cpu_type(CPU_TYPE_G65816)
+{
+}
+
+
+g65816_device::g65816_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source, int cpu_type, address_map_constructor internal)
+ : cpu_device(mconfig, type, name, tag, owner, clock, shortname, source)
+ , m_program_config("program", ENDIANNESS_LITTLE, 8, 24, 0, internal)
+ , m_cpu_type(cpu_type)
+{
+}
+
+
+static ADDRESS_MAP_START(_5a22_map, AS_PROGRAM, 8, _5a22_device)
+ AM_RANGE(0x4202, 0x4202) AM_MIRROR(0xbf0000) AM_WRITE(wrmpya_w)
+ AM_RANGE(0x4203, 0x4203) AM_MIRROR(0xbf0000) AM_WRITE(wrmpyb_w)
+ AM_RANGE(0x4204, 0x4204) AM_MIRROR(0xbf0000) AM_WRITE(wrdivl_w)
+ AM_RANGE(0x4205, 0x4205) AM_MIRROR(0xbf0000) AM_WRITE(wrdivh_w)
+ AM_RANGE(0x4206, 0x4206) AM_MIRROR(0xbf0000) AM_WRITE(wrdvdd_w)
+
+ AM_RANGE(0x420d, 0x420d) AM_MIRROR(0xbf0000) AM_WRITE(memsel_w)
+
+ AM_RANGE(0x4214, 0x4214) AM_MIRROR(0xbf0000) AM_READ(rddivl_r)
+ AM_RANGE(0x4215, 0x4215) AM_MIRROR(0xbf0000) AM_READ(rddivh_r)
+ AM_RANGE(0x4216, 0x4216) AM_MIRROR(0xbf0000) AM_READ(rdmpyl_r)
+ AM_RANGE(0x4217, 0x4217) AM_MIRROR(0xbf0000) AM_READ(rdmpyh_r)
+ADDRESS_MAP_END
+
+
+_5a22_device::_5a22_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
+ : g65816_device(mconfig, _5A22, "5A22", tag, owner, clock, "5a22", __FILE__, CPU_TYPE_5A22, ADDRESS_MAP_NAME(_5a22_map))
+{
+}
+
+
+void g65816_device::g65816i_set_execution_mode(uint mode)
+{
+ assert(mode < 5);
+ switch (mode)
+ {
+ case 0: FTABLE_OPCODES = g65816i_opcodes_M0X0; break;
+ case 1: FTABLE_OPCODES = g65816i_opcodes_M0X1; break;
+ case 2: FTABLE_OPCODES = g65816i_opcodes_M1X0; break;
+ case 3: FTABLE_OPCODES = g65816i_opcodes_M1X1; break;
+ case 4: FTABLE_OPCODES = g65816i_opcodes_E; break;
+ }
+ FTABLE_GET_REG = s_g65816_get_reg[mode];
+ FTABLE_SET_REG = s_g65816_set_reg[mode];
+ FTABLE_SET_LINE = s_g65816_set_line[mode];
+ FTABLE_EXECUTE = s_g65816_execute[mode];
+}
+
+
+const g65816_device::get_reg_func g65816_device::s_g65816_get_reg[5] =
+{
+ &g65816_device::g65816i_get_reg_M0X0,
+ &g65816_device::g65816i_get_reg_M0X1,
+ &g65816_device::g65816i_get_reg_M1X0,
+ &g65816_device::g65816i_get_reg_M1X1,
+ &g65816_device::g65816i_get_reg_E
+};
+
+const g65816_device::set_reg_func g65816_device::s_g65816_set_reg[5] =
+{
+ &g65816_device::g65816i_set_reg_M0X0,
+ &g65816_device::g65816i_set_reg_M0X1,
+ &g65816_device::g65816i_set_reg_M1X0,
+ &g65816_device::g65816i_set_reg_M1X1,
+ &g65816_device::g65816i_set_reg_E
+};
+
+const g65816_device::set_line_func g65816_device::s_g65816_set_line[5] =
+{
+ &g65816_device::g65816i_set_line_M0X0,
+ &g65816_device::g65816i_set_line_M0X1,
+ &g65816_device::g65816i_set_line_M1X0,
+ &g65816_device::g65816i_set_line_M1X1,
+ &g65816_device::g65816i_set_line_E
+};
+
+const g65816_device::execute_func g65816_device::s_g65816_execute[5] =
+{
+ &g65816_device::g65816i_execute_M0X0,
+ &g65816_device::g65816i_execute_M0X1,
+ &g65816_device::g65816i_execute_M1X0,
+ &g65816_device::g65816i_execute_M1X1,
+ &g65816_device::g65816i_execute_E
+};
+
+
+/* ======================================================================== */
+/* ================================= MEMORY =============================== */
+/* ======================================================================== */
+
+#define ADDRESS_65816(A) ((A)&0x00ffffff)
+
+uint g65816_device::g65816i_read_8_normal(uint address)
+{
+ address = ADDRESS_65816(address);
+ CLOCKS -= (bus_5A22_cycle_burst(address));
+ return g65816_read_8(address);
+}
+
+uint g65816_device::g65816i_read_8_immediate(uint address)
+{
+ address = ADDRESS_65816(address);
+ CLOCKS -= (bus_5A22_cycle_burst(address));
+ return g65816_read_8_immediate(address);
+}
+
+uint g65816_device::g65816i_read_8_direct(uint address)
+{
+ if (FLAG_E)
+ {
+ /* force address into zero page */
+ address = REGISTER_D + MAKE_UINT_8(address - REGISTER_D);
+ CLOCKS -= (bus_5A22_cycle_burst(address));
+ }
+ else
+ {
+ address = ADDRESS_65816(address);
+ CLOCKS -= (bus_5A22_cycle_burst(address));
+ }
+ return g65816_read_8(address);
+}
+
+uint g65816_device::g65816i_read_8_vector(uint address)
+{
+ if (!READ_VECTOR.isnull())
+ return READ_VECTOR(*m_program, address, 0xff);
+ else
+ return g65816i_read_8_normal(address);
+}
+
+void g65816_device::g65816i_write_8_normal(uint address, uint value)
+{
+ address = ADDRESS_65816(address);
+ CLOCKS -= (bus_5A22_cycle_burst(address));
+ g65816_write_8(address, MAKE_UINT_8(value));
+}
+
+void g65816_device::g65816i_write_8_direct(uint address, uint value)
+{
+ if (FLAG_E)
+ {
+ /* force address into zero page */
+ address = REGISTER_D + MAKE_UINT_8(address - REGISTER_D);
+ CLOCKS -= (bus_5A22_cycle_burst(address));
+ }
+ else
+ {
+ address = ADDRESS_65816(address);
+ CLOCKS -= (bus_5A22_cycle_burst(address));
+ }
+ g65816_write_8(address, MAKE_UINT_8(value));
+}
+
+uint g65816_device::g65816i_read_16_normal(uint address)
+{
+ return g65816i_read_8_normal(address) |
+ (g65816i_read_8_normal(address+1)<<8);
+}
+
+uint g65816_device::g65816i_read_16_immediate(uint address)
+{
+ return g65816i_read_8_immediate(address) |
+ (g65816i_read_8_immediate(address+1)<<8);
+}
+
+uint g65816_device::g65816i_read_16_direct(uint address)
+{
+ return g65816i_read_8_direct(address) |
+ (g65816i_read_8_direct(address+1)<<8);
+}
+
+uint g65816_device::g65816i_read_16_vector(uint address)
+{
+ return g65816i_read_8_vector(address) |
+ (g65816i_read_8_vector(address+1)<<8);
+}
+
+void g65816_device::g65816i_write_16_normal(uint address, uint value)
+{
+ g65816i_write_8_normal(address, value&0xff);
+ g65816i_write_8_normal(address+1, value>>8);
+}
+
+void g65816_device::g65816i_write_16_direct(uint address, uint value)
+{
+ g65816i_write_8_direct(address, value&0xff);
+ g65816i_write_8_direct(address+1, value>>8);
+}
+
+uint g65816_device::g65816i_read_24_normal(uint address)
+{
+ return g65816i_read_8_normal(address) |
+ (g65816i_read_8_normal(address+1)<<8) |
+ (g65816i_read_8_normal(address+2)<<16);
+}
+
+uint g65816_device::g65816i_read_24_immediate(uint address)
+{
+ return g65816i_read_8_immediate(address) |
+ (g65816i_read_8_immediate(address+1)<<8) |
+ (g65816i_read_8_immediate(address+2)<<16);
+}
+
+uint g65816_device::g65816i_read_24_direct(uint address)
+{
+ return g65816i_read_8_direct(address) |
+ (g65816i_read_8_direct(address+1)<<8) |
+ (g65816i_read_8_direct(address+2)<<16);
+}
+
+
+/* ======================================================================== */
+/* ================================= STACK ================================ */
+/* ======================================================================== */
+
+void g65816_device::g65816i_push_8(uint value)
+{
+ g65816i_write_8_normal(REGISTER_S, value);
+ if (FLAG_E)
+ {
+ REGISTER_S = MAKE_UINT_8(REGISTER_S-1) | 0x100;
+ }
+ else
+ {
+ REGISTER_S = MAKE_UINT_16(REGISTER_S-1);
+ }
+}
+
+uint g65816_device::g65816i_pull_8()
+{
+ if (FLAG_E)
+ {
+ REGISTER_S = MAKE_UINT_8(REGISTER_S+1) | 0x100;
+ }
+ else
+ {
+ REGISTER_S = MAKE_UINT_16(REGISTER_S+1);
+ }
+ return g65816i_read_8_normal(REGISTER_S);
+}
+
+void g65816_device::g65816i_push_16(uint value)
+{
+ g65816i_push_8(value>>8);
+ g65816i_push_8(value&0xff);
+}
+
+uint g65816_device::g65816i_pull_16()
+{
+ uint res = g65816i_pull_8();
+ return res | (g65816i_pull_8() << 8);
+}
+
+void g65816_device::g65816i_push_24(uint value)
+{
+ g65816i_push_8(value>>16);
+ g65816i_push_8((value>>8)&0xff);
+ g65816i_push_8(value&0xff);
+}
+
+uint g65816_device::g65816i_pull_24()
+{
+ uint res = g65816i_pull_8();
+ res |= g65816i_pull_8() << 8;
+ return ((res + 1) & 0xffff) | (g65816i_pull_8() << 16);
+}
+
+
+/* ======================================================================== */
+/* ============================ PROGRAM COUNTER =========================== */
+/* ======================================================================== */
+
+void g65816_device::g65816i_jump_16(uint address)
+{
+ REGISTER_PC = MAKE_UINT_16(address);
+ g65816i_jumping(REGISTER_PC);
+}
+
+void g65816_device::g65816i_jump_24(uint address)
+{
+ REGISTER_PB = address&0xff0000;
+ REGISTER_PC = MAKE_UINT_16(address);
+ g65816i_jumping(REGISTER_PC);
+}
+
+void g65816_device::g65816i_branch_8(uint offset)
+{
+ if (FLAG_E)
+ {
+ uint old_pc = REGISTER_PC;
+ REGISTER_PC = MAKE_UINT_16(REGISTER_PC + MAKE_INT_8(offset));
+ if((REGISTER_PC^old_pc)&0xff00)
+ CLK(1);
+ }
+ else
+ {
+ REGISTER_PC = MAKE_UINT_16(REGISTER_PC + MAKE_INT_8(offset));
+ }
+ g65816i_branching(REGISTER_PC);
+}
+
+void g65816_device::g65816i_branch_16(uint offset)
+{
+ REGISTER_PC = MAKE_UINT_16(REGISTER_PC + offset);
+ g65816i_branching(REGISTER_PC);
+}
+
+
+/* ======================================================================== */
+/* ============================ STATUS REGISTER =========================== */
+/* ======================================================================== */
+
+void g65816_device::g65816i_set_flag_mx(uint value)
+{
+ if (FLAG_M)
+ {
+ if(!(value & FLAGPOS_M))
+ {
+ REGISTER_A |= REGISTER_B;
+ REGISTER_B = 0;
+ FLAG_M = MFLAG_CLEAR;
+ }
+ }
+ else
+ {
+ if(value & FLAGPOS_M)
+ {
+ REGISTER_B = REGISTER_A & 0xff00;
+ REGISTER_A = MAKE_UINT_8(REGISTER_A);
+ FLAG_M = MFLAG_SET;
+ }
+ }
+ if (FLAG_X)
+ {
+ if(!(value & FLAGPOS_X))
+ {
+ FLAG_X = XFLAG_CLEAR;
+ }
+ }
+ else
+ {
+ if(value & FLAGPOS_X)
+ {
+ REGISTER_X = MAKE_UINT_8(REGISTER_X);
+ REGISTER_Y = MAKE_UINT_8(REGISTER_Y);
+ FLAG_X = XFLAG_SET;
+ }
+ }
+ g65816i_set_execution_mode((FLAG_M>>4) | (FLAG_X>>4));
+}
+
+void g65816_device::g65816i_set_flag_e(uint value)
+{
+ if (FLAG_E)
+ {
+ if(!value)
+ {
+ FLAG_E = EFLAG_CLEAR;
+ g65816i_set_execution_mode(EXECUTION_MODE_M1X1);
+ }
+ }
+ else
+ {
+ if(value)
+ {
+ if (!FLAG_M)
+ {
+ REGISTER_B = REGISTER_A & 0xff00;
+ REGISTER_A &= 0x00ff;
+ FLAG_M = MFLAG_SET;
+ }
+ if (!FLAG_X)
+ {
+ REGISTER_X = MAKE_UINT_8(REGISTER_X);
+ REGISTER_Y = MAKE_UINT_8(REGISTER_Y);
+ FLAG_X = XFLAG_SET;
+ }
+ REGISTER_S = MAKE_UINT_8(REGISTER_S) | 0x100;
+ FLAG_E = EFLAG_SET;
+ g65816i_set_execution_mode(EXECUTION_MODE_E);
+ }
+ }
+}
+
+void g65816_device::g65816i_set_flag_i(uint value)
+{
+ value &= FLAGPOS_I;
+ if(!FLAG_I || value)
+ {
+ FLAG_I = value;
+ return;
+ }
+ FLAG_I = value;
+}
+
+/* Get the Processor Status Register */
+uint g65816_device::g65816i_get_reg_p()
+{
+ return (FLAG_N&0x80) |
+ ((FLAG_V>>1)&0x40) |
+ FLAG_M |
+ FLAG_X |
+ FLAG_D |
+ FLAG_I |
+ ((!FLAG_Z)<<1) |
+ ((FLAG_C>>8)&1);
+}
+
+void g65816_device::g65816i_set_reg_p(uint value)
+{
+ if (FLAG_E)
+ {
+ FLAG_N = value;
+ FLAG_V = value << 1;
+ FLAG_D = value & FLAGPOS_D;
+ FLAG_Z = !(value & FLAGPOS_Z);
+ FLAG_C = value << 8;
+ g65816i_set_flag_i(value);
+ }
+ else
+ {
+ FLAG_N = value;
+ FLAG_V = value << 1;
+ FLAG_D = value & FLAGPOS_D;
+ FLAG_Z = !(value & FLAGPOS_Z);
+ FLAG_C = value << 8;
+ g65816i_set_flag_mx(value);
+ g65816i_set_flag_i(value);
+ }
+}
+
+
+/* ======================================================================== */
+/* =============================== INTERRUPTS ============================= */
+/* ======================================================================== */
+
+void g65816_device::g65816i_interrupt_hardware(uint vector)
+{
+ if (FLAG_E)
+ {
+ CLK(7);
+ g65816i_push_16(REGISTER_PC);
+ g65816i_push_8(g65816i_get_reg_p() & ~FLAGPOS_B);
+ FLAG_D = DFLAG_CLEAR;
+ g65816i_set_flag_i(IFLAG_SET);
+ REGISTER_PB = 0;
+ g65816i_jump_16(g65816i_read_16_vector(vector));
+ standard_irq_callback(0);
+ }
+ else
+ {
+ CLK(8);
+ g65816i_push_8(REGISTER_PB>>16);
+ g65816i_push_16(REGISTER_PC);
+ g65816i_push_8(g65816i_get_reg_p());
+ FLAG_D = DFLAG_CLEAR;
+ g65816i_set_flag_i(IFLAG_SET);
+ REGISTER_PB = 0;
+ g65816i_jump_16(g65816i_read_16_vector(vector));
+ standard_irq_callback(0);
+ }
+}
+
+void g65816_device::g65816i_interrupt_software(uint vector)
+{
+ if (FLAG_E)
+ {
+ CLK(7);
+ g65816i_push_16(REGISTER_PC);
+ g65816i_push_8(g65816i_get_reg_p());
+ FLAG_D = DFLAG_CLEAR;
+ g65816i_set_flag_i(IFLAG_SET);
+ REGISTER_PB = 0;
+ g65816i_jump_16(g65816i_read_16_normal(vector));
+ }
+ else
+ {
+ CLK(8);
+ g65816i_push_8(REGISTER_PB>>16);
+ g65816i_push_16(REGISTER_PC);
+ g65816i_push_8(g65816i_get_reg_p());
+ FLAG_D = DFLAG_CLEAR;
+ g65816i_set_flag_i(IFLAG_SET);
+ REGISTER_PB = 0;
+ g65816i_jump_16(g65816i_read_16_normal(vector));
+ }
+}
+
+void g65816_device::g65816i_interrupt_nmi()
+{
+ if (FLAG_E)
+ {
+ CLK(7);
+ g65816i_push_16(REGISTER_PC);
+ g65816i_push_8(g65816i_get_reg_p() & ~FLAGPOS_B);
+ FLAG_D = DFLAG_CLEAR;
+ REGISTER_PB = 0;
+ g65816i_jump_16(g65816i_read_16_normal((FLAG_E) ? VECTOR_NMI_E : VECTOR_NMI_N));
+ }
+ else
+ {
+ CLK(8);
+ g65816i_push_8(REGISTER_PB>>16);
+ g65816i_push_16(REGISTER_PC);
+ g65816i_push_8(g65816i_get_reg_p());
+ FLAG_D = DFLAG_CLEAR;
+ REGISTER_PB = 0;
+ g65816i_jump_16(g65816i_read_16_normal((FLAG_E) ? VECTOR_NMI_E : VECTOR_NMI_N));
+ }
+}
+
+
+void g65816_device::g65816i_check_maskable_interrupt()
+{
+ if(!(CPU_STOPPED & STOP_LEVEL_STOP) && LINE_IRQ && !FLAG_I)
+ {
+ g65816i_interrupt_hardware((FLAG_E) ? VECTOR_IRQ_E : VECTOR_IRQ_N);
+ CPU_STOPPED &= ~STOP_LEVEL_WAI;
+ LINE_IRQ=0;
+ }
+}
+
+
+uint g65816_device::EA_IMM8() {REGISTER_PC += 1; return REGISTER_PB | MAKE_UINT_16(REGISTER_PC-1);}
+uint g65816_device::EA_IMM16() {REGISTER_PC += 2; return REGISTER_PB | MAKE_UINT_16(REGISTER_PC-2);}
+uint g65816_device::EA_IMM24() {REGISTER_PC += 3; return REGISTER_PB | MAKE_UINT_16(REGISTER_PC-3);}
+uint g65816_device::EA_D() {if(MAKE_UINT_8(REGISTER_D)) CLK(1); return MAKE_UINT_16(REGISTER_D + g65816i_read_8_immediate(EA_IMM8()));}
+uint g65816_device::EA_A() {return REGISTER_DB | g65816i_read_16_immediate(EA_IMM16());}
+uint g65816_device::EA_AL() {return g65816i_read_24_immediate(EA_IMM24());}
+uint g65816_device::EA_DX() {return MAKE_UINT_16(REGISTER_D + g65816i_read_8_immediate(EA_IMM8()) + REGISTER_X);}
+uint g65816_device::EA_DY() {return MAKE_UINT_16(REGISTER_D + g65816i_read_8_immediate(EA_IMM8()) + REGISTER_Y);}
+uint g65816_device::EA_AX() {uint tmp = EA_A(); if((tmp^(tmp+REGISTER_X))&0xff00) CLK(1); return tmp + REGISTER_X;}
+uint g65816_device::EA_ALX() {return EA_AL() + REGISTER_X;}
+uint g65816_device::EA_AY() {uint tmp = EA_A(); if((tmp^(tmp+REGISTER_X))&0xff00) CLK(1); return tmp + REGISTER_Y;}
+uint g65816_device::EA_DI() {return REGISTER_DB | g65816i_read_16_direct(EA_D());}
+uint g65816_device::EA_DLI() {return g65816i_read_24_direct(EA_D());}
+uint g65816_device::EA_AI() {return g65816i_read_16_normal(g65816i_read_16_immediate(EA_IMM16()));}
+uint g65816_device::EA_ALI() {return g65816i_read_24_normal(EA_A());}
+uint g65816_device::EA_DXI() {return REGISTER_DB | g65816i_read_16_direct(EA_DX());}
+uint g65816_device::EA_DIY() {uint tmp = REGISTER_DB | g65816i_read_16_direct(EA_D()); if((tmp^(tmp+REGISTER_X))&0xff00) CLK(1); return tmp + REGISTER_Y;}
+uint g65816_device::EA_DLIY() {return g65816i_read_24_direct(EA_D()) + REGISTER_Y;}
+uint g65816_device::EA_AXI() {return g65816i_read_16_normal(MAKE_UINT_16(g65816i_read_16_immediate(EA_IMM16()) + REGISTER_X));}
+uint g65816_device::EA_S() {return MAKE_UINT_16(REGISTER_S + g65816i_read_8_immediate(EA_IMM8()));}
+uint g65816_device::EA_SIY() {return MAKE_UINT_16(g65816i_read_16_normal(REGISTER_S + g65816i_read_8_immediate(EA_IMM8())) + REGISTER_Y) | REGISTER_DB;}
+
+
+
+/* ======================================================================== */
+/* ================================= API ================================== */
+/* ======================================================================== */
+
+
+void g65816_device::device_reset()
+{
+ /* Start the CPU */
+ CPU_STOPPED = 0;
+
+ /* Put into emulation mode */
+ REGISTER_D = 0;
+ REGISTER_PB = 0;
+ REGISTER_DB = 0;
+ REGISTER_S = (REGISTER_S & 0xff) | 0x100;
+ REGISTER_X &= 0xff;
+ REGISTER_Y &= 0xff;
+ if(!FLAG_M)
+ {
+ REGISTER_B = REGISTER_A & 0xff00;
+ REGISTER_A &= 0xff;
+ }
+ FLAG_E = EFLAG_SET;
+ FLAG_M = MFLAG_SET;
+ FLAG_X = XFLAG_SET;
+
+ /* Clear D and set I */
+ FLAG_D = DFLAG_CLEAR;
+ FLAG_I = IFLAG_SET;
+
+ /* Clear all pending interrupts (should we really do this?) */
+ LINE_IRQ = 0;
+ LINE_NMI = 0;
+ IRQ_DELAY = 0;
+
+ /* Set the function tables to emulation mode */
+ g65816i_set_execution_mode(EXECUTION_MODE_E);
+
+ /* 6502 expects these, but its not in the 65816 spec */
+ FLAG_Z = ZFLAG_CLEAR;
+ REGISTER_S = 0x1ff;
+
+ /* Fetch the reset vector */
+ REGISTER_PC = g65816_read_8(VECTOR_RESET) | (g65816_read_8(VECTOR_RESET+1)<<8);
+ g65816i_jumping(REGISTER_PB | REGISTER_PC);
+}
+
+
+/* Execute some instructions */
+void g65816_device::execute_run()
+{
+ int clocks = m_ICount;
+ m_ICount = clocks - (this->*FTABLE_EXECUTE)(m_ICount);
+}
+
+
+/* Get the current Program Counter */
+unsigned g65816_device::g65816_get_pc()
+{
+ return REGISTER_PB | REGISTER_PC;
+}
+
+/* Set the Program Counter */
+void g65816_device::g65816_set_pc(unsigned val)
+{
+ REGISTER_PC = MAKE_UINT_16(val);
+ REGISTER_PB = (val >> 16) & 0xFF;
+ g65816_jumping(REGISTER_PB | REGISTER_PC);
+}
+
+/* Get the current Stack Pointer */
+unsigned g65816_device::g65816_get_sp()
+{
+ return REGISTER_S;
+}
+
+/* Set the Stack Pointer */
+void g65816_device::g65816_set_sp(unsigned val)
+{
+ REGISTER_S = FLAG_E ? MAKE_UINT_8(val) | 0x100 : MAKE_UINT_16(val);
+}
+
+/* Get a register */
+unsigned g65816_device::g65816_get_reg(int regnum)
+{
+ /* Set the function tables to emulation mode if the FTABLE is NULL */
+ if( FTABLE_GET_REG == NULL )
+ g65816i_set_execution_mode(EXECUTION_MODE_E);
+
+ return (this->*FTABLE_GET_REG)(regnum);
+}
+
+/* Set a register */
+void g65816_device::g65816_set_reg(int regnum, unsigned value)
+{
+ (this->*FTABLE_SET_REG)(regnum, value);
+}
+
+/* Set an interrupt line */
+void g65816_device::execute_set_input(int line, int state)
+{
+ (this->*FTABLE_SET_LINE)(line, state);
+}
+
+/* Disassemble an instruction */
+#include "g65816ds.h"
+
+
+offs_t g65816_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
+{
+ return g65816_disassemble(buffer, (pc & 0x00ffff), (pc & 0xff0000) >> 16, oprom, FLAG_M, FLAG_X);
+}
+
+CPU_DISASSEMBLE( g65816 )
+{
+ return g65816_disassemble(buffer, (pc & 0x00ffff), (pc & 0xff0000) >> 16, oprom, 0/*FLAG_M*/, 0/*FLAG_X*/);
+}
+
+void g65816_device::g65816_restore_state()
+{
+ // restore proper function pointers
+ g65816i_set_execution_mode((FLAG_M>>4) | (FLAG_X>>4));
+
+ // make sure the memory system can keep up
+ g65816i_jumping(REGISTER_PB | REGISTER_PC);
+}
+
+void g65816_device::device_start()
+{
+ m_a = 0;
+ m_b = 0;
+ m_x = 0;
+ m_y = 0;
+ m_s = 0;
+ m_pc = 0;
+ m_ppc = 0;
+ m_pb = 0;
+ m_db = 0;
+ m_d = 0;
+ m_flag_e = 0;
+ m_flag_m = 0;
+ m_flag_x = 0;
+ m_flag_n = 0;
+ m_flag_v = 0;
+ m_flag_d = 0;
+ m_flag_i = 0;
+ m_flag_z = 0;
+ m_flag_c = 0;
+ m_line_irq = 0;
+ m_line_nmi = 0;
+ m_fastROM = 0;
+ m_ir = 0;
+ m_irq_delay = 0;
+ m_stopped = 0;
+ m_source = 0;
+ m_destination = 0;
+ m_wrmpya = 0;
+ m_wrmpyb = 0;
+ m_rdmpy = 0;
+ m_wrdiv = 0;
+ m_dvdd = 0;
+ m_rddiv = 0;
+ m_opcodes = NULL;
+ m_get_reg = NULL;
+ m_set_reg = NULL;
+ m_set_line = NULL;
+ m_execute = NULL;
+ m_debugger_temp = 0;
+
+ m_program = &space(AS_PROGRAM);
+
+ save_item(NAME(m_a));
+ save_item(NAME(m_b));
+ save_item(NAME(m_x));
+ save_item(NAME(m_y));
+ save_item(NAME(m_s));
+ save_item(NAME(m_pc));
+ save_item(NAME(m_ppc));
+ save_item(NAME(m_pb));
+ save_item(NAME(m_db));
+ save_item(NAME(m_d));
+ save_item(NAME(m_flag_e));
+ save_item(NAME(m_flag_m));
+ save_item(NAME(m_flag_x));
+ save_item(NAME(m_flag_n));
+ save_item(NAME(m_flag_v));
+ save_item(NAME(m_flag_d));
+ save_item(NAME(m_flag_i));
+ save_item(NAME(m_flag_z));
+ save_item(NAME(m_flag_c));
+ save_item(NAME(m_line_irq));
+ save_item(NAME(m_line_nmi));
+ save_item(NAME(m_ir));
+ save_item(NAME(m_irq_delay));
+ save_item(NAME(m_stopped));
+ save_item(NAME(m_fastROM));
+
+ machine().save().register_postload(save_prepost_delegate(FUNC(g65816_device::g65816_restore_state), this));
+
+ m_rw8_cycles = 1;
+ m_rw16_cycles = 2;
+ m_rw24_cycles = 3;
+
+ state_add( G65816_PC, "PC", m_debugger_temp).callimport().callexport().formatstr("%06X");
+ state_add( G65816_S, "S", m_s).callimport().formatstr("%04X");
+ state_add( G65816_P, "P", m_debugger_temp).callimport().callexport().formatstr("%02X");
+ state_add( G65816_A, "A", m_debugger_temp).callimport().callexport().formatstr("%04X");
+ state_add( G65816_X, "X", m_x).callimport().formatstr("%04X");
+ state_add( G65816_Y, "Y", m_y).callimport().formatstr("%04X");
+ state_add( G65816_PB, "PB", m_debugger_temp).callimport().callexport().formatstr("%02X");
+ state_add( G65816_DB, "DB", m_debugger_temp).callimport().callexport().formatstr("%02X");
+ state_add( G65816_D, "D", m_d).callimport().formatstr("%04X");
+ state_add( G65816_E, "E", m_flag_e).mask(0x01).callimport().formatstr("%01X");
+ state_add( G65816_NMI_STATE, "NMI", m_line_nmi).mask(0x01).callimport().formatstr("%01X");
+ state_add( G65816_IRQ_STATE, "IRQ", m_line_irq).mask(0x01).callimport().formatstr("%01X");
+
+ state_add( STATE_GENPC, "GENPC", m_debugger_temp).callimport().callexport().formatstr("%06X").noshow();
+ state_add( STATE_GENSP, "GENSP", m_debugger_temp).callimport().callexport().formatstr("%06X").noshow();
+ state_add( STATE_GENFLAGS, "GENFLAGS", m_debugger_temp).formatstr("%8s").noshow();
+
+ m_icountptr = &m_ICount;
+}
+
+void g65816_device::state_import(const device_state_entry &entry)
+{
+ switch (entry.index())
+ {
+ case STATE_GENPC:
+ g65816_set_pc(m_debugger_temp);
+ break;
+ case STATE_GENSP:
+ g65816_set_sp(m_debugger_temp);
+ break;
+ case G65816_PC:
+ case G65816_PB:
+ case G65816_DB:
+ g65816_set_reg(entry.index(), m_debugger_temp);
+ break;
+ case G65816_D:
+ g65816_set_reg(G65816_D, m_d);
+ break;
+ case G65816_S:
+ g65816_set_reg(G65816_S, m_s);
+ break;
+ case G65816_P:
+ g65816_set_reg(G65816_P, m_debugger_temp);
+ break;
+ case G65816_E:
+ g65816_set_reg(G65816_E, m_flag_e);
+ break;
+ case G65816_A:
+ g65816_set_reg(G65816_A, m_debugger_temp);
+ break;
+ case G65816_X:
+ g65816_set_reg(G65816_X, m_x);
+ break;
+ case G65816_Y:
+ g65816_set_reg(G65816_Y, m_y);
+ break;
+ case G65816_NMI_STATE:
+ g65816_set_reg(G65816_NMI_STATE, m_line_nmi);
+ break;
+ case G65816_IRQ_STATE:
+ g65816_set_reg(G65816_IRQ_STATE, m_line_irq);
+ break;
+ }
+}
+
+void g65816_device::state_export(const device_state_entry &entry)
+{
+ switch (entry.index())
+ {
+ case STATE_GENPC:
+ case G65816_PC:
+ m_debugger_temp = g65816_get_pc();
+ break;
+ case STATE_GENSP:
+ m_debugger_temp = g65816_get_sp();
+ break;
+ case G65816_PB:
+ m_debugger_temp = m_pb>>16;
+ break;
+ case G65816_DB:
+ m_debugger_temp = m_db>>16;
+ break;
+ case G65816_P:
+ m_debugger_temp = (m_flag_n&0x80) |
+ ((m_flag_v>>1)&0x40) |
+ m_flag_m |
+ m_flag_x |
+ m_flag_d |
+ m_flag_i |
+ ((!m_flag_z)<<1) |
+ ((m_flag_c>>8)&1);
+ break;
+ case G65816_A:
+ m_debugger_temp = m_a | m_b;
+ break;
+ }
+}
+
+void g65816_device::state_string_export(const device_state_entry &entry, std::string &str)
+{
+ switch (entry.index())
+ {
+ case STATE_GENFLAGS:
+ strprintf(str, "%c%c%c%c%c%c%c%c",
+ m_flag_n & NFLAG_SET ? 'N':'.',
+ m_flag_v & VFLAG_SET ? 'V':'.',
+ m_flag_m & MFLAG_SET ? 'M':'.',
+ m_flag_x & XFLAG_SET ? 'X':'.',
+ m_flag_d & DFLAG_SET ? 'D':'.',
+
+ m_flag_i & IFLAG_SET ? 'I':'.',
+ m_flag_z == 0 ? 'Z':'.',
+ m_flag_c & CFLAG_SET ? 'C':'.');
+ break;
+ }
+}
+
+void g65816_device::set_read_vector_callback(read8_delegate read_vector)
+{
+ READ_VECTOR = read_vector;
+}
+
+
+/*
+SNES specific, used to handle master cycles, based off byuu's BSNES code
+*/
+
+int g65816_device::bus_5A22_cycle_burst(uint addr)
+{
+ if(m_cpu_type == CPU_TYPE_G65816)
+ return 0;
+
+ if(addr & 0x408000) {
+ if(addr & 0x800000)
+ return (m_fastROM & 1) ? 6 : 8;
+
+ return 8;
+ }
+ if((addr + 0x6000) & 0x4000) return 8;
+ if((addr - 0x4000) & 0x7e00) return 6;
+
+ return 12;
+}
+
+
+void _5a22_device::device_start()
+{
+ g65816_device::device_start();
+
+ state_add( _5A22_FASTROM, "fastROM", m_debugger_temp).mask(0x01).callimport().callexport().formatstr("%01X");
+
+ m_rw8_cycles = 0;
+ m_rw16_cycles = 0;
+ m_rw24_cycles = 0;
+}
+
+void _5a22_device::state_import(const device_state_entry &entry)
+{
+ switch (entry.index())
+ {
+ case _5A22_FASTROM:
+ g65816_set_reg(_5A22_FASTROM, m_debugger_temp);
+ break;
+ default:
+ g65816_device::state_import(entry);
+ break;
+ }
+}
+
+void _5a22_device::state_export(const device_state_entry &entry)
+{
+ switch (entry.index())
+ {
+ case _5A22_FASTROM:
+ m_debugger_temp = g65816_get_reg(_5A22_FASTROM);
+ break;
+ default:
+ g65816_device::state_export(entry);
+ break;
+ }
+}
+
+void _5a22_device::device_reset()
+{
+ g65816_device::device_reset();
+
+ m_fastROM = 0;
+ m_wrmpya = 0xff;
+ m_wrdiv = 0xffff;
+}
+
+/* TODO: multiplication / division should actually occur inside CPU_EXECUTE */
+/* (Old note, for reference): multiplication should take 8 CPU cycles &
+division 16 CPU cycles, but using these timers breaks e.g. Chrono Trigger
+intro and Super Tennis gameplay. On the other hand, timers are needed for the
+translation of Breath of Fire 2 to work. More weirdness: we might need to leave
+8 CPU cycles for division at first, since using 16 produces bugs (see e.g.
+Triforce pieces in Zelda 3 intro) */
+
+WRITE8_MEMBER( _5a22_device::wrmpya_w )
+{
+ m_wrmpya = data;
+}
+
+WRITE8_MEMBER( _5a22_device::wrmpyb_w )
+{
+ m_wrmpyb = data;
+ m_rdmpy = m_wrmpya * m_wrmpyb;
+ /* TODO: m_rddiv == 0? */
+}
+
+WRITE8_MEMBER( _5a22_device::wrdivl_w )
+{
+ m_wrdiv = (data) | (m_wrdiv & 0xff00);
+}
+
+WRITE8_MEMBER( _5a22_device::wrdivh_w )
+{
+ m_wrdiv = (data << 8) | (m_wrdiv & 0xff);
+}
+
+WRITE8_MEMBER( _5a22_device::wrdvdd_w )
+{
+ UINT16 quotient, remainder;
+
+ m_dvdd = data;
+
+ quotient = (m_dvdd == 0) ? 0xffff : m_wrdiv / m_dvdd;
+ remainder = (m_dvdd == 0) ? 0x000c : m_wrdiv % m_dvdd;
+
+ m_rddiv = quotient;
+ m_rdmpy = remainder;
+}
+
+WRITE8_MEMBER( _5a22_device::memsel_w )
+{
+ m_fastROM = data & 1;
+}
+
+READ8_MEMBER( _5a22_device::rddivl_r )
+{
+ return m_rddiv & 0xff;
+}
+
+READ8_MEMBER( _5a22_device::rddivh_r )
+{
+ return m_rddiv >> 8;
+}
+
+READ8_MEMBER( _5a22_device::rdmpyl_r )
+{
+ return m_rdmpy & 0xff;
+}
+
+READ8_MEMBER( _5a22_device::rdmpyh_r )
+{
+ return m_rdmpy >> 8;
+}
+
+
+void _5a22_device::set_5a22_map()
+{
+ space(AS_PROGRAM).install_write_handler(0x4202, 0x4202, 0, 0xbf0000, write8_delegate(FUNC(_5a22_device::wrmpya_w),this));
+ space(AS_PROGRAM).install_write_handler(0x4203, 0x4203, 0, 0xbf0000, write8_delegate(FUNC(_5a22_device::wrmpyb_w),this));
+ space(AS_PROGRAM).install_write_handler(0x4204, 0x4204, 0, 0xbf0000, write8_delegate(FUNC(_5a22_device::wrdivl_w),this));
+ space(AS_PROGRAM).install_write_handler(0x4205, 0x4205, 0, 0xbf0000, write8_delegate(FUNC(_5a22_device::wrdivh_w),this));
+ space(AS_PROGRAM).install_write_handler(0x4206, 0x4206, 0, 0xbf0000, write8_delegate(FUNC(_5a22_device::wrdvdd_w),this));
+
+ space(AS_PROGRAM).install_write_handler(0x420d, 0x420d, 0, 0xbf0000, write8_delegate(FUNC(_5a22_device::memsel_w),this));
+
+ space(AS_PROGRAM).install_read_handler(0x4214, 0x4214, 0, 0xbf0000, read8_delegate(FUNC(_5a22_device::rddivl_r),this));
+ space(AS_PROGRAM).install_read_handler(0x4215, 0x4215, 0, 0xbf0000, read8_delegate(FUNC(_5a22_device::rddivh_r),this));
+ space(AS_PROGRAM).install_read_handler(0x4216, 0x4216, 0, 0xbf0000, read8_delegate(FUNC(_5a22_device::rdmpyl_r),this));
+ space(AS_PROGRAM).install_read_handler(0x4217, 0x4217, 0, 0xbf0000, read8_delegate(FUNC(_5a22_device::rdmpyh_r),this));
+}
+
+
+/* ======================================================================== */
+/* ============================== END OF FILE ============================= */
+/* ======================================================================== */
diff --git a/src/devices/cpu/g65816/g65816.h b/src/devices/cpu/g65816/g65816.h
new file mode 100644
index 00000000000..19b76fb3d31
--- /dev/null
+++ b/src/devices/cpu/g65816/g65816.h
@@ -0,0 +1,1570 @@
+// license:BSD-3-Clause
+// copyright-holders:Karl Stenerud
+#pragma once
+
+#ifndef __G65816_H__
+#define __G65816_H__
+
+#include "g65816cm.h"
+
+/* ======================================================================== */
+/* =============================== COPYRIGHT ============================== */
+/* ======================================================================== */
+/*
+
+G65C816 CPU Emulator V0.92
+
+Copyright Karl Stenerud
+All rights reserved.
+
+*/
+/* ======================================================================== */
+/* ============================= Configuration ============================ */
+/* ======================================================================== */
+
+/* GTE Microcircuits G65816 */
+
+/* ======================================================================== */
+/* =============================== DEFINES ================================ */
+/* ======================================================================== */
+
+/* Interrupt lines - used with g65816_set_irq_line() */
+enum
+{
+ G65816_LINE_NONE,
+ G65816_LINE_IRQ,
+ G65816_LINE_NMI,
+ G65816_LINE_ABORT,
+ G65816_LINE_SO,
+ G65816_LINE_RDY,
+ G65816_LINE_RESET
+};
+
+#define G65816_INT_NONE G65816_LINE_NONE
+#define G65816_INT_IRQ G65816_LINE_IRQ
+#define G65816_INT_NMI G65816_LINE_NMI
+
+
+/* Registers - used by g65816_set_reg() and g65816_get_reg() */
+enum
+{
+ G65816_PC=1, G65816_S, G65816_P, G65816_A, G65816_X, G65816_Y,
+ G65816_PB, G65816_DB, G65816_D, G65816_E,
+ G65816_NMI_STATE, G65816_IRQ_STATE,
+ _5A22_FASTROM
+};
+
+
+class g65816_device : public cpu_device
+{
+public:
+ // construction/destruction
+ g65816_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+ g65816_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source, int cpu_type, address_map_constructor internal = NULL);
+
+ void set_read_vector_callback(read8_delegate read_vector);
+
+protected:
+ // device-level overrides
+ virtual void device_start();
+ virtual void device_reset();
+
+ // device_execute_interface overrides
+ virtual UINT32 execute_min_cycles() const { return 1; }
+ virtual UINT32 execute_max_cycles() const { return 20; }
+ virtual UINT32 execute_input_lines() const { return 5; }
+ virtual void execute_run();
+ virtual void execute_set_input(int inputnum, int state);
+
+ // device_memory_interface overrides
+ virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : NULL; }
+
+ // device_state_interface overrides
+ virtual void state_import(const device_state_entry &entry);
+ virtual void state_export(const device_state_entry &entry);
+ virtual void state_string_export(const device_state_entry &entry, std::string &str);
+
+ // device_disasm_interface overrides
+ virtual UINT32 disasm_min_opcode_bytes() const { return 1; }
+ virtual UINT32 disasm_max_opcode_bytes() const { return 4; }
+ virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
+
+ address_space_config m_program_config;
+
+ typedef void (g65816_device::*opcode_func) ();
+ typedef uint (g65816_device::*get_reg_func)(int regnum);
+ typedef void (g65816_device::*set_reg_func)(int regnum, uint val);
+ typedef void (g65816_device::*set_line_func)(int line, int state);
+ typedef int (g65816_device::*execute_func)(int cycles);
+
+ static const opcode_func g65816i_opcodes_M0X0[];
+ uint g65816i_get_reg_M0X0(int regnum);
+ void g65816i_set_reg_M0X0(int regnum, uint val);
+ void g65816i_set_line_M0X0(int line, int state);
+ int g65816i_execute_M0X0(int cycles);
+
+ static const opcode_func g65816i_opcodes_M0X1[];
+ uint g65816i_get_reg_M0X1(int regnum);
+ void g65816i_set_reg_M0X1(int regnum, uint val);
+ void g65816i_set_line_M0X1(int line, int state);
+ int g65816i_execute_M0X1(int cycles);
+
+ static const opcode_func g65816i_opcodes_M1X0[];
+ uint g65816i_get_reg_M1X0(int regnum);
+ void g65816i_set_reg_M1X0(int regnum, uint val);
+ void g65816i_set_line_M1X0(int line, int state);
+ int g65816i_execute_M1X0(int cycles);
+
+ static const opcode_func g65816i_opcodes_M1X1[];
+ uint g65816i_get_reg_M1X1(int regnum);
+ void g65816i_set_reg_M1X1(int regnum, uint val);
+ void g65816i_set_line_M1X1(int line, int state);
+ int g65816i_execute_M1X1(int cycles);
+
+ static const opcode_func g65816i_opcodes_E[];
+ uint g65816i_get_reg_E(int regnum);
+ void g65816i_set_reg_E(int regnum, uint val);
+ void g65816i_set_line_E(int line, int state);
+ int g65816i_execute_E(int cycles);
+
+ void g65816i_set_execution_mode(uint mode);
+ int bus_5A22_cycle_burst(uint addr);
+ unsigned g65816_get_pc();
+ void g65816_set_pc(unsigned val);
+ unsigned g65816_get_sp();
+ void g65816_set_sp(unsigned val);
+ unsigned g65816_get_reg(int regnum);
+ void g65816_set_reg(int regnum, unsigned value);
+ void g65816_restore_state();
+ uint g65816i_read_8_normal(uint address);
+ uint g65816i_read_8_immediate(uint address);
+ uint g65816i_read_8_direct(uint address);
+ uint g65816i_read_8_vector(uint address);
+ void g65816i_write_8_normal(uint address, uint value);
+ void g65816i_write_8_direct(uint address, uint value);
+ uint g65816i_read_16_normal(uint address);
+ uint g65816i_read_16_immediate(uint address);
+ uint g65816i_read_16_direct(uint address);
+ uint g65816i_read_16_vector(uint address);
+ void g65816i_write_16_normal(uint address, uint value);
+ void g65816i_write_16_direct(uint address, uint value);
+ uint g65816i_read_24_normal(uint address);
+ uint g65816i_read_24_immediate(uint address);
+ uint g65816i_read_24_direct(uint address);
+ void g65816i_push_8(uint value);
+ uint g65816i_pull_8();
+ void g65816i_push_16(uint value);
+ uint g65816i_pull_16();
+ void g65816i_push_24(uint value);
+ uint g65816i_pull_24();
+ void g65816i_jump_16(uint address);
+ void g65816i_jump_24(uint address);
+ void g65816i_branch_8(uint offset);
+ void g65816i_branch_16(uint offset);
+ void g65816i_set_flag_mx(uint value);
+ void g65816i_set_flag_e(uint value);
+ void g65816i_set_flag_i(uint value);
+ uint g65816i_get_reg_p();
+ void g65816i_set_reg_p(uint value);
+ void g65816i_interrupt_hardware(uint vector);
+ void g65816i_interrupt_software(uint vector);
+ void g65816i_interrupt_nmi();
+ void g65816i_check_maskable_interrupt();
+ uint EA_IMM8();
+ uint EA_IMM16();
+ uint EA_IMM24();
+ uint EA_D();
+ uint EA_A();
+ uint EA_AL();
+ uint EA_DX();
+ uint EA_DY();
+ uint EA_AX();
+ uint EA_ALX();
+ uint EA_AY();
+ uint EA_DI();
+ uint EA_DLI();
+ uint EA_AI();
+ uint EA_ALI();
+ uint EA_DXI();
+ uint EA_DIY();
+ uint EA_DLIY();
+ uint EA_AXI();
+ uint EA_S();
+ uint EA_SIY();
+
+ static const get_reg_func s_g65816_get_reg[5];
+ static const set_reg_func s_g65816_set_reg[5];
+ static const set_line_func s_g65816_set_line[5];
+ static const execute_func s_g65816_execute[5];
+
+ uint m_a; /* Accumulator */
+ uint m_b; /* holds high byte of accumulator */
+ uint m_x; /* Index Register X */
+ uint m_y; /* Index Register Y */
+ uint m_s; /* Stack Pointer */
+ uint m_pc; /* Program Counter */
+ uint m_ppc; /* Previous Program Counter */
+ uint m_pb; /* Program Bank (shifted left 16) */
+ uint m_db; /* Data Bank (shifted left 16) */
+ uint m_d; /* Direct Register */
+ uint m_flag_e; /* Emulation Mode Flag */
+ uint m_flag_m; /* Memory/Accumulator Select Flag */
+ uint m_flag_x; /* Index Select Flag */
+ uint m_flag_n; /* Negative Flag */
+ uint m_flag_v; /* Overflow Flag */
+ uint m_flag_d; /* Decimal Mode Flag */
+ uint m_flag_i; /* Interrupt Mask Flag */
+ uint m_flag_z; /* Zero Flag (inverted) */
+ uint m_flag_c; /* Carry Flag */
+ uint m_line_irq; /* Status of the IRQ line */
+ uint m_line_nmi; /* Status of the NMI line */
+ uint m_fastROM; /* SNES specific */
+ uint m_ir; /* Instruction Register */
+ uint m_irq_delay; /* delay 1 instruction before checking irq */
+ address_space *m_program;
+ read8_delegate m_read_vector; /* Read vector override */
+ uint m_stopped; /* Sets how the CPU is stopped */
+ const opcode_func* m_opcodes;
+ get_reg_func m_get_reg;
+ set_reg_func m_set_reg;
+ set_line_func m_set_line;
+ execute_func m_execute;
+ uint m_source;
+ uint m_destination;
+ int m_ICount;
+ int m_cpu_type;
+ UINT8 m_rw8_cycles, m_rw16_cycles, m_rw24_cycles;
+ UINT32 m_debugger_temp;
+
+ /* 5A22 specific registers */
+ UINT8 m_wrmpya, m_wrmpyb;
+ UINT16 m_rdmpy;
+ UINT16 m_wrdiv;
+ UINT8 m_dvdd;
+ UINT16 m_rddiv;
+
+ void g65816i_00_M0X0();
+ void g65816i_01_M0X0();
+ void g65816i_02_M0X0();
+ void g65816i_03_M0X0();
+ void g65816i_04_M0X0();
+ void g65816i_05_M0X0();
+ void g65816i_06_M0X0();
+ void g65816i_07_M0X0();
+ void g65816i_08_M0X0();
+ void g65816i_09_M0X0();
+ void g65816i_0a_M0X0();
+ void g65816i_0b_M0X0();
+ void g65816i_0c_M0X0();
+ void g65816i_0d_M0X0();
+ void g65816i_0e_M0X0();
+ void g65816i_0f_M0X0();
+ void g65816i_10_M0X0();
+ void g65816i_11_M0X0();
+ void g65816i_12_M0X0();
+ void g65816i_13_M0X0();
+ void g65816i_14_M0X0();
+ void g65816i_15_M0X0();
+ void g65816i_16_M0X0();
+ void g65816i_17_M0X0();
+ void g65816i_18_M0X0();
+ void g65816i_19_M0X0();
+ void g65816i_1a_M0X0();
+ void g65816i_1b_M0X0();
+ void g65816i_1c_M0X0();
+ void g65816i_1d_M0X0();
+ void g65816i_1e_M0X0();
+ void g65816i_1f_M0X0();
+ void g65816i_20_M0X0();
+ void g65816i_21_M0X0();
+ void g65816i_22_M0X0();
+ void g65816i_23_M0X0();
+ void g65816i_24_M0X0();
+ void g65816i_25_M0X0();
+ void g65816i_26_M0X0();
+ void g65816i_27_M0X0();
+ void g65816i_28_M0X0();
+ void g65816i_29_M0X0();
+ void g65816i_2a_M0X0();
+ void g65816i_2b_M0X0();
+ void g65816i_2c_M0X0();
+ void g65816i_2d_M0X0();
+ void g65816i_2e_M0X0();
+ void g65816i_2f_M0X0();
+ void g65816i_30_M0X0();
+ void g65816i_31_M0X0();
+ void g65816i_32_M0X0();
+ void g65816i_33_M0X0();
+ void g65816i_34_M0X0();
+ void g65816i_35_M0X0();
+ void g65816i_36_M0X0();
+ void g65816i_37_M0X0();
+ void g65816i_38_M0X0();
+ void g65816i_39_M0X0();
+ void g65816i_3a_M0X0();
+ void g65816i_3b_M0X0();
+ void g65816i_3c_M0X0();
+ void g65816i_3d_M0X0();
+ void g65816i_3e_M0X0();
+ void g65816i_3f_M0X0();
+ void g65816i_40_M0X0();
+ void g65816i_41_M0X0();
+ void g65816i_42_M0X0();
+ void g65816i_43_M0X0();
+ void g65816i_44_M0X0();
+ void g65816i_45_M0X0();
+ void g65816i_46_M0X0();
+ void g65816i_47_M0X0();
+ void g65816i_48_M0X0();
+ void g65816i_49_M0X0();
+ void g65816i_4a_M0X0();
+ void g65816i_4b_M0X0();
+ void g65816i_4c_M0X0();
+ void g65816i_4d_M0X0();
+ void g65816i_4e_M0X0();
+ void g65816i_4f_M0X0();
+ void g65816i_50_M0X0();
+ void g65816i_51_M0X0();
+ void g65816i_52_M0X0();
+ void g65816i_53_M0X0();
+ void g65816i_54_M0X0();
+ void g65816i_55_M0X0();
+ void g65816i_56_M0X0();
+ void g65816i_57_M0X0();
+ void g65816i_58_M0X0();
+ void g65816i_59_M0X0();
+ void g65816i_5a_M0X0();
+ void g65816i_5b_M0X0();
+ void g65816i_5c_M0X0();
+ void g65816i_5d_M0X0();
+ void g65816i_5e_M0X0();
+ void g65816i_5f_M0X0();
+ void g65816i_60_M0X0();
+ void g65816i_61_M0X0();
+ void g65816i_62_M0X0();
+ void g65816i_63_M0X0();
+ void g65816i_64_M0X0();
+ void g65816i_65_M0X0();
+ void g65816i_66_M0X0();
+ void g65816i_67_M0X0();
+ void g65816i_68_M0X0();
+ void g65816i_69_M0X0();
+ void g65816i_6a_M0X0();
+ void g65816i_6b_M0X0();
+ void g65816i_6c_M0X0();
+ void g65816i_6d_M0X0();
+ void g65816i_6e_M0X0();
+ void g65816i_6f_M0X0();
+ void g65816i_70_M0X0();
+ void g65816i_71_M0X0();
+ void g65816i_72_M0X0();
+ void g65816i_73_M0X0();
+ void g65816i_74_M0X0();
+ void g65816i_75_M0X0();
+ void g65816i_76_M0X0();
+ void g65816i_77_M0X0();
+ void g65816i_78_M0X0();
+ void g65816i_79_M0X0();
+ void g65816i_7a_M0X0();
+ void g65816i_7b_M0X0();
+ void g65816i_7c_M0X0();
+ void g65816i_7d_M0X0();
+ void g65816i_7e_M0X0();
+ void g65816i_7f_M0X0();
+ void g65816i_80_M0X0();
+ void g65816i_81_M0X0();
+ void g65816i_82_M0X0();
+ void g65816i_83_M0X0();
+ void g65816i_84_M0X0();
+ void g65816i_85_M0X0();
+ void g65816i_86_M0X0();
+ void g65816i_87_M0X0();
+ void g65816i_88_M0X0();
+ void g65816i_89_M0X0();
+ void g65816i_8a_M0X0();
+ void g65816i_8b_M0X0();
+ void g65816i_8c_M0X0();
+ void g65816i_8d_M0X0();
+ void g65816i_8e_M0X0();
+ void g65816i_8f_M0X0();
+ void g65816i_90_M0X0();
+ void g65816i_91_M0X0();
+ void g65816i_92_M0X0();
+ void g65816i_93_M0X0();
+ void g65816i_94_M0X0();
+ void g65816i_95_M0X0();
+ void g65816i_96_M0X0();
+ void g65816i_97_M0X0();
+ void g65816i_98_M0X0();
+ void g65816i_99_M0X0();
+ void g65816i_9a_M0X0();
+ void g65816i_9b_M0X0();
+ void g65816i_9c_M0X0();
+ void g65816i_9d_M0X0();
+ void g65816i_9e_M0X0();
+ void g65816i_9f_M0X0();
+ void g65816i_a0_M0X0();
+ void g65816i_a1_M0X0();
+ void g65816i_a2_M0X0();
+ void g65816i_a3_M0X0();
+ void g65816i_a4_M0X0();
+ void g65816i_a5_M0X0();
+ void g65816i_a6_M0X0();
+ void g65816i_a7_M0X0();
+ void g65816i_a8_M0X0();
+ void g65816i_a9_M0X0();
+ void g65816i_aa_M0X0();
+ void g65816i_ab_M0X0();
+ void g65816i_ac_M0X0();
+ void g65816i_ad_M0X0();
+ void g65816i_ae_M0X0();
+ void g65816i_af_M0X0();
+ void g65816i_b0_M0X0();
+ void g65816i_b1_M0X0();
+ void g65816i_b2_M0X0();
+ void g65816i_b3_M0X0();
+ void g65816i_b4_M0X0();
+ void g65816i_b5_M0X0();
+ void g65816i_b6_M0X0();
+ void g65816i_b7_M0X0();
+ void g65816i_b8_M0X0();
+ void g65816i_b9_M0X0();
+ void g65816i_ba_M0X0();
+ void g65816i_bb_M0X0();
+ void g65816i_bc_M0X0();
+ void g65816i_bd_M0X0();
+ void g65816i_be_M0X0();
+ void g65816i_bf_M0X0();
+ void g65816i_c0_M0X0();
+ void g65816i_c1_M0X0();
+ void g65816i_c2_M0X0();
+ void g65816i_c3_M0X0();
+ void g65816i_c4_M0X0();
+ void g65816i_c5_M0X0();
+ void g65816i_c6_M0X0();
+ void g65816i_c7_M0X0();
+ void g65816i_c8_M0X0();
+ void g65816i_c9_M0X0();
+ void g65816i_ca_M0X0();
+ void g65816i_cb_M0X0();
+ void g65816i_cc_M0X0();
+ void g65816i_cd_M0X0();
+ void g65816i_ce_M0X0();
+ void g65816i_cf_M0X0();
+ void g65816i_d0_M0X0();
+ void g65816i_d1_M0X0();
+ void g65816i_d2_M0X0();
+ void g65816i_d3_M0X0();
+ void g65816i_d4_M0X0();
+ void g65816i_d5_M0X0();
+ void g65816i_d6_M0X0();
+ void g65816i_d7_M0X0();
+ void g65816i_d8_M0X0();
+ void g65816i_d9_M0X0();
+ void g65816i_da_M0X0();
+ void g65816i_db_M0X0();
+ void g65816i_dc_M0X0();
+ void g65816i_dd_M0X0();
+ void g65816i_de_M0X0();
+ void g65816i_df_M0X0();
+ void g65816i_e0_M0X0();
+ void g65816i_e1_M0X0();
+ void g65816i_e2_M0X0();
+ void g65816i_e3_M0X0();
+ void g65816i_e4_M0X0();
+ void g65816i_e5_M0X0();
+ void g65816i_e6_M0X0();
+ void g65816i_e7_M0X0();
+ void g65816i_e8_M0X0();
+ void g65816i_e9_M0X0();
+ void g65816i_ea_M0X0();
+ void g65816i_eb_M0X0();
+ void g65816i_ec_M0X0();
+ void g65816i_ed_M0X0();
+ void g65816i_ee_M0X0();
+ void g65816i_ef_M0X0();
+ void g65816i_f0_M0X0();
+ void g65816i_f1_M0X0();
+ void g65816i_f2_M0X0();
+ void g65816i_f3_M0X0();
+ void g65816i_f4_M0X0();
+ void g65816i_f5_M0X0();
+ void g65816i_f6_M0X0();
+ void g65816i_f7_M0X0();
+ void g65816i_f8_M0X0();
+ void g65816i_f9_M0X0();
+ void g65816i_fa_M0X0();
+ void g65816i_fb_M0X0();
+ void g65816i_fc_M0X0();
+ void g65816i_fd_M0X0();
+ void g65816i_fe_M0X0();
+ void g65816i_ff_M0X0();
+ void g65816i_00_M0X1();
+ void g65816i_01_M0X1();
+ void g65816i_02_M0X1();
+ void g65816i_03_M0X1();
+ void g65816i_04_M0X1();
+ void g65816i_05_M0X1();
+ void g65816i_06_M0X1();
+ void g65816i_07_M0X1();
+ void g65816i_08_M0X1();
+ void g65816i_09_M0X1();
+ void g65816i_0a_M0X1();
+ void g65816i_0b_M0X1();
+ void g65816i_0c_M0X1();
+ void g65816i_0d_M0X1();
+ void g65816i_0e_M0X1();
+ void g65816i_0f_M0X1();
+ void g65816i_10_M0X1();
+ void g65816i_11_M0X1();
+ void g65816i_12_M0X1();
+ void g65816i_13_M0X1();
+ void g65816i_14_M0X1();
+ void g65816i_15_M0X1();
+ void g65816i_16_M0X1();
+ void g65816i_17_M0X1();
+ void g65816i_18_M0X1();
+ void g65816i_19_M0X1();
+ void g65816i_1a_M0X1();
+ void g65816i_1b_M0X1();
+ void g65816i_1c_M0X1();
+ void g65816i_1d_M0X1();
+ void g65816i_1e_M0X1();
+ void g65816i_1f_M0X1();
+ void g65816i_20_M0X1();
+ void g65816i_21_M0X1();
+ void g65816i_22_M0X1();
+ void g65816i_23_M0X1();
+ void g65816i_24_M0X1();
+ void g65816i_25_M0X1();
+ void g65816i_26_M0X1();
+ void g65816i_27_M0X1();
+ void g65816i_28_M0X1();
+ void g65816i_29_M0X1();
+ void g65816i_2a_M0X1();
+ void g65816i_2b_M0X1();
+ void g65816i_2c_M0X1();
+ void g65816i_2d_M0X1();
+ void g65816i_2e_M0X1();
+ void g65816i_2f_M0X1();
+ void g65816i_30_M0X1();
+ void g65816i_31_M0X1();
+ void g65816i_32_M0X1();
+ void g65816i_33_M0X1();
+ void g65816i_34_M0X1();
+ void g65816i_35_M0X1();
+ void g65816i_36_M0X1();
+ void g65816i_37_M0X1();
+ void g65816i_38_M0X1();
+ void g65816i_39_M0X1();
+ void g65816i_3a_M0X1();
+ void g65816i_3b_M0X1();
+ void g65816i_3c_M0X1();
+ void g65816i_3d_M0X1();
+ void g65816i_3e_M0X1();
+ void g65816i_3f_M0X1();
+ void g65816i_40_M0X1();
+ void g65816i_41_M0X1();
+ void g65816i_42_M0X1();
+ void g65816i_43_M0X1();
+ void g65816i_44_M0X1();
+ void g65816i_45_M0X1();
+ void g65816i_46_M0X1();
+ void g65816i_47_M0X1();
+ void g65816i_48_M0X1();
+ void g65816i_49_M0X1();
+ void g65816i_4a_M0X1();
+ void g65816i_4b_M0X1();
+ void g65816i_4c_M0X1();
+ void g65816i_4d_M0X1();
+ void g65816i_4e_M0X1();
+ void g65816i_4f_M0X1();
+ void g65816i_50_M0X1();
+ void g65816i_51_M0X1();
+ void g65816i_52_M0X1();
+ void g65816i_53_M0X1();
+ void g65816i_54_M0X1();
+ void g65816i_55_M0X1();
+ void g65816i_56_M0X1();
+ void g65816i_57_M0X1();
+ void g65816i_58_M0X1();
+ void g65816i_59_M0X1();
+ void g65816i_5a_M0X1();
+ void g65816i_5b_M0X1();
+ void g65816i_5c_M0X1();
+ void g65816i_5d_M0X1();
+ void g65816i_5e_M0X1();
+ void g65816i_5f_M0X1();
+ void g65816i_60_M0X1();
+ void g65816i_61_M0X1();
+ void g65816i_62_M0X1();
+ void g65816i_63_M0X1();
+ void g65816i_64_M0X1();
+ void g65816i_65_M0X1();
+ void g65816i_66_M0X1();
+ void g65816i_67_M0X1();
+ void g65816i_68_M0X1();
+ void g65816i_69_M0X1();
+ void g65816i_6a_M0X1();
+ void g65816i_6b_M0X1();
+ void g65816i_6c_M0X1();
+ void g65816i_6d_M0X1();
+ void g65816i_6e_M0X1();
+ void g65816i_6f_M0X1();
+ void g65816i_70_M0X1();
+ void g65816i_71_M0X1();
+ void g65816i_72_M0X1();
+ void g65816i_73_M0X1();
+ void g65816i_74_M0X1();
+ void g65816i_75_M0X1();
+ void g65816i_76_M0X1();
+ void g65816i_77_M0X1();
+ void g65816i_78_M0X1();
+ void g65816i_79_M0X1();
+ void g65816i_7a_M0X1();
+ void g65816i_7b_M0X1();
+ void g65816i_7c_M0X1();
+ void g65816i_7d_M0X1();
+ void g65816i_7e_M0X1();
+ void g65816i_7f_M0X1();
+ void g65816i_80_M0X1();
+ void g65816i_81_M0X1();
+ void g65816i_82_M0X1();
+ void g65816i_83_M0X1();
+ void g65816i_84_M0X1();
+ void g65816i_85_M0X1();
+ void g65816i_86_M0X1();
+ void g65816i_87_M0X1();
+ void g65816i_88_M0X1();
+ void g65816i_89_M0X1();
+ void g65816i_8a_M0X1();
+ void g65816i_8b_M0X1();
+ void g65816i_8c_M0X1();
+ void g65816i_8d_M0X1();
+ void g65816i_8e_M0X1();
+ void g65816i_8f_M0X1();
+ void g65816i_90_M0X1();
+ void g65816i_91_M0X1();
+ void g65816i_92_M0X1();
+ void g65816i_93_M0X1();
+ void g65816i_94_M0X1();
+ void g65816i_95_M0X1();
+ void g65816i_96_M0X1();
+ void g65816i_97_M0X1();
+ void g65816i_98_M0X1();
+ void g65816i_99_M0X1();
+ void g65816i_9a_M0X1();
+ void g65816i_9b_M0X1();
+ void g65816i_9c_M0X1();
+ void g65816i_9d_M0X1();
+ void g65816i_9e_M0X1();
+ void g65816i_9f_M0X1();
+ void g65816i_a0_M0X1();
+ void g65816i_a1_M0X1();
+ void g65816i_a2_M0X1();
+ void g65816i_a3_M0X1();
+ void g65816i_a4_M0X1();
+ void g65816i_a5_M0X1();
+ void g65816i_a6_M0X1();
+ void g65816i_a7_M0X1();
+ void g65816i_a8_M0X1();
+ void g65816i_a9_M0X1();
+ void g65816i_aa_M0X1();
+ void g65816i_ab_M0X1();
+ void g65816i_ac_M0X1();
+ void g65816i_ad_M0X1();
+ void g65816i_ae_M0X1();
+ void g65816i_af_M0X1();
+ void g65816i_b0_M0X1();
+ void g65816i_b1_M0X1();
+ void g65816i_b2_M0X1();
+ void g65816i_b3_M0X1();
+ void g65816i_b4_M0X1();
+ void g65816i_b5_M0X1();
+ void g65816i_b6_M0X1();
+ void g65816i_b7_M0X1();
+ void g65816i_b8_M0X1();
+ void g65816i_b9_M0X1();
+ void g65816i_ba_M0X1();
+ void g65816i_bb_M0X1();
+ void g65816i_bc_M0X1();
+ void g65816i_bd_M0X1();
+ void g65816i_be_M0X1();
+ void g65816i_bf_M0X1();
+ void g65816i_c0_M0X1();
+ void g65816i_c1_M0X1();
+ void g65816i_c2_M0X1();
+ void g65816i_c3_M0X1();
+ void g65816i_c4_M0X1();
+ void g65816i_c5_M0X1();
+ void g65816i_c6_M0X1();
+ void g65816i_c7_M0X1();
+ void g65816i_c8_M0X1();
+ void g65816i_c9_M0X1();
+ void g65816i_ca_M0X1();
+ void g65816i_cb_M0X1();
+ void g65816i_cc_M0X1();
+ void g65816i_cd_M0X1();
+ void g65816i_ce_M0X1();
+ void g65816i_cf_M0X1();
+ void g65816i_d0_M0X1();
+ void g65816i_d1_M0X1();
+ void g65816i_d2_M0X1();
+ void g65816i_d3_M0X1();
+ void g65816i_d4_M0X1();
+ void g65816i_d5_M0X1();
+ void g65816i_d6_M0X1();
+ void g65816i_d7_M0X1();
+ void g65816i_d8_M0X1();
+ void g65816i_d9_M0X1();
+ void g65816i_da_M0X1();
+ void g65816i_db_M0X1();
+ void g65816i_dc_M0X1();
+ void g65816i_dd_M0X1();
+ void g65816i_de_M0X1();
+ void g65816i_df_M0X1();
+ void g65816i_e0_M0X1();
+ void g65816i_e1_M0X1();
+ void g65816i_e2_M0X1();
+ void g65816i_e3_M0X1();
+ void g65816i_e4_M0X1();
+ void g65816i_e5_M0X1();
+ void g65816i_e6_M0X1();
+ void g65816i_e7_M0X1();
+ void g65816i_e8_M0X1();
+ void g65816i_e9_M0X1();
+ void g65816i_ea_M0X1();
+ void g65816i_eb_M0X1();
+ void g65816i_ec_M0X1();
+ void g65816i_ed_M0X1();
+ void g65816i_ee_M0X1();
+ void g65816i_ef_M0X1();
+ void g65816i_f0_M0X1();
+ void g65816i_f1_M0X1();
+ void g65816i_f2_M0X1();
+ void g65816i_f3_M0X1();
+ void g65816i_f4_M0X1();
+ void g65816i_f5_M0X1();
+ void g65816i_f6_M0X1();
+ void g65816i_f7_M0X1();
+ void g65816i_f8_M0X1();
+ void g65816i_f9_M0X1();
+ void g65816i_fa_M0X1();
+ void g65816i_fb_M0X1();
+ void g65816i_fc_M0X1();
+ void g65816i_fd_M0X1();
+ void g65816i_fe_M0X1();
+ void g65816i_ff_M0X1();
+ void g65816i_00_M1X0();
+ void g65816i_01_M1X0();
+ void g65816i_02_M1X0();
+ void g65816i_03_M1X0();
+ void g65816i_04_M1X0();
+ void g65816i_05_M1X0();
+ void g65816i_06_M1X0();
+ void g65816i_07_M1X0();
+ void g65816i_08_M1X0();
+ void g65816i_09_M1X0();
+ void g65816i_0a_M1X0();
+ void g65816i_0b_M1X0();
+ void g65816i_0c_M1X0();
+ void g65816i_0d_M1X0();
+ void g65816i_0e_M1X0();
+ void g65816i_0f_M1X0();
+ void g65816i_10_M1X0();
+ void g65816i_11_M1X0();
+ void g65816i_12_M1X0();
+ void g65816i_13_M1X0();
+ void g65816i_14_M1X0();
+ void g65816i_15_M1X0();
+ void g65816i_16_M1X0();
+ void g65816i_17_M1X0();
+ void g65816i_18_M1X0();
+ void g65816i_19_M1X0();
+ void g65816i_1a_M1X0();
+ void g65816i_1b_M1X0();
+ void g65816i_1c_M1X0();
+ void g65816i_1d_M1X0();
+ void g65816i_1e_M1X0();
+ void g65816i_1f_M1X0();
+ void g65816i_20_M1X0();
+ void g65816i_21_M1X0();
+ void g65816i_22_M1X0();
+ void g65816i_23_M1X0();
+ void g65816i_24_M1X0();
+ void g65816i_25_M1X0();
+ void g65816i_26_M1X0();
+ void g65816i_27_M1X0();
+ void g65816i_28_M1X0();
+ void g65816i_29_M1X0();
+ void g65816i_2a_M1X0();
+ void g65816i_2b_M1X0();
+ void g65816i_2c_M1X0();
+ void g65816i_2d_M1X0();
+ void g65816i_2e_M1X0();
+ void g65816i_2f_M1X0();
+ void g65816i_30_M1X0();
+ void g65816i_31_M1X0();
+ void g65816i_32_M1X0();
+ void g65816i_33_M1X0();
+ void g65816i_34_M1X0();
+ void g65816i_35_M1X0();
+ void g65816i_36_M1X0();
+ void g65816i_37_M1X0();
+ void g65816i_38_M1X0();
+ void g65816i_39_M1X0();
+ void g65816i_3a_M1X0();
+ void g65816i_3b_M1X0();
+ void g65816i_3c_M1X0();
+ void g65816i_3d_M1X0();
+ void g65816i_3e_M1X0();
+ void g65816i_3f_M1X0();
+ void g65816i_40_M1X0();
+ void g65816i_41_M1X0();
+ void g65816i_42_M1X0();
+ void g65816i_43_M1X0();
+ void g65816i_44_M1X0();
+ void g65816i_45_M1X0();
+ void g65816i_46_M1X0();
+ void g65816i_47_M1X0();
+ void g65816i_48_M1X0();
+ void g65816i_49_M1X0();
+ void g65816i_4a_M1X0();
+ void g65816i_4b_M1X0();
+ void g65816i_4c_M1X0();
+ void g65816i_4d_M1X0();
+ void g65816i_4e_M1X0();
+ void g65816i_4f_M1X0();
+ void g65816i_50_M1X0();
+ void g65816i_51_M1X0();
+ void g65816i_52_M1X0();
+ void g65816i_53_M1X0();
+ void g65816i_54_M1X0();
+ void g65816i_55_M1X0();
+ void g65816i_56_M1X0();
+ void g65816i_57_M1X0();
+ void g65816i_58_M1X0();
+ void g65816i_59_M1X0();
+ void g65816i_5a_M1X0();
+ void g65816i_5b_M1X0();
+ void g65816i_5c_M1X0();
+ void g65816i_5d_M1X0();
+ void g65816i_5e_M1X0();
+ void g65816i_5f_M1X0();
+ void g65816i_60_M1X0();
+ void g65816i_61_M1X0();
+ void g65816i_62_M1X0();
+ void g65816i_63_M1X0();
+ void g65816i_64_M1X0();
+ void g65816i_65_M1X0();
+ void g65816i_66_M1X0();
+ void g65816i_67_M1X0();
+ void g65816i_68_M1X0();
+ void g65816i_69_M1X0();
+ void g65816i_6a_M1X0();
+ void g65816i_6b_M1X0();
+ void g65816i_6c_M1X0();
+ void g65816i_6d_M1X0();
+ void g65816i_6e_M1X0();
+ void g65816i_6f_M1X0();
+ void g65816i_70_M1X0();
+ void g65816i_71_M1X0();
+ void g65816i_72_M1X0();
+ void g65816i_73_M1X0();
+ void g65816i_74_M1X0();
+ void g65816i_75_M1X0();
+ void g65816i_76_M1X0();
+ void g65816i_77_M1X0();
+ void g65816i_78_M1X0();
+ void g65816i_79_M1X0();
+ void g65816i_7a_M1X0();
+ void g65816i_7b_M1X0();
+ void g65816i_7c_M1X0();
+ void g65816i_7d_M1X0();
+ void g65816i_7e_M1X0();
+ void g65816i_7f_M1X0();
+ void g65816i_80_M1X0();
+ void g65816i_81_M1X0();
+ void g65816i_82_M1X0();
+ void g65816i_83_M1X0();
+ void g65816i_84_M1X0();
+ void g65816i_85_M1X0();
+ void g65816i_86_M1X0();
+ void g65816i_87_M1X0();
+ void g65816i_88_M1X0();
+ void g65816i_89_M1X0();
+ void g65816i_8a_M1X0();
+ void g65816i_8b_M1X0();
+ void g65816i_8c_M1X0();
+ void g65816i_8d_M1X0();
+ void g65816i_8e_M1X0();
+ void g65816i_8f_M1X0();
+ void g65816i_90_M1X0();
+ void g65816i_91_M1X0();
+ void g65816i_92_M1X0();
+ void g65816i_93_M1X0();
+ void g65816i_94_M1X0();
+ void g65816i_95_M1X0();
+ void g65816i_96_M1X0();
+ void g65816i_97_M1X0();
+ void g65816i_98_M1X0();
+ void g65816i_99_M1X0();
+ void g65816i_9a_M1X0();
+ void g65816i_9b_M1X0();
+ void g65816i_9c_M1X0();
+ void g65816i_9d_M1X0();
+ void g65816i_9e_M1X0();
+ void g65816i_9f_M1X0();
+ void g65816i_a0_M1X0();
+ void g65816i_a1_M1X0();
+ void g65816i_a2_M1X0();
+ void g65816i_a3_M1X0();
+ void g65816i_a4_M1X0();
+ void g65816i_a5_M1X0();
+ void g65816i_a6_M1X0();
+ void g65816i_a7_M1X0();
+ void g65816i_a8_M1X0();
+ void g65816i_a9_M1X0();
+ void g65816i_aa_M1X0();
+ void g65816i_ab_M1X0();
+ void g65816i_ac_M1X0();
+ void g65816i_ad_M1X0();
+ void g65816i_ae_M1X0();
+ void g65816i_af_M1X0();
+ void g65816i_b0_M1X0();
+ void g65816i_b1_M1X0();
+ void g65816i_b2_M1X0();
+ void g65816i_b3_M1X0();
+ void g65816i_b4_M1X0();
+ void g65816i_b5_M1X0();
+ void g65816i_b6_M1X0();
+ void g65816i_b7_M1X0();
+ void g65816i_b8_M1X0();
+ void g65816i_b9_M1X0();
+ void g65816i_ba_M1X0();
+ void g65816i_bb_M1X0();
+ void g65816i_bc_M1X0();
+ void g65816i_bd_M1X0();
+ void g65816i_be_M1X0();
+ void g65816i_bf_M1X0();
+ void g65816i_c0_M1X0();
+ void g65816i_c1_M1X0();
+ void g65816i_c2_M1X0();
+ void g65816i_c3_M1X0();
+ void g65816i_c4_M1X0();
+ void g65816i_c5_M1X0();
+ void g65816i_c6_M1X0();
+ void g65816i_c7_M1X0();
+ void g65816i_c8_M1X0();
+ void g65816i_c9_M1X0();
+ void g65816i_ca_M1X0();
+ void g65816i_cb_M1X0();
+ void g65816i_cc_M1X0();
+ void g65816i_cd_M1X0();
+ void g65816i_ce_M1X0();
+ void g65816i_cf_M1X0();
+ void g65816i_d0_M1X0();
+ void g65816i_d1_M1X0();
+ void g65816i_d2_M1X0();
+ void g65816i_d3_M1X0();
+ void g65816i_d4_M1X0();
+ void g65816i_d5_M1X0();
+ void g65816i_d6_M1X0();
+ void g65816i_d7_M1X0();
+ void g65816i_d8_M1X0();
+ void g65816i_d9_M1X0();
+ void g65816i_da_M1X0();
+ void g65816i_db_M1X0();
+ void g65816i_dc_M1X0();
+ void g65816i_dd_M1X0();
+ void g65816i_de_M1X0();
+ void g65816i_df_M1X0();
+ void g65816i_e0_M1X0();
+ void g65816i_e1_M1X0();
+ void g65816i_e2_M1X0();
+ void g65816i_e3_M1X0();
+ void g65816i_e4_M1X0();
+ void g65816i_e5_M1X0();
+ void g65816i_e6_M1X0();
+ void g65816i_e7_M1X0();
+ void g65816i_e8_M1X0();
+ void g65816i_e9_M1X0();
+ void g65816i_ea_M1X0();
+ void g65816i_eb_M1X0();
+ void g65816i_ec_M1X0();
+ void g65816i_ed_M1X0();
+ void g65816i_ee_M1X0();
+ void g65816i_ef_M1X0();
+ void g65816i_f0_M1X0();
+ void g65816i_f1_M1X0();
+ void g65816i_f2_M1X0();
+ void g65816i_f3_M1X0();
+ void g65816i_f4_M1X0();
+ void g65816i_f5_M1X0();
+ void g65816i_f6_M1X0();
+ void g65816i_f7_M1X0();
+ void g65816i_f8_M1X0();
+ void g65816i_f9_M1X0();
+ void g65816i_fa_M1X0();
+ void g65816i_fb_M1X0();
+ void g65816i_fc_M1X0();
+ void g65816i_fd_M1X0();
+ void g65816i_fe_M1X0();
+ void g65816i_ff_M1X0();
+ void g65816i_00_M1X1();
+ void g65816i_01_M1X1();
+ void g65816i_02_M1X1();
+ void g65816i_03_M1X1();
+ void g65816i_04_M1X1();
+ void g65816i_05_M1X1();
+ void g65816i_06_M1X1();
+ void g65816i_07_M1X1();
+ void g65816i_08_M1X1();
+ void g65816i_09_M1X1();
+ void g65816i_0a_M1X1();
+ void g65816i_0b_M1X1();
+ void g65816i_0c_M1X1();
+ void g65816i_0d_M1X1();
+ void g65816i_0e_M1X1();
+ void g65816i_0f_M1X1();
+ void g65816i_10_M1X1();
+ void g65816i_11_M1X1();
+ void g65816i_12_M1X1();
+ void g65816i_13_M1X1();
+ void g65816i_14_M1X1();
+ void g65816i_15_M1X1();
+ void g65816i_16_M1X1();
+ void g65816i_17_M1X1();
+ void g65816i_18_M1X1();
+ void g65816i_19_M1X1();
+ void g65816i_1a_M1X1();
+ void g65816i_1b_M1X1();
+ void g65816i_1c_M1X1();
+ void g65816i_1d_M1X1();
+ void g65816i_1e_M1X1();
+ void g65816i_1f_M1X1();
+ void g65816i_20_M1X1();
+ void g65816i_21_M1X1();
+ void g65816i_22_M1X1();
+ void g65816i_23_M1X1();
+ void g65816i_24_M1X1();
+ void g65816i_25_M1X1();
+ void g65816i_26_M1X1();
+ void g65816i_27_M1X1();
+ void g65816i_28_M1X1();
+ void g65816i_29_M1X1();
+ void g65816i_2a_M1X1();
+ void g65816i_2b_M1X1();
+ void g65816i_2c_M1X1();
+ void g65816i_2d_M1X1();
+ void g65816i_2e_M1X1();
+ void g65816i_2f_M1X1();
+ void g65816i_30_M1X1();
+ void g65816i_31_M1X1();
+ void g65816i_32_M1X1();
+ void g65816i_33_M1X1();
+ void g65816i_34_M1X1();
+ void g65816i_35_M1X1();
+ void g65816i_36_M1X1();
+ void g65816i_37_M1X1();
+ void g65816i_38_M1X1();
+ void g65816i_39_M1X1();
+ void g65816i_3a_M1X1();
+ void g65816i_3b_M1X1();
+ void g65816i_3c_M1X1();
+ void g65816i_3d_M1X1();
+ void g65816i_3e_M1X1();
+ void g65816i_3f_M1X1();
+ void g65816i_40_M1X1();
+ void g65816i_41_M1X1();
+ void g65816i_42_M1X1();
+ void g65816i_43_M1X1();
+ void g65816i_44_M1X1();
+ void g65816i_45_M1X1();
+ void g65816i_46_M1X1();
+ void g65816i_47_M1X1();
+ void g65816i_48_M1X1();
+ void g65816i_49_M1X1();
+ void g65816i_4a_M1X1();
+ void g65816i_4b_M1X1();
+ void g65816i_4c_M1X1();
+ void g65816i_4d_M1X1();
+ void g65816i_4e_M1X1();
+ void g65816i_4f_M1X1();
+ void g65816i_50_M1X1();
+ void g65816i_51_M1X1();
+ void g65816i_52_M1X1();
+ void g65816i_53_M1X1();
+ void g65816i_54_M1X1();
+ void g65816i_55_M1X1();
+ void g65816i_56_M1X1();
+ void g65816i_57_M1X1();
+ void g65816i_58_M1X1();
+ void g65816i_59_M1X1();
+ void g65816i_5a_M1X1();
+ void g65816i_5b_M1X1();
+ void g65816i_5c_M1X1();
+ void g65816i_5d_M1X1();
+ void g65816i_5e_M1X1();
+ void g65816i_5f_M1X1();
+ void g65816i_60_M1X1();
+ void g65816i_61_M1X1();
+ void g65816i_62_M1X1();
+ void g65816i_63_M1X1();
+ void g65816i_64_M1X1();
+ void g65816i_65_M1X1();
+ void g65816i_66_M1X1();
+ void g65816i_67_M1X1();
+ void g65816i_68_M1X1();
+ void g65816i_69_M1X1();
+ void g65816i_6a_M1X1();
+ void g65816i_6b_M1X1();
+ void g65816i_6c_M1X1();
+ void g65816i_6d_M1X1();
+ void g65816i_6e_M1X1();
+ void g65816i_6f_M1X1();
+ void g65816i_70_M1X1();
+ void g65816i_71_M1X1();
+ void g65816i_72_M1X1();
+ void g65816i_73_M1X1();
+ void g65816i_74_M1X1();
+ void g65816i_75_M1X1();
+ void g65816i_76_M1X1();
+ void g65816i_77_M1X1();
+ void g65816i_78_M1X1();
+ void g65816i_79_M1X1();
+ void g65816i_7a_M1X1();
+ void g65816i_7b_M1X1();
+ void g65816i_7c_M1X1();
+ void g65816i_7d_M1X1();
+ void g65816i_7e_M1X1();
+ void g65816i_7f_M1X1();
+ void g65816i_80_M1X1();
+ void g65816i_81_M1X1();
+ void g65816i_82_M1X1();
+ void g65816i_83_M1X1();
+ void g65816i_84_M1X1();
+ void g65816i_85_M1X1();
+ void g65816i_86_M1X1();
+ void g65816i_87_M1X1();
+ void g65816i_88_M1X1();
+ void g65816i_89_M1X1();
+ void g65816i_8a_M1X1();
+ void g65816i_8b_M1X1();
+ void g65816i_8c_M1X1();
+ void g65816i_8d_M1X1();
+ void g65816i_8e_M1X1();
+ void g65816i_8f_M1X1();
+ void g65816i_90_M1X1();
+ void g65816i_91_M1X1();
+ void g65816i_92_M1X1();
+ void g65816i_93_M1X1();
+ void g65816i_94_M1X1();
+ void g65816i_95_M1X1();
+ void g65816i_96_M1X1();
+ void g65816i_97_M1X1();
+ void g65816i_98_M1X1();
+ void g65816i_99_M1X1();
+ void g65816i_9a_M1X1();
+ void g65816i_9b_M1X1();
+ void g65816i_9c_M1X1();
+ void g65816i_9d_M1X1();
+ void g65816i_9e_M1X1();
+ void g65816i_9f_M1X1();
+ void g65816i_a0_M1X1();
+ void g65816i_a1_M1X1();
+ void g65816i_a2_M1X1();
+ void g65816i_a3_M1X1();
+ void g65816i_a4_M1X1();
+ void g65816i_a5_M1X1();
+ void g65816i_a6_M1X1();
+ void g65816i_a7_M1X1();
+ void g65816i_a8_M1X1();
+ void g65816i_a9_M1X1();
+ void g65816i_aa_M1X1();
+ void g65816i_ab_M1X1();
+ void g65816i_ac_M1X1();
+ void g65816i_ad_M1X1();
+ void g65816i_ae_M1X1();
+ void g65816i_af_M1X1();
+ void g65816i_b0_M1X1();
+ void g65816i_b1_M1X1();
+ void g65816i_b2_M1X1();
+ void g65816i_b3_M1X1();
+ void g65816i_b4_M1X1();
+ void g65816i_b5_M1X1();
+ void g65816i_b6_M1X1();
+ void g65816i_b7_M1X1();
+ void g65816i_b8_M1X1();
+ void g65816i_b9_M1X1();
+ void g65816i_ba_M1X1();
+ void g65816i_bb_M1X1();
+ void g65816i_bc_M1X1();
+ void g65816i_bd_M1X1();
+ void g65816i_be_M1X1();
+ void g65816i_bf_M1X1();
+ void g65816i_c0_M1X1();
+ void g65816i_c1_M1X1();
+ void g65816i_c2_M1X1();
+ void g65816i_c3_M1X1();
+ void g65816i_c4_M1X1();
+ void g65816i_c5_M1X1();
+ void g65816i_c6_M1X1();
+ void g65816i_c7_M1X1();
+ void g65816i_c8_M1X1();
+ void g65816i_c9_M1X1();
+ void g65816i_ca_M1X1();
+ void g65816i_cb_M1X1();
+ void g65816i_cc_M1X1();
+ void g65816i_cd_M1X1();
+ void g65816i_ce_M1X1();
+ void g65816i_cf_M1X1();
+ void g65816i_d0_M1X1();
+ void g65816i_d1_M1X1();
+ void g65816i_d2_M1X1();
+ void g65816i_d3_M1X1();
+ void g65816i_d4_M1X1();
+ void g65816i_d5_M1X1();
+ void g65816i_d6_M1X1();
+ void g65816i_d7_M1X1();
+ void g65816i_d8_M1X1();
+ void g65816i_d9_M1X1();
+ void g65816i_da_M1X1();
+ void g65816i_db_M1X1();
+ void g65816i_dc_M1X1();
+ void g65816i_dd_M1X1();
+ void g65816i_de_M1X1();
+ void g65816i_df_M1X1();
+ void g65816i_e0_M1X1();
+ void g65816i_e1_M1X1();
+ void g65816i_e2_M1X1();
+ void g65816i_e3_M1X1();
+ void g65816i_e4_M1X1();
+ void g65816i_e5_M1X1();
+ void g65816i_e6_M1X1();
+ void g65816i_e7_M1X1();
+ void g65816i_e8_M1X1();
+ void g65816i_e9_M1X1();
+ void g65816i_ea_M1X1();
+ void g65816i_eb_M1X1();
+ void g65816i_ec_M1X1();
+ void g65816i_ed_M1X1();
+ void g65816i_ee_M1X1();
+ void g65816i_ef_M1X1();
+ void g65816i_f0_M1X1();
+ void g65816i_f1_M1X1();
+ void g65816i_f2_M1X1();
+ void g65816i_f3_M1X1();
+ void g65816i_f4_M1X1();
+ void g65816i_f5_M1X1();
+ void g65816i_f6_M1X1();
+ void g65816i_f7_M1X1();
+ void g65816i_f8_M1X1();
+ void g65816i_f9_M1X1();
+ void g65816i_fa_M1X1();
+ void g65816i_fb_M1X1();
+ void g65816i_fc_M1X1();
+ void g65816i_fd_M1X1();
+ void g65816i_fe_M1X1();
+ void g65816i_ff_M1X1();
+ void g65816i_00_E();
+ void g65816i_01_E();
+ void g65816i_02_E();
+ void g65816i_03_E();
+ void g65816i_04_E();
+ void g65816i_05_E();
+ void g65816i_06_E();
+ void g65816i_07_E();
+ void g65816i_08_E();
+ void g65816i_09_E();
+ void g65816i_0a_E();
+ void g65816i_0b_E();
+ void g65816i_0c_E();
+ void g65816i_0d_E();
+ void g65816i_0e_E();
+ void g65816i_0f_E();
+ void g65816i_10_E();
+ void g65816i_11_E();
+ void g65816i_12_E();
+ void g65816i_13_E();
+ void g65816i_14_E();
+ void g65816i_15_E();
+ void g65816i_16_E();
+ void g65816i_17_E();
+ void g65816i_18_E();
+ void g65816i_19_E();
+ void g65816i_1a_E();
+ void g65816i_1b_E();
+ void g65816i_1c_E();
+ void g65816i_1d_E();
+ void g65816i_1e_E();
+ void g65816i_1f_E();
+ void g65816i_20_E();
+ void g65816i_21_E();
+ void g65816i_22_E();
+ void g65816i_23_E();
+ void g65816i_24_E();
+ void g65816i_25_E();
+ void g65816i_26_E();
+ void g65816i_27_E();
+ void g65816i_28_E();
+ void g65816i_29_E();
+ void g65816i_2a_E();
+ void g65816i_2b_E();
+ void g65816i_2c_E();
+ void g65816i_2d_E();
+ void g65816i_2e_E();
+ void g65816i_2f_E();
+ void g65816i_30_E();
+ void g65816i_31_E();
+ void g65816i_32_E();
+ void g65816i_33_E();
+ void g65816i_34_E();
+ void g65816i_35_E();
+ void g65816i_36_E();
+ void g65816i_37_E();
+ void g65816i_38_E();
+ void g65816i_39_E();
+ void g65816i_3a_E();
+ void g65816i_3b_E();
+ void g65816i_3c_E();
+ void g65816i_3d_E();
+ void g65816i_3e_E();
+ void g65816i_3f_E();
+ void g65816i_40_E();
+ void g65816i_41_E();
+ void g65816i_42_E();
+ void g65816i_43_E();
+ void g65816i_44_E();
+ void g65816i_45_E();
+ void g65816i_46_E();
+ void g65816i_47_E();
+ void g65816i_48_E();
+ void g65816i_49_E();
+ void g65816i_4a_E();
+ void g65816i_4b_E();
+ void g65816i_4c_E();
+ void g65816i_4d_E();
+ void g65816i_4e_E();
+ void g65816i_4f_E();
+ void g65816i_50_E();
+ void g65816i_51_E();
+ void g65816i_52_E();
+ void g65816i_53_E();
+ void g65816i_54_E();
+ void g65816i_55_E();
+ void g65816i_56_E();
+ void g65816i_57_E();
+ void g65816i_58_E();
+ void g65816i_59_E();
+ void g65816i_5a_E();
+ void g65816i_5b_E();
+ void g65816i_5c_E();
+ void g65816i_5d_E();
+ void g65816i_5e_E();
+ void g65816i_5f_E();
+ void g65816i_60_E();
+ void g65816i_61_E();
+ void g65816i_62_E();
+ void g65816i_63_E();
+ void g65816i_64_E();
+ void g65816i_65_E();
+ void g65816i_66_E();
+ void g65816i_67_E();
+ void g65816i_68_E();
+ void g65816i_69_E();
+ void g65816i_6a_E();
+ void g65816i_6b_E();
+ void g65816i_6c_E();
+ void g65816i_6d_E();
+ void g65816i_6e_E();
+ void g65816i_6f_E();
+ void g65816i_70_E();
+ void g65816i_71_E();
+ void g65816i_72_E();
+ void g65816i_73_E();
+ void g65816i_74_E();
+ void g65816i_75_E();
+ void g65816i_76_E();
+ void g65816i_77_E();
+ void g65816i_78_E();
+ void g65816i_79_E();
+ void g65816i_7a_E();
+ void g65816i_7b_E();
+ void g65816i_7c_E();
+ void g65816i_7d_E();
+ void g65816i_7e_E();
+ void g65816i_7f_E();
+ void g65816i_80_E();
+ void g65816i_81_E();
+ void g65816i_82_E();
+ void g65816i_83_E();
+ void g65816i_84_E();
+ void g65816i_85_E();
+ void g65816i_86_E();
+ void g65816i_87_E();
+ void g65816i_88_E();
+ void g65816i_89_E();
+ void g65816i_8a_E();
+ void g65816i_8b_E();
+ void g65816i_8c_E();
+ void g65816i_8d_E();
+ void g65816i_8e_E();
+ void g65816i_8f_E();
+ void g65816i_90_E();
+ void g65816i_91_E();
+ void g65816i_92_E();
+ void g65816i_93_E();
+ void g65816i_94_E();
+ void g65816i_95_E();
+ void g65816i_96_E();
+ void g65816i_97_E();
+ void g65816i_98_E();
+ void g65816i_99_E();
+ void g65816i_9a_E();
+ void g65816i_9b_E();
+ void g65816i_9c_E();
+ void g65816i_9d_E();
+ void g65816i_9e_E();
+ void g65816i_9f_E();
+ void g65816i_a0_E();
+ void g65816i_a1_E();
+ void g65816i_a2_E();
+ void g65816i_a3_E();
+ void g65816i_a4_E();
+ void g65816i_a5_E();
+ void g65816i_a6_E();
+ void g65816i_a7_E();
+ void g65816i_a8_E();
+ void g65816i_a9_E();
+ void g65816i_aa_E();
+ void g65816i_ab_E();
+ void g65816i_ac_E();
+ void g65816i_ad_E();
+ void g65816i_ae_E();
+ void g65816i_af_E();
+ void g65816i_b0_E();
+ void g65816i_b1_E();
+ void g65816i_b2_E();
+ void g65816i_b3_E();
+ void g65816i_b4_E();
+ void g65816i_b5_E();
+ void g65816i_b6_E();
+ void g65816i_b7_E();
+ void g65816i_b8_E();
+ void g65816i_b9_E();
+ void g65816i_ba_E();
+ void g65816i_bb_E();
+ void g65816i_bc_E();
+ void g65816i_bd_E();
+ void g65816i_be_E();
+ void g65816i_bf_E();
+ void g65816i_c0_E();
+ void g65816i_c1_E();
+ void g65816i_c2_E();
+ void g65816i_c3_E();
+ void g65816i_c4_E();
+ void g65816i_c5_E();
+ void g65816i_c6_E();
+ void g65816i_c7_E();
+ void g65816i_c8_E();
+ void g65816i_c9_E();
+ void g65816i_ca_E();
+ void g65816i_cb_E();
+ void g65816i_cc_E();
+ void g65816i_cd_E();
+ void g65816i_ce_E();
+ void g65816i_cf_E();
+ void g65816i_d0_E();
+ void g65816i_d1_E();
+ void g65816i_d2_E();
+ void g65816i_d3_E();
+ void g65816i_d4_E();
+ void g65816i_d5_E();
+ void g65816i_d6_E();
+ void g65816i_d7_E();
+ void g65816i_d8_E();
+ void g65816i_d9_E();
+ void g65816i_da_E();
+ void g65816i_db_E();
+ void g65816i_dc_E();
+ void g65816i_dd_E();
+ void g65816i_de_E();
+ void g65816i_df_E();
+ void g65816i_e0_E();
+ void g65816i_e1_E();
+ void g65816i_e2_E();
+ void g65816i_e3_E();
+ void g65816i_e4_E();
+ void g65816i_e5_E();
+ void g65816i_e6_E();
+ void g65816i_e7_E();
+ void g65816i_e8_E();
+ void g65816i_e9_E();
+ void g65816i_ea_E();
+ void g65816i_eb_E();
+ void g65816i_ec_E();
+ void g65816i_ed_E();
+ void g65816i_ee_E();
+ void g65816i_ef_E();
+ void g65816i_f0_E();
+ void g65816i_f1_E();
+ void g65816i_f2_E();
+ void g65816i_f3_E();
+ void g65816i_f4_E();
+ void g65816i_f5_E();
+ void g65816i_f6_E();
+ void g65816i_f7_E();
+ void g65816i_f8_E();
+ void g65816i_f9_E();
+ void g65816i_fa_E();
+ void g65816i_fb_E();
+ void g65816i_fc_E();
+ void g65816i_fd_E();
+ void g65816i_fe_E();
+ void g65816i_ff_E();
+};
+
+
+class _5a22_device : public g65816_device
+{
+public:
+ _5a22_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
+
+ DECLARE_WRITE8_MEMBER( wrmpya_w );
+ DECLARE_WRITE8_MEMBER( wrmpyb_w );
+ DECLARE_WRITE8_MEMBER( wrdivl_w );
+ DECLARE_WRITE8_MEMBER( wrdivh_w );
+ DECLARE_WRITE8_MEMBER( wrdvdd_w );
+ DECLARE_WRITE8_MEMBER( memsel_w );
+ DECLARE_READ8_MEMBER( rddivl_r );
+ DECLARE_READ8_MEMBER( rddivh_r );
+ DECLARE_READ8_MEMBER( rdmpyl_r );
+ DECLARE_READ8_MEMBER( rdmpyh_r );
+
+ void set_5a22_map();
+
+protected:
+ // device-level overrides
+ virtual void device_start();
+ virtual void device_reset();
+
+ // device_state_interface overrides
+ virtual void state_import(const device_state_entry &entry);
+ virtual void state_export(const device_state_entry &entry);
+};
+
+
+extern const device_type G65816;
+extern const device_type _5A22;
+
+
+#define CPU_TYPE_G65816 0
+#define CPU_TYPE_5A22 1
+
+
+/* ======================================================================== */
+/* ============================== END OF FILE ============================= */
+/* ======================================================================== */
+
+#endif /* __G65816_H__ */
diff --git a/src/devices/cpu/g65816/g65816cm.h b/src/devices/cpu/g65816/g65816cm.h
new file mode 100644
index 00000000000..7cfbcdf2cfb
--- /dev/null
+++ b/src/devices/cpu/g65816/g65816cm.h
@@ -0,0 +1,262 @@
+// license:BSD-3-Clause
+// copyright-holders:Karl Stenerud
+#pragma once
+
+#ifndef __G65816CM_H__
+#define __G65816CM_H__
+
+
+#define g65816i_branching(A)
+#define g65816i_jumping(A)
+
+
+#undef G65816_CALL_DEBUGGER
+#define G65816_CALL_DEBUGGER(x) debugger_instruction_hook(this, x)
+
+#define g65816_read_8(addr) m_program->read_byte(addr)
+#define g65816_write_8(addr,data) m_program->write_byte(addr,data)
+#define g65816_read_8_immediate(A) m_program->read_byte(A)
+#define g65816_jumping(A)
+#define g65816_branching(A)
+
+
+/* ======================================================================== */
+/* ================================ INCLUDES ============================== */
+/* ======================================================================== */
+
+#include <limits.h>
+
+
+/* ======================================================================== */
+/* ================================ GENERAL =============================== */
+/* ======================================================================== */
+
+/* This should be set to the default size of your processor (min 16 bit) */
+#undef uint
+#define uint unsigned int
+
+#undef uint8
+#define uint8 unsigned char
+
+#undef int8
+
+/* Allow for architectures that don't have 8-bit sizes */
+#if UCHAR_MAX == 0xff
+#define int8 signed char
+#define MAKE_INT_8(A) (int8)((A)&0xff)
+#else
+#define int8 int
+INLINE int MAKE_INT_8(int A) {return (A & 0x80) ? A | ~0xff : A & 0xff;}
+#endif /* UCHAR_MAX == 0xff */
+
+#define MAKE_UINT_8(A) ((A)&0xff)
+#define MAKE_UINT_16(A) ((A)&0xffff)
+#define MAKE_UINT_24(A) ((A)&0xffffff)
+
+/* Bits */
+#define BIT_0 0x01
+#define BIT_1 0x02
+#define BIT_2 0x04
+#define BIT_3 0x08
+#define BIT_4 0x10
+#define BIT_5 0x20
+#define BIT_6 0x40
+#define BIT_7 0x80
+
+
+/* ======================================================================== */
+/* ================================== CPU ================================= */
+/* ======================================================================== */
+
+
+#define REGISTER_A m_a /* Accumulator */
+#define REGISTER_B m_b /* Accumulator hi byte */
+#define REGISTER_X m_x /* Index X Register */
+#define REGISTER_Y m_y /* Index Y Register */
+#define REGISTER_S m_s /* Stack Pointer */
+#define REGISTER_PC m_pc /* Program Counter */
+#define REGISTER_PPC m_ppc /* Previous Program Counter */
+#define REGISTER_PB m_pb /* Program Bank */
+#define REGISTER_DB m_db /* Data Bank */
+#define REGISTER_D m_d /* Direct Register */
+#define FLAG_E m_flag_e /* Emulation Mode Flag */
+#define FLAG_M m_flag_m /* Memory/Accumulator Select Flag */
+#define FLAG_X m_flag_x /* Index Select Flag */
+#define FLAG_N m_flag_n /* Negative Flag */
+#define FLAG_V m_flag_v /* Overflow Flag */
+#define FLAG_D m_flag_d /* Decimal Mode Flag */
+#define FLAG_I m_flag_i /* Interrupt Mask Flag */
+#define FLAG_Z m_flag_z /* Zero Flag (inverted) */
+#define FLAG_C m_flag_c /* Carry Flag */
+#define LINE_IRQ m_line_irq /* Status of the IRQ line */
+#define LINE_NMI m_line_nmi /* Status of the NMI line */
+#define REGISTER_IR m_ir /* Instruction Register */
+#define INT_ACK m_int_ack /* Interrupt Acknowledge function pointer */
+#define READ_VECTOR m_read_vector /* Vector reading override */
+#define CLOCKS m_ICount /* Clock cycles remaining */
+#define IRQ_DELAY m_irq_delay /* Delay 1 instruction before checking IRQ */
+#define CPU_STOPPED m_stopped /* Stopped status of the CPU */
+
+#define FTABLE_OPCODES m_opcodes
+#define FTABLE_GET_REG m_get_reg
+#define FTABLE_SET_REG m_set_reg
+#define FTABLE_SET_LINE m_set_line
+#define FTABLE_EXECUTE m_execute
+
+#define SRC m_source /* Source Operand */
+#define DST m_destination /* Destination Operand */
+
+#define STOP_LEVEL_WAI 1
+#define STOP_LEVEL_STOP 2
+
+#define EXECUTION_MODE_M0X0 0
+#define EXECUTION_MODE_M0X1 1
+#define EXECUTION_MODE_M1X0 2
+#define EXECUTION_MODE_M1X1 3
+#define EXECUTION_MODE_E 4
+
+#define VECTOR_RESET 0xfffc /* Reset */
+#define VECTOR_IRQ_E 0xfffe /* Interrupt Request */
+#define VECTOR_NMI_E 0xfffa /* Non-Maskable Interrupt */
+#define VECTOR_ABORT_E 0xfff8 /* ABORT asserted */
+#define VECTOR_BRK_E 0xfffe /* Break Instruction */
+#define VECTOR_COP_E 0xfff4 /* Coprocessor instruction */
+
+#define VECTOR_IRQ_N 0xffee /* Interrupt Request */
+#define VECTOR_NMI_N 0xffea /* Non-Maskable Interrupt */
+#define VECTOR_ABORT_N 0xffe8 /* ABORT asserted */
+#define VECTOR_BRK_N 0xffe6 /* Break Instruction */
+#define VECTOR_COP_N 0xffe4 /* Coprocessor instruction */
+
+
+/* ======================================================================== */
+/* ================================= CLOCK ================================ */
+/* ======================================================================== */
+
+#define CLK_OP 1
+#define CLK_R8 m_rw8_cycles
+#define CLK_R16 m_rw16_cycles
+#define CLK_R24 m_rw24_cycles
+#define CLK_W8 m_rw8_cycles
+#define CLK_W16 m_rw16_cycles
+#define CLK_W24 m_rw24_cycles
+#define CLK_RMW8 m_rw8_cycles+m_rw8_cycles + 1
+#define CLK_RMW16 m_rw16_cycles+m_rw16_cycles + 1
+
+#define CLK_IMPLIED 1
+#define CLK_IMPLIED 1
+#define CLK_RELATIVE_8 1
+#define CLK_RELATIVE_16 2
+#define CLK_IMM 0
+#define CLK_AI 4
+#define CLK_AXI 4
+#define CLK_A 2
+#define CLK_AL 3
+#define CLK_ALX 3
+#define CLK_AX 2
+#define CLK_AY 2
+#define CLK_D 1
+#define CLK_DI 3
+#define CLK_DIY 3
+#define CLK_DLI 4
+#define CLK_DLIY 4
+#define CLK_DX 2
+#define CLK_DXI 4
+#define CLK_DY 2
+#define CLK_S 2
+#define CLK_SIY 5
+
+/* AX and AY addressing modes take 1 extra cycle when writing */
+#define CLK_W_IMM 0
+#define CLK_W_AI 4
+#define CLK_W_AXI 4
+#define CLK_W_A 2
+#define CLK_W_AL 3
+#define CLK_W_ALX 3
+#define CLK_W_AX 3
+#define CLK_W_AY 3
+#define CLK_W_D 1
+#define CLK_W_DI 3
+#define CLK_W_DIY 3
+#define CLK_W_DLI 4
+#define CLK_W_DLIY 4
+#define CLK_W_DX 2
+#define CLK_W_DXI 4
+#define CLK_W_DY 2
+#define CLK_W_S 2
+#define CLK_W_SIY 5
+
+#define CLK(A) CLOCKS -= (m_cpu_type == CPU_TYPE_G65816 ? A : A*6)
+#define CLK_BUS(A) CLOCKS -= A
+#define USE_ALL_CLKS() CLOCKS = 0
+
+
+/* ======================================================================== */
+/* ============================ STATUS REGISTER =========================== */
+/* ======================================================================== */
+
+/* Flag positions in Processor Status Register */
+/* common */
+#define FLAGPOS_N BIT_7 /* Negative */
+#define FLAGPOS_V BIT_6 /* Overflow */
+#define FLAGPOS_D BIT_3 /* Decimal Mode */
+#define FLAGPOS_I BIT_2 /* Interrupt Mask */
+#define FLAGPOS_Z BIT_1 /* Zero */
+#define FLAGPOS_C BIT_0 /* Carry */
+/* emulation */
+#define FLAGPOS_R BIT_5 /* Reserved */
+#define FLAGPOS_B BIT_4 /* BRK Instruction */
+/* native */
+#define FLAGPOS_M BIT_5 /* Mem/Reg Select */
+#define FLAGPOS_X BIT_4 /* Index Select */
+
+#define EFLAG_SET 1
+#define EFLAG_CLEAR 0
+#define MFLAG_SET FLAGPOS_M
+#define MFLAG_CLEAR 0
+#define XFLAG_SET FLAGPOS_X
+#define XFLAG_CLEAR 0
+#define NFLAG_SET 0x80
+#define NFLAG_CLEAR 0
+#define VFLAG_SET 0x80
+#define VFLAG_CLEAR 0
+#define DFLAG_SET FLAGPOS_D
+#define DFLAG_CLEAR 0
+#define IFLAG_SET FLAGPOS_I
+#define IFLAG_CLEAR 0
+#define BFLAG_SET FLAGPOS_B
+#define BFLAG_CLEAR 0
+#define ZFLAG_SET 0
+#define ZFLAG_CLEAR 1
+#define CFLAG_SET 0x100
+#define CFLAG_CLEAR 0
+
+/* Codition code tests */
+#define COND_CC() (!(FLAG_C&0x100)) /* Carry Clear */
+#define COND_CS() (FLAG_C&0x100) /* Carry Set */
+#define COND_EQ() (!FLAG_Z) /* Equal */
+#define COND_NE() FLAG_Z /* Not Equal */
+#define COND_MI() (FLAG_N&0x80) /* Minus */
+#define COND_PL() (!(FLAG_N&0x80)) /* Plus */
+#define COND_VC() (!(FLAG_V&0x80)) /* Overflow Clear */
+#define COND_VS() (FLAG_V&0x80) /* Overflow Set */
+
+/* Set Overflow flag in math operations */
+#define VFLAG_ADD_8(S, D, R) ((S^R) & (D^R))
+#define VFLAG_ADD_16(S, D, R) (((S^R) & (D^R))>>8)
+#define VFLAG_SUB_8(S, D, R) ((S^D) & (R^D))
+#define VFLAG_SUB_16(S, D, R) (((S^D) & (R^D))>>8)
+
+#define CFLAG_8(A) (A)
+#define CFLAG_16(A) ((A)>>8)
+#define NFLAG_8(A) (A)
+#define NFLAG_16(A) ((A)>>8)
+
+#define CFLAG_AS_1() ((FLAG_C>>8)&1)
+
+
+
+/* ======================================================================== */
+/* ================================== CPU ================================= */
+/* ======================================================================== */
+#endif /* __G65816CM_H__ */
diff --git a/src/devices/cpu/g65816/g65816ds.c b/src/devices/cpu/g65816/g65816ds.c
new file mode 100644
index 00000000000..17af208a822
--- /dev/null
+++ b/src/devices/cpu/g65816/g65816ds.c
@@ -0,0 +1,349 @@
+// license:BSD-3-Clause
+// copyright-holders:Karl Stenerud
+/* ======================================================================== */
+/* =============================== COPYRIGHT ============================== */
+/* ======================================================================== */
+/*
+
+G65C816 CPU Emulator V0.90
+
+Copyright Karl Stenerud
+All rights reserved.
+
+*/
+
+
+#include "emu.h"
+#include "g65816ds.h"
+
+#ifdef SEC
+#undef SEC
+#endif
+
+#define ADDRESS_65816(A) ((A)&0xffffff)
+
+
+struct g65816_opcode_struct
+{
+ unsigned char name;
+ unsigned char flag;
+ unsigned char ea;
+};
+
+enum
+{
+ IMP , ACC , RELB, RELW, IMM , A , AI , AL , ALX , AX , AXI ,
+ AY , D , DI , DIY , DLI , DLIY, DX , DXI , DY , S , SIY ,
+ SIG /*, MVN , MVP , PEA , PEI , PER */
+};
+
+enum
+{
+ I, /* ignore */
+ M, /* check m bit */
+ X /* check x bit */
+};
+
+enum
+{
+ ADC , AND , ASL , BCC , BCS , BEQ , BIT , BMI , BNE , BPL , BRA ,
+ BRK , BRL , BVC , BVS , CLC , CLD , CLI , CLV , CMP , COP , CPX ,
+ CPY , DEA , DEC , DEX , DEY , EOR , INA , INC , INX , INY , JML ,
+ JMP , JSL , JSR , LDA , LDX , LDY , LSR , MVN , MVP , NOP , ORA ,
+ PEA , PEI , PER , PHA , PHB , PHD , PHK , PHP , PHX , PHY , PLA ,
+ PLB , PLD , PLP , PLX , PLY , REP , ROL , ROR , RTI , RTL , RTS ,
+ SBC , SEC , SED , SEI , SEP , STA , STP , STX , STY , STZ , TAX ,
+ TAY , TCS , TCD , TDC , TRB , TSB , TSC , TSX , TXA , TXS , TXY ,
+ TYA , TYX , WAI , WDM , XBA , XCE
+};
+
+static const char *const g_opnames[] =
+{
+ "ADC", "AND", "ASL", "BCC", "BCS", "BEQ", "BIT", "BMI", "BNE", "BPL", "BRA",
+ "BRK", "BRL", "BVC", "BVS", "CLC", "CLD", "CLI", "CLV", "CMP", "COP", "CPX",
+ "CPY", "DEA", "DEC", "DEX", "DEY", "EOR", "INA", "INC", "INX", "INY", "JML",
+ "JMP", "JSL", "JSR", "LDA", "LDX", "LDY", "LSR", "MVN", "MVP", "NOP", "ORA",
+ "PEA", "PEI", "PER", "PHA", "PHB", "PHD", "PHK", "PHP", "PHX", "PHY", "PLA",
+ "PLB", "PLD", "PLP", "PLX", "PLY", "REP", "ROL", "ROR", "RTI", "RTL", "RTS",
+ "SBC", "SEC", "SED", "SEI", "SEP", "STA", "STP", "STX", "STY", "STZ", "TAX",
+ "TAY", "TCS", "TCD", "TDC", "TRB", "TSB", "TSC", "TSX", "TXA", "TXS", "TXY",
+ "TYA", "TYX", "WAI", "WDM", "XBA", "XCE"
+};
+
+static const g65816_opcode_struct g_opcodes[256] =
+{
+ {BRK, I, SIG }, {ORA, M, DXI }, {COP, I, SIG }, {ORA, M, S },
+ {TSB, M, D }, {ORA, M, D }, {ASL, M, D }, {ORA, M, DLI },
+ {PHP, I, IMP }, {ORA, M, IMM }, {ASL, M, ACC }, {PHD, I, IMP },
+ {TSB, M, A }, {ORA, M, A }, {ASL, M, A }, {ORA, M, AL },
+ {BPL, I, RELB}, {ORA, M, DIY }, {ORA, M, DI }, {ORA, M, SIY },
+ {TRB, M, D }, {ORA, M, DX }, {ASL, M, DX }, {ORA, M, DLIY},
+ {CLC, I, IMP }, {ORA, M, AY }, {INA, I, IMP }, {TCS, I, IMP },
+ {TRB, M, A }, {ORA, M, AX }, {ASL, M, AX }, {ORA, M, ALX },
+ {JSR, I, A }, {AND, M, DXI }, {JSL, I, AL }, {AND, M, S },
+ {BIT, M, D }, {AND, M, D }, {ROL, M, D }, {AND, M, DLI },
+ {PLP, I, IMP }, {AND, M, IMM }, {ROL, M, ACC }, {PLD, I, IMP },
+ {BIT, M, A }, {AND, M, A }, {ROL, M, A }, {AND, M, AL },
+ {BMI, I, RELB}, {AND, M, DIY }, {AND, M, DI }, {AND, M, SIY },
+ {BIT, M, DX }, {AND, M, DX }, {ROL, M, DX }, {AND, M, DLIY},
+ {SEC, I, IMP }, {AND, M, AY }, {DEA, I, IMP }, {TSC, I, IMP },
+ {BIT, M, AX }, {AND, M, AX }, {ROL, M, AX }, {AND, M, ALX },
+ {RTI, I, IMP }, {EOR, M, DXI }, {WDM, I, IMP }, {EOR, M, S },
+ {MVP, I, MVP }, {EOR, M, D }, {LSR, M, D }, {EOR, M, DLI },
+ {PHA, I, IMP }, {EOR, M, IMM }, {LSR, M, ACC }, {PHK, I, IMP },
+ {JMP, I, A }, {EOR, M, A }, {LSR, M, A }, {EOR, M, AL },
+ {BVC, I, RELB}, {EOR, M, DIY }, {EOR, M, DI }, {EOR, M, SIY },
+ {MVN, I, MVN }, {EOR, M, DX }, {LSR, M, DX }, {EOR, M, DLIY},
+ {CLI, I, IMP }, {EOR, M, AY }, {PHY, I, IMP }, {TCD, I, IMP },
+ {JMP, I, AL }, {EOR, M, AX }, {LSR, M, AX }, {EOR, M, ALX },
+ {RTS, I, IMP }, {ADC, M, DXI }, {PER, I, PER }, {ADC, M, S },
+ {STZ, M, D }, {ADC, M, D }, {ROR, M, D }, {ADC, M, DLI },
+ {PLA, I, IMP }, {ADC, M, IMM }, {ROR, M, ACC }, {RTL, I, IMP },
+ {JMP, I, AI }, {ADC, M, A }, {ROR, M, A }, {ADC, M, AL },
+ {BVS, I, RELB}, {ADC, M, DIY }, {ADC, M, DI }, {ADC, M, SIY },
+ {STZ, M, DX }, {ADC, M, DX }, {ROR, M, DX }, {ADC, M, DLIY},
+ {SEI, I, IMP }, {ADC, M, AY }, {PLY, I, IMP }, {TDC, I, IMP },
+ {JMP, I, AXI }, {ADC, M, AX }, {ROR, M, AX }, {ADC, M, ALX },
+ {BRA, I, RELB}, {STA, M, DXI }, {BRL, I, RELW}, {STA, M, S },
+ {STY, X, D }, {STA, M, D }, {STX, X, D }, {STA, M, DLI },
+ {DEY, I, IMP }, {BIT, M, IMM }, {TXA, I, IMP }, {PHB, I, IMP },
+ {STY, X, A }, {STA, M, A }, {STX, X, A }, {STA, M, AL },
+ {BCC, I, RELB}, {STA, M, DIY }, {STA, M, DI }, {STA, M, SIY },
+ {STY, X, DX }, {STA, M, DX }, {STX, X, DY }, {STA, M, DLIY},
+ {TYA, I, IMP }, {STA, M, AY }, {TXS, I, IMP }, {TXY, I, IMP },
+ {STZ, M, A }, {STA, M, AX }, {STZ, M, AX }, {STA, M, ALX },
+ {LDY, X, IMM }, {LDA, M, DXI }, {LDX, X, IMM }, {LDA, M, S },
+ {LDY, X, D }, {LDA, M, D }, {LDX, X, D }, {LDA, M, DLI },
+ {TAY, I, IMP }, {LDA, M, IMM }, {TAX, I, IMP }, {PLB, I, IMP },
+ {LDY, X, A }, {LDA, M, A }, {LDX, X, A }, {LDA, M, AL },
+ {BCS, I, RELB}, {LDA, M, DIY }, {LDA, M, DI }, {LDA, M, SIY },
+ {LDY, X, DX }, {LDA, M, DX }, {LDX, X, DY }, {LDA, M, DLIY},
+ {CLV, I, IMP }, {LDA, M, AY }, {TSX, I, IMP }, {TYX, I, IMP },
+ {LDY, X, AX }, {LDA, M, AX }, {LDX, X, AY }, {LDA, M, ALX },
+ {CPY, X, IMM }, {CMP, M, DXI }, {REP, I, IMM }, {CMP, M, S },
+ {CPY, X, D }, {CMP, M, D }, {DEC, M, D }, {CMP, M, DLI },
+ {INY, I, IMP }, {CMP, M, IMM }, {DEX, I, IMP }, {WAI, I, IMP },
+ {CPY, X, A }, {CMP, M, A }, {DEC, M, A }, {CMP, M, AL },
+ {BNE, I, RELB}, {CMP, M, DIY }, {CMP, M, DI }, {CMP, M, SIY },
+ {PEI, I, PEI }, {CMP, M, DX }, {DEC, M, DX }, {CMP, M, DLIY},
+ {CLD, I, IMP }, {CMP, M, AY }, {PHX, I, IMP }, {STP, I, IMP },
+ {JML, I, AI }, {CMP, M, AX }, {DEC, M, AX }, {CMP, M, ALX },
+ {CPX, X, IMM }, {SBC, M, DXI }, {SEP, I, IMM }, {SBC, M, S },
+ {CPX, X, D }, {SBC, M, D }, {INC, M, D }, {SBC, M, DLI },
+ {INX, M, IMP }, {SBC, M, IMM }, {NOP, I, IMP }, {XBA, I, IMP },
+ {CPX, X, A }, {SBC, M, A }, {INC, M, A }, {SBC, M, AL },
+ {BEQ, I, RELB}, {SBC, M, DIY }, {SBC, M, DI }, {SBC, M, SIY },
+ {PEA, I, PEA }, {SBC, M, DX }, {INC, M, DX }, {SBC, M, DLIY},
+ {SED, I, IMP }, {SBC, M, AY }, {PLX, I, IMP }, {XCE, I, IMP },
+ {JSR, I, AXI }, {SBC, M, AX }, {INC, M, AX }, {SBC, M, ALX }
+};
+
+static const UINT8 *base_oprom;
+static UINT32 base_pc;
+
+INLINE unsigned int read_8(unsigned int address)
+{
+ address = ADDRESS_65816(address);
+ return base_oprom[address - base_pc];
+}
+
+INLINE unsigned int read_16(unsigned int address)
+{
+ unsigned int val = read_8(address);
+ return val | (read_8(address+1)<<8);
+}
+
+INLINE unsigned int read_24(unsigned int address)
+{
+ unsigned int val = read_8(address);
+ val |= (read_8(address+1)<<8);
+ return val | (read_8(address+2)<<16);
+}
+
+INLINE char* int_8_str(unsigned int val)
+{
+ static char str[20];
+
+ val &= 0xff;
+
+ if(val & 0x80)
+ sprintf(str, "-$%x", (0-val) & 0x7f);
+ else
+ sprintf(str, "$%x", val & 0x7f);
+
+ return str;
+}
+
+INLINE char* int_16_str(unsigned int val)
+{
+ static char str[20];
+
+ val &= 0xffff;
+
+ if(val & 0x8000)
+ sprintf(str, "-$%x", (0-val) & 0x7fff);
+ else
+ sprintf(str, "$%x", val & 0x7fff);
+
+ return str;
+}
+
+
+unsigned g65816_disassemble(char* buff, unsigned int pc, unsigned int pb, const UINT8 *oprom, int m_flag, int x_flag)
+{
+ unsigned int instruction;
+ const g65816_opcode_struct* opcode;
+ char* ptr;
+ int var;
+ int length = 1;
+ unsigned int address;
+ unsigned dasm_flags;
+
+ pb <<= 16;
+ address = pc | pb;
+
+ base_oprom = oprom;
+ base_pc = address;
+
+ instruction = read_8(address);
+ opcode = g_opcodes + instruction;
+
+ strcpy(buff, g_opnames[opcode->name]);
+ ptr = buff + strlen(buff);
+
+ switch(opcode->name)
+ {
+ case JSR:
+ case JSL:
+ dasm_flags = DASMFLAG_STEP_OVER;
+ break;
+
+ case RTI:
+ case RTL:
+ case RTS:
+ dasm_flags = DASMFLAG_STEP_OUT;
+ break;
+
+ default:
+ dasm_flags = 0;
+ break;
+ }
+
+ switch(opcode->ea)
+ {
+ case IMP :
+ break;
+ case ACC :
+ sprintf(ptr, "A");
+ break;
+ case RELB:
+ var = (INT8) read_8(address+1);
+ length++;
+ sprintf(ptr, " %06x (%s)", pb | ((pc + length + var)&0xffff), int_8_str(var));
+ break;
+ case RELW:
+ case PER :
+ var = read_16(address+1);
+ length += 2;
+ sprintf(ptr, " %06x (%s)", pb | ((pc + length + var)&0xffff), int_16_str(var));
+ break;
+ case IMM :
+ if((opcode->flag == M && !m_flag) || (opcode->flag == X && !x_flag))
+ {
+ sprintf(ptr, " #$%04x", read_16(address+1));
+ length += 2;
+ }
+ else
+ {
+ sprintf(ptr, " #$%02x", read_8(address+1));
+ length++;
+ }
+ break;
+ case A :
+ case PEA :
+ sprintf(ptr, " $%04x", read_16(address+1));
+ length += 2;
+ break;
+ case AI :
+ sprintf(ptr, " ($%04x)", read_16(address+1));
+ length += 2;
+ break;
+ case AL :
+ sprintf(ptr, " $%06x", read_24(address+1));
+ length += 3;
+ break;
+ case ALX :
+ sprintf(ptr, " $%06x,X", read_24(address+1));
+ length += 3;
+ break;
+ case AX :
+ sprintf(ptr, " $%04x,X", read_16(address+1));
+ length += 2;
+ break;
+ case AXI :
+ sprintf(ptr, " ($%04x,X)", read_16(address+1));
+ length += 2;
+ break;
+ case AY :
+ sprintf(ptr, " $%04x,Y", read_16(address+1));
+ length += 2;
+ break;
+ case D :
+ sprintf(ptr, " $%02x", read_8(address+1));
+ length++;
+ break;
+ case DI :
+ case PEI :
+ sprintf(ptr, " ($%02x)", read_8(address+1));
+ length++;
+ break;
+ case DIY :
+ sprintf(ptr, " ($%02x),Y", read_8(address+1));
+ length++;
+ break;
+ case DLI :
+ sprintf(ptr, " [$%02x]", read_8(address+1));
+ length++;
+ break;
+ case DLIY:
+ sprintf(ptr, " [$%02x],Y", read_8(address+1));
+ length++;
+ break;
+ case DX :
+ sprintf(ptr, " $%02x,X", read_8(address+1));
+ length++;
+ break;
+ case DXI :
+ sprintf(ptr, " ($%02x,X)", read_8(address+1));
+ length++;
+ break;
+ case DY :
+ sprintf(ptr, " $%02x,Y", read_8(address+1));
+ length++;
+ break;
+ case S :
+ sprintf(ptr, " %s,S", int_8_str(read_8(address+1)));
+ length++;
+ break;
+ case SIY :
+ sprintf(ptr, " (%s,S),Y", int_8_str(read_8(address+1)));
+ length++;
+ break;
+ case SIG :
+ sprintf(ptr, " #$%02x", read_8(address+1));
+ length++;
+ break;
+ case MVN :
+ case MVP :
+ sprintf(ptr, " $%02x, $%02x", read_8(address+2), read_8(address+1));
+ length += 2;
+ break;
+ }
+
+ return length | DASMFLAG_SUPPORTED | dasm_flags;
+}
+
+CPU_DISASSEMBLE( g65816_generic )
+{
+ return g65816_disassemble(buffer, (pc & 0x00ffff), (pc & 0xff0000) >> 16, oprom, 0, 0);
+}
diff --git a/src/devices/cpu/g65816/g65816ds.h b/src/devices/cpu/g65816/g65816ds.h
new file mode 100644
index 00000000000..58b47752ca5
--- /dev/null
+++ b/src/devices/cpu/g65816/g65816ds.h
@@ -0,0 +1,22 @@
+// license:BSD-3-Clause
+// copyright-holders:Karl Stenerud
+#pragma once
+
+#ifndef __G65816DS_H__
+#define __G65816DS_H__
+/* ======================================================================== */
+/* =============================== COPYRIGHT ============================== */
+/* ======================================================================== */
+/*
+
+G65C816 CPU Emulator V0.92
+
+Copyright Karl Stenerud
+All rights reserved.
+
+*/
+
+unsigned g65816_disassemble(char* buff, unsigned int pc, unsigned int pb, const UINT8 *oprom, int m_flag, int x_flag);
+
+
+#endif /* __G65816DS_H__ */
diff --git a/src/devices/cpu/g65816/g65816o0.c b/src/devices/cpu/g65816/g65816o0.c
new file mode 100644
index 00000000000..5829325bd37
--- /dev/null
+++ b/src/devices/cpu/g65816/g65816o0.c
@@ -0,0 +1,8 @@
+// license:BSD-3-Clause
+// copyright-holders:Karl Stenerud
+#include "emu.h"
+#include "debugger.h"
+#include "g65816.h"
+#include "g65816cm.h"
+#define EXECUTION_MODE EXECUTION_MODE_M0X0
+#include "g65816op.h"
diff --git a/src/devices/cpu/g65816/g65816o1.c b/src/devices/cpu/g65816/g65816o1.c
new file mode 100644
index 00000000000..4b277c9abf2
--- /dev/null
+++ b/src/devices/cpu/g65816/g65816o1.c
@@ -0,0 +1,8 @@
+// license:BSD-3-Clause
+// copyright-holders:Karl Stenerud
+#include "emu.h"
+#include "debugger.h"
+#include "g65816.h"
+#include "g65816cm.h"
+#define EXECUTION_MODE EXECUTION_MODE_M0X1
+#include "g65816op.h"
diff --git a/src/devices/cpu/g65816/g65816o2.c b/src/devices/cpu/g65816/g65816o2.c
new file mode 100644
index 00000000000..63a8157e961
--- /dev/null
+++ b/src/devices/cpu/g65816/g65816o2.c
@@ -0,0 +1,8 @@
+// license:BSD-3-Clause
+// copyright-holders:Karl Stenerud
+#include "emu.h"
+#include "debugger.h"
+#include "g65816.h"
+#include "g65816cm.h"
+#define EXECUTION_MODE EXECUTION_MODE_M1X0
+#include "g65816op.h"
diff --git a/src/devices/cpu/g65816/g65816o3.c b/src/devices/cpu/g65816/g65816o3.c
new file mode 100644
index 00000000000..24cdebf05b6
--- /dev/null
+++ b/src/devices/cpu/g65816/g65816o3.c
@@ -0,0 +1,8 @@
+// license:BSD-3-Clause
+// copyright-holders:Karl Stenerud
+#include "emu.h"
+#include "debugger.h"
+#include "g65816.h"
+#include "g65816cm.h"
+#define EXECUTION_MODE EXECUTION_MODE_M1X1
+#include "g65816op.h"
diff --git a/src/devices/cpu/g65816/g65816o4.c b/src/devices/cpu/g65816/g65816o4.c
new file mode 100644
index 00000000000..60262c859fb
--- /dev/null
+++ b/src/devices/cpu/g65816/g65816o4.c
@@ -0,0 +1,8 @@
+// license:BSD-3-Clause
+// copyright-holders:Karl Stenerud
+#include "emu.h"
+#include "debugger.h"
+#include "g65816.h"
+#include "g65816cm.h"
+#define EXECUTION_MODE EXECUTION_MODE_E
+#include "g65816op.h"
diff --git a/src/devices/cpu/g65816/g65816op.h b/src/devices/cpu/g65816/g65816op.h
new file mode 100644
index 00000000000..81f887b3e12
--- /dev/null
+++ b/src/devices/cpu/g65816/g65816op.h
@@ -0,0 +1,1961 @@
+// license:BSD-3-Clause
+// copyright-holders:Karl Stenerud
+
+/* ======================================================================== */
+/* ============================= CONFIGURATION ============================ */
+/* ======================================================================== */
+
+#undef FLAG_SET_E
+#undef FLAG_SET_M
+#undef FLAG_SET_X
+#if EXECUTION_MODE == EXECUTION_MODE_E
+#define FLAG_SET_E 1
+#define FLAG_SET_M 1
+#define FLAG_SET_X 1
+#elif EXECUTION_MODE == EXECUTION_MODE_M0X0
+#define FLAG_SET_E 0
+#define FLAG_SET_M 0
+#define FLAG_SET_X 0
+#elif EXECUTION_MODE == EXECUTION_MODE_M0X1
+#define FLAG_SET_E 0
+#define FLAG_SET_M 0
+#define FLAG_SET_X 1
+#elif EXECUTION_MODE == EXECUTION_MODE_M1X0
+#define FLAG_SET_E 0
+#define FLAG_SET_M 1
+#define FLAG_SET_X 0
+#elif EXECUTION_MODE == EXECUTION_MODE_M1X1
+#define FLAG_SET_E 0
+#define FLAG_SET_M 1
+#define FLAG_SET_X 1
+#endif
+
+#undef VECTOR_IRQ
+#undef VECTOR_NMI
+#undef VECTOR_ABORT
+#undef VECTOR_BRK
+#undef VECTOR_COP
+
+#if FLAG_SET_E
+#define VECTOR_IRQ VECTOR_IRQ_E
+#define VECTOR_NMI VECTOR_NMI_E
+#define VECTOR_ABORT VECTOR_ABORT_E
+#define VECTOR_BRK VECTOR_BRK_E
+#define VECTOR_COP VECTOR_COP_E
+#else /* FLAG_SET_E */
+#define VECTOR_IRQ VECTOR_IRQ_N
+#define VECTOR_NMI VECTOR_NMI_N
+#define VECTOR_ABORT VECTOR_ABORT_N
+#define VECTOR_BRK VECTOR_BRK_N
+#define VECTOR_COP VECTOR_COP_N
+#endif
+
+
+
+/* ======================================================================== */
+/* ========================== EFFECTIVE ADDRESSES ========================= */
+/* ======================================================================== */
+
+/* Effective-address based memory access macros */
+#define read_8_NORM(A) g65816i_read_8_normal(A)
+#define read_8_IMM(A) g65816i_read_8_immediate(A)
+#define read_8_D(A) g65816i_read_8_direct(A)
+#define read_8_A(A) g65816i_read_8_normal(A)
+#define read_8_AL(A) g65816i_read_8_normal(A)
+#define read_8_DX(A) g65816i_read_8_direct(A)
+#define read_8_DY(A) g65816i_read_8_direct(A)
+#define read_8_AX(A) g65816i_read_8_normal(A)
+#define read_8_ALX(A) g65816i_read_8_normal(A)
+#define read_8_AY(A) g65816i_read_8_normal(A)
+#define read_8_DI(A) g65816i_read_8_normal(A)
+#define read_8_DLI(A) g65816i_read_8_normal(A)
+#define read_8_AI(A) g65816i_read_8_normal(A)
+#define read_8_ALI(A) g65816i_read_8_normal(A)
+#define read_8_DXI(A) g65816i_read_8_normal(A)
+#define read_8_DIY(A) g65816i_read_8_normal(A)
+#define read_8_DLIY(A) g65816i_read_8_normal(A)
+#define read_8_AXI(A) g65816i_read_8_normal(A)
+#define read_8_S(A) g65816i_read_8_normal(A)
+#define read_8_SIY(A) g65816i_read_8_normal(A)
+
+#define read_16_NORM(A) g65816i_read_16_normal(A)
+#define read_16_IMM(A) g65816i_read_16_immediate(A)
+#define read_16_D(A) g65816i_read_16_direct(A)
+#define read_16_A(A) g65816i_read_16_normal(A)
+#define read_16_AL(A) g65816i_read_16_normal(A)
+#define read_16_DX(A) g65816i_read_16_direct(A)
+#define read_16_DY(A) g65816i_read_16_direct(A)
+#define read_16_AX(A) g65816i_read_16_normal(A)
+#define read_16_ALX(A) g65816i_read_16_normal(A)
+#define read_16_AY(A) g65816i_read_16_normal(A)
+#define read_16_DI(A) g65816i_read_16_normal(A)
+#define read_16_DLI(A) g65816i_read_16_normal(A)
+#define read_16_AI(A) g65816i_read_16_normal(A)
+#define read_16_ALI(A) g65816i_read_16_normal(A)
+#define read_16_DXI(A) g65816i_read_16_normal(A)
+#define read_16_DIY(A) g65816i_read_16_normal(A)
+#define read_16_DLIY(A) g65816i_read_16_normal(A)
+#define read_16_AXI(A) g65816i_read_16_normal(A)
+#define read_16_S(A) g65816i_read_16_normal(A)
+#define read_16_SIY(A) g65816i_read_16_normal(A)
+
+#define read_24_NORM(A) g65816i_read_24_normal(A)
+#define read_24_IMM(A) g65816i_read_24_immediate(A)
+#define read_24_D(A) g65816i_read_24_direct(A)
+#define read_24_A(A) g65816i_read_24_normal(A)
+#define read_24_AL(A) g65816i_read_24_normal(A)
+#define read_24_DX(A) g65816i_read_24_direct(A)
+#define read_24_DY(A) g65816i_read_24_direct(A)
+#define read_24_AX(A) g65816i_read_24_normal(A)
+#define read_24_ALX(A) g65816i_read_24_normal(A)
+#define read_24_AY(A) g65816i_read_24_normal(A)
+#define read_24_DI(A) g65816i_read_24_normal(A)
+#define read_24_DLI(A) g65816i_read_24_normal(A)
+#define read_24_AI(A) g65816i_read_24_normal(A)
+#define read_24_ALI(A) g65816i_read_24_normal(A)
+#define read_24_DXI(A) g65816i_read_24_normal(A)
+#define read_24_DIY(A) g65816i_read_24_normal(A)
+#define read_24_DLIY(A) g65816i_read_24_normal(A)
+#define read_24_AXI(A) g65816i_read_24_normal(A)
+#define read_24_S(A) g65816i_read_24_normal(A)
+#define read_24_SIY(A) g65816i_read_24_normal(A)
+
+#define write_8_NORM(A, V) g65816i_write_8_normal(A, V)
+#define write_8_D(A, V) g65816i_write_8_direct(A, V)
+#define write_8_A(A, V) g65816i_write_8_normal(A, V)
+#define write_8_AL(A, V) g65816i_write_8_normal(A, V)
+#define write_8_DX(A, V) g65816i_write_8_direct(A, V)
+#define write_8_DY(A, V) g65816i_write_8_direct(A, V)
+#define write_8_AX(A, V) g65816i_write_8_normal(A, V)
+#define write_8_ALX(A, V) g65816i_write_8_normal(A, V)
+#define write_8_AY(A, V) g65816i_write_8_normal(A, V)
+#define write_8_DI(A, V) g65816i_write_8_normal(A, V)
+#define write_8_DLI(A, V) g65816i_write_8_normal(A, V)
+#define write_8_AI(A, V) g65816i_write_8_normal(A, V)
+#define write_8_ALI(A, V) g65816i_write_8_normal(A, V)
+#define write_8_DXI(A, V) g65816i_write_8_normal(A, V)
+#define write_8_DIY(A, V) g65816i_write_8_normal(A, V)
+#define write_8_DLIY(A, V) g65816i_write_8_normal(A, V)
+#define write_8_AXI(A, V) g65816i_write_8_normal(A, V)
+#define write_8_S(A, V) g65816i_write_8_normal(A, V)
+#define write_8_SIY(A, V) g65816i_write_8_normal(A, V)
+
+#define write_16_NORM(A, V) g65816i_write_16_normal(A, V)
+#define write_16_D(A, V) g65816i_write_16_direct(A, V)
+#define write_16_A(A, V) g65816i_write_16_normal(A, V)
+#define write_16_AL(A, V) g65816i_write_16_normal(A, V)
+#define write_16_DX(A, V) g65816i_write_16_direct(A, V)
+#define write_16_DY(A, V) g65816i_write_16_direct(A, V)
+#define write_16_AX(A, V) g65816i_write_16_normal(A, V)
+#define write_16_ALX(A, V) g65816i_write_16_normal(A, V)
+#define write_16_AY(A, V) g65816i_write_16_normal(A, V)
+#define write_16_DI(A, V) g65816i_write_16_normal(A, V)
+#define write_16_DLI(A, V) g65816i_write_16_normal(A, V)
+#define write_16_AI(A, V) g65816i_write_16_normal(A, V)
+#define write_16_ALI(A, V) g65816i_write_16_normal(A, V)
+#define write_16_DXI(A, V) g65816i_write_16_normal(A, V)
+#define write_16_DIY(A, V) g65816i_write_16_normal(A, V)
+#define write_16_DLIY(A, V) g65816i_write_16_normal(A, V)
+#define write_16_AXI(A, V) g65816i_write_16_normal(A, V)
+#define write_16_S(A, V) g65816i_write_16_normal(A, V)
+#define write_16_SIY(A, V) g65816i_write_16_normal(A, V)
+
+
+#define OPER_8_IMM() read_8_IMM(EA_IMM8())
+#define OPER_8_D() read_8_D(EA_D())
+#define OPER_8_A() read_8_A(EA_A())
+#define OPER_8_AL() read_8_AL(EA_AL())
+#define OPER_8_DX() read_8_DX(EA_DX())
+#define OPER_8_DY() read_8_DY(EA_DY())
+#define OPER_8_AX() read_8_AX(EA_AX())
+#define OPER_8_ALX() read_8_ALX(EA_ALX())
+#define OPER_8_AY() read_8_AY(EA_AY())
+#define OPER_8_DI() read_8_DI(EA_DI())
+#define OPER_8_DLI() read_8_DLI(EA_DLI())
+#define OPER_8_AI() read_8_AI(EA_AI())
+#define OPER_8_ALI() read_8_ALI(EA_ALI())
+#define OPER_8_DXI() read_8_DXI(EA_DXI())
+#define OPER_8_DIY() read_8_DIY(EA_DIY())
+#define OPER_8_DLIY() read_8_DLIY(EA_DLIY())
+#define OPER_8_AXI() read_8_AXI(EA_AXI())
+#define OPER_8_S() read_8_S(EA_S())
+#define OPER_8_SIY() read_8_SIY(EA_SIY())
+
+#define OPER_16_IMM() read_16_IMM(EA_IMM16())
+#define OPER_16_D() read_16_D(EA_D())
+#define OPER_16_A() read_16_A(EA_A())
+#define OPER_16_AL() read_16_AL(EA_AL())
+#define OPER_16_DX() read_16_DX(EA_DX())
+#define OPER_16_DY() read_16_DY(EA_DY())
+#define OPER_16_AX() read_16_AX(EA_AX())
+#define OPER_16_ALX() read_16_ALX(EA_ALX())
+#define OPER_16_AY() read_16_AY(EA_AY())
+#define OPER_16_DI() read_16_DI(EA_DI())
+#define OPER_16_DLI() read_16_DLI(EA_DLI())
+#define OPER_16_AI() read_16_AI(EA_AI())
+#define OPER_16_ALI() read_16_ALI(EA_ALI())
+#define OPER_16_DXI() read_16_DXI(EA_DXI())
+#define OPER_16_DIY() read_16_DIY(EA_DIY())
+#define OPER_16_DLIY() read_16_DLIY(EA_DLIY())
+#define OPER_16_AXI() read_16_AXI(EA_AXI())
+#define OPER_16_S() read_16_S(EA_S())
+#define OPER_16_SIY() read_16_SIY(EA_SIY())
+
+#define OPER_24_IMM() read_24_IMM(EA_IMM24())
+#define OPER_24_D() read_24_D(EA_D())
+#define OPER_24_A() read_24_A(EA_A())
+#define OPER_24_AL() read_24_AL(EA_AL())
+#define OPER_24_DX() read_24_DX(EA_DX())
+#define OPER_24_DY() read_24_DY(EA_DY())
+#define OPER_24_AX() read_24_AX(EA_AX())
+#define OPER_24_ALX() read_24_ALX(EA_ALX())
+#define OPER_24_AY() read_24_AY(EA_AY())
+#define OPER_24_DI() read_24_DI(EA_DI())
+#define OPER_24_DLI() read_24_DLI(EA_DLI())
+#define OPER_24_AI() read_24_AI(EA_AI())
+#define OPER_24_ALI() read_24_ALI(EA_ALI())
+#define OPER_24_DXI() read_24_DXI(EA_DXI())
+#define OPER_24_DIY() read_24_DIY(EA_DIY())
+#define OPER_24_DLIY() read_24_DLIY(EA_DLIY())
+#define OPER_24_AXI() read_24_AXI(EA_AXI())
+#define OPER_24_S() read_24_S(EA_S())
+#define OPER_24_SIY() read_24_SIY(EA_SIY())
+
+
+
+/* ======================================================================== */
+/* =========================== OPERATION MACROS =========================== */
+/* ======================================================================== */
+
+/* M6502 Add With Carry */
+#undef OP_ADC
+#if FLAG_SET_M
+#define OP_ADC(MODE) \
+ { \
+ unsigned tmp16; \
+ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
+ SRC = OPER_8_##MODE(); \
+ if(FLAG_D) \
+ { \
+ INT32 result, r0, r1, carry; \
+ r0 = REGISTER_A; \
+ r1 = SRC; \
+ carry = CFLAG_AS_1(); \
+ result = (r0 & 0x0f) + (r1 & 0x0f) + (carry << 0); \
+ if (result > 0x09) result += 0x06; \
+ carry = result > 0x0f; \
+ result = (r0 & 0xf0) + (r1 & 0xf0) + (carry << 4) + (result & 0x0f); \
+ FLAG_V = ~(r0 ^ SRC) & (r0 ^ result) & 0x80; \
+ if (result > 0x9f) result += 0x60; \
+ FLAG_C = (result > 0xff) ? 0x100 : 0; \
+ FLAG_N = (result & 0x80); \
+ FLAG_Z = REGISTER_A = MAKE_UINT_8(result); \
+ } \
+ else \
+ { \
+ FLAG_C = tmp16 = REGISTER_A + SRC + CFLAG_AS_1(); \
+ FLAG_V = VFLAG_ADD_8(SRC, REGISTER_A, FLAG_C); \
+ FLAG_N = FLAG_Z = REGISTER_A = MAKE_UINT_8(tmp16); \
+ } \
+ }
+
+#else
+#define OP_ADC(MODE) \
+ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
+ SRC = OPER_16_##MODE(); \
+ INT32 result, r0, r1, carry; \
+ r0 = REGISTER_A; \
+ r1 = SRC; \
+ carry = CFLAG_AS_1(); \
+ if (!FLAG_D) \
+ { \
+ result = r0 + r1 + carry; \
+ } \
+ else \
+ { \
+ result = (r0 & 0x000f) + (r1 & 0x000f) + (carry << 0); \
+ if(result > 0x0009) result += 0x0006; \
+ carry = result > 0x000f; \
+ result = (r0 & 0x00f0) + (r1 & 0x00f0) + (carry << 4) + (result & 0x000f); \
+ if(result > 0x009f) result += 0x0060; \
+ carry = result > 0x00ff; \
+ result = (r0 & 0x0f00) + (r1 & 0x0f00) + (carry << 8) + (result & 0x00ff); \
+ if(result > 0x09ff) result += 0x0600; \
+ carry = result > 0x0fff; \
+ result = (r0 & 0xf000) + (r1 & 0xf000) + (carry << 12) + (result & 0x0fff); \
+ } \
+ FLAG_V = ~(r0 ^ r1) & (r0 ^ result) & 0x8000; \
+ FLAG_V >>= 8; \
+ if (FLAG_D && result > 0x9fff) result += 0x6000; \
+ FLAG_C = (result > 0xffff) ? 0x100 : 0; \
+ FLAG_Z = REGISTER_A = MAKE_UINT_16(result); \
+ FLAG_N = NFLAG_16(REGISTER_A);
+#endif
+
+/* M6502 Logical AND with accumulator */
+#undef OP_AND
+#if FLAG_SET_M
+#define OP_AND(MODE) \
+ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
+ FLAG_N = FLAG_Z = REGISTER_A &= OPER_8_##MODE()
+#else
+#define OP_AND(MODE) \
+ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
+ FLAG_Z = REGISTER_A &= OPER_16_##MODE(); \
+ FLAG_N = NFLAG_16(REGISTER_A)
+#endif
+
+/* M6502 Arithmetic Shift Left accumulator */
+#undef OP_ASL
+#if FLAG_SET_M
+#define OP_ASL() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_C = REGISTER_A << 1; \
+ FLAG_N = FLAG_Z = REGISTER_A = MAKE_UINT_8(FLAG_C)
+#else
+#define OP_ASL() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_C = REGISTER_A << 1; \
+ FLAG_Z = REGISTER_A = MAKE_UINT_16(FLAG_C); \
+ FLAG_N = NFLAG_16(FLAG_C); \
+ FLAG_C = CFLAG_16(FLAG_C)
+#endif
+
+/* M6502 Arithmetic Shift Left operand */
+#undef OP_ASLM
+#if FLAG_SET_M
+#define OP_ASLM(MODE) \
+ CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \
+ DST = EA_##MODE(); \
+ FLAG_C = read_8_##MODE(DST) << 1; \
+ FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C); \
+ write_8_##MODE(DST, FLAG_Z)
+#else
+#define OP_ASLM(MODE) \
+ CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \
+ DST = EA_##MODE(); \
+ FLAG_C = read_16_##MODE(DST) << 1; \
+ FLAG_Z = MAKE_UINT_16(FLAG_C); \
+ FLAG_N = NFLAG_16(FLAG_C); \
+ FLAG_C = CFLAG_16(FLAG_C); \
+ write_16_##MODE(DST, FLAG_Z)
+#endif
+
+/* M6502 Branch on Condition Code */
+#undef OP_BCC
+#define OP_BCC(COND) \
+ DST = OPER_8_IMM(); \
+ if(COND) \
+ { \
+ CLK(CLK_OP + CLK_RELATIVE_8 + 1); \
+ g65816i_branch_8(DST); \
+ BREAKOUT; \
+ } \
+ CLK(CLK_OP + CLK_RELATIVE_8);
+/* M6502 Set flags according to bits */
+#undef OP_BIT
+#if FLAG_SET_M
+#define OP_BIT(MODE) \
+ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
+ FLAG_N = OPER_8_##MODE(); \
+ FLAG_Z = FLAG_N & REGISTER_A; \
+ FLAG_V = FLAG_N << 1
+#else
+#define OP_BIT(MODE) \
+ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
+ FLAG_N = OPER_16_##MODE(); \
+ FLAG_Z = FLAG_N & REGISTER_A; \
+ FLAG_N = NFLAG_16(FLAG_N); \
+ FLAG_V = FLAG_N << 1
+#endif
+
+/* G65816 Set flags according to bits (immediate addressing mode) */
+#undef OP_BITI
+#if FLAG_SET_M
+#define OP_BITI() \
+ CLK(CLK_OP + CLK_R8 + CLK_IMM); \
+ FLAG_Z = REGISTER_A & OPER_8_IMM()
+#else
+#define OP_BITI() \
+ CLK(CLK_OP + CLK_R16 + CLK_IMM); \
+ FLAG_Z = REGISTER_A & OPER_16_IMM()
+#endif
+
+/* M6502 Cause a Break interrupt */
+#undef OP_BRK
+#define OP_BRK() \
+ REGISTER_PC++; \
+ g65816i_interrupt_software(VECTOR_BRK)
+
+/* G65816 Branch Always */
+#undef OP_BRA
+#define OP_BRA() \
+ CLK(CLK_OP + CLK_IMPLIED + CLK_RELATIVE_8); \
+ g65816i_branch_8(OPER_8_IMM())
+
+/* G65816 Branch Always Long */
+#undef OP_BRL
+#define OP_BRL() \
+ CLK(CLK_OP + CLK_IMPLIED + CLK_RELATIVE_16); \
+ g65816i_branch_16(OPER_16_IMM())
+
+/* M6502 Clear Carry flag */
+#undef OP_CLC
+#define OP_CLC() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_C = CFLAG_CLEAR
+
+/* M6502 Clear Decimal flag */
+#undef OP_CLD
+#define OP_CLD() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_D = DFLAG_CLEAR
+
+/* M6502 Clear Interrupt Mask flag */
+#undef OP_CLI
+#define OP_CLI() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ g65816i_set_flag_i(IFLAG_CLEAR)
+
+/* M6502 Clear oVerflow flag */
+#undef OP_CLV
+#define OP_CLV() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_V = VFLAG_CLEAR
+
+/* M6502 Compare operand to accumulator */
+/* Unusual behavior: C flag is inverted */
+#undef OP_CMP
+#if FLAG_SET_M
+#define OP_CMP(MODE) \
+ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
+ FLAG_C = REGISTER_A - OPER_8_##MODE(); \
+ FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C); \
+ FLAG_C ^= CFLAG_SET
+#else
+#define OP_CMP(MODE) \
+ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
+ FLAG_C = REGISTER_A - OPER_16_##MODE(); \
+ FLAG_Z = MAKE_UINT_16(FLAG_C); \
+ FLAG_N = NFLAG_16(FLAG_C); \
+ FLAG_C = ~CFLAG_16(FLAG_C)
+#endif
+
+/* M6502 Compare operand to index register */
+/* Unusual behavior: C flag is inverted */
+#undef OP_CMPX
+#if FLAG_SET_X
+#define OP_CMPX(REG, MODE) \
+ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
+ FLAG_C = REG - OPER_8_##MODE(); \
+ FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C); \
+ FLAG_C ^= CFLAG_SET
+#else
+#define OP_CMPX(REG, MODE) \
+ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
+ FLAG_C = REG - OPER_16_##MODE(); \
+ FLAG_Z = MAKE_UINT_16(FLAG_C); \
+ FLAG_N = NFLAG_16(FLAG_C); \
+ FLAG_C = ~CFLAG_16(FLAG_C)
+#endif
+
+/* G65816 Coprocessor operation */
+#undef OP_COP
+#define OP_COP() \
+ REGISTER_PC++; \
+ g65816i_interrupt_software(VECTOR_COP)
+
+/* M6502 Decrement accumulator */
+#undef OP_DEC
+#if FLAG_SET_M
+#define OP_DEC() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_N = FLAG_Z = REGISTER_A = MAKE_UINT_8(REGISTER_A - 1)
+#else
+#define OP_DEC() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REGISTER_A = MAKE_UINT_16(REGISTER_A - 1); \
+ FLAG_N = NFLAG_16(REGISTER_A)
+#endif
+
+/* M6502 Decrement operand */
+#undef OP_DECM
+#if FLAG_SET_M
+#define OP_DECM(MODE) \
+ CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \
+ DST = EA_##MODE(); \
+ FLAG_N = FLAG_Z = MAKE_UINT_8(read_8_##MODE(DST) - 1); \
+ write_8_##MODE(DST, FLAG_Z)
+#else
+#define OP_DECM(MODE) \
+ CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \
+ DST = EA_##MODE(); \
+ FLAG_Z = MAKE_UINT_16(read_16_##MODE(DST) - 1); \
+ FLAG_N = NFLAG_16(FLAG_Z); \
+ write_16_##MODE(DST, FLAG_Z)
+#endif
+
+/* M6502 Decrement index register */
+#undef OP_DECX
+#if FLAG_SET_X
+#define OP_DECX(REG) \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_N = FLAG_Z = REG = MAKE_UINT_8(REG - 1)
+#else
+#define OP_DECX(REG) \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG = MAKE_UINT_16(REG - 1); \
+ FLAG_N = NFLAG_16(REG)
+#endif
+
+/* M6502 Exclusive Or operand to accumulator */
+#undef OP_EOR
+#if FLAG_SET_M
+#define OP_EOR(MODE) \
+ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
+ FLAG_N = FLAG_Z = REGISTER_A ^= OPER_8_##MODE()
+#else
+#define OP_EOR(MODE) \
+ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
+ FLAG_Z = REGISTER_A ^= OPER_16_##MODE(); \
+ FLAG_N = NFLAG_16(REGISTER_A)
+#endif
+
+/* M6502 Increment accumulator */
+#undef OP_INC
+#if FLAG_SET_M
+#define OP_INC() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_N = FLAG_Z = REGISTER_A = MAKE_UINT_8(REGISTER_A + 1)
+#else
+#define OP_INC() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REGISTER_A = MAKE_UINT_16(REGISTER_A + 1); \
+ FLAG_N = NFLAG_16(REGISTER_A)
+#endif
+
+/* M6502 Increment operand */
+#undef OP_INCM
+#if FLAG_SET_M
+#define OP_INCM(MODE) \
+ CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \
+ DST = EA_##MODE(); \
+ FLAG_N = FLAG_Z = MAKE_UINT_8(read_8_##MODE(DST) + 1); \
+ write_8_##MODE(DST, FLAG_Z)
+#else
+#define OP_INCM(MODE) \
+ CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \
+ DST = EA_##MODE(); \
+ FLAG_Z = MAKE_UINT_16(read_16_##MODE(DST) + 1); \
+ FLAG_N = NFLAG_16(FLAG_Z); \
+ write_16_##MODE(DST, FLAG_Z)
+#endif
+
+/* M6502 Increment index register */
+#undef OP_INCX
+#if FLAG_SET_X
+#define OP_INCX(REG) \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_N = FLAG_Z = REG = MAKE_UINT_8(REG + 1)
+#else
+#define OP_INCX(REG) \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG = MAKE_UINT_16(REG + 1); \
+ FLAG_N = NFLAG_16(REG)
+#endif
+
+/* G65816 Jump Long */
+#undef OP_JMLAI
+#define OP_JMLAI() \
+ CLK(CLK_OP + CLK_AI + 1); \
+ g65816i_jump_24(read_24_A(OPER_16_IMM()))
+
+/* M6502 Jump */
+#undef OP_JMP
+#define OP_JMP(MODE) \
+ CLK(CLK_OP + CLK_##MODE); \
+ g65816i_jump_16(EA_##MODE())
+
+/* M6502 Jump absolute indexed indirect */
+#undef OP_JMPAXI
+#define OP_JMPAXI() \
+ CLK(CLK_OP + CLK_AXI); \
+ g65816i_jump_16(read_16_AXI(REGISTER_PB | (MAKE_UINT_16(OPER_16_IMM() + REGISTER_X))))
+
+/* G65816 Jump absolute long */
+#undef OP_JMPAL
+#define OP_JMPAL() \
+ CLK(CLK_OP + CLK_AL); \
+ g65816i_jump_24(EA_AL())
+
+/* G65816 Jump to Subroutine Long */
+/* Unusual behavior: stacks PC-1 */
+#undef OP_JSL
+#define OP_JSL(MODE) \
+ CLK(CLK_OP + CLK_W24 + CLK_##MODE + 1); \
+ DST = EA_##MODE(); \
+ g65816i_push_8(REGISTER_PB>>16); \
+ g65816i_push_16(REGISTER_PC-1); \
+ g65816i_jump_24(DST)
+
+/* M6502 Jump to Subroutine */
+/* Unusual behavior: stacks PC-1 */
+#undef OP_JSR
+#define OP_JSR(MODE) \
+ CLK(CLK_OP + CLK_W16 + CLK_##MODE); \
+ DST = EA_##MODE(); \
+ g65816i_push_16(REGISTER_PC-1); \
+ g65816i_jump_16(DST)
+
+/* M6502 Jump to Subroutine */
+/* Unusual behavior: stacks PC-1 */
+#undef OP_JSRAXI
+#define OP_JSRAXI() \
+ CLK(CLK_OP + CLK_W16 + CLK_AXI); \
+ DST = read_16_AXI(REGISTER_PB | (MAKE_UINT_16(OPER_16_IMM() + REGISTER_X))); \
+ g65816i_push_16(REGISTER_PC-1); \
+ g65816i_jump_16(DST)
+
+/* M6502 Load accumulator with operand */
+#undef OP_LDA
+#if FLAG_SET_M
+#define OP_LDA(MODE) \
+ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
+ FLAG_N = FLAG_Z = REGISTER_A = OPER_8_##MODE()
+#else
+#define OP_LDA(MODE) \
+ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
+ FLAG_Z = REGISTER_A = OPER_16_##MODE(); \
+ FLAG_N = NFLAG_16(REGISTER_A)
+#endif
+
+/* M6502 Load index register with operand */
+#undef OP_LDX
+#if FLAG_SET_X
+#define OP_LDX(REG, MODE) \
+ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
+ FLAG_N = FLAG_Z = REG = OPER_8_##MODE()
+#else
+#define OP_LDX(REG, MODE) \
+ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
+ FLAG_Z = REG = OPER_16_##MODE(); \
+ FLAG_N = NFLAG_16(REG)
+#endif
+
+/* M6502 Logical Shift Right accumulator */
+#undef OP_LSR
+#if FLAG_SET_M
+#define OP_LSR() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_N = 0; \
+ FLAG_C = REGISTER_A << 8; \
+ FLAG_Z = REGISTER_A >>= 1
+#else
+#define OP_LSR() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_N = 0; \
+ FLAG_C = REGISTER_A << 8; \
+ FLAG_Z = REGISTER_A >>= 1
+#endif
+
+/* M6502 Logical Shift Right operand */
+#undef OP_LSRM
+#if FLAG_SET_M
+#define OP_LSRM(MODE) \
+ CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \
+ DST = EA_##MODE(); \
+ FLAG_N = 0; \
+ FLAG_Z = read_8_##MODE(DST); \
+ FLAG_C = FLAG_Z << 8; \
+ FLAG_Z >>= 1; \
+ write_8_##MODE(DST, FLAG_Z)
+#else
+#define OP_LSRM(MODE) \
+ CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \
+ DST = EA_##MODE(); \
+ FLAG_N = 0; \
+ FLAG_Z = read_16_##MODE(DST); \
+ FLAG_C = FLAG_Z << 8; \
+ FLAG_Z >>= 1; \
+ write_16_##MODE(DST, FLAG_Z)
+#endif
+
+/* G65816 Move Block Negative */
+#undef OP_MVN
+#if FLAG_SET_M
+#if FLAG_SET_X
+#define OP_MVN() \
+ DST = OPER_8_IMM()<<16; \
+ SRC = OPER_8_IMM()<<16; \
+ REGISTER_DB = DST; \
+ CLK(7); \
+ write_8_NORM(DST | REGISTER_Y, read_8_NORM(SRC | REGISTER_X)); \
+ REGISTER_X = MAKE_UINT_8(REGISTER_X+1); \
+ REGISTER_Y = MAKE_UINT_8(REGISTER_Y+1); \
+ REGISTER_A--; \
+ REGISTER_A &= 0xff; \
+ if ((REGISTER_A&0xff) != 0xff) \
+ {\
+ REGISTER_PC -= 3; \
+ }\
+ else \
+ { \
+ REGISTER_B -= 0x100;\
+ REGISTER_B &= 0xff00; \
+ if ((REGISTER_B & 0xff00) != 0xff00)\
+ { \
+ REGISTER_PC -= 3;\
+ } \
+ }
+#else
+#define OP_MVN() \
+ DST = OPER_8_IMM()<<16; \
+ SRC = OPER_8_IMM()<<16; \
+ REGISTER_DB = DST; \
+ CLK(7); \
+ write_8_NORM(DST | REGISTER_Y, read_8_NORM(SRC | REGISTER_X)); \
+ REGISTER_X = MAKE_UINT_16(REGISTER_X+1); \
+ REGISTER_Y = MAKE_UINT_16(REGISTER_Y+1); \
+ REGISTER_A--; \
+ REGISTER_A &= 0xff; \
+ if ((REGISTER_A&0xff) != 0xff) \
+ {\
+ REGISTER_PC -= 3; \
+ }\
+ else \
+ { \
+ REGISTER_B -= 0x100;\
+ REGISTER_B &= 0xff00; \
+ if ((REGISTER_B & 0xff00) != 0xff00)\
+ { \
+ REGISTER_PC -= 3;\
+ } \
+ }
+#endif
+#else
+#if FLAG_SET_X
+#define OP_MVN() \
+ DST = OPER_8_IMM()<<16; \
+ SRC = OPER_8_IMM()<<16; \
+ REGISTER_DB = DST; \
+ REGISTER_A |= REGISTER_B; \
+ CLK(7); \
+ write_8_NORM(DST | REGISTER_Y, read_8_NORM(SRC | REGISTER_X)); \
+ REGISTER_X = MAKE_UINT_8(REGISTER_X+1); \
+ REGISTER_Y = MAKE_UINT_8(REGISTER_Y+1); \
+ REGISTER_A--; \
+ if ((REGISTER_A&0xffff) != 0xffff) \
+ {\
+ REGISTER_PC -= 3; \
+ }
+#else
+#define OP_MVN() \
+ DST = OPER_8_IMM()<<16; \
+ SRC = OPER_8_IMM()<<16; \
+ REGISTER_DB = DST; \
+ REGISTER_A |= REGISTER_B; \
+ CLK(7); \
+ write_8_NORM(DST | REGISTER_Y, read_8_NORM(SRC | REGISTER_X)); \
+ REGISTER_X = MAKE_UINT_16(REGISTER_X+1); \
+ REGISTER_Y = MAKE_UINT_16(REGISTER_Y+1); \
+ REGISTER_A--; \
+ if ((REGISTER_A&0xffff) != 0xffff) \
+ {\
+ REGISTER_PC -= 3; \
+ }
+#endif
+#endif
+
+/* G65816 Move Block Positive */
+#undef OP_MVP
+#if FLAG_SET_M
+#if FLAG_SET_X
+#define OP_MVP() \
+ DST = OPER_8_IMM()<<16; \
+ SRC = OPER_8_IMM()<<16; \
+ REGISTER_DB = DST; \
+ CLK(7); \
+ write_8_NORM(DST | REGISTER_Y, read_8_NORM(SRC | REGISTER_X)); \
+ REGISTER_X = MAKE_UINT_8(REGISTER_X-1); \
+ REGISTER_Y = MAKE_UINT_8(REGISTER_Y-1); \
+ REGISTER_A--; \
+ REGISTER_A &= 0xff; \
+ if ((REGISTER_A&0xff) != 0xff) \
+ {\
+ REGISTER_PC -= 3; \
+ }\
+ else \
+ { \
+ REGISTER_B -= 0x100;\
+ REGISTER_B &= 0xff00; \
+ if ((REGISTER_B & 0xff00) != 0xff00)\
+ { \
+ REGISTER_PC -= 3;\
+ } \
+ }
+#else
+#define OP_MVP() \
+ DST = OPER_8_IMM()<<16; \
+ SRC = OPER_8_IMM()<<16; \
+ REGISTER_DB = DST; \
+ CLK(7); \
+ write_8_NORM(DST | REGISTER_Y, read_8_NORM(SRC | REGISTER_X)); \
+ REGISTER_X = MAKE_UINT_16(REGISTER_X-1); \
+ REGISTER_Y = MAKE_UINT_16(REGISTER_Y-1); \
+ REGISTER_A--; \
+ REGISTER_A &= 0xff; \
+ if ((REGISTER_A&0xff) != 0xff) \
+ {\
+ REGISTER_PC -= 3; \
+ }\
+ else \
+ { \
+ REGISTER_B -= 0x100;\
+ REGISTER_B &= 0xff00; \
+ if ((REGISTER_B & 0xff00) != 0xff00)\
+ { \
+ REGISTER_PC -= 3;\
+ } \
+ }
+#endif
+#else
+#if FLAG_SET_X
+#define OP_MVP() \
+ DST = OPER_8_IMM()<<16; \
+ SRC = OPER_8_IMM()<<16; \
+ REGISTER_DB = DST; \
+ REGISTER_A |= REGISTER_B; \
+ CLK(7); \
+ write_8_NORM(DST | REGISTER_Y, read_8_NORM(SRC | REGISTER_X)); \
+ REGISTER_X = MAKE_UINT_8(REGISTER_X-1); \
+ REGISTER_Y = MAKE_UINT_8(REGISTER_Y-1); \
+ REGISTER_A--; \
+ if ((REGISTER_A&0xffff) != 0xffff) \
+ {\
+ REGISTER_PC -= 3; \
+ }
+#else
+#define OP_MVP() \
+ DST = OPER_8_IMM()<<16; \
+ SRC = OPER_8_IMM()<<16; \
+ REGISTER_DB = DST; \
+ REGISTER_A |= REGISTER_B; \
+ CLK(7); \
+ write_8_NORM(DST | REGISTER_Y, read_8_NORM(SRC | REGISTER_X)); \
+ REGISTER_X = MAKE_UINT_16(REGISTER_X-1); \
+ REGISTER_Y = MAKE_UINT_16(REGISTER_Y-1); \
+ REGISTER_A--; \
+ if ((REGISTER_A&0xffff) != 0xffff) \
+ {\
+ REGISTER_PC -= 3; \
+ }
+#endif
+#endif
+
+/* M6502 No Operation */
+#undef OP_NOP
+#define OP_NOP() \
+ CLK(CLK_OP + CLK_IMPLIED)
+
+/* M6502 Logical OR operand to accumulator */
+#undef OP_ORA
+#if FLAG_SET_M
+#define OP_ORA(MODE) \
+ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
+ FLAG_N = FLAG_Z = REGISTER_A |= OPER_8_ ## MODE()
+#else
+#define OP_ORA(MODE) \
+ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
+ FLAG_Z = REGISTER_A |= OPER_16_##MODE(); \
+ FLAG_N = NFLAG_16(REGISTER_A)
+#endif
+
+/* G65816 Push Effective Address */
+#undef OP_PEA
+#define OP_PEA() \
+ CLK(CLK_OP + CLK_R16 + CLK_W16); \
+ g65816i_push_16(OPER_16_IMM())
+
+/* G65816 Push Effective Indirect Address */
+#undef OP_PEI
+#define OP_PEI() \
+ CLK(CLK_OP + CLK_R16 + CLK_W16 + CLK_D); \
+ g65816i_push_16(EA_DI())
+
+/* G65816 Push Effective PC-Relative Address */
+#undef OP_PER
+#define OP_PER() \
+ CLK(CLK_OP + CLK_R16 + CLK_W16 + 1); \
+ SRC = OPER_16_IMM(); \
+ g65816i_push_16(REGISTER_PC + SRC)
+
+/* M6502 Push accumulator to the stack */
+#undef OP_PHA
+#if FLAG_SET_M
+#define OP_PHA() \
+ CLK(CLK_OP + CLK_W8 + 1); \
+ g65816i_push_8(REGISTER_A)
+#else
+#define OP_PHA() \
+ CLK(CLK_OP + CLK_W16 + 1); \
+ g65816i_push_16(REGISTER_A)
+#endif
+
+/* M6502 Push index register to the stack */
+#undef OP_PHX
+#if FLAG_SET_X
+#define OP_PHX(REG) \
+ CLK(CLK_OP + CLK_W8 + 1); \
+ g65816i_push_8(REG)
+#else
+#define OP_PHX(REG) \
+ CLK(CLK_OP + CLK_W16 + 1); \
+ g65816i_push_16(REG)
+#endif
+
+/* G65816 Push data bank register */
+#undef OP_PHB
+#define OP_PHB() \
+ CLK(CLK_OP + CLK_W8 + 1); \
+ g65816i_push_8(REGISTER_DB>>16)
+
+/* G65816 Push direct register */
+#undef OP_PHD
+#define OP_PHD() \
+ CLK(CLK_OP + CLK_W16 + 1); \
+ g65816i_push_16(REGISTER_D)
+
+/* G65816 Push program bank register */
+#undef OP_PHK
+#define OP_PHK() \
+ CLK(CLK_OP + CLK_W8 + 1); \
+ g65816i_push_8(REGISTER_PB>>16)
+
+/* M6502 Push the Processor Status Register to the stack */
+#undef OP_PHP
+#define OP_PHP() \
+ CLK(CLK_OP + CLK_W8 + 1); \
+ g65816i_push_8(g65816i_get_reg_p())
+
+/* M6502 Pull accumulator from the stack */
+#undef OP_PLA
+#if FLAG_SET_M
+#define OP_PLA() \
+ CLK(CLK_OP + CLK_R8 + 2); \
+ FLAG_N = FLAG_Z = REGISTER_A = g65816i_pull_8()
+#else
+#define OP_PLA() \
+ CLK(CLK_OP + CLK_R16 + 2); \
+ FLAG_Z = REGISTER_A = g65816i_pull_16(); \
+ FLAG_N = NFLAG_16(FLAG_Z)
+#endif
+
+/* M6502 Pull index register from the stack */
+#undef OP_PLX
+#if FLAG_SET_X
+#define OP_PLX(REG) \
+ CLK(CLK_OP + CLK_R8 + 2); \
+ FLAG_N = FLAG_Z = REG = g65816i_pull_8()
+#else
+#define OP_PLX(REG) \
+ CLK(CLK_OP + CLK_R16 + 2); \
+ FLAG_Z = REG = g65816i_pull_16(); \
+ FLAG_N = NFLAG_16(FLAG_Z)
+#endif
+
+/* G65816 Pull data bank register */
+#undef OP_PLB
+#define OP_PLB() \
+ CLK(CLK_OP + CLK_R8 + 2); \
+ FLAG_N = FLAG_Z = g65816i_pull_8(); \
+ REGISTER_DB = FLAG_Z << 16
+
+/* G65816 Pull direct register */
+#undef OP_PLD
+#define OP_PLD() \
+ CLK(CLK_OP + CLK_R16 + 2); \
+ FLAG_Z = REGISTER_D = g65816i_pull_16(); \
+ FLAG_N = NFLAG_16(FLAG_Z)
+
+/* M6502 Pull the Processor Status Register from the stack */
+#undef OP_PLP
+#define OP_PLP() \
+ CLK(CLK_OP + CLK_R8 + 2); \
+ g65816i_set_reg_p(g65816i_pull_8())
+
+/* G65816 Reset Program status word */
+#undef OP_REP
+#define OP_REP() \
+ CLK(CLK_OP + CLK_R8 + 1); \
+ g65816i_set_reg_p(g65816i_get_reg_p() & ~OPER_8_IMM())
+
+/* M6502 Rotate Left the accumulator */
+#undef OP_ROL
+#if FLAG_SET_M
+#define OP_ROL() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_C = (REGISTER_A<<1) | CFLAG_AS_1(); \
+ FLAG_N = FLAG_Z = REGISTER_A = MAKE_UINT_8(FLAG_C)
+#else
+#define OP_ROL() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_C = (REGISTER_A<<1) | CFLAG_AS_1(); \
+ FLAG_Z = REGISTER_A = MAKE_UINT_16(FLAG_C); \
+ FLAG_N = NFLAG_16(FLAG_C); \
+ FLAG_C = CFLAG_16(FLAG_C)
+#endif
+
+/* M6502 Rotate Left an operand */
+#undef OP_ROLM
+#if FLAG_SET_M
+#define OP_ROLM(MODE) \
+ CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \
+ DST = EA_##MODE(); \
+ FLAG_C = (read_8_##MODE(DST)<<1) | CFLAG_AS_1(); \
+ FLAG_N = FLAG_Z = MAKE_UINT_8(FLAG_C); \
+ write_8_##MODE(DST, FLAG_Z)
+#else
+#define OP_ROLM(MODE) \
+ CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \
+ DST = EA_##MODE(); \
+ FLAG_C = (read_16_##MODE(DST)<<1) | CFLAG_AS_1(); \
+ FLAG_Z = MAKE_UINT_16(FLAG_C); \
+ FLAG_N = NFLAG_16(FLAG_C); \
+ FLAG_C = CFLAG_16(FLAG_C); \
+ write_16_##MODE(DST, FLAG_Z)
+#endif
+
+/* M6502 Rotate Right the accumulator */
+#undef OP_ROR
+#if FLAG_SET_M
+#define OP_ROR() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ REGISTER_A |= FLAG_C & 0x100; \
+ FLAG_C = REGISTER_A << 8; \
+ FLAG_N = FLAG_Z = REGISTER_A >>= 1
+#else
+#define OP_ROR() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ REGISTER_A |= (FLAG_C<<8) & 0x10000; \
+ FLAG_C = REGISTER_A << 8; \
+ FLAG_Z = REGISTER_A >>= 1; \
+ FLAG_N = NFLAG_16(REGISTER_A)
+#endif
+
+/* M6502 Rotate Right an operand */
+#undef OP_RORM
+#if FLAG_SET_M
+#define OP_RORM(MODE) \
+ CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \
+ DST = EA_##MODE(); \
+ FLAG_Z = read_8_##MODE(DST) | (FLAG_C & 0x100); \
+ FLAG_C = FLAG_Z << 8; \
+ FLAG_N = FLAG_Z >>= 1; \
+ write_8_##MODE(DST, FLAG_Z)
+#else
+#define OP_RORM(MODE) \
+ CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \
+ DST = EA_##MODE(); \
+ FLAG_Z = read_16_##MODE(DST) | ((FLAG_C<<8) & 0x10000); \
+ FLAG_C = FLAG_Z << 8; \
+ FLAG_Z >>= 1; \
+ FLAG_N = NFLAG_16(FLAG_Z); \
+ write_16_##MODE(DST, FLAG_Z)
+#endif
+
+/* M6502 Return from Interrupt */
+#undef OP_RTI
+#if FLAG_SET_E
+#define OP_RTI() \
+ CLK(7); \
+ g65816i_set_reg_p(g65816i_pull_8()); \
+ g65816i_jump_16(g65816i_pull_16())
+#else
+#define OP_RTI() \
+ CLK(8); \
+ g65816i_set_reg_p(g65816i_pull_8()); \
+ g65816i_jump_16(g65816i_pull_16()); \
+ REGISTER_PB = g65816i_pull_8() << 16
+#endif
+
+/* G65816 Return from Subroutine Long */
+/* Unusual behavior: Gets PC and increments */
+#undef OP_RTL
+#define OP_RTL() \
+ CLK(6); \
+ g65816i_jump_24(g65816i_pull_24())
+
+/* M6502 Return from Subroutine */
+/* Unusual behavior: Gets PC and increments */
+#undef OP_RTS
+#define OP_RTS() \
+ CLK(6); \
+ g65816i_jump_16(g65816i_pull_16()+1)
+
+/* M6502 Subtract with Carry */
+/* Unusual behavior: C flag is inverted */
+#undef OP_SBC
+#if FLAG_SET_M
+#define OP_SBC(MODE) \
+ CLK(CLK_OP + CLK_R8 + CLK_##MODE); \
+ SRC = OPER_8_##MODE(); \
+ if(!FLAG_D) \
+ { \
+ FLAG_C = ~FLAG_C; \
+ FLAG_C = REGISTER_A - SRC - CFLAG_AS_1(); \
+ FLAG_V = VFLAG_SUB_8(SRC, REGISTER_A, FLAG_C); \
+ FLAG_N = FLAG_Z = REGISTER_A = MAKE_UINT_8(FLAG_C); \
+ FLAG_C = ~FLAG_C; \
+ BREAKOUT; \
+ } \
+ else \
+ { \
+ INT32 result, r0, r1, carry; \
+ r0 = REGISTER_A; \
+ r1 = SRC; \
+ r1 ^= 0xff; \
+ carry = CFLAG_AS_1(); \
+ result = (r0 & 0x0f) + (r1 & 0x0f) + (carry << 0); \
+ if (result <= 0x0f) result -= 0x06; \
+ carry = result > 0x0f; \
+ result = (r0 & 0xf0) + (r1 & 0xf0) + (carry << 4) + (result & 0x0f); \
+ FLAG_V = ~(r0 ^ r1) & (r0 ^ result) & 0x80; \
+ if (result <= 0xff) result -= 0x60; \
+ FLAG_C = (result > 0xff) ? 0x100 : 0; \
+ FLAG_N = (result & 0x80); \
+ FLAG_Z = REGISTER_A = MAKE_UINT_8(result); \
+ }
+#else
+#define OP_SBC(MODE) \
+ CLK(CLK_OP + CLK_R16 + CLK_##MODE); \
+ SRC = OPER_16_##MODE(); \
+ INT32 result, r0, r1, carry; \
+ r0 = REGISTER_A; \
+ r1 = SRC; \
+ r1 ^= 0xffff; \
+ carry = CFLAG_AS_1(); \
+ if (!FLAG_D) \
+ { \
+ result = r0 + r1 + carry; \
+ } \
+ else \
+ { \
+ result = (r0 & 0x000f) + (r1 & 0x000f) + (carry << 0); \
+ if(result <= 0x000f) result -= 0x0006; \
+ carry = result > 0x000f; \
+ result = (r0 & 0x00f0) + (r1 & 0x00f0) + (carry << 4) + (result & 0x000f); \
+ if(result <= 0x00ff) result -= 0x0060; \
+ carry = result > 0x00ff; \
+ result = (r0 & 0x0f00) + (r1 & 0x0f00) + (carry << 8) + (result & 0x00ff); \
+ if(result <= 0x0fff) result -= 0x0600; \
+ carry = result > 0x0fff; \
+ result = (r0 & 0xf000) + (r1 & 0xf000) + (carry << 12) + (result & 0x0fff); \
+ } \
+ FLAG_V = ~(r0 ^ r1) & (r0 ^ result) & 0x8000; \
+ FLAG_V >>= 8; \
+ if (FLAG_D && result <= 0xffff) result -= 0x6000; \
+ FLAG_C = (result > 0xffff) ? 0x100 : 0; \
+ FLAG_Z = REGISTER_A = MAKE_UINT_16(result); \
+ FLAG_N = NFLAG_16(REGISTER_A);
+#endif
+
+
+/* M6502 Set Carry flag */
+#undef OP_SEC
+#define OP_SEC() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_C = CFLAG_SET
+
+/* M6502 Set Decimal flag */
+#undef OP_SED
+#define OP_SED() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_D = DFLAG_SET
+
+/* M6502 Set Interrupt Mask flag */
+#undef OP_SEI
+#define OP_SEI() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ g65816i_set_flag_i(IFLAG_SET)
+
+/* G65816 Set Program status word */
+#undef OP_SEP
+#define OP_SEP() \
+ CLK(CLK_OP + CLK_R8 + 1); \
+ g65816i_set_reg_p(g65816i_get_reg_p() | OPER_8_IMM())
+
+/* M6502 Store accumulator to memory */
+#undef OP_STA
+#if FLAG_SET_M
+#define OP_STA(MODE) \
+ CLK(CLK_OP + CLK_W8 + CLK_W_##MODE); \
+ write_8_##MODE(EA_##MODE(), REGISTER_A)
+#else
+#define OP_STA(MODE) \
+ CLK(CLK_OP + CLK_W16 + CLK_W_##MODE); \
+ write_16_##MODE(EA_##MODE(), REGISTER_A)
+#endif
+
+/* M6502 Store index register to memory */
+#undef OP_STX
+#if FLAG_SET_X
+#define OP_STX(REG, MODE) \
+ CLK(CLK_OP + CLK_W8 + CLK_W_##MODE); \
+ write_8_##MODE(EA_##MODE(), REG)
+#else
+#define OP_STX(REG, MODE) \
+ CLK(CLK_OP + CLK_W16 + CLK_W_##MODE); \
+ write_16_##MODE(EA_##MODE(), REG)
+#endif
+
+/* M6502 Store zero to memory */
+#undef OP_STZ
+#if FLAG_SET_M
+#define OP_STZ(MODE) \
+ CLK(CLK_OP + CLK_W8 + CLK_W_##MODE); \
+ write_8_##MODE(EA_##MODE(), 0)
+#else
+#define OP_STZ(MODE) \
+ CLK(CLK_OP + CLK_W16 + CLK_W_##MODE); \
+ write_16_##MODE(EA_##MODE(), 0)
+#endif
+
+/* G65816 Stop the clock */
+#undef OP_STP
+#define OP_STP() \
+ USE_ALL_CLKS(); \
+ CPU_STOPPED |= STOP_LEVEL_STOP
+
+/* M6502 Transfer accumulator to index */
+#undef OP_TAX
+#if FLAG_SET_M
+#if FLAG_SET_X
+#define OP_TAX(REG) \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG = REGISTER_A; \
+ FLAG_N = NFLAG_8(FLAG_Z)
+#else /* FLAG_SET_X */
+#define OP_TAX(REG) \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG = REGISTER_B | REGISTER_A; \
+ FLAG_N = NFLAG_16(FLAG_Z)
+#endif /* FLAG_SET_X */
+#else /* FLAG_SET_M */
+#if FLAG_SET_X
+#define OP_TAX(REG) \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG = MAKE_UINT_8(REGISTER_A); \
+ FLAG_N = NFLAG_8(FLAG_Z)
+#else /* FLAG_SET_X */
+#define OP_TAX(REG) \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REG = REGISTER_A; \
+ FLAG_N = NFLAG_16(FLAG_Z)
+#endif /* FLAG_SET_X */
+#endif /* FLAG_SET_M */
+
+
+/* M6502 Transfer index to accumulator */
+#undef OP_TXA
+#if FLAG_SET_M
+#define OP_TXA(REG) \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REGISTER_A = MAKE_UINT_8(REG); \
+ FLAG_N = NFLAG_8(FLAG_Z)
+#else
+#define OP_TXA(REG) \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REGISTER_A = REG; \
+ FLAG_N = NFLAG_16(FLAG_Z)
+#endif
+
+/* G65816 Transfer C to direct register */
+#undef OP_TCD
+#if FLAG_SET_M
+#define OP_TCD() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REGISTER_D = REGISTER_A | REGISTER_B; \
+ FLAG_N = NFLAG_16(FLAG_Z)
+#else
+#define OP_TCD() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REGISTER_D = REGISTER_A; \
+ FLAG_N = NFLAG_16(FLAG_Z)
+#endif
+
+/* G65816 Transfer direct register to C */
+#undef OP_TDC
+#if FLAG_SET_M
+#define OP_TDC() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REGISTER_D; \
+ FLAG_N = NFLAG_16(FLAG_Z); \
+ REGISTER_A = MAKE_UINT_8(REGISTER_D); \
+ REGISTER_B = REGISTER_D & 0xff00
+#else
+#define OP_TDC() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REGISTER_A = REGISTER_D; \
+ FLAG_N = NFLAG_16(FLAG_Z)
+#endif
+
+/* G65816 Transfer C to stack pointer */
+#undef OP_TCS
+#if FLAG_SET_E
+#define OP_TCS() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ REGISTER_S = MAKE_UINT_8(REGISTER_A) | 0x100
+#else
+#define OP_TCS() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ REGISTER_S = REGISTER_A | REGISTER_B
+#endif
+
+/* G65816 Transfer stack pointer to C */
+#undef OP_TSC
+#if FLAG_SET_M
+#define OP_TSC() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REGISTER_S; \
+ FLAG_N = NFLAG_16(FLAG_Z); \
+ REGISTER_A = MAKE_UINT_8(REGISTER_S); \
+ REGISTER_B = REGISTER_S & 0xff00
+#else
+#define OP_TSC() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REGISTER_A = REGISTER_S; \
+ FLAG_N = NFLAG_16(FLAG_Z)
+#endif
+
+/* M6502 Transfer stack pointer to X */
+#undef OP_TSX
+#if FLAG_SET_X
+#define OP_TSX() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REGISTER_X = MAKE_UINT_8(REGISTER_S); \
+ FLAG_N = NFLAG_8(FLAG_Z)
+#else
+#define OP_TSX() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REGISTER_X = REGISTER_S; \
+ FLAG_N = NFLAG_16(FLAG_Z)
+#endif
+
+/* M6502 Transfer X to stack pointer */
+#undef OP_TXS
+#if FLAG_SET_E
+#define OP_TXS() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ REGISTER_S = MAKE_UINT_8(REGISTER_X) | 0x100
+#else
+#define OP_TXS() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ REGISTER_S = REGISTER_X
+#endif
+
+/* G65816 Transfer X to Y */
+#undef OP_TXY
+#if FLAG_SET_X
+#define OP_TXY() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REGISTER_Y = REGISTER_X; \
+ FLAG_N = NFLAG_8(FLAG_Z)
+#else
+#define OP_TXY() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REGISTER_Y = REGISTER_X; \
+ FLAG_N = NFLAG_16(FLAG_Z)
+#endif
+
+/* G65816 Transfer Y to X */
+#undef OP_TYX
+#if FLAG_SET_X
+#define OP_TYX() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REGISTER_X = REGISTER_Y; \
+ FLAG_N = NFLAG_8(FLAG_Z)
+#else
+#define OP_TYX() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REGISTER_X = REGISTER_Y; \
+ FLAG_N = NFLAG_16(FLAG_Z)
+#endif
+
+/* G65816 Test and reset bit */
+#undef OP_TRB
+#if FLAG_SET_M
+#define OP_TRB(MODE) \
+ CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \
+ DST = EA_##MODE(); \
+ FLAG_Z = read_8_##MODE(DST); \
+ write_8_##MODE(DST, FLAG_Z & ~REGISTER_A); \
+ FLAG_Z &= REGISTER_A
+#else
+#define OP_TRB(MODE) \
+ CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \
+ DST = EA_##MODE(); \
+ FLAG_Z = read_16_##MODE(DST); \
+ write_16_##MODE(DST, FLAG_Z & ~REGISTER_A); \
+ FLAG_Z &= REGISTER_A
+#endif
+
+/* G65816 Test and set bit */
+#undef OP_TSB
+#if FLAG_SET_M
+#define OP_TSB(MODE) \
+ CLK(CLK_OP + CLK_RMW8 + CLK_W_##MODE); \
+ DST = EA_##MODE(); \
+ FLAG_Z = read_8_##MODE(DST); \
+ write_8_##MODE(DST, FLAG_Z | REGISTER_A); \
+ FLAG_Z &= REGISTER_A
+#else
+#define OP_TSB(MODE) \
+ CLK(CLK_OP + CLK_RMW16 + CLK_W_##MODE); \
+ DST = EA_##MODE(); \
+ FLAG_Z = read_16_##MODE(DST); \
+ write_16_##MODE(DST, FLAG_Z | REGISTER_A); \
+ FLAG_Z &= REGISTER_A
+#endif
+
+/* G65816 Wait for interrupt */
+#undef OP_WAI
+#define OP_WAI() \
+ USE_ALL_CLKS(); \
+ CPU_STOPPED |= STOP_LEVEL_WAI
+
+/* G65816 William D. Mensch, JR. (65816 designer) - future expansion */
+#undef OP_WDM
+#define OP_WDM() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ REGISTER_PC++
+
+/* G65816 Exchange accum high and low bytes */
+#undef OP_XBA
+#if FLAG_SET_M
+#define OP_XBA() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ FLAG_Z = REGISTER_B>>8; \
+ REGISTER_B = REGISTER_A<<8; \
+ REGISTER_A = FLAG_Z; \
+ FLAG_N = NFLAG_8(FLAG_Z)
+#else
+#define OP_XBA() \
+ CLK(CLK_OP + CLK_IMPLIED + 1); \
+ FLAG_Z = REGISTER_A >> 8; \
+ REGISTER_A = MAKE_UINT_16(REGISTER_A<<8) | FLAG_Z; \
+ FLAG_N = NFLAG_8(FLAG_Z)
+#endif
+
+/* G65816 Exchange carry and emulation bits */
+#undef OP_XCE
+#define OP_XCE() \
+ CLK(CLK_OP + CLK_IMPLIED); \
+ SRC = CFLAG_AS_1(); \
+ FLAG_C = FLAG_E<<8; \
+ g65816i_set_flag_e(SRC)
+
+
+
+
+/* ======================================================================== */
+/* ======================== OPCODE & FUNCTION TABLES ====================== */
+/* ======================================================================== */
+
+#undef OP
+#undef O
+#undef TABLE_OPCODES
+#undef TABLE_FUNCTION
+
+#if FLAG_SET_E
+#define OP(CODE, OPERATION) void g65816_device::g65816i_ ## CODE ## _E() {OPERATION;}
+#define O(CODE) &g65816_device::g65816i_ ## CODE ## _E
+#define TABLE_OPCODES const g65816_device::opcode_func g65816_device::g65816i_opcodes_E[256]
+#define TABLE_FUNCTION(RTYPE, NAME, ARGS) RTYPE g65816_device::g65816i_ ## NAME ## _E ARGS
+
+#else
+
+#if !FLAG_SET_M && !FLAG_SET_X
+#define OP(CODE, OPERATION) void g65816_device::g65816i_ ## CODE ## _M0X0() {OPERATION;}
+#define O(CODE) &g65816_device::g65816i_ ## CODE ## _M0X0
+#define TABLE_OPCODES const g65816_device::opcode_func g65816_device::g65816i_opcodes_M0X0[256]
+#define TABLE_FUNCTION(RTYPE, NAME, ARGS) RTYPE g65816_device::g65816i_ ## NAME ## _M0X0 ARGS
+
+#elif !FLAG_SET_M && FLAG_SET_X
+
+#define OP(CODE, OPERATION) void g65816_device::g65816i_ ## CODE ## _M0X1() {OPERATION;}
+#define O(CODE) &g65816_device::g65816i_ ## CODE ## _M0X1
+#define TABLE_OPCODES const g65816_device::opcode_func g65816_device::g65816i_opcodes_M0X1[256]
+#define TABLE_FUNCTION(RTYPE, NAME, ARGS) RTYPE g65816_device::g65816i_ ## NAME ## _M0X1 ARGS
+
+#elif FLAG_SET_M && !FLAG_SET_X
+
+#define OP(CODE, OPERATION) void g65816_device::g65816i_ ## CODE ## _M1X0() {OPERATION;}
+#define O(CODE) &g65816_device::g65816i_ ## CODE ## _M1X0
+#define TABLE_OPCODES const g65816_device::opcode_func g65816_device::g65816i_opcodes_M1X0[256]
+#define TABLE_FUNCTION(RTYPE, NAME, ARGS) RTYPE g65816_device::g65816i_ ## NAME ## _M1X0 ARGS
+
+#elif FLAG_SET_M && FLAG_SET_X
+
+#define OP(CODE, OPERATION) void g65816_device::g65816i_ ## CODE ## _M1X1() {OPERATION;}
+#define O(CODE) &g65816_device::g65816i_ ## CODE ## _M1X1
+#define TABLE_OPCODES const g65816_device::opcode_func g65816_device::g65816i_opcodes_M1X1[256]
+#define TABLE_FUNCTION(RTYPE, NAME, ARGS) RTYPE g65816_device::g65816i_ ## NAME ## _M1X1 ARGS
+
+#endif
+#endif
+#define BREAKOUT return
+
+
+
+/* OP FUNCTION Comment */
+OP(00, OP_BRK ( ) ) /* BRK */
+OP(01, OP_ORA ( DXI ) ) /* ORA dxi */
+OP(02, OP_COP ( ) ) /* COP (G) */
+OP(03, OP_ORA ( S ) ) /* ORA s (G) */
+OP(04, OP_TSB ( D ) ) /* TSB d (C) */
+OP(05, OP_ORA ( D ) ) /* ORA d */
+OP(06, OP_ASLM ( D ) ) /* ASL d */
+OP(07, OP_ORA ( DLI ) ) /* ORA dli (G) */
+OP(08, OP_PHP ( ) ) /* PHP */
+OP(09, OP_ORA ( IMM ) ) /* ORA imm */
+OP(0a, OP_ASL ( ) ) /* ASL acc */
+OP(0b, OP_PHD ( ) ) /* PHD (G) */
+OP(0c, OP_TSB ( A ) ) /* TSB a (C) */
+OP(0d, OP_ORA ( A ) ) /* ORA a */
+OP(0e, OP_ASLM ( A ) ) /* ASL a */
+OP(0f, OP_ORA ( AL ) ) /* ORA al (G) */
+OP(10, OP_BCC ( COND_PL() ) ) /* BPL */
+OP(11, OP_ORA ( DIY ) ) /* ORA diy */
+OP(12, OP_ORA ( DI ) ) /* ORA di (C) */
+OP(13, OP_ORA ( SIY ) ) /* ORA siy (G) */
+OP(14, OP_TRB ( D ) ) /* TRB d (C) */
+OP(15, OP_ORA ( DX ) ) /* ORA dx */
+OP(16, OP_ASLM ( DX ) ) /* ASL dx */
+OP(17, OP_ORA ( DLIY ) ) /* ORA dliy(C) */
+OP(18, OP_CLC ( ) ) /* CLC */
+OP(19, OP_ORA ( AY ) ) /* ORA ay */
+OP(1a, OP_INC ( ) ) /* INA (C) */
+OP(1b, OP_TCS ( ) ) /* TCS (G) */
+OP(1c, OP_TRB ( A ) ) /* TRB a (C) */
+OP(1d, OP_ORA ( AX ) ) /* ORA ax */
+OP(1e, OP_ASLM ( AX ) ) /* ASL ax */
+OP(1f, OP_ORA ( ALX ) ) /* ORA alx (G) */
+OP(20, OP_JSR ( A ) ) /* JSR a */
+OP(21, OP_AND ( DXI ) ) /* AND dxi */
+OP(22, OP_JSL ( AL ) ) /* JSL al (G) */
+OP(23, OP_AND ( S ) ) /* AND s (G) */
+OP(24, OP_BIT ( D ) ) /* BIT d */
+OP(25, OP_AND ( D ) ) /* AND d */
+OP(26, OP_ROLM ( D ) ) /* ROL d */
+OP(27, OP_AND ( DLI ) ) /* AND dli (G) */
+OP(28, OP_PLP ( ) ) /* PLP */
+OP(29, OP_AND ( IMM ) ) /* AND imm */
+OP(2a, OP_ROL ( ) ) /* ROL acc */
+OP(2b, OP_PLD ( ) ) /* PLD (G) */
+OP(2c, OP_BIT ( A ) ) /* BIT a */
+OP(2d, OP_AND ( A ) ) /* AND a */
+OP(2e, OP_ROLM ( A ) ) /* ROL a */
+OP(2f, OP_AND ( AL ) ) /* AND al (G) */
+OP(30, OP_BCC ( COND_MI() ) ) /* BMI */
+OP(31, OP_AND ( DIY ) ) /* AND diy */
+OP(32, OP_AND ( DI ) ) /* AND di (C) */
+OP(33, OP_AND ( SIY ) ) /* AND siy */
+OP(34, OP_BIT ( DX ) ) /* BIT dx (C) */
+OP(35, OP_AND ( DX ) ) /* AND dx */
+OP(36, OP_ROLM ( DX ) ) /* ROL dx */
+OP(37, OP_AND ( DLIY ) ) /* AND dliy(G) */
+OP(38, OP_SEC ( ) ) /* SEC */
+OP(39, OP_AND ( AY ) ) /* AND ay */
+OP(3a, OP_DEC ( ) ) /* DEA (C) */
+OP(3b, OP_TSC ( ) ) /* TSC (G) */
+OP(3c, OP_BIT ( AX ) ) /* BIT abx (C) */
+OP(3d, OP_AND ( AX ) ) /* AND ax */
+OP(3e, OP_ROLM ( AX ) ) /* ROL ax */
+OP(3f, OP_AND ( ALX ) ) /* AND alx (G) */
+OP(40, OP_RTI ( ) ) /* RTI */
+OP(41, OP_EOR ( DXI ) ) /* EOR dxi */
+OP(42, OP_WDM ( ) ) /* WDM */
+OP(43, OP_EOR ( S ) ) /* EOR s (G) */
+OP(44, OP_MVP ( ) ) /* MVP (G) */
+OP(45, OP_EOR ( D ) ) /* EOR d */
+OP(46, OP_LSRM ( D ) ) /* LSR d */
+OP(47, OP_EOR ( DLI ) ) /* EOR dli (G) */
+OP(48, OP_PHA ( ) ) /* PHA */
+OP(49, OP_EOR ( IMM ) ) /* EOR imm */
+OP(4a, OP_LSR ( ) ) /* LSR acc */
+OP(4b, OP_PHK ( ) ) /* PHK (G) */
+OP(4c, OP_JMP ( A ) ) /* JMP a */
+OP(4d, OP_EOR ( A ) ) /* EOR a */
+OP(4e, OP_LSRM ( A ) ) /* LSR a */
+OP(4f, OP_EOR ( AL ) ) /* EOR al (G) */
+OP(50, OP_BCC ( COND_VC() ) ) /* BVC */
+OP(51, OP_EOR ( DIY ) ) /* EOR diy */
+OP(52, OP_EOR ( DI ) ) /* EOR di (C) */
+OP(53, OP_EOR ( SIY ) ) /* EOR siy (G) */
+OP(54, OP_MVN ( ) ) /* MVN (G) */
+OP(55, OP_EOR ( DX ) ) /* EOR dx */
+OP(56, OP_LSRM ( DX ) ) /* LSR dx */
+OP(57, OP_EOR ( DLIY ) ) /* EOR dliy(G) */
+OP(58, OP_CLI ( ) ) /* CLI */
+OP(59, OP_EOR ( AY ) ) /* EOR ay */
+OP(5a, OP_PHX ( REGISTER_Y ) ) /* PHY (C) */
+OP(5b, OP_TCD ( ) ) /* TCD (G) */
+OP(5c, OP_JMPAL( ) ) /* JMP al (G) */
+OP(5d, OP_EOR ( AX ) ) /* EOR ax */
+OP(5e, OP_LSRM ( AX ) ) /* LSR ax */
+OP(5f, OP_EOR ( ALX ) ) /* EOR alx (G) */
+OP(60, OP_RTS ( ) ) /* RTS */
+OP(61, OP_ADC ( DXI ) ) /* ADC dxi */
+OP(62, OP_PER ( ) ) /* PER (G) */
+OP(63, OP_ADC ( S ) ) /* ADC s (G) */
+OP(64, OP_STZ ( D ) ) /* STZ d (C) */
+OP(65, OP_ADC ( D ) ) /* ADC d */
+OP(66, OP_RORM ( D ) ) /* ROR d */
+OP(67, OP_ADC ( DLI ) ) /* ADC dli (G) */
+OP(68, OP_PLA ( ) ) /* PLA */
+OP(69, OP_ADC ( IMM ) ) /* ADC imm */
+OP(6a, OP_ROR ( ) ) /* ROR acc */
+OP(6b, OP_RTL ( ) ) /* RTL (G) */
+OP(6c, OP_JMP ( AI ) ) /* JMP ai */
+OP(6d, OP_ADC ( A ) ) /* ADC a */
+OP(6e, OP_RORM ( A ) ) /* ROR a */
+OP(6f, OP_ADC ( AL ) ) /* ADC al (G) */
+OP(70, OP_BCC ( COND_VS() ) ) /* BVS */
+OP(71, OP_ADC ( DIY ) ) /* ADC diy */
+OP(72, OP_ADC ( DI ) ) /* ADC di (G) */
+OP(73, OP_ADC ( SIY ) ) /* ADC siy (G) */
+OP(74, OP_STZ ( DX ) ) /* STZ dx (C) */
+OP(75, OP_ADC ( DX ) ) /* ADC dx */
+OP(76, OP_RORM ( DX ) ) /* ROR dx */
+OP(77, OP_ADC ( DLIY ) ) /* ADC dliy(G) */
+OP(78, OP_SEI ( ) ) /* SEI */
+OP(79, OP_ADC ( AY ) ) /* ADC ay */
+OP(7a, OP_PLX ( REGISTER_Y ) ) /* PLY (C) */
+OP(7b, OP_TDC ( ) ) /* TDC (G) */
+OP(7c, OP_JMPAXI( ) ) /* JMP axi (C) */
+OP(7d, OP_ADC ( AX ) ) /* ADC ax */
+OP(7e, OP_RORM ( AX ) ) /* ROR ax */
+OP(7f, OP_ADC ( ALX ) ) /* ADC alx (G) */
+OP(80, OP_BRA ( ) ) /* BRA (C) */
+OP(81, OP_STA ( DXI ) ) /* STA dxi */
+OP(82, OP_BRL ( ) ) /* BRL (G) */
+OP(83, OP_STA ( S ) ) /* STA s (G) */
+OP(84, OP_STX ( REGISTER_Y, D ) ) /* STY d */
+OP(85, OP_STA ( D ) ) /* STA d */
+OP(86, OP_STX ( REGISTER_X, D ) ) /* STX d */
+OP(87, OP_STA ( DLI ) ) /* STA dli (G) */
+OP(88, OP_DECX ( REGISTER_Y ) ) /* DEY */
+OP(89, OP_BITI ( ) ) /* BIT imm (C) */
+OP(8a, OP_TXA ( REGISTER_X ) ) /* TXA */
+OP(8b, OP_PHB ( ) ) /* PHB (G) */
+OP(8c, OP_STX ( REGISTER_Y, A ) ) /* STY a */
+OP(8d, OP_STA ( A ) ) /* STA a */
+OP(8e, OP_STX ( REGISTER_X, A ) ) /* STX a */
+OP(8f, OP_STA ( AL ) ) /* STA al (G) */
+OP(90, OP_BCC ( COND_CC() ) ) /* BCC */
+OP(91, OP_STA ( DIY ) ) /* STA diy */
+OP(92, OP_STA ( DI ) ) /* STA di (C) */
+OP(93, OP_STA ( SIY ) ) /* STA siy (G) */
+OP(94, OP_STX ( REGISTER_Y, DX ) ) /* STY dx */
+OP(95, OP_STA ( DX ) ) /* STA dx */
+OP(96, OP_STX ( REGISTER_X, DY ) ) /* STX dy */
+OP(97, OP_STA ( DLIY ) ) /* STA dliy(G) */
+OP(98, OP_TXA ( REGISTER_Y ) ) /* TYA */
+OP(99, OP_STA ( AY ) ) /* STA ay */
+OP(9a, OP_TXS ( ) ) /* TXS */
+OP(9b, OP_TXY ( ) ) /* TXY (G) */
+OP(9c, OP_STZ ( A ) ) /* STZ a (C) */
+OP(9d, OP_STA ( AX ) ) /* STA ax */
+OP(9e, OP_STZ ( AX ) ) /* STZ ax (C) */
+OP(9f, OP_STA ( ALX ) ) /* STA alx (G) */
+OP(a0, OP_LDX ( REGISTER_Y, IMM ) ) /* LDY imm */
+OP(a1, OP_LDA ( DXI ) ) /* LDA dxi */
+OP(a2, OP_LDX ( REGISTER_X, IMM ) ) /* LDX imm */
+OP(a3, OP_LDA ( S ) ) /* LDA s (G) */
+OP(a4, OP_LDX ( REGISTER_Y, D ) ) /* LDY d */
+OP(a5, OP_LDA ( D ) ) /* LDA d */
+OP(a6, OP_LDX ( REGISTER_X, D ) ) /* LDX d */
+OP(a7, OP_LDA ( DLI ) ) /* LDA dli (G) */
+OP(a8, OP_TAX ( REGISTER_Y ) ) /* TAY */
+OP(a9, OP_LDA ( IMM ) ) /* LDA imm */
+OP(aa, OP_TAX ( REGISTER_X ) ) /* TAX */
+OP(ab, OP_PLB ( ) ) /* PLB (G) */
+OP(ac, OP_LDX ( REGISTER_Y, A ) ) /* LDY a */
+OP(ad, OP_LDA ( A ) ) /* LDA a */
+OP(ae, OP_LDX ( REGISTER_X, A ) ) /* LDX a */
+OP(af, OP_LDA ( AL ) ) /* LDA al (G) */
+OP(b0, OP_BCC ( COND_CS() ) ) /* BCS */
+OP(b1, OP_LDA ( DIY ) ) /* LDA diy */
+OP(b2, OP_LDA ( DI ) ) /* LDA di (C) */
+OP(b3, OP_LDA ( SIY ) ) /* LDA siy (G) */
+OP(b4, OP_LDX ( REGISTER_Y, DX ) ) /* LDY dx */
+OP(b5, OP_LDA ( DX ) ) /* LDA dx */
+OP(b6, OP_LDX ( REGISTER_X, DY ) ) /* LDX dy */
+OP(b7, OP_LDA ( DLIY ) ) /* LDA dliy(G) */
+OP(b8, OP_CLV ( ) ) /* CLV */
+OP(b9, OP_LDA ( AY ) ) /* LDA ay */
+OP(ba, OP_TSX ( ) ) /* TSX */
+OP(bb, OP_TYX ( ) ) /* TYX (G) */
+OP(bc, OP_LDX ( REGISTER_Y, AX ) ) /* LDY ax */
+OP(bd, OP_LDA ( AX ) ) /* LDA ax */
+OP(be, OP_LDX ( REGISTER_X, AY ) ) /* LDX ay */
+OP(bf, OP_LDA ( ALX ) ) /* LDA alx (G) */
+OP(c0, OP_CMPX ( REGISTER_Y, IMM ) ) /* CPY imm */
+OP(c1, OP_CMP ( DXI ) ) /* CMP dxi */
+OP(c2, OP_REP ( ) ) /* REP (G) */
+OP(c3, OP_CMP ( S ) ) /* CMP s (G) */
+OP(c4, OP_CMPX ( REGISTER_Y, D ) ) /* CPY d */
+OP(c5, OP_CMP ( D ) ) /* CMP d */
+OP(c6, OP_DECM ( D ) ) /* DEC d */
+OP(c7, OP_CMP ( DLI ) ) /* CMP dli (G) */
+OP(c8, OP_INCX ( REGISTER_Y ) ) /* INY */
+OP(c9, OP_CMP ( IMM ) ) /* CMP imm */
+OP(ca, OP_DECX ( REGISTER_X ) ) /* DEX */
+OP(cb, OP_WAI ( ) ) /* WAI (G) */
+OP(cc, OP_CMPX ( REGISTER_Y, A ) ) /* CPY a */
+OP(cd, OP_CMP ( A ) ) /* CMP a */
+OP(ce, OP_DECM ( A ) ) /* DEC a */
+OP(cf, OP_CMP ( AL ) ) /* CMP al (G) */
+OP(d0, OP_BCC ( COND_NE() ) ) /* BNE */
+OP(d1, OP_CMP ( DIY ) ) /* CMP diy */
+OP(d2, OP_CMP ( DI ) ) /* CMP di (C) */
+OP(d3, OP_CMP ( SIY ) ) /* CMP siy (G) */
+OP(d4, OP_PEI ( ) ) /* PEI (G) */
+OP(d5, OP_CMP ( DX ) ) /* CMP dx */
+OP(d6, OP_DECM ( DX ) ) /* DEC dx */
+OP(d7, OP_CMP ( DLIY ) ) /* CMP dliy(G) */
+OP(d8, OP_CLD ( ) ) /* CLD */
+OP(d9, OP_CMP ( AY ) ) /* CMP ay */
+OP(da, OP_PHX ( REGISTER_X ) ) /* PHX (C) */
+OP(db, OP_STP ( ) ) /* STP (G) */
+OP(dc, OP_JMLAI( ) ) /* JML ai (G) */
+OP(dd, OP_CMP ( AX ) ) /* CMP ax */
+OP(de, OP_DECM ( AX ) ) /* DEC ax */
+OP(df, OP_CMP ( ALX ) ) /* CMP alx (G) */
+OP(e0, OP_CMPX ( REGISTER_X, IMM ) ) /* CPX imm */
+OP(e1, OP_SBC ( DXI ) ) /* SBC dxi */
+OP(e2, OP_SEP ( ) ) /* SEP imm (G) */
+OP(e3, OP_SBC ( S ) ) /* SBC s (G) */
+OP(e4, OP_CMPX ( REGISTER_X, D ) ) /* CPX d */
+OP(e5, OP_SBC ( D ) ) /* SBC d */
+OP(e6, OP_INCM ( D ) ) /* INC d */
+OP(e7, OP_SBC ( DLI ) ) /* SBC dli (G) */
+OP(e8, OP_INCX ( REGISTER_X ) ) /* INX */
+OP(e9, OP_SBC ( IMM ) ) /* SBC imm */
+OP(ea, OP_NOP ( ) ) /* NOP */
+OP(eb, OP_XBA ( ) ) /* XBA (G) */
+OP(ec, OP_CMPX ( REGISTER_X, A ) ) /* CPX a */
+OP(ed, OP_SBC ( A ) ) /* SBC a */
+OP(ee, OP_INCM ( A ) ) /* INC a */
+OP(ef, OP_SBC ( AL ) ) /* SBC al (G) */
+OP(f0, OP_BCC ( COND_EQ() ) ) /* BEQ */
+OP(f1, OP_SBC ( DIY ) ) /* SBC diy */
+OP(f2, OP_SBC ( DI ) ) /* SBC di (C) */
+OP(f3, OP_SBC ( SIY ) ) /* SBC siy (G) */
+OP(f4, OP_PEA ( ) ) /* PEA (G) */
+OP(f5, OP_SBC ( DX ) ) /* SBC dx */
+OP(f6, OP_INCM ( DX ) ) /* INC dx */
+OP(f7, OP_SBC ( DLIY ) ) /* SBC dliy(G) */
+OP(f8, OP_SED ( ) ) /* SED */
+OP(f9, OP_SBC ( AY ) ) /* SBC ay */
+OP(fa, OP_PLX ( REGISTER_X ) ) /* PLX (C) */
+OP(fb, OP_XCE ( ) ) /* XCE (G) */
+OP(fc, OP_JSRAXI( ) ) /* JSR axi (G) */
+OP(fd, OP_SBC ( AX ) ) /* SBC ax */
+OP(fe, OP_INCM ( AX ) ) /* INC ax */
+OP(ff, OP_SBC ( ALX ) ) /* SBC alx (G) */
+
+
+
+TABLE_OPCODES =
+{
+ O(00),O(01),O(02),O(03),O(04),O(05),O(06),O(07),
+ O(08),O(09),O(0a),O(0b),O(0c),O(0d),O(0e),O(0f),
+ O(10),O(11),O(12),O(13),O(14),O(15),O(16),O(17),
+ O(18),O(19),O(1a),O(1b),O(1c),O(1d),O(1e),O(1f),
+ O(20),O(21),O(22),O(23),O(24),O(25),O(26),O(27),
+ O(28),O(29),O(2a),O(2b),O(2c),O(2d),O(2e),O(2f),
+ O(30),O(31),O(32),O(33),O(34),O(35),O(36),O(37),
+ O(38),O(39),O(3a),O(3b),O(3c),O(3d),O(3e),O(3f),
+ O(40),O(41),O(42),O(43),O(44),O(45),O(46),O(47),
+ O(48),O(49),O(4a),O(4b),O(4c),O(4d),O(4e),O(4f),
+ O(50),O(51),O(52),O(53),O(54),O(55),O(56),O(57),
+ O(58),O(59),O(5a),O(5b),O(5c),O(5d),O(5e),O(5f),
+ O(60),O(61),O(62),O(63),O(64),O(65),O(66),O(67),
+ O(68),O(69),O(6a),O(6b),O(6c),O(6d),O(6e),O(6f),
+ O(70),O(71),O(72),O(73),O(74),O(75),O(76),O(77),
+ O(78),O(79),O(7a),O(7b),O(7c),O(7d),O(7e),O(7f),
+ O(80),O(81),O(82),O(83),O(84),O(85),O(86),O(87),
+ O(88),O(89),O(8a),O(8b),O(8c),O(8d),O(8e),O(8f),
+ O(90),O(91),O(92),O(93),O(94),O(95),O(96),O(97),
+ O(98),O(99),O(9a),O(9b),O(9c),O(9d),O(9e),O(9f),
+ O(a0),O(a1),O(a2),O(a3),O(a4),O(a5),O(a6),O(a7),
+ O(a8),O(a9),O(aa),O(ab),O(ac),O(ad),O(ae),O(af),
+ O(b0),O(b1),O(b2),O(b3),O(b4),O(b5),O(b6),O(b7),
+ O(b8),O(b9),O(ba),O(bb),O(bc),O(bd),O(be),O(bf),
+ O(c0),O(c1),O(c2),O(c3),O(c4),O(c5),O(c6),O(c7),
+ O(c8),O(c9),O(ca),O(cb),O(cc),O(cd),O(ce),O(cf),
+ O(d0),O(d1),O(d2),O(d3),O(d4),O(d5),O(d6),O(d7),
+ O(d8),O(d9),O(da),O(db),O(dc),O(dd),O(de),O(df),
+ O(e0),O(e1),O(e2),O(e3),O(e4),O(e5),O(e6),O(e7),
+ O(e8),O(e9),O(ea),O(eb),O(ec),O(ed),O(ee),O(ef),
+ O(f0),O(f1),O(f2),O(f3),O(f4),O(f5),O(f6),O(f7),
+ O(f8),O(f9),O(fa),O(fb),O(fc),O(fd),O(fe),O(ff)
+};
+
+
+
+/* Assert or clear a line on the CPU */
+TABLE_FUNCTION(void, set_line, (int line, int state))
+{
+ switch(line)
+ {
+ case G65816_LINE_IRQ:
+ switch(state)
+ {
+ case CLEAR_LINE:
+ LINE_IRQ = 0;
+ return;
+ case ASSERT_LINE:
+ case HOLD_LINE:
+ LINE_IRQ = 1;
+ }
+ if(FLAG_I)
+ {
+ if(CPU_STOPPED & STOP_LEVEL_WAI)
+ {
+ CPU_STOPPED &= ~STOP_LEVEL_WAI;
+ }
+ return;
+ }
+ return;
+ case G65816_LINE_NMI:
+ if(state == CLEAR_LINE)
+ {
+ LINE_NMI = 0;
+ return;
+ }
+ if(!LINE_NMI)
+ {
+ LINE_NMI = 1;
+ CPU_STOPPED &= ~STOP_LEVEL_WAI;
+ if(!CPU_STOPPED)
+ g65816i_interrupt_nmi();
+ }
+ return;
+ case G65816_LINE_SO:
+ FLAG_V = VFLAG_SET;
+ break;
+ case G65816_LINE_RESET:
+ case G65816_LINE_ABORT:
+ case G65816_LINE_RDY:
+ return;
+ }
+
+ LINE_IRQ=1;
+}
+
+
+
+/* Get a register from the CPU core */
+TABLE_FUNCTION(uint, get_reg, (int regnum))
+{
+ switch(regnum)
+ {
+ case G65816_A: return REGISTER_B | REGISTER_A;
+ case G65816_X: return REGISTER_X;
+ case G65816_Y: return REGISTER_Y;
+ case STATE_GENSP: return REGISTER_S;
+ case G65816_S: return REGISTER_S;
+ case STATE_GENPC: return REGISTER_PC;
+ case G65816_PC: return REGISTER_PC;
+ case G65816_PB: return REGISTER_PB >> 16;
+ case G65816_DB: return REGISTER_DB >> 16;
+ case G65816_D: return REGISTER_D;
+ case G65816_P: return g65816i_get_reg_p();
+ case G65816_NMI_STATE: return LINE_NMI;
+ case G65816_IRQ_STATE: return LINE_IRQ;
+ case STATE_GENPCBASE: return REGISTER_PPC;
+ case _5A22_FASTROM: return m_fastROM;
+ }
+ return 0;
+}
+
+
+
+TABLE_FUNCTION(void, set_reg, (int regnum, uint val))
+{
+ switch(regnum)
+ {
+ case STATE_GENPC: case G65816_PC: REGISTER_PC = MAKE_UINT_16(val); break;
+#if FLAG_SET_E
+ case STATE_GENSP: case G65816_S: REGISTER_S = MAKE_UINT_8(val) | 0x100; break;
+#else
+ case STATE_GENSP: case G65816_S: REGISTER_S = MAKE_UINT_16(val); break;
+#endif
+ case G65816_P: g65816i_set_reg_p(val); break;
+#if FLAG_SET_M
+ case G65816_A: REGISTER_A = MAKE_UINT_8(val); REGISTER_B = val&0xff00; break;
+#else
+ case G65816_A: REGISTER_A = MAKE_UINT_16(val); break;
+#endif
+#if FLAG_SET_X
+ case G65816_X: REGISTER_X = MAKE_UINT_8(val); break;
+ case G65816_Y: REGISTER_Y = MAKE_UINT_8(val); break;
+#else
+ case G65816_X: REGISTER_X = MAKE_UINT_16(val); break;
+ case G65816_Y: REGISTER_Y = MAKE_UINT_16(val); break;
+#endif
+ case G65816_DB: REGISTER_DB = MAKE_UINT_8(val); break;
+ case G65816_PB: REGISTER_PB = MAKE_UINT_8(val); break;
+ case G65816_NMI_STATE: (this->*FTABLE_SET_LINE)(G65816_LINE_NMI, val == 0 ? CLEAR_LINE : ASSERT_LINE); break;
+ case G65816_IRQ_STATE: (this->*FTABLE_SET_LINE)(G65816_LINE_IRQ, val == 0 ? CLEAR_LINE : ASSERT_LINE); break;
+ case _5A22_FASTROM: m_fastROM = val; break;
+ }
+}
+
+
+
+#if EXECUTION_MODE == EXECUTION_MODE_E
+#define g65816i_correct_mode() (FLAG_E == EFLAG_SET)
+#elif EXECUTION_MODE == EXECUTION_MODE_M0X0
+#define g65816i_correct_mode() ((FLAG_E == EFLAG_CLEAR) && (FLAG_M == MFLAG_CLEAR) && (FLAG_X == XFLAG_CLEAR))
+#elif EXECUTION_MODE == EXECUTION_MODE_M0X1
+#define g65816i_correct_mode() ((FLAG_E == EFLAG_CLEAR) && (FLAG_M == MFLAG_CLEAR) && (FLAG_X == XFLAG_SET))
+#elif EXECUTION_MODE == EXECUTION_MODE_M1X0
+#define g65816i_correct_mode() ((FLAG_E == EFLAG_CLEAR) && (FLAG_M == MFLAG_SET) && (FLAG_X == XFLAG_CLEAR))
+#elif EXECUTION_MODE == EXECUTION_MODE_M1X1
+#define g65816i_correct_mode() ((FLAG_E == EFLAG_CLEAR) && (FLAG_M == MFLAG_SET) && (FLAG_X == XFLAG_SET))
+#else
+#error Invalid EXECUTION_MODE
+#endif
+
+
+
+TABLE_FUNCTION(int, execute, (int clocks))
+{
+ // do a check here also in case we're in STOP_WAI mode - this'll clear it when the IRQ happens
+ g65816i_check_maskable_interrupt();
+
+ if (!CPU_STOPPED)
+ {
+ CLOCKS = clocks;
+ do
+ {
+ /* Note that I'm doing a per-instruction interrupt
+ * check until this core is working well enough
+ * to start trying fancy stuff.
+ */
+ g65816i_check_maskable_interrupt();
+
+ REGISTER_PPC = REGISTER_PC;
+ G65816_CALL_DEBUGGER(REGISTER_PB | REGISTER_PC);
+
+ REGISTER_PC++;
+ REGISTER_IR = read_8_IMM(REGISTER_PB | REGISTER_PPC);
+ (this->*FTABLE_OPCODES[REGISTER_IR])();
+ } while((CLOCKS > 0) && g65816i_correct_mode());
+ return clocks - CLOCKS;
+ }
+ return clocks;
+}