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author Vas Crabb <vas@vastheman.com>2025-03-29 04:53:34 +1100
committer Vas Crabb <vas@vastheman.com>2025-03-29 04:56:48 +1100
commit40a0638ba76b91b0b213788ed5a6b259fa5b84a5 (patch)
tree22a38fdebcfafa96a6165e1a346ecaaf4bd52d29 /src/devices/cpu/drcbex64.cpp
parent345ab51e9dfc6c4a13a27a453da896873eab6de0 (diff)
-cpu/e132xs: General cleanup and usability improvements:
* Aligned the operand field in disassembly. * Calculate results of immediate values against the PC to make position-independent code easier to read without constantly using a calculator (e.g. this shows destinations for call Rd, PC, imm). * Added more symbols to the UML helper to make logged generated code more readable. * Made single-instruction-per-sequence mode configurable rather than a compile-time option. * Got rid of a criminal amount of copy/paste in the disassembler, and got rid of all the deprecated strcpy calls. * Got rid of some duplicated constants, changed some constants from macros to enumerated values or constexpr globals. * Reduced the amound of stuff in headers that doesn't need to be there. -cpu/drcbex64.cpp: Don't construct std::function objects during code generation - they require allocation. -eolith/eolith.cpp: Turned single-instruction-per-sequence mode on for now until someone works out why turning it off causes Raccoon World to generate so much code it's unplayably slow.
Diffstat (limited to 'src/devices/cpu/drcbex64.cpp')
-rw-r--r--src/devices/cpu/drcbex64.cpp29
1 files changed, 16 insertions, 13 deletions
diff --git a/src/devices/cpu/drcbex64.cpp b/src/devices/cpu/drcbex64.cpp
index 776bd17e29c..45d442e8576 100644
--- a/src/devices/cpu/drcbex64.cpp
+++ b/src/devices/cpu/drcbex64.cpp
@@ -594,7 +594,9 @@ private:
// alu and shift operation helpers
static bool ones(u64 const value, unsigned const size) noexcept { return (size == 4) ? u32(value) == 0xffffffffU : value == 0xffffffff'ffffffffULL; }
- void alu_op_param(asmjit::x86::Assembler &a, asmjit::x86::Inst::Id const opcode, asmjit::Operand const &dst, be_parameter const &param, std::function<bool(asmjit::x86::Assembler &a, asmjit::Operand const &dst, be_parameter const &src)> optimize = [](asmjit::x86::Assembler &a, asmjit::Operand dst, be_parameter const &src) { return false; });
+ template <typename T>
+ void alu_op_param(asmjit::x86::Assembler &a, asmjit::x86::Inst::Id const opcode, asmjit::Operand const &dst, be_parameter const &param, T &&optimize);
+ void alu_op_param(asmjit::x86::Assembler &a, asmjit::x86::Inst::Id const opcode, asmjit::Operand const &dst, be_parameter const &param) { alu_op_param(a, opcode, dst, param, [] (asmjit::x86::Assembler &a, asmjit::Operand dst, be_parameter const &src) { return false; }); }
void shift_op_param(asmjit::x86::Assembler &a, asmjit::x86::Inst::Id const opcode, size_t opsize, asmjit::Operand const &dst, be_parameter const &param, u8 update_flags);
// parameter helpers
@@ -1401,7 +1403,8 @@ void drcbe_x64::get_info(drcbe_info &info) const noexcept
break;
}
-void drcbe_x64::alu_op_param(Assembler &a, Inst::Id const opcode, Operand const &dst, be_parameter const &param, std::function<bool(Assembler &a, Operand const &dst, be_parameter const &src)> optimize)
+template <typename T>
+void drcbe_x64::alu_op_param(Assembler &a, Inst::Id const opcode, Operand const &dst, be_parameter const &param, T &&optimize)
{
bool const is64 = dst.x86RmSize() == 8;
@@ -3945,7 +3948,7 @@ void drcbe_x64::op_roland(Assembler &a, const instruction &inst)
a.rol(dstreg, cl);
}
alu_op_param(a, Inst::kIdAnd, dstreg, maskp,
- [inst](Assembler &a, Operand const &dst, be_parameter const &src)
+ [inst] (Assembler &a, Operand const &dst, be_parameter const &src)
{
// all-one cases
if (ones(src.immediate(), inst.size()))
@@ -4277,7 +4280,7 @@ void drcbe_x64::op_add(Assembler &a, const instruction &inst)
{
// dstp == src1p in memory
alu_op_param(a, Inst::kIdAdd, MABS(dstp.memory(), inst.size()), src2p, // add [dstp],src2p
- [inst](Assembler &a, Operand const &dst, be_parameter const &src)
+ [inst] (Assembler &a, Operand const &dst, be_parameter const &src)
{
// optimize zero case
return (!inst.flags() && !src.immediate());
@@ -4309,7 +4312,7 @@ void drcbe_x64::op_add(Assembler &a, const instruction &inst)
mov_reg_param(a, dstreg, src1p); // mov dstreg,src1p
alu_op_param(a, Inst::kIdAdd, dstreg, src2p, // add dstreg,src2p
- [inst](Assembler &a, Operand const &dst, be_parameter const &src)
+ [inst] (Assembler &a, Operand const &dst, be_parameter const &src)
{
// optimize zero case
return (!inst.flags() && !src.immediate() && (inst.size() != 4));
@@ -4375,7 +4378,7 @@ void drcbe_x64::op_sub(Assembler &a, const instruction &inst)
{
// dstp == src1p in memory
alu_op_param(a, Inst::kIdSub, MABS(dstp.memory(), inst.size()), src2p, // sub [dstp],src2p
- [inst](Assembler &a, Operand const &dst, be_parameter const &src)
+ [inst] (Assembler &a, Operand const &dst, be_parameter const &src)
{
// optimize zero case
return (!inst.flags() && !src.immediate());
@@ -4398,7 +4401,7 @@ void drcbe_x64::op_sub(Assembler &a, const instruction &inst)
mov_reg_param(a, dstreg, src1p); // mov dstreg,src1p
alu_op_param(a, Inst::kIdSub, dstreg, src2p, // sub dstreg,src2p
- [inst](Assembler &a, Operand const &dst, be_parameter const &src)
+ [inst] (Assembler &a, Operand const &dst, be_parameter const &src)
{
// optimize zero case
return (!inst.flags() && !src.immediate() && (inst.size() != 4));
@@ -5006,7 +5009,7 @@ void drcbe_x64::op_test(Assembler &a, const instruction &inst)
mov_reg_param(a, src1reg, src1p);
alu_op_param(a, Inst::kIdTest, src1reg, src2p,
- [inst](Assembler &a, Operand const &dst, be_parameter const &src)
+ [inst] (Assembler &a, Operand const &dst, be_parameter const &src)
{
// optimize all-one cases
if (ones(src.immediate(), inst.size()))
@@ -5042,7 +5045,7 @@ void drcbe_x64::op_or(Assembler &a, const instruction &inst)
{
// dstp == src1p in memory
alu_op_param(a, Inst::kIdOr, MABS(dstp.memory(), inst.size()), src2p, // or [dstp],src2p
- [inst](Assembler &a, Operand const &dst, be_parameter const &src)
+ [inst] (Assembler &a, Operand const &dst, be_parameter const &src)
{
// optimize all-zero and all-one cases
if (!inst.flags() && ones(src.immediate(), inst.size()))
@@ -5066,7 +5069,7 @@ void drcbe_x64::op_or(Assembler &a, const instruction &inst)
mov_reg_param(a, dstreg, src1p); // mov dstreg,src1p
alu_op_param(a, Inst::kIdOr, dstreg, src2p, // or dstreg,src2p
- [inst](Assembler &a, Operand const &dst, be_parameter const &src)
+ [inst] (Assembler &a, Operand const &dst, be_parameter const &src)
{
// optimize all-zero and all-one cases
if (!inst.flags() && ones(src.immediate(), inst.size()))
@@ -5120,7 +5123,7 @@ void drcbe_x64::op_xor(Assembler &a, const instruction &inst)
{
// dstp == src1p in memory
alu_op_param(a, Inst::kIdXor, MABS(dstp.memory(), inst.size()), src2p, // xor [dstp],src2p
- [inst](Assembler &a, Operand const &dst, be_parameter const &src)
+ [inst] (Assembler &a, Operand const &dst, be_parameter const &src)
{
// optimize all-zero and all-one cases
if (!inst.flags() && ones(src.immediate(), inst.size()))
@@ -5140,7 +5143,7 @@ void drcbe_x64::op_xor(Assembler &a, const instruction &inst)
Gp const dst = Gp::fromTypeAndId((inst.size() == 4) ? RegType::kX86_Gpd : RegType::kX86_Gpq, dstp.ireg());
alu_op_param(a, Inst::kIdXor, dst, src2p,
- [inst](Assembler &a, Operand const &dst, be_parameter const &src)
+ [inst] (Assembler &a, Operand const &dst, be_parameter const &src)
{
// optimize all-zero and all-one cases
if (!inst.flags() && ones(src.immediate(), inst.size()))
@@ -5173,7 +5176,7 @@ void drcbe_x64::op_xor(Assembler &a, const instruction &inst)
mov_reg_param(a, dstreg, src1p);
alu_op_param(a, Inst::kIdXor, dstreg, src2p,
- [inst](Assembler &a, Operand const &dst, be_parameter const &src)
+ [inst] (Assembler &a, Operand const &dst, be_parameter const &src)
{
// optimize all-zero and all-one cases
if (!inst.flags() && ones(src.immediate(), inst.size()))